diff options
Diffstat (limited to 'tests')
44 files changed, 14176 insertions, 14341 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 0876dc614..a9e8e7d4a 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.903548 # Number of seconds simulated -sim_ticks 1903548166500 # Number of ticks simulated -final_tick 1903548166500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.902683 # Number of seconds simulated +sim_ticks 1902682770000 # Number of ticks simulated +final_tick 1902682770000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123505 # Simulator instruction rate (inst/s) -host_op_rate 123505 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4187441182 # Simulator tick rate (ticks/s) -host_mem_usage 303204 # Number of bytes of host memory used -host_seconds 454.59 # Real time elapsed on the host -sim_insts 56143492 # Number of instructions simulated -sim_ops 56143492 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 879488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24796480 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 101696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 559552 # Number of bytes read from this memory -system.physmem.bytes_read::total 28986880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 879488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 101696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 981184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7925376 # Number of bytes written to this memory -system.physmem.bytes_written::total 7925376 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13742 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387445 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41401 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1589 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8743 # Number of read requests responded to by this memory -system.physmem.num_reads::total 452920 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123834 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123834 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 462026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13026453 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1391961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 293952 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15227815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 462026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53424 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 515450 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4163475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4163475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4163475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 462026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13026453 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1391961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 293952 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19391291 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 346033 # number of replacements -system.l2c.tagsinuse 65330.743124 # Cycle average of tags in use -system.l2c.total_refs 2608063 # Total number of references to valid blocks. -system.l2c.sampled_refs 411178 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.342905 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6380526000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53708.225390 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5276.213951 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 6113.589929 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 198.792297 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 33.921558 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.819522 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.080509 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.093286 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.003033 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000518 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996868 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 970913 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 780748 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 107670 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 39067 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1898398 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 832636 # number of Writeback hits -system.l2c.Writeback_hits::total 832636 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 184 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 54 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 238 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 27 # number of SCUpgradeReq hits +host_inst_rate 192931 # Simulator instruction rate (inst/s) +host_op_rate 192931 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6436506827 # Simulator tick rate (ticks/s) +host_mem_usage 296908 # Number of bytes of host memory used +host_seconds 295.61 # Real time elapsed on the host +sim_insts 57032045 # Number of instructions simulated +sim_ops 57032045 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 906816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24518592 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 73984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 789824 # Number of bytes read from this memory +system.physmem.bytes_read::total 28940032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 906816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 73984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 980800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7895360 # Number of bytes written to this memory +system.physmem.bytes_written::total 7895360 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 383103 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1156 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 12341 # Number of read requests responded to by this memory +system.physmem.num_reads::total 452188 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123365 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123365 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 476599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12886327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1393199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 38884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 415111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15210119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 476599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 38884 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 515483 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4149593 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4149593 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4149593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 476599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12886327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1393199 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 38884 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 415111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19359713 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 345291 # number of replacements +system.l2c.tagsinuse 65280.360301 # Cycle average of tags in use +system.l2c.total_refs 2575351 # Total number of references to valid blocks. +system.l2c.sampled_refs 410382 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.275497 # Average number of references to valid blocks. +system.l2c.warmup_cycle 6143524000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 53635.672684 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5378.326569 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 6042.958234 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 144.667579 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 78.735234 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.818415 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.082067 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.092208 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.002207 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.001201 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996099 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 798441 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 696934 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 292090 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 99595 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1887060 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 812223 # number of Writeback hits +system.l2c.Writeback_hits::total 812223 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 397 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 566 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 46 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 29 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 56 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 168538 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 13567 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 182105 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 970913 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 949286 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 107670 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 52634 # number of demand (read+write) hits -system.l2c.demand_hits::total 2080503 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 970913 # number of overall hits -system.l2c.overall_hits::cpu0.data 949286 # number of overall hits -system.l2c.overall_hits::cpu1.inst 107670 # number of overall hits -system.l2c.overall_hits::cpu1.data 52634 # number of overall hits -system.l2c.overall_hits::total 2080503 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13744 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 272909 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1606 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 887 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289146 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2478 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 531 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3009 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 43 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 77 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 120 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114968 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7955 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122923 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13744 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 387877 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1606 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8842 # number of demand (read+write) misses -system.l2c.demand_misses::total 412069 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13744 # number of overall misses -system.l2c.overall_misses::cpu0.data 387877 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1606 # number of overall misses -system.l2c.overall_misses::cpu1.data 8842 # number of overall misses -system.l2c.overall_misses::total 412069 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 731783998 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 14210594000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 85626000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 48439997 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 15076443995 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 2486000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1250500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 3736500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 522000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 156500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 678500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6190320497 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 441967499 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6632287996 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 731783998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 20400914497 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 85626000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 490407496 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21708731991 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 731783998 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 20400914497 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 85626000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 490407496 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21708731991 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 984657 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1053657 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 109276 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 39954 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2187544 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 832636 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 832636 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2662 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 585 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3247 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 70 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 106 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 176 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 283506 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 21522 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 305028 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 984657 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1337163 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 109276 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 61476 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2492572 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 984657 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1337163 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 109276 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 61476 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2492572 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.013958 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.259011 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.014697 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.022201 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.132178 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.930879 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.907692 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.926702 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.614286 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.726415 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.681818 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.405522 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.369622 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.402989 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.013958 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.290075 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.014697 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.143828 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.165319 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.013958 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.290075 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.014697 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.143828 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.165319 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53243.888097 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52070.814814 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53316.313823 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 54611.045096 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52141.285008 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1003.228410 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2354.990584 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1241.774676 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12139.534884 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2032.467532 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 5654.166667 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53843.856525 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 55558.453677 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53954.817211 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 53243.888097 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52596.350124 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 53316.313823 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 55463.412803 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52682.274063 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 53243.888097 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52596.350124 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 53316.313823 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 55463.412803 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52682.274063 # average overall miss latency +system.l2c.SCUpgradeReq_hits::total 75 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 135544 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 39704 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 175248 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 798441 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 832478 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 292090 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 139299 # number of demand (read+write) hits +system.l2c.demand_hits::total 2062308 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 798441 # number of overall hits +system.l2c.overall_hits::cpu0.data 832478 # number of overall hits +system.l2c.overall_hits::cpu1.inst 292090 # number of overall hits +system.l2c.overall_hits::cpu1.data 139299 # number of overall hits +system.l2c.overall_hits::total 2062308 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 14171 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 272326 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1173 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1502 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289172 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2767 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1411 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4178 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 606 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 630 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1236 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 111402 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 10975 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 122377 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 14171 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 383728 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1173 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 12477 # number of demand (read+write) misses +system.l2c.demand_misses::total 411549 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 14171 # number of overall misses +system.l2c.overall_misses::cpu0.data 383728 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1173 # number of overall misses +system.l2c.overall_misses::cpu1.data 12477 # number of overall misses +system.l2c.overall_misses::total 411549 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 755985500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 14184372500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 62331000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 81509998 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 15084198998 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1749500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 16214497 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 17963997 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2002500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 367000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2369500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6034072500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 609639000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6643711500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 755985500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 20218445000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 62331000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 691148998 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21727910498 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 755985500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 20218445000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 62331000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 691148998 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21727910498 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 812612 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 969260 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 293263 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 101097 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2176232 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 812223 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 812223 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2936 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1808 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4744 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 652 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 659 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1311 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 246946 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 50679 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 297625 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 812612 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1216206 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 293263 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 151776 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2473857 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 812612 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1216206 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 293263 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 151776 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2473857 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.017439 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.280963 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.004000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.014857 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.132877 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942439 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.780420 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.880691 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.929448 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.955994 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.942792 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.451119 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.216559 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.411178 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.017439 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.315512 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.082207 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.166359 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.017439 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.315512 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.082207 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.166359 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53347.364336 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52086.001704 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53138.107417 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 54267.641811 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52163.414847 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 632.273220 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 11491.493267 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 4299.664193 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3304.455446 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 582.539683 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1917.071197 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 54164.848926 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 55547.972665 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 54288.890069 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 53347.364336 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52689.522266 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 53138.107417 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 55393.844514 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52795.439906 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 53347.364336 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52689.522266 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 53138.107417 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 55393.844514 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52795.439906 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -221,8 +221,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 82314 # number of writebacks -system.l2c.writebacks::total 82314 # number of writebacks +system.l2c.writebacks::writebacks 81845 # number of writebacks +system.l2c.writebacks::total 81845 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 17 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits @@ -232,111 +232,111 @@ system.l2c.demand_mshr_hits::total 18 # nu system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 13743 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 272909 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1589 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 887 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 289128 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2478 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 531 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3009 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 43 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 77 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 120 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 114968 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 7955 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 122923 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13743 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 387877 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1589 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 8842 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 412051 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13743 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 387877 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1589 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 8842 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 412051 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 563800998 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10943970500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 65437000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 37722500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 11610930998 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 99235500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 21259000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 120494500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1720000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 3080000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 4800000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4801585997 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 345787499 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5147373496 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 563800998 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 15745556497 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 65437000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 383509999 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16758304494 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 563800998 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 15745556497 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 65437000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 383509999 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16758304494 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1363601000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 23660000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1387261000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1941911500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 514448500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2456360000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3305512500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 538108500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 3843621000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013957 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.259011 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014541 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.022201 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.132170 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.930879 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.907692 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.926702 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.614286 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.726415 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.681818 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.405522 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.369622 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.402989 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013957 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.290075 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014541 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.143828 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.165312 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013957 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.290075 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014541 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.143828 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.165312 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41024.594193 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40101.171086 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41181.246067 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42528.184893 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40158.445388 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40046.610169 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40035.781544 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40044.699236 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41764.543151 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 43467.944563 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41874.779301 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41024.594193 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40594.199958 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41181.246067 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43373.671002 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40670.461894 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41024.594193 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40594.199958 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41181.246067 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43373.671002 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40670.461894 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 14170 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 272326 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1156 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1502 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 289154 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2767 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1411 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4178 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 606 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 630 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1236 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 111402 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 10975 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 122377 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 14170 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 383728 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1156 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 12477 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 411531 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 14170 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 383728 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1156 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 12477 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 411531 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 582633500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10923275000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 47336500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 63194498 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 11616439498 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 110819971 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 56511497 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 167331468 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 24296484 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 25202500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 49498984 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4677812000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 476518500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5154330500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 582633500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 15601087000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 47336500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 539712998 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16770769998 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 582633500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 15601087000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 47336500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 539712998 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16770769998 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1358127000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28700000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1386827000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2042144000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 647379000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2689523000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3400271000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 676079000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4076350000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.017438 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.280963 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.003942 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.014857 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.132869 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942439 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.780420 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.880691 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.929448 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.955994 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.942792 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.451119 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.216559 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.411178 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017438 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.315512 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.003942 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.082207 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.166352 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017438 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.315512 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.003942 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.082207 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.166352 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41117.395907 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40111.025021 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40948.529412 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42073.567244 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40173.884843 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40050.585833 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40050.671155 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40050.614648 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40093.207921 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40003.968254 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40047.721683 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41990.377193 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 43418.542141 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 42118.457717 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41117.395907 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40656.629175 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40948.529412 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43256.632043 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40752.142604 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41117.395907 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40656.629175 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40948.529412 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43256.632043 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40752.142604 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -347,39 +347,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41696 # number of replacements -system.iocache.tagsinuse 0.468369 # Cycle average of tags in use +system.iocache.replacements 41697 # number of replacements +system.iocache.tagsinuse 0.492574 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1712293009000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.468369 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.029273 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.029273 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses -system.iocache.ReadReq_misses::total 176 # number of ReadReq misses +system.iocache.warmup_cycle 1709348959000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.492574 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.030786 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.030786 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses +system.iocache.ReadReq_misses::total 177 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses -system.iocache.demand_misses::total 41728 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses -system.iocache.overall_misses::total 41728 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21012998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21012998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 11487114806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11487114806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 11508127804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11508127804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 11508127804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11508127804 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses +system.iocache.demand_misses::total 41729 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses +system.iocache.overall_misses::total 41729 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21127998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21127998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 11486516806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11486516806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 11507644804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11507644804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 11507644804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11507644804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -388,40 +388,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119392.034091 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119392.034091 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276451.550010 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 276451.550010 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 275789.105732 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 275789.105732 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 275789.105732 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 275789.105732 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 201643000 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119367.220339 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119367.220339 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276437.158404 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 276437.158404 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 275770.921997 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 275770.921997 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 275770.921997 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 275770.921997 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 200533 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 24752 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 24673 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8146.533613 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.127629 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11860000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11860000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9326257976 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9326257976 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9338117976 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9338117976 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9338117976 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9338117976 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11923998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11923998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9325812806 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9325812806 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9337736804 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9337736804 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9337736804 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9337736804 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -430,14 +430,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67386.363636 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67386.363636 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224447.871968 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 224447.871968 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223785.419287 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 223785.419287 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223785.419287 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 223785.419287 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67367.220339 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67367.220339 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224437.158404 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 224437.158404 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223770.921997 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 223770.921997 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223770.921997 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 223770.921997 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -455,22 +455,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9377828 # DTB read hits -system.cpu0.dtb.read_misses 33360 # DTB read misses -system.cpu0.dtb.read_acv 521 # DTB read access violations -system.cpu0.dtb.read_accesses 633373 # DTB read accesses -system.cpu0.dtb.write_hits 6221809 # DTB write hits -system.cpu0.dtb.write_misses 7167 # DTB write misses -system.cpu0.dtb.write_acv 341 # DTB write access violations -system.cpu0.dtb.write_accesses 216042 # DTB write accesses -system.cpu0.dtb.data_hits 15599637 # DTB hits -system.cpu0.dtb.data_misses 40527 # DTB misses -system.cpu0.dtb.data_acv 862 # DTB access violations -system.cpu0.dtb.data_accesses 849415 # DTB accesses -system.cpu0.itb.fetch_hits 1073423 # ITB hits -system.cpu0.itb.fetch_misses 26403 # ITB misses -system.cpu0.itb.fetch_acv 1051 # ITB acv -system.cpu0.itb.fetch_accesses 1099826 # ITB accesses +system.cpu0.dtb.read_hits 8304100 # DTB read hits +system.cpu0.dtb.read_misses 28307 # DTB read misses +system.cpu0.dtb.read_acv 549 # DTB read access violations +system.cpu0.dtb.read_accesses 542239 # DTB read accesses +system.cpu0.dtb.write_hits 5411904 # DTB write hits +system.cpu0.dtb.write_misses 5987 # DTB write misses +system.cpu0.dtb.write_acv 347 # DTB write access violations +system.cpu0.dtb.write_accesses 182798 # DTB write accesses +system.cpu0.dtb.data_hits 13716004 # DTB hits +system.cpu0.dtb.data_misses 34294 # DTB misses +system.cpu0.dtb.data_acv 896 # DTB access violations +system.cpu0.dtb.data_accesses 725037 # DTB accesses +system.cpu0.itb.fetch_hits 908718 # ITB hits +system.cpu0.itb.fetch_misses 19910 # ITB misses +system.cpu0.itb.fetch_acv 927 # ITB acv +system.cpu0.itb.fetch_accesses 928628 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -483,277 +483,277 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 120667689 # number of cpu cycles simulated +system.cpu0.numCycles 102599658 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 13362893 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 11185412 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 402804 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 9622475 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5627170 # Number of BTB hits +system.cpu0.BPredUnit.lookups 11825647 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 9917652 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 342692 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 8240217 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5044056 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 884758 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 37477 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 30221705 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 67571030 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 13362893 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6511928 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12734942 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1928304 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 41309111 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 28714 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 205220 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 305503 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8304621 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 277902 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 86063714 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.785128 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.113854 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 768623 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 31919 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 23566044 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 60418395 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 11825647 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5812679 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11434253 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1624928 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 35275815 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31363 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 170412 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 309547 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 160 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7444211 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 224420 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 71849758 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.840899 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.174060 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 73328772 85.20% 85.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 837915 0.97% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1666262 1.94% 88.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 768356 0.89% 89.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2658731 3.09% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 585060 0.68% 92.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 622966 0.72% 93.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 967713 1.12% 94.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4627939 5.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 60415505 84.09% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 744936 1.04% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1526054 2.12% 87.25% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 669496 0.93% 88.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2482176 3.45% 91.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 513952 0.72% 92.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 559997 0.78% 93.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 746719 1.04% 94.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4190923 5.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 86063714 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.110741 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.559976 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 31149327 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 41124977 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 11584676 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 985581 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1219152 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 571369 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 39493 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 66407813 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 120728 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1219152 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 32233219 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 16872016 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 20344281 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10880828 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4514216 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 62880643 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6942 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 700700 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1661735 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 42005938 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 76144064 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 75702119 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 441945 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36517182 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 5488748 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1574453 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 239002 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12018911 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9888186 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6523659 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1201517 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 824194 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 55665948 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1995313 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 54317533 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 112244 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6696159 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3338542 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1358752 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 86063714 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.631132 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.280124 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 71849758 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.115260 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.588875 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 24832568 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 34702410 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10423010 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 862232 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1029537 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 502827 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 32976 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 59359454 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 95150 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1029537 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 25748676 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 14416729 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17004300 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9792924 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3857590 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 56337606 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6610 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 598180 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1362975 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 37819724 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 68629747 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 68286150 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 343597 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33121112 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4698612 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1343902 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 201432 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10333121 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8734327 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5677673 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1105299 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 704273 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 50005822 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1695696 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 48865145 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 103608 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5731519 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2860845 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1151664 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 71849758 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.680102 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.326568 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 61486843 71.44% 71.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 11432526 13.28% 84.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 5063556 5.88% 90.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3287093 3.82% 94.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2517985 2.93% 97.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1255115 1.46% 98.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 648079 0.75% 99.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 319509 0.37% 99.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53008 0.06% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 50068220 69.68% 69.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9955153 13.86% 83.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4454682 6.20% 89.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2911875 4.05% 93.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2358569 3.28% 97.08% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1157257 1.61% 98.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 610758 0.85% 99.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 286058 0.40% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 47186 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 86063714 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 71849758 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 73354 10.53% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 330176 47.38% 57.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 293358 42.10% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 80509 12.84% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 294043 46.91% 59.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 252280 40.25% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3296 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 37287239 68.65% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 60152 0.11% 68.76% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.76% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15662 0.03% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1646 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9781142 18.01% 86.80% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6293081 11.59% 98.39% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 875315 1.61% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2557 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 33918404 69.41% 69.42% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 54116 0.11% 69.53% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.53% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 12070 0.02% 69.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.56% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8648673 17.70% 87.25% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5478002 11.21% 98.47% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 750056 1.53% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 54317533 # Type of FU issued -system.cpu0.iq.rate 0.450141 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 696889 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.012830 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 194880881 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 64065914 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 53156794 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 627031 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 303977 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 294706 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 54682626 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 328500 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 571695 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 48865145 # Type of FU issued +system.cpu0.iq.rate 0.476270 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 626833 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.012828 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 169818867 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 57206555 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 47890608 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 491622 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 238128 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 232129 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 49232078 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 257343 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 523556 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1271953 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2828 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12731 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 517788 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1075506 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2442 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 11895 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 454594 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18545 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 107284 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18421 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 86028 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1219152 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 12163042 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 861940 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 61112544 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 659342 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9888186 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6523659 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1757966 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 617572 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 9941 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12731 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 210191 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 389993 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 600184 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 53834482 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9436308 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 483050 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1029537 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10326104 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 769928 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 54791843 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 549393 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8734327 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5677673 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1493453 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 559696 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5669 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 11895 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 183351 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 329192 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 512543 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 48451300 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8354077 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 413845 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3451283 # number of nop insts executed -system.cpu0.iew.exec_refs 15679571 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8587439 # Number of branches executed -system.cpu0.iew.exec_stores 6243263 # Number of stores executed -system.cpu0.iew.exec_rate 0.446138 # Inst execution rate -system.cpu0.iew.wb_sent 53546468 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 53451500 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26356174 # num instructions producing a value -system.cpu0.iew.wb_consumers 35593959 # num instructions consuming a value +system.cpu0.iew.exec_nop 3090325 # number of nop insts executed +system.cpu0.iew.exec_refs 13784796 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7754310 # Number of branches executed +system.cpu0.iew.exec_stores 5430719 # Number of stores executed +system.cpu0.iew.exec_rate 0.472236 # Inst execution rate +system.cpu0.iew.wb_sent 48208648 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 48122737 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24107105 # num instructions producing a value +system.cpu0.iew.wb_consumers 32426814 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.442964 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.740468 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.469034 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.743431 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 7303960 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 636561 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 562819 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 84844562 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.633202 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.547709 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6216029 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 544032 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 479899 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 70820221 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.684637 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.594318 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 64556270 76.09% 76.09% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8510919 10.03% 86.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4635841 5.46% 91.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2494817 2.94% 94.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1390539 1.64% 96.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 576056 0.68% 96.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 484846 0.57% 97.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 456978 0.54% 97.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1738296 2.05% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 52470926 74.09% 74.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7676401 10.84% 84.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4235846 5.98% 90.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2227139 3.14% 94.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1283042 1.81% 95.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 528527 0.75% 96.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 441494 0.62% 97.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 421867 0.60% 97.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1534979 2.17% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 84844562 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 53723778 # Number of instructions committed -system.cpu0.commit.committedOps 53723778 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 70820221 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 48486178 # Number of instructions committed +system.cpu0.commit.committedOps 48486178 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14622104 # Number of memory references committed -system.cpu0.commit.loads 8616233 # Number of loads committed -system.cpu0.commit.membars 216543 # Number of memory barriers committed -system.cpu0.commit.branches 8113778 # Number of branches committed -system.cpu0.commit.fp_insts 292474 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 49705714 # Number of committed integer instructions. -system.cpu0.commit.function_calls 703203 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1738296 # number cycles where commit BW limit reached +system.cpu0.commit.refs 12881900 # Number of memory references committed +system.cpu0.commit.loads 7658821 # Number of loads committed +system.cpu0.commit.membars 183715 # Number of memory barriers committed +system.cpu0.commit.branches 7346956 # Number of branches committed +system.cpu0.commit.fp_insts 229898 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 44900899 # Number of committed integer instructions. +system.cpu0.commit.function_calls 613493 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1534979 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 143945633 # The number of ROB reads -system.cpu0.rob.rob_writes 123274808 # The number of ROB writes -system.cpu0.timesIdled 1363780 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 34603975 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3686422279 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 50608732 # Number of Instructions Simulated -system.cpu0.committedOps 50608732 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 50608732 # Number of Instructions Simulated -system.cpu0.cpi 2.384325 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.384325 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.419406 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.419406 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 70600527 # number of integer regfile reads -system.cpu0.int_regfile_writes 38607300 # number of integer regfile writes -system.cpu0.fp_regfile_reads 144193 # number of floating regfile reads -system.cpu0.fp_regfile_writes 146198 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1863622 # number of misc regfile reads -system.cpu0.misc_regfile_writes 886886 # number of misc regfile writes +system.cpu0.rob.rob_reads 123809295 # The number of ROB reads +system.cpu0.rob.rob_writes 110434143 # The number of ROB writes +system.cpu0.timesIdled 1033297 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 30749900 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3702120338 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 45684021 # Number of Instructions Simulated +system.cpu0.committedOps 45684021 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 45684021 # Number of Instructions Simulated +system.cpu0.cpi 2.245854 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.245854 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.445265 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.445265 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 63838240 # number of integer regfile reads +system.cpu0.int_regfile_writes 34928793 # number of integer regfile writes +system.cpu0.fp_regfile_reads 112215 # number of floating regfile reads +system.cpu0.fp_regfile_writes 113746 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1561574 # number of misc regfile reads +system.cpu0.misc_regfile_writes 757779 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -785,245 +785,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 984085 # number of replacements -system.cpu0.icache.tagsinuse 509.993322 # Cycle average of tags in use -system.cpu0.icache.total_refs 7264923 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 984594 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.378598 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23948219000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.993322 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996081 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996081 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 7264923 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7264923 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7264923 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7264923 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7264923 # number of overall hits -system.cpu0.icache.overall_hits::total 7264923 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1039697 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1039697 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1039697 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1039697 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1039697 # number of overall misses -system.cpu0.icache.overall_misses::total 1039697 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16868456488 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 16868456488 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 16868456488 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 16868456488 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 16868456488 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 16868456488 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8304620 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8304620 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8304620 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8304620 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8304620 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8304620 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125195 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.125195 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125195 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.125195 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125195 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.125195 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16224.396616 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 16224.396616 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16224.396616 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 16224.396616 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16224.396616 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 16224.396616 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1612994 # number of cycles access was blocked +system.cpu0.icache.replacements 812060 # number of replacements +system.cpu0.icache.tagsinuse 510.054551 # Cycle average of tags in use +system.cpu0.icache.total_refs 6590229 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 812572 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.110332 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23200943000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.054551 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996200 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996200 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6590229 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6590229 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6590229 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6590229 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6590229 # number of overall hits +system.cpu0.icache.overall_hits::total 6590229 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 853981 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 853981 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 853981 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 853981 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 853981 # number of overall misses +system.cpu0.icache.overall_misses::total 853981 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11857055495 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11857055495 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11857055495 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11857055495 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11857055495 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11857055495 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7444210 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7444210 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7444210 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7444210 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7444210 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7444210 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.114717 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.114717 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.114717 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.114717 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.114717 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.114717 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13884.448828 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13884.448828 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13884.448828 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13884.448828 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13884.448828 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13884.448828 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2511 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 171 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 127 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 9432.713450 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.771654 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54925 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 54925 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 54925 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 54925 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 54925 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 54925 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 984772 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 984772 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 984772 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 984772 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 984772 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 984772 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13041683494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 13041683494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13041683494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 13041683494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13041683494 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 13041683494 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.118581 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.118581 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.118581 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.118581 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.118581 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.118581 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13243.353278 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13243.353278 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13243.353278 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13243.353278 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13243.353278 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13243.353278 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41272 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 41272 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 41272 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 41272 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 41272 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 41272 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 812709 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 812709 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 812709 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 812709 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 812709 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 812709 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9799988995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9799988995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9799988995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9799988995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9799988995 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9799988995 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.109173 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.109173 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.109173 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.109173 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.109173 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.109173 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12058.423119 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12058.423119 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12058.423119 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12058.423119 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12058.423119 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12058.423119 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1341345 # number of replacements -system.cpu0.dcache.tagsinuse 506.494858 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11161433 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1341857 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.317900 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 23750000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 506.494858 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.989248 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.989248 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6822568 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6822568 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3942957 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3942957 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 181355 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 181355 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208341 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 208341 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10765525 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10765525 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10765525 # number of overall hits -system.cpu0.dcache.overall_hits::total 10765525 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1719034 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1719034 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1839372 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1839372 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22429 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22429 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 711 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 711 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3558406 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3558406 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3558406 # number of overall misses -system.cpu0.dcache.overall_misses::total 3558406 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 46470872000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 46470872000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71479264510 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 71479264510 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 406558000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 406558000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 6746500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 6746500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 117950136510 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 117950136510 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 117950136510 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 117950136510 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8541602 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8541602 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5782329 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5782329 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 203784 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203784 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 209052 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 209052 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14323931 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14323931 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14323931 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14323931 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.201254 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.201254 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.318102 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.318102 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110063 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110063 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003401 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003401 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248424 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248424 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248424 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248424 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27033.131398 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27033.131398 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38860.689686 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38860.689686 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18126.443444 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18126.443444 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9488.748242 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9488.748242 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33146.902436 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33146.902436 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33146.902436 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33146.902436 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 754476476 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 245500 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 70452 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10709.085278 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 27277.777778 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 1218511 # number of replacements +system.cpu0.dcache.tagsinuse 505.616339 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9815926 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1218945 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.052805 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 23286000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 505.616339 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.987532 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.987532 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6063177 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6063177 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3417347 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3417347 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151987 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 151987 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 174443 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 174443 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9480524 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9480524 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9480524 # number of overall hits +system.cpu0.dcache.overall_hits::total 9480524 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1492446 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1492446 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1612731 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1612731 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19429 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19429 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4062 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 4062 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3105177 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3105177 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3105177 # number of overall misses +system.cpu0.dcache.overall_misses::total 3105177 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34499425000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 34499425000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 55944257946 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 55944257946 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 264930500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 264930500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 47614500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 47614500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 90443682946 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 90443682946 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 90443682946 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 90443682946 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7555623 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7555623 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5030078 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5030078 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 171416 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 171416 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 178505 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 178505 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12585701 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12585701 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12585701 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12585701 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197528 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.197528 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320617 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.320617 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113344 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113344 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.022756 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.022756 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.246723 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.246723 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.246723 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.246723 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23116.028989 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 23116.028989 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34689.144033 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 34689.144033 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13635.827886 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13635.827886 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11721.935007 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11721.935007 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 29126.739940 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 29126.739940 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29126.739940 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 29126.739940 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1403245 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 435 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 52795 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.579127 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 62.142857 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 796119 # number of writebacks -system.cpu0.dcache.writebacks::total 796119 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 675047 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 675047 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1552745 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1552745 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5057 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5057 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2227792 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2227792 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2227792 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2227792 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1043987 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1043987 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 286627 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 286627 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17372 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17372 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 711 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 711 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1330614 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1330614 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1330614 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1330614 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27461612037 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27461612037 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9493856805 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9493856805 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 250184001 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 250184001 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4525001 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4525001 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 36955468842 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 36955468842 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 36955468842 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 36955468842 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1456541500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1456541500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2062903998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2062903998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3519445498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3519445498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122224 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122224 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049569 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049569 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085247 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085247 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003401 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003401 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092894 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092894 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092894 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092894 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26304.553636 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26304.553636 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33122.688389 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33122.688389 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14401.565796 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14401.565796 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6364.277075 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6364.277075 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27773.245165 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27773.245165 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27773.245165 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 27773.245165 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 710192 # number of writebacks +system.cpu0.dcache.writebacks::total 710192 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 524907 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 524907 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1358576 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1358576 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4179 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4179 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1883483 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1883483 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1883483 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1883483 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 967539 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 967539 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 254155 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 254155 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15250 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15250 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4062 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 4062 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1221694 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1221694 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1221694 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1221694 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23357450000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23357450000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8081474275 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8081474275 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 163906000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 163906000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 39490500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 39490500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31438924275 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 31438924275 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31438924275 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 31438924275 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1451861000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1451861000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2167064498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2167064498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3618925498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3618925498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128055 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128055 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050527 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050527 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088965 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088965 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.022756 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.022756 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097070 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097070 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097070 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097070 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24141.094054 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24141.094054 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31797.423915 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31797.423915 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10747.934426 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10747.934426 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 9721.935007 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 9721.935007 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25733.877939 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25733.877939 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25733.877939 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25733.877939 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1035,22 +1035,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1298594 # DTB read hits -system.cpu1.dtb.read_misses 11503 # DTB read misses -system.cpu1.dtb.read_acv 6 # DTB read access violations -system.cpu1.dtb.read_accesses 332098 # DTB read accesses -system.cpu1.dtb.write_hits 765153 # DTB write hits -system.cpu1.dtb.write_misses 2957 # DTB write misses -system.cpu1.dtb.write_acv 47 # DTB write access violations -system.cpu1.dtb.write_accesses 125840 # DTB write accesses -system.cpu1.dtb.data_hits 2063747 # DTB hits -system.cpu1.dtb.data_misses 14460 # DTB misses -system.cpu1.dtb.data_acv 53 # DTB access violations -system.cpu1.dtb.data_accesses 457938 # DTB accesses -system.cpu1.itb.fetch_hits 372513 # ITB hits -system.cpu1.itb.fetch_misses 8563 # ITB misses -system.cpu1.itb.fetch_acv 155 # ITB acv -system.cpu1.itb.fetch_accesses 381076 # ITB accesses +system.cpu1.dtb.read_hits 2472786 # DTB read hits +system.cpu1.dtb.read_misses 14686 # DTB read misses +system.cpu1.dtb.read_acv 33 # DTB read access violations +system.cpu1.dtb.read_accesses 413814 # DTB read accesses +system.cpu1.dtb.write_hits 1645990 # DTB write hits +system.cpu1.dtb.write_misses 3399 # DTB write misses +system.cpu1.dtb.write_acv 61 # DTB write access violations +system.cpu1.dtb.write_accesses 158815 # DTB write accesses +system.cpu1.dtb.data_hits 4118776 # DTB hits +system.cpu1.dtb.data_misses 18085 # DTB misses +system.cpu1.dtb.data_acv 94 # DTB access violations +system.cpu1.dtb.data_accesses 572629 # DTB accesses +system.cpu1.itb.fetch_hits 546471 # ITB hits +system.cpu1.itb.fetch_misses 10636 # ITB misses +system.cpu1.itb.fetch_acv 251 # ITB acv +system.cpu1.itb.fetch_accesses 557107 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1063,516 +1063,516 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 10640951 # number of cpu cycles simulated +system.cpu1.numCycles 20144234 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 1701905 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 1402674 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 62577 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 862370 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 552113 # Number of BTB hits +system.cpu1.BPredUnit.lookups 3332472 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 2756183 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 108633 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 2168857 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 1160511 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 115027 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 5500 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 3435420 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 8139615 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 1701905 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 667140 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1472350 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 326710 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 4537469 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 24627 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 73138 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 47601 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1039363 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 39149 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 9806707 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.830005 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.196976 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 228547 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 10150 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 7838813 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 15883595 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3332472 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1389058 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2861385 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 534677 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 7961253 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 27792 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 84864 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 61219 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 2 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1925840 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 71197 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 19177134 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.828257 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.199800 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 8334357 84.99% 84.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 78230 0.80% 85.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 173812 1.77% 87.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 130927 1.34% 88.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 215769 2.20% 91.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 90418 0.92% 92.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 98526 1.00% 93.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 62686 0.64% 93.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 621982 6.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 16315749 85.08% 85.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 188313 0.98% 86.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 313367 1.63% 87.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 233008 1.22% 88.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 393584 2.05% 90.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 151826 0.79% 91.75% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 167771 0.87% 92.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 278696 1.45% 94.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1134820 5.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 9806707 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.159939 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.764933 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 3510066 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 4639401 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1367694 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 78184 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 211361 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 75357 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 4832 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 7943726 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 14591 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 211361 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 3646380 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 524692 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 3638231 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1300485 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 485556 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 7343826 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 139 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 57550 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 136110 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 4921664 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 8958013 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 8905584 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52429 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 3978815 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 942849 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 306458 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 22346 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1365387 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1395502 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 827989 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 138090 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 96967 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 6484639 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 311488 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 6173957 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 24546 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1207593 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 679802 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 236614 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 9806707 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.629565 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.304884 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 19177134 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.165431 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.788493 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 7716271 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 8310209 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2661595 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 156637 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 332421 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 147192 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 9531 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 15577857 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 28018 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 332421 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 7986115 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 672083 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6791538 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2542197 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 852778 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 14454091 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 131 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 86206 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 218054 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 9478411 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 17286766 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 17086477 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 200289 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 8045295 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1433108 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 570111 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 60569 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2590157 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2624799 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1738404 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 257229 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 149585 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 12667252 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 630653 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 12308685 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 34992 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1859186 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 963032 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 447479 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 19177134 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.641842 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.313805 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 7075152 72.15% 72.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1257607 12.82% 84.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 548751 5.60% 90.57% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 366543 3.74% 94.30% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 274418 2.80% 97.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 146525 1.49% 98.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 78833 0.80% 99.40% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 55100 0.56% 99.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 3778 0.04% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 13743416 71.67% 71.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2506419 13.07% 84.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1066336 5.56% 90.30% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 706714 3.69% 93.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 606260 3.16% 97.14% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 273557 1.43% 98.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 174545 0.91% 99.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 89739 0.47% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 10148 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 9806707 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 19177134 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2937 2.09% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 77829 55.26% 57.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 60078 42.66% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 4629 1.86% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 131937 52.95% 54.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 112626 45.20% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3992 0.06% 0.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 3816770 61.82% 61.89% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 10118 0.16% 62.05% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.05% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10095 0.16% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1996 0.03% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.24% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1354962 21.95% 84.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 784960 12.71% 96.91% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 191064 3.09% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 7659302 62.23% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 19564 0.16% 62.42% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 14781 0.12% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2596890 21.10% 83.66% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1675725 13.61% 97.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 335297 2.72% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 6173957 # Type of FU issued -system.cpu1.iq.rate 0.580207 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 140844 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.022813 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 22242262 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 7966601 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 5994284 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 77749 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 38725 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 37333 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 6270612 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 40197 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 68178 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 12308685 # Type of FU issued +system.cpu1.iq.rate 0.611028 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 249192 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020245 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 43789272 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 15018387 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 11932725 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 289415 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 141077 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 136872 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 12402102 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 151024 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 115183 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 253497 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 450 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1694 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 109535 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 382493 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 680 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 2469 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 155910 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 346 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 8387 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 398 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 20099 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 211361 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 294243 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 17071 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 7057887 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 102198 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1395502 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 827989 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 289869 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 6102 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3806 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1694 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 30581 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 71547 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 102128 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 6103512 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1313696 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 70445 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 332421 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 409059 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 59053 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 13963733 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 192284 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2624799 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1738404 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 567278 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 49311 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2791 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 2469 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 54746 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 126604 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 181350 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 12183266 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2497630 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 125418 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 261760 # number of nop insts executed -system.cpu1.iew.exec_refs 2085126 # number of memory reference insts executed -system.cpu1.iew.exec_branches 894247 # Number of branches executed -system.cpu1.iew.exec_stores 771430 # Number of stores executed -system.cpu1.iew.exec_rate 0.573587 # Inst execution rate -system.cpu1.iew.wb_sent 6061366 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 6031617 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 2917806 # num instructions producing a value -system.cpu1.iew.wb_consumers 4086073 # num instructions consuming a value +system.cpu1.iew.exec_nop 665828 # number of nop insts executed +system.cpu1.iew.exec_refs 4154589 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1827055 # Number of branches executed +system.cpu1.iew.exec_stores 1656959 # Number of stores executed +system.cpu1.iew.exec_rate 0.604802 # Inst execution rate +system.cpu1.iew.wb_sent 12107744 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 12069597 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5640555 # num instructions producing a value +system.cpu1.iew.wb_consumers 7931807 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.566831 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.714086 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.599159 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.711131 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1232464 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 74874 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 96289 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 9595346 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.599743 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.518608 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1943114 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 183174 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 170211 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 18844713 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.633421 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.575988 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 7360615 76.71% 76.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1091727 11.38% 88.09% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 382276 3.98% 92.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 236221 2.46% 94.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 149500 1.56% 96.09% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 68368 0.71% 96.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 77096 0.80% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 48958 0.51% 98.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 180585 1.88% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 14387001 76.35% 76.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2066578 10.97% 87.31% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 777942 4.13% 91.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 478446 2.54% 93.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 347277 1.84% 95.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 135394 0.72% 96.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 132721 0.70% 97.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 138400 0.73% 97.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 380954 2.02% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 9595346 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 5754744 # Number of instructions committed -system.cpu1.commit.committedOps 5754744 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 18844713 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 11936636 # Number of instructions committed +system.cpu1.commit.committedOps 11936636 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 1860459 # Number of memory references committed -system.cpu1.commit.loads 1142005 # Number of loads committed -system.cpu1.commit.membars 20259 # Number of memory barriers committed -system.cpu1.commit.branches 814036 # Number of branches committed -system.cpu1.commit.fp_insts 36051 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 5384897 # Number of committed integer instructions. -system.cpu1.commit.function_calls 87726 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 180585 # number cycles where commit BW limit reached +system.cpu1.commit.refs 3824800 # Number of memory references committed +system.cpu1.commit.loads 2242306 # Number of loads committed +system.cpu1.commit.membars 59908 # Number of memory barriers committed +system.cpu1.commit.branches 1711003 # Number of branches committed +system.cpu1.commit.fp_insts 135276 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 11053668 # Number of committed integer instructions. +system.cpu1.commit.function_calls 186526 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 380954 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 16310969 # The number of ROB reads -system.cpu1.rob.rob_writes 14184459 # The number of ROB writes -system.cpu1.timesIdled 82580 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 834244 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3796004491 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 5534760 # Number of Instructions Simulated -system.cpu1.committedOps 5534760 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 5534760 # Number of Instructions Simulated -system.cpu1.cpi 1.922568 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.922568 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.520138 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.520138 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 7951221 # number of integer regfile reads -system.cpu1.int_regfile_writes 4345022 # number of integer regfile writes -system.cpu1.fp_regfile_reads 24272 # number of floating regfile reads -system.cpu1.fp_regfile_writes 22982 # number of floating regfile writes -system.cpu1.misc_regfile_reads 283160 # number of misc regfile reads -system.cpu1.misc_regfile_writes 134137 # number of misc regfile writes -system.cpu1.icache.replacements 108736 # number of replacements -system.cpu1.icache.tagsinuse 452.848051 # Cycle average of tags in use -system.cpu1.icache.total_refs 924017 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 109246 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 8.458131 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1880838222000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 452.848051 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.884469 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.884469 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 924017 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 924017 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 924017 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 924017 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 924017 # number of overall hits -system.cpu1.icache.overall_hits::total 924017 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 115346 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 115346 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 115346 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 115346 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 115346 # number of overall misses -system.cpu1.icache.overall_misses::total 115346 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1915256999 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1915256999 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1915256999 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1915256999 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1915256999 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1915256999 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1039363 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1039363 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1039363 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1039363 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1039363 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1039363 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.110978 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.110978 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.110978 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.110978 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.110978 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.110978 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16604.450948 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 16604.450948 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16604.450948 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 16604.450948 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16604.450948 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 16604.450948 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 222999 # number of cycles access was blocked +system.cpu1.rob.rob_reads 32234171 # The number of ROB reads +system.cpu1.rob.rob_writes 28090700 # The number of ROB writes +system.cpu1.timesIdled 170938 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 967100 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3785218747 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 11348024 # Number of Instructions Simulated +system.cpu1.committedOps 11348024 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 11348024 # Number of Instructions Simulated +system.cpu1.cpi 1.775131 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.775131 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.563339 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.563339 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 15713233 # number of integer regfile reads +system.cpu1.int_regfile_writes 8535659 # number of integer regfile writes +system.cpu1.fp_regfile_reads 74431 # number of floating regfile reads +system.cpu1.fp_regfile_writes 74222 # number of floating regfile writes +system.cpu1.misc_regfile_reads 667576 # number of misc regfile reads +system.cpu1.misc_regfile_writes 284444 # number of misc regfile writes +system.cpu1.icache.replacements 292722 # number of replacements +system.cpu1.icache.tagsinuse 471.494279 # Cycle average of tags in use +system.cpu1.icache.total_refs 1621349 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 293230 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.529274 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1876700215000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 471.494279 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.920887 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.920887 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1621349 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1621349 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1621349 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1621349 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1621349 # number of overall hits +system.cpu1.icache.overall_hits::total 1621349 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 304491 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 304491 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 304491 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 304491 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 304491 # number of overall misses +system.cpu1.icache.overall_misses::total 304491 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4065162500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4065162500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4065162500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4065162500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4065162500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4065162500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1925840 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1925840 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1925840 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1925840 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1925840 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1925840 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.158108 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.158108 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.158108 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.158108 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.158108 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.158108 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13350.681958 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13350.681958 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13350.681958 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13350.681958 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13350.681958 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13350.681958 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 203 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7433.300000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 8.826087 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6038 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 6038 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 6038 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 6038 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 6038 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 6038 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 109308 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 109308 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 109308 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 109308 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 109308 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 109308 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1491398999 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1491398999 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1491398999 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1491398999 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1491398999 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1491398999 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.105168 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.105168 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.105168 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13644.005919 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13644.005919 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13644.005919 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11170 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 11170 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 11170 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 11170 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 11170 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 11170 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 293321 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 293321 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 293321 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 293321 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 293321 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 293321 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3385018500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3385018500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3385018500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3385018500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3385018500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3385018500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.152308 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.152308 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.152308 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.152308 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.152308 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.152308 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11540.321013 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11540.321013 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11540.321013 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11540.321013 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11540.321013 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11540.321013 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 61811 # number of replacements -system.cpu1.dcache.tagsinuse 423.387508 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1665798 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 62157 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 26.799846 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1880297158000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 423.387508 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.826929 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.826929 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1100458 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1100458 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 541491 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 541491 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 16674 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 16674 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 14757 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 14757 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1641949 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1641949 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1641949 # number of overall hits -system.cpu1.dcache.overall_hits::total 1641949 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 110209 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 110209 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 156496 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 156496 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1520 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1520 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 666 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 666 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 266705 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 266705 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 266705 # number of overall misses -system.cpu1.dcache.overall_misses::total 266705 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2207117500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2207117500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6428377585 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 6428377585 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 25057000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 25057000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8004500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 8004500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8635495085 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8635495085 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8635495085 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8635495085 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1210667 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1210667 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 697987 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 697987 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 18194 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 18194 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 15423 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 15423 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1908654 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1908654 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1908654 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1908654 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.091032 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.091032 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.224210 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.224210 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.083544 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.083544 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.043182 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.043182 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.139735 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.139735 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.139735 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.139735 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20026.653903 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 20026.653903 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41076.945002 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41076.945002 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16484.868421 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16484.868421 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12018.768769 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 12018.768769 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32378.452166 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 32378.452166 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32378.452166 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 32378.452166 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 48117991 # number of cycles access was blocked +system.cpu1.dcache.replacements 154238 # number of replacements +system.cpu1.dcache.tagsinuse 492.768701 # Cycle average of tags in use +system.cpu1.dcache.total_refs 3312022 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 154750 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 21.402404 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 38606824000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 492.768701 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.962439 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.962439 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2009764 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2009764 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1195197 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1195197 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47136 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 47136 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 45762 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 45762 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3204961 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3204961 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3204961 # number of overall hits +system.cpu1.dcache.overall_hits::total 3204961 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 288765 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 288765 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 330549 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 330549 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7490 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 7490 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 4284 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 4284 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 619314 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 619314 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 619314 # number of overall misses +system.cpu1.dcache.overall_misses::total 619314 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4275169500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4275169500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8473061608 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 8473061608 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77853000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 77853000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49370500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 49370500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12748231108 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12748231108 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12748231108 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12748231108 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2298529 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2298529 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1525746 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1525746 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 54626 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 54626 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 50046 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 50046 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3824275 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3824275 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3824275 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3824275 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.125630 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.125630 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.216647 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.216647 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137114 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137114 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085601 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.085601 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.161943 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.161943 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.161943 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.161943 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14805.012727 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14805.012727 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25633.299777 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 25633.299777 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10394.259012 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10394.259012 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11524.393091 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11524.393091 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20584.438763 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20584.438763 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20584.438763 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20584.438763 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 148655 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 4997 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 7912 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9629.375825 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 18.788549 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 36517 # number of writebacks -system.cpu1.dcache.writebacks::total 36517 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 66699 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 66699 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 133155 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 133155 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 347 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 347 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 199854 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 199854 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 199854 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 199854 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 43510 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 43510 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 23341 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 23341 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1173 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1173 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 665 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 665 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 66851 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 66851 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 66851 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 66851 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 664874003 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 664874003 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 774412476 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 774412476 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 13964500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 13964500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5940500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5940500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1439286479 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1439286479 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1439286479 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1439286479 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 25429000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 25429000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 545455000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 545455000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 570884000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 570884000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035939 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035939 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033440 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033440 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064472 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064472 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.043117 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.043117 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.035025 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.035025 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035025 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035025 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15280.946978 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15280.946978 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33178.204704 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33178.204704 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11904.944587 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.944587 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 8933.082707 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 8933.082707 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21529.767378 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21529.767378 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21529.767378 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21529.767378 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 102031 # number of writebacks +system.cpu1.dcache.writebacks::total 102031 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 180109 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 180109 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 273076 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 273076 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 765 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 765 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 453185 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 453185 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 453185 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 453185 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 108656 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 108656 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57473 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 57473 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6725 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6725 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 4282 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 4282 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 166129 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 166129 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 166129 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 166129 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1328748500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1328748500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1211037987 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1211037987 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 54734500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 54734500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 40806500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 40806500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2539786487 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2539786487 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2539786487 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2539786487 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30975000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30975000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 686558000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 686558000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 717533000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 717533000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.047272 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.047272 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037669 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.037669 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.123110 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.123110 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085561 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.085561 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043441 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043441 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043441 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043441 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12228.947320 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12228.947320 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21071.424617 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21071.424617 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8138.959108 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8138.959108 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9529.775806 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9529.775806 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15288.038133 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15288.038133 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15288.038133 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15288.038133 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1581,162 +1581,170 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 199157 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 71465 40.61% 40.61% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.07% 40.69% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1927 1.10% 41.78% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 9 0.01% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 102444 58.21% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 175976 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 70100 49.28% 49.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.09% 49.37% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1927 1.35% 50.72% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 9 0.01% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 70091 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 142258 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1862744375000 97.86% 97.86% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 69542000 0.00% 97.86% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 583001500 0.03% 97.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 5982500 0.00% 97.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 40144359500 2.11% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1903547260500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.980900 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6652 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 169834 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 59752 40.24% 40.24% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.32% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1927 1.30% 41.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 283 0.19% 41.81% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 86412 58.19% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 148505 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 58939 49.14% 49.14% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.25% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1927 1.61% 50.86% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 283 0.24% 51.09% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 58656 48.91% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 119936 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1864736682500 98.02% 98.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 62604500 0.00% 98.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 575436000 0.03% 98.06% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 137989000 0.01% 98.06% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 36850597000 1.94% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1902363309000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.986394 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684188 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808394 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.65% 3.65% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.68% 12.33% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.37% 13.70% # number of syscalls executed -system.cpu0.kern.syscall::6 32 14.61% 28.31% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.46% 28.77% # number of syscalls executed -system.cpu0.kern.syscall::17 8 3.65% 32.42% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.57% 36.99% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.74% 39.73% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.46% 40.18% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.37% 41.55% # number of syscalls executed -system.cpu0.kern.syscall::33 6 2.74% 44.29% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.91% 45.21% # number of syscalls executed -system.cpu0.kern.syscall::45 36 16.44% 61.64% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.37% 63.01% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.57% 67.58% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.57% 72.15% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.46% 72.60% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.74% 75.34% # number of syscalls executed -system.cpu0.kern.syscall::71 23 10.50% 85.84% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.37% 87.21% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.74% 89.95% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.46% 90.41% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.37% 91.78% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.11% 95.89% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.91% 96.80% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.91% 97.72% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.46% 98.17% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.91% 99.09% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.91% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 219 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.678795 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.807623 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.93% 3.93% # number of syscalls executed +system.cpu0.kern.syscall::3 15 8.43% 12.36% # number of syscalls executed +system.cpu0.kern.syscall::4 4 2.25% 14.61% # number of syscalls executed +system.cpu0.kern.syscall::6 26 14.61% 29.21% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.56% 29.78% # number of syscalls executed +system.cpu0.kern.syscall::17 6 3.37% 33.15% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.93% 37.08% # number of syscalls executed +system.cpu0.kern.syscall::20 4 2.25% 39.33% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.56% 39.89% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.69% 41.57% # number of syscalls executed +system.cpu0.kern.syscall::33 6 3.37% 44.94% # number of syscalls executed +system.cpu0.kern.syscall::41 2 1.12% 46.07% # number of syscalls executed +system.cpu0.kern.syscall::45 29 16.29% 62.36% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.69% 64.04% # number of syscalls executed +system.cpu0.kern.syscall::48 8 4.49% 68.54% # number of syscalls executed +system.cpu0.kern.syscall::54 8 4.49% 73.03% # number of syscalls executed +system.cpu0.kern.syscall::59 6 3.37% 76.40% # number of syscalls executed +system.cpu0.kern.syscall::71 17 9.55% 85.96% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.69% 87.64% # number of syscalls executed +system.cpu0.kern.syscall::74 4 2.25% 89.89% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.56% 90.45% # number of syscalls executed +system.cpu0.kern.syscall::90 2 1.12% 91.57% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.93% 95.51% # number of syscalls executed +system.cpu0.kern.syscall::97 2 1.12% 96.63% # number of syscalls executed +system.cpu0.kern.syscall::98 2 1.12% 97.75% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.56% 98.31% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.56% 98.88% # number of syscalls executed +system.cpu0.kern.syscall::147 2 1.12% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 178 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 101 0.05% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3850 2.08% 2.14% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.17% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.17% # number of callpals executed -system.cpu0.kern.callpal::swpipl 169235 91.57% 93.74% # number of callpals executed -system.cpu0.kern.callpal::rdps 6384 3.45% 97.19% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 97.19% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed -system.cpu0.kern.callpal::rti 4673 2.53% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 373 0.20% 99.93% # number of callpals executed -system.cpu0.kern.callpal::imb 133 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 184824 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7179 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1251 # number of protection mode switches +system.cpu0.kern.callpal::wripir 383 0.25% 0.25% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.25% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.25% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.25% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3188 2.04% 2.29% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.32% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.32% # number of callpals executed +system.cpu0.kern.callpal::swpipl 141921 90.80% 93.12% # number of callpals executed +system.cpu0.kern.callpal::rdps 6055 3.87% 96.99% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.01% 97.00% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.00% # number of callpals executed +system.cpu0.kern.callpal::rti 4242 2.71% 99.71% # number of callpals executed +system.cpu0.kern.callpal::callsys 315 0.20% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 156308 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6637 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1098 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1250 -system.cpu0.kern.mode_good::user 1251 +system.cpu0.kern.mode_good::kernel 1098 +system.cpu0.kern.mode_good::user 1098 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.174119 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.165436 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.296679 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1901642531000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1904721500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.283904 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1900423407500 99.92% 99.92% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1609733000 0.08% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3851 # number of times the context was actually changed +system.cpu0.kern.swap_context 3189 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2262 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 38430 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10197 33.29% 33.29% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1926 6.29% 39.58% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 101 0.33% 39.91% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18406 60.09% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 30630 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10185 45.68% 45.68% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1926 8.64% 54.32% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 101 0.45% 54.77% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10084 45.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22296 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1876291886000 98.58% 98.58% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533607500 0.03% 98.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 52904000 0.00% 98.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 26445439500 1.39% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1903323837000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998823 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2560 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 70963 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 22970 38.17% 38.17% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 3.20% 41.37% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 383 0.64% 42.01% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 34900 57.99% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 60178 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 22406 47.94% 47.94% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 4.12% 52.06% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 383 0.82% 52.88% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 22023 47.12% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 46737 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1874192202500 98.50% 98.50% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 532510000 0.03% 98.53% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 178162000 0.01% 98.54% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 27779026000 1.46% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1902681900500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.975446 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.547865 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.727914 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 11 10.28% 10.28% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.93% 11.21% # number of syscalls executed -system.cpu1.kern.syscall::6 10 9.35% 20.56% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.93% 21.50% # number of syscalls executed -system.cpu1.kern.syscall::17 7 6.54% 28.04% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.80% 30.84% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.80% 33.64% # number of syscalls executed -system.cpu1.kern.syscall::33 5 4.67% 38.32% # number of syscalls executed -system.cpu1.kern.syscall::45 18 16.82% 55.14% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.80% 57.94% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.93% 58.88% # number of syscalls executed -system.cpu1.kern.syscall::71 31 28.97% 87.85% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.35% 97.20% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.80% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 107 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.631032 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.776646 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.68% 0.68% # number of syscalls executed +system.cpu1.kern.syscall::3 15 10.14% 10.81% # number of syscalls executed +system.cpu1.kern.syscall::6 16 10.81% 21.62% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.68% 22.30% # number of syscalls executed +system.cpu1.kern.syscall::17 9 6.08% 28.38% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.03% 30.41% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.35% 31.76% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.03% 33.78% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.03% 35.81% # number of syscalls executed +system.cpu1.kern.syscall::33 5 3.38% 39.19% # number of syscalls executed +system.cpu1.kern.syscall::45 25 16.89% 56.08% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.03% 58.11% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.35% 59.46% # number of syscalls executed +system.cpu1.kern.syscall::54 2 1.35% 60.81% # number of syscalls executed +system.cpu1.kern.syscall::58 1 0.68% 61.49% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.68% 62.16% # number of syscalls executed +system.cpu1.kern.syscall::71 37 25.00% 87.16% # number of syscalls executed +system.cpu1.kern.syscall::74 12 8.11% 95.27% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.68% 95.95% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.35% 97.30% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.03% 99.32% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.68% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 148 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 9 0.03% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.04% # number of callpals executed -system.cpu1.kern.callpal::swpctx 385 1.22% 1.26% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.27% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.29% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26077 82.56% 83.85% # number of callpals executed -system.cpu1.kern.callpal::rdps 2376 7.52% 91.38% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.38% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.02% 91.39% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.40% # number of callpals executed -system.cpu1.kern.callpal::rti 2525 7.99% 99.40% # number of callpals executed -system.cpu1.kern.callpal::callsys 142 0.45% 99.85% # number of callpals executed -system.cpu1.kern.callpal::imb 47 0.15% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 283 0.45% 0.45% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.46% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1593 2.54% 3.00% # number of callpals executed +system.cpu1.kern.callpal::tbi 5 0.01% 3.00% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.01% # number of callpals executed +system.cpu1.kern.callpal::swpipl 54358 86.66% 89.67% # number of callpals executed +system.cpu1.kern.callpal::rdps 2709 4.32% 93.99% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.99% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.01% 94.00% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 94.00% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.01% # number of callpals executed +system.cpu1.kern.callpal::rti 3511 5.60% 99.60% # number of callpals executed +system.cpu1.kern.callpal::callsys 200 0.32% 99.92% # number of callpals executed +system.cpu1.kern.callpal::imb 48 0.08% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 31584 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 861 # number of protection mode switches -system.cpu1.kern.mode_switch::user 488 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2051 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 514 -system.cpu1.kern.mode_good::user 488 -system.cpu1.kern.mode_good::idle 26 -system.cpu1.kern.mode_switch_good::kernel 0.596980 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 62728 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1948 # number of protection mode switches +system.cpu1.kern.mode_switch::user 639 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2607 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 948 +system.cpu1.kern.mode_good::user 639 +system.cpu1.kern.mode_good::idle 309 +system.cpu1.kern.mode_switch_good::kernel 0.486653 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.012677 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.302353 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 2103355500 0.11% 0.11% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 871184500 0.05% 0.16% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1899849485000 99.84% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 386 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.118527 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.365037 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 6500961500 0.34% 0.34% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1047066000 0.06% 0.40% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1895133865000 99.60% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1594 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 05077073e..76f868d7e 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.855236 # Nu sim_ticks 1855236450500 # Number of ticks simulated final_tick 1855236450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87142 # Simulator instruction rate (inst/s) -host_op_rate 87142 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3050446700 # Simulator tick rate (ticks/s) -host_mem_usage 299400 # Number of bytes of host memory used -host_seconds 608.19 # Real time elapsed on the host +host_inst_rate 182093 # Simulator instruction rate (inst/s) +host_op_rate 182093 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6374280472 # Simulator tick rate (ticks/s) +host_mem_usage 298212 # Number of bytes of host memory used +host_seconds 291.05 # Real time elapsed on the host sim_insts 52998368 # Number of instructions simulated sim_ops 52998368 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 969536 # Number of bytes read from this memory @@ -87,11 +87,11 @@ system.iocache.demand_avg_miss_latency::tsunami.ide 275380.989910 system.iocache.demand_avg_miss_latency::total 275380.989910 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency system.iocache.overall_avg_miss_latency::total 275380.989910 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 200042000 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 200042 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 24684 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8104.116027 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.104116 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -105,14 +105,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308744998 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9308744998 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9320420998 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9320420998 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9320420998 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9320420998 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11676998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308894806 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9308894806 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9320571804 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9320571804 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9320571804 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9320571804 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -121,14 +121,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224026.400606 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 224026.400606 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67497.098266 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67497.098266 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224030.005920 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 224030.005920 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -258,12 +258,12 @@ system.cpu.iq.iqSquashedOperandsExamined 3652702 # Nu system.cpu.iq.iqSquashedNonSpecRemoved 1416008 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 80977441 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.704819 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.361988 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.361989 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56039618 69.20% 69.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11066888 13.67% 82.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5221753 6.45% 89.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3374540 4.17% 93.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56039637 69.20% 69.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11066851 13.67% 82.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5221770 6.45% 89.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3374541 4.17% 93.49% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 2635998 3.26% 96.74% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 1459561 1.80% 98.54% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 750162 0.93% 99.47% # Number of insts issued each cycle @@ -521,11 +521,11 @@ system.cpu.icache.demand_avg_miss_latency::cpu.inst 13450.989067 system.cpu.icache.demand_avg_miss_latency::total 13450.989067 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 13450.989067 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1416996 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 2830 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 136 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10419.088235 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.808824 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -541,24 +541,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1021072 system.cpu.icache.demand_mshr_misses::total 1021072 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1021072 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1021072 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11930954998 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11930954998 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11930954998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11930954998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11930954998 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11930954998 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11930955996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11930955996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11930955996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11930955996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11930955996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11930955996 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116808 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.116808 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.116808 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.734277 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.734277 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.734277 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.734277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.734277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.734277 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.735255 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.735255 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.735255 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.735255 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.735255 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.735255 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1402622 # number of replacements system.cpu.dcache.tagsinuse 511.994917 # Cycle average of tags in use @@ -595,16 +595,16 @@ system.cpu.dcache.overall_misses::cpu.data 3739889 # system.cpu.dcache.overall_misses::total 3739889 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 35378004500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 35378004500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 56417912677 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 56417912677 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 56417909184 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 56417909184 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304480000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 304480000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91795917177 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91795917177 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91795917177 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91795917177 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91795913684 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91795913684 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91795913684 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91795913684 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 9072218 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 9072218 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6147230 # number of WriteReq accesses(hits+misses) @@ -631,22 +631,22 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.245731 system.cpu.dcache.overall_miss_rate::total 0.245731 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19682.056496 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 19682.056496 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29045.256406 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29045.256406 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29045.254608 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29045.254608 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13215.277778 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13215.277778 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24545.091359 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24545.091359 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24545.091359 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24545.091359 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 807907785 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 221000 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24545.090425 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24545.090425 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24545.090425 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24545.090425 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1615102 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 442 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 110012 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7343.815084 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 24555.555556 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.681144 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 49.111111 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 841878 # number of writebacks @@ -675,16 +675,16 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 1385390 system.cpu.dcache.overall_mshr_misses::total 1385390 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23663666500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 23663666500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402021809 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402021809 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402034783 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402034783 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201708000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201708000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32065688309 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 32065688309 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32065688309 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 32065688309 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32065701283 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 32065701283 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32065701283 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 32065701283 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424101000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424101000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997524498 # number of WriteReq MSHR uncacheable cycles @@ -705,16 +705,16 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091028 system.cpu.dcache.overall_mshr_miss_rate::total 0.091028 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21806.574963 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21806.574963 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27985.470406 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27985.470406 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27985.513620 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27985.513620 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11276.162791 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11276.162791 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23145.603988 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23145.603988 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23145.603988 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23145.603988 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23145.613353 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23145.613353 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23145.613353 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23145.613353 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -765,19 +765,19 @@ system.cpu.l2cache.demand_misses::total 404416 # nu system.cpu.l2cache.overall_misses::cpu.inst 15151 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 389265 # number of overall misses system.cpu.l2cache.overall_misses::total 404416 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 808284498 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 808283500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14265189000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 15073473498 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 15073472500 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 384500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 384500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6187378482 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6187378482 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 808284498 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20452567482 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21260851980 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 808284498 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20452567482 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21260851980 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6187369500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6187369500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 808283500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 20452558500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21260842000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 808283500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 20452558500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21260842000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1020962 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1102389 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 2123351 # number of ReadReq accesses(hits+misses) @@ -808,19 +808,19 @@ system.cpu.l2cache.demand_miss_rate::total 0.166826 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014840 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.277408 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.166826 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53348.590720 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53348.524850 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52084.593899 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52150.851444 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52150.847991 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11651.515152 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11651.515152 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53626.091888 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53626.091888 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53348.590720 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52541.501245 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52571.737963 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53348.590720 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52541.501245 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52571.737963 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53626.014041 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53626.014041 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53348.524850 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52541.478170 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52571.713285 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53348.524850 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52541.478170 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52571.713285 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -850,25 +850,25 @@ system.cpu.l2cache.demand_mshr_misses::total 404415 system.cpu.l2cache.overall_mshr_misses::cpu.inst 15150 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 389265 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 404415 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 622919998 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10986726000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11609645998 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 622919500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10986768000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11609687500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1412500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1412500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4791053982 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4791053982 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 622919998 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15777779982 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16400699980 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 622919998 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15777779982 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16400699980 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4791050000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4791050000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 622919500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15777818000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16400737500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 622919500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15777818000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16400737500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331599500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331599500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1880939999 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1880939999 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212539499 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212539499 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1880939500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1880939500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212539000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212539000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248447 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136122 # mshr miss rate for ReadReq accesses @@ -882,19 +882,19 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.166825 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.166825 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41116.831551 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40114.376472 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40166.920954 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41116.798680 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40114.529821 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40167.064542 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 42803.030303 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 42803.030303 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41524.128809 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41524.128809 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41116.831551 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40532.233779 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40554.133699 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41116.831551 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40532.233779 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40554.133699 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41524.094297 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41524.094297 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41116.798680 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40532.331445 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40554.226475 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41116.798680 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40532.331445 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40554.226475 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index a59fc99d0..156205699 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.534231 # Number of seconds simulated -sim_ticks 2534231333000 # Number of ticks simulated -final_tick 2534231333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.534230 # Number of seconds simulated +sim_ticks 2534229746000 # Number of ticks simulated +final_tick 2534229746000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 44913 # Simulator instruction rate (inst/s) -host_op_rate 57771 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1878262368 # Simulator tick rate (ticks/s) -host_mem_usage 387000 # Number of bytes of host memory used -host_seconds 1349.24 # Real time elapsed on the host -sim_insts 60598653 # Number of instructions simulated -sim_ops 77947265 # Number of ops (including micro ops) simulated +host_inst_rate 65745 # Simulator instruction rate (inst/s) +host_op_rate 84567 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2749446134 # Simulator tick rate (ticks/s) +host_mem_usage 380664 # Number of bytes of host memory used +host_seconds 921.72 # Real time elapsed on the host +sim_insts 60598794 # Number of instructions simulated +sim_ops 77947430 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 798016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094928 # Number of bytes read from this memory -system.physmem.bytes_read::total 129434320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9095568 # Number of bytes read from this memory +system.physmem.bytes_read::total 129434640 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 798016 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 798016 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784256 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 3784576 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800328 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800648 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 57 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 12469 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142142 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096877 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59129 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.data 142152 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096882 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59134 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813147 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47169200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1439 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813152 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47169229 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1313 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 314895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3588831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51074390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51074548 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 314895 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 314895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493256 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190133 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683389 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47169200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493383 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190134 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683517 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47169229 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1313 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 314895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4778964 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53757779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4779219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53758065 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -69,9 +69,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15049411 # DTB read hits +system.cpu.checker.dtb.read_hits 15049421 # DTB read hits system.cpu.checker.dtb.read_misses 7302 # DTB read misses -system.cpu.checker.dtb.write_hits 11294478 # DTB write hits +system.cpu.checker.dtb.write_hits 11294481 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -82,13 +82,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15056713 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11296667 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15056723 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11296670 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26343889 # DTB hits +system.cpu.checker.dtb.hits 26343902 # DTB hits system.cpu.checker.dtb.misses 9491 # DTB misses -system.cpu.checker.dtb.accesses 26353380 # DTB accesses -system.cpu.checker.itb.inst_hits 61777417 # ITB inst hits +system.cpu.checker.dtb.accesses 26353393 # DTB accesses +system.cpu.checker.itb.inst_hits 61777557 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -105,36 +105,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61781888 # ITB inst accesses -system.cpu.checker.itb.hits 61777417 # DTB hits +system.cpu.checker.itb.inst_accesses 61782028 # ITB inst accesses +system.cpu.checker.itb.hits 61777557 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61781888 # DTB accesses -system.cpu.checker.numCycles 78237836 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61782028 # DTB accesses +system.cpu.checker.numCycles 78238000 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51729232 # DTB read hits -system.cpu.dtb.read_misses 76957 # DTB read misses -system.cpu.dtb.write_hits 11808980 # DTB write hits -system.cpu.dtb.write_misses 17307 # DTB write misses +system.cpu.dtb.read_hits 51729015 # DTB read hits +system.cpu.dtb.read_misses 77642 # DTB read misses +system.cpu.dtb.write_hits 11810988 # DTB write hits +system.cpu.dtb.write_misses 17459 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 7736 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2685 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 493 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 7775 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2642 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 530 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1359 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51806189 # DTB read accesses -system.cpu.dtb.write_accesses 11826287 # DTB write accesses +system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51806657 # DTB read accesses +system.cpu.dtb.write_accesses 11828447 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63538212 # DTB hits -system.cpu.dtb.misses 94264 # DTB misses -system.cpu.dtb.accesses 63632476 # DTB accesses -system.cpu.itb.inst_hits 13079160 # ITB inst hits -system.cpu.itb.inst_misses 12175 # ITB inst misses +system.cpu.dtb.hits 63540003 # DTB hits +system.cpu.dtb.misses 95101 # DTB misses +system.cpu.dtb.accesses 63635104 # DTB accesses +system.cpu.itb.inst_hits 13083995 # ITB inst hits +system.cpu.itb.inst_misses 12083 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -143,121 +143,121 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5196 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5178 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3091 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3112 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13091335 # ITB inst accesses -system.cpu.itb.hits 13079160 # DTB hits -system.cpu.itb.misses 12175 # DTB misses -system.cpu.itb.accesses 13091335 # DTB accesses -system.cpu.numCycles 475963827 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13096078 # ITB inst accesses +system.cpu.itb.hits 13083995 # DTB hits +system.cpu.itb.misses 12083 # DTB misses +system.cpu.itb.accesses 13096078 # DTB accesses +system.cpu.numCycles 475967538 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15173200 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12164115 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 783934 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10408500 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8322467 # Number of BTB hits +system.cpu.BPredUnit.lookups 15172784 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12163693 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 783478 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10392072 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8320250 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1454459 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 82493 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31372709 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 100925223 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15173200 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9776926 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22188702 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5931906 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 131502 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 97682240 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2742 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 97772 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 209251 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 367 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13075329 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1015161 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6456 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 155760556 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.799528 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.166845 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1454874 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 82640 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 31374160 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 100930999 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15172784 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9775124 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22189039 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5936170 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 131560 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 97680943 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2725 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 99805 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208737 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 364 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13080141 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1016234 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6355 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 155765235 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.799529 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.166844 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 133588722 85.77% 85.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1382794 0.89% 86.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1756872 1.13% 87.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2657278 1.71% 89.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2325995 1.49% 90.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1138064 0.73% 91.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2914708 1.87% 93.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 785042 0.50% 94.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9211081 5.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 133592933 85.77% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1382764 0.89% 86.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1755577 1.13% 87.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2658359 1.71% 89.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2327487 1.49% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1136384 0.73% 91.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2915896 1.87% 93.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 784165 0.50% 94.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9211670 5.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 155760556 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031879 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.212044 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 33510183 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 97305420 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20012915 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1028503 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3903535 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2022769 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174789 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 117637896 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 576974 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3903535 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 35608044 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37583370 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53602713 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18875511 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6187383 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110135538 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21282 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1015019 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4145584 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 32208 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 114982743 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 504362437 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 504271413 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 91024 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78733155 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36249587 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 891770 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797348 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12515452 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21000461 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13838053 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1958528 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2462024 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 100930109 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2057680 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126222278 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 188912 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24421115 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65012350 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 513116 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 155760556 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.810361 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.523302 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 155765235 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031878 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.212054 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33515539 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 97301422 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20013824 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1028268 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3906182 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2022458 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174763 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 117645711 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 578390 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3906182 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 35614317 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37590587 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53594123 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18875472 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6184554 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110140296 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21341 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1015182 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4143290 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 32170 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 114983026 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 504387694 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 504296628 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91066 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78733405 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36249620 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 891466 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797109 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12509806 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21006076 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13841580 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1961226 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2453000 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 100941360 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2057614 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126221061 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 189445 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24437015 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65086313 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 513058 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 155765235 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.810329 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.523325 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 110556788 70.98% 70.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13998731 8.99% 79.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7311876 4.69% 84.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6076948 3.90% 88.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12739380 8.18% 96.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2787527 1.79% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1678652 1.08% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 483348 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127306 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 110569920 70.98% 70.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13988875 8.98% 79.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7307591 4.69% 84.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6076063 3.90% 88.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12752921 8.19% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2780626 1.79% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1679008 1.08% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 481895 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128336 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 155760556 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 155765235 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57641 0.65% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 57759 0.65% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 2 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available @@ -286,13 +286,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8370517 94.61% 95.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 419308 4.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8370724 94.64% 95.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 416242 4.71% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59916595 47.47% 47.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95459 0.08% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59912166 47.47% 47.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95497 0.08% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued @@ -305,10 +305,10 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued @@ -316,365 +316,365 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53391379 42.30% 90.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12453015 9.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53392141 42.30% 90.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12455427 9.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126222278 # Type of FU issued -system.cpu.iq.rate 0.265193 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8847468 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070094 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 417312006 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 127425546 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87185779 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12560 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10301 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134693654 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12426 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624535 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126221061 # Type of FU issued +system.cpu.iq.rate 0.265188 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8844727 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070073 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 417312910 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 127452442 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87180232 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23310 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12552 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10294 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134689743 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12379 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 626582 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5283990 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7463 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30379 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2039233 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5289586 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7312 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30140 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2042757 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34106900 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1029053 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34106883 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1034668 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3903535 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28661313 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 449961 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103213314 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 232487 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21000461 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13838053 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1466210 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113940 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30379 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 409944 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 293507 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 703451 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 122976352 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52416933 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3245926 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3906182 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28670725 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 450645 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103223935 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 233802 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21006076 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13841580 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1466072 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 114504 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3680 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30140 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 409816 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 293009 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 702825 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 122971529 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52416599 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3249532 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 225525 # number of nop insts executed -system.cpu.iew.exec_refs 64738243 # number of memory reference insts executed -system.cpu.iew.exec_branches 11734992 # Number of branches executed -system.cpu.iew.exec_stores 12321310 # Number of stores executed -system.cpu.iew.exec_rate 0.258373 # Inst execution rate -system.cpu.iew.wb_sent 121627349 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87196080 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47712496 # num instructions producing a value -system.cpu.iew.wb_consumers 88865437 # num instructions consuming a value +system.cpu.iew.exec_nop 224961 # number of nop insts executed +system.cpu.iew.exec_refs 64739842 # number of memory reference insts executed +system.cpu.iew.exec_branches 11733959 # Number of branches executed +system.cpu.iew.exec_stores 12323243 # Number of stores executed +system.cpu.iew.exec_rate 0.258361 # Inst execution rate +system.cpu.iew.wb_sent 121621677 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87190526 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47712664 # num instructions producing a value +system.cpu.iew.wb_consumers 88871095 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.183199 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536907 # average fanout of values written-back +system.cpu.iew.wb_rate 0.183186 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536875 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24286652 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544564 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 612198 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151939453 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.514005 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.494998 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24296365 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544556 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 611758 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151941485 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.513999 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.495079 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 124139967 81.70% 81.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13583489 8.94% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3975420 2.62% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2135851 1.41% 94.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1949883 1.28% 95.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 999128 0.66% 96.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1578626 1.04% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 727876 0.48% 98.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2849213 1.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 124150656 81.71% 81.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13572481 8.93% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3978264 2.62% 93.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2132059 1.40% 94.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1949397 1.28% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 999089 0.66% 96.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1584839 1.04% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 727042 0.48% 98.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2847658 1.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151939453 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60749034 # Number of instructions committed -system.cpu.commit.committedOps 78097646 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151941485 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60749175 # Number of instructions committed +system.cpu.commit.committedOps 78097811 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27515291 # Number of memory references committed -system.cpu.commit.loads 15716471 # Number of loads committed +system.cpu.commit.refs 27515313 # Number of memory references committed +system.cpu.commit.loads 15716490 # Number of loads committed system.cpu.commit.membars 413125 # Number of memory barriers committed -system.cpu.commit.branches 10023270 # Number of branches committed +system.cpu.commit.branches 10023277 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69135938 # Number of committed integer instructions. +system.cpu.commit.int_insts 69136099 # Number of committed integer instructions. system.cpu.commit.function_calls 996018 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2849213 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 2847658 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 249559242 # The number of ROB reads -system.cpu.rob.rob_writes 208759201 # The number of ROB writes -system.cpu.timesIdled 1773088 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320203271 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4592410806 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60598653 # Number of Instructions Simulated -system.cpu.committedOps 77947265 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60598653 # Number of Instructions Simulated -system.cpu.cpi 7.854363 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.854363 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127318 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127318 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 556742715 # number of integer regfile reads -system.cpu.int_regfile_writes 89972067 # number of integer regfile writes +system.cpu.rob.rob_reads 249572720 # The number of ROB reads +system.cpu.rob.rob_writes 208783952 # The number of ROB writes +system.cpu.timesIdled 1774345 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320202303 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4592403923 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60598794 # Number of Instructions Simulated +system.cpu.committedOps 77947430 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60598794 # Number of Instructions Simulated +system.cpu.cpi 7.854406 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.854406 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127317 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127317 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 556725628 # number of integer regfile reads +system.cpu.int_regfile_writes 89967061 # number of integer regfile writes system.cpu.fp_regfile_reads 8371 # number of floating regfile reads -system.cpu.fp_regfile_writes 2922 # number of floating regfile writes -system.cpu.misc_regfile_reads 133101437 # number of misc regfile reads -system.cpu.misc_regfile_writes 912914 # number of misc regfile writes -system.cpu.icache.replacements 989669 # number of replacements -system.cpu.icache.tagsinuse 511.593818 # Cycle average of tags in use -system.cpu.icache.total_refs 12001618 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 990181 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.120630 # Average number of references to valid blocks. +system.cpu.fp_regfile_writes 2914 # number of floating regfile writes +system.cpu.misc_regfile_reads 133111894 # number of misc regfile reads +system.cpu.misc_regfile_writes 912902 # number of misc regfile writes +system.cpu.icache.replacements 989535 # number of replacements +system.cpu.icache.tagsinuse 511.594104 # Cycle average of tags in use +system.cpu.icache.total_refs 12006884 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 990047 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.127590 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6924990000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.593818 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 511.594104 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999207 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999207 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12001618 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12001618 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12001618 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12001618 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12001618 # number of overall hits -system.cpu.icache.overall_hits::total 12001618 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1073577 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1073577 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1073577 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1073577 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1073577 # number of overall misses -system.cpu.icache.overall_misses::total 1073577 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14108104991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14108104991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14108104991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14108104991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14108104991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14108104991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13075195 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13075195 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13075195 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13075195 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13075195 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13075195 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082108 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.082108 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.082108 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.082108 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.082108 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.082108 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13141.213896 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13141.213896 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13141.213896 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13141.213896 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13141.213896 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13141.213896 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2357994 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 12006884 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12006884 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12006884 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12006884 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12006884 # number of overall hits +system.cpu.icache.overall_hits::total 12006884 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1073125 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1073125 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1073125 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1073125 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1073125 # number of overall misses +system.cpu.icache.overall_misses::total 1073125 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14103457490 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14103457490 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14103457490 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14103457490 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14103457490 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14103457490 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13080009 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13080009 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13080009 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13080009 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13080009 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13080009 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082043 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.082043 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.082043 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.082043 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.082043 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.082043 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13142.418162 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13142.418162 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13142.418162 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13142.418162 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13142.418162 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13142.418162 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4497 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 295 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7993.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.244068 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 83350 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 83350 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 83350 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 83350 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 83350 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 83350 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 990227 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 990227 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 990227 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 990227 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 990227 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 990227 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11450107511 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11450107511 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11450107511 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11450107511 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11450107511 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11450107511 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 83043 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 83043 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 83043 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 83043 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 83043 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 83043 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 990082 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 990082 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 990082 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 990082 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 990082 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 990082 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11447874492 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11447874492 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11447874492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11447874492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11447874492 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11447874492 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7934000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7934000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7934000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7934000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075733 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075733 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075733 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075733 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075733 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075733 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11563.113822 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11563.113822 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11563.113822 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11563.113822 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11563.113822 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11563.113822 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075694 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075694 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075694 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075694 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075694 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075694 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11562.551882 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11562.551882 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11562.551882 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11562.551882 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11562.551882 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11562.551882 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 645165 # number of replacements +system.cpu.dcache.replacements 645234 # number of replacements system.cpu.dcache.tagsinuse 511.991712 # Cycle average of tags in use -system.cpu.dcache.total_refs 21796404 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 645677 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.757442 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 21791132 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 645746 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.745671 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 48877000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.991712 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13934718 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13934718 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7288473 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7288473 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 284342 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 284342 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285730 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285730 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21223191 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21223191 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21223191 # number of overall hits -system.cpu.dcache.overall_hits::total 21223191 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 726725 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 726725 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2962478 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2962478 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13561 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13561 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3689203 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3689203 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3689203 # number of overall misses -system.cpu.dcache.overall_misses::total 3689203 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9436874000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9436874000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104178007737 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104178007737 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180640000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 180640000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 370500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 370500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 113614881737 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 113614881737 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 113614881737 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 113614881737 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14661443 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14661443 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10250951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10250951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297903 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 297903 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285749 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285749 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24912394 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24912394 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24912394 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24912394 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049567 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049567 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288995 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288995 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045522 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045522 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000066 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000066 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148087 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.148087 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.148087 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.148087 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12985.481441 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12985.481441 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35165.833379 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35165.833379 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13320.551582 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13320.551582 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19500 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30796.592580 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30796.592580 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30796.592580 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30796.592580 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12775922 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7850000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2526 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5057.768013 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 27738.515901 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13929737 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13929737 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7288383 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7288383 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 284164 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 284164 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21218120 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21218120 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21218120 # number of overall hits +system.cpu.dcache.overall_hits::total 21218120 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 727325 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 727325 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2962578 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2962578 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13599 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13599 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3689903 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3689903 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3689903 # number of overall misses +system.cpu.dcache.overall_misses::total 3689903 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9441506500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9441506500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104195765238 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104195765238 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181224000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 181224000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 305500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 305500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 113637271738 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 113637271738 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 113637271738 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 113637271738 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14657062 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14657062 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10250961 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10250961 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297763 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 297763 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285742 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285742 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24908023 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24908023 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24908023 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24908023 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049623 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.049623 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289005 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289005 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045671 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045671 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000049 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000049 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148141 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148141 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148141 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148141 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12981.138418 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12981.138418 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35170.640313 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35170.640313 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13326.273991 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13326.273991 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21821.428571 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21821.428571 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30796.818165 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30796.818165 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30796.818165 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30796.818165 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 25623 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15683 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2532 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.119668 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 56.211470 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 609206 # number of writebacks -system.cpu.dcache.writebacks::total 609206 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 339325 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 339325 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713436 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713436 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1355 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1355 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3052761 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3052761 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3052761 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3052761 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387400 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 387400 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249042 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249042 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12206 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12206 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636442 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636442 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636442 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636442 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4757620458 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4757620458 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8541364957 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8541364957 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141415500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141415500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 332500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 332500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13298985415 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13298985415 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13298985415 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13298985415 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182407548000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182407548000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41944273253 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41944273253 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224351821253 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 224351821253 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026423 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026423 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024295 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024295 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040973 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040973 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000066 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000066 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025547 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025547 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025547 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12280.899479 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12280.899479 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34296.885493 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34296.885493 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11585.736523 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11585.736523 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17500 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20895.832480 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20895.832480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20895.832480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20895.832480 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 609265 # number of writebacks +system.cpu.dcache.writebacks::total 609265 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 339927 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 339927 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713517 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2713517 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1356 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1356 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3053444 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3053444 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3053444 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3053444 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387398 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 387398 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249061 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249061 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12243 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12243 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 636459 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 636459 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 636459 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 636459 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4758834000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4758834000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8540298916 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8540298916 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141913000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141913000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 277500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 277500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13299132916 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13299132916 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13299132916 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13299132916 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182407357500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182407357500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42045203371 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42045203371 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224452560871 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 224452560871 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024296 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024296 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041117 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041117 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000049 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000049 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025552 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025552 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025552 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025552 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12284.095426 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12284.095426 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34289.988862 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34289.988862 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11591.358327 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11591.358327 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19821.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19821.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20895.506099 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20895.506099 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20895.506099 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20895.506099 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -682,149 +682,149 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64397 # number of replacements -system.cpu.l2cache.tagsinuse 51351.941492 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1929097 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129792 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.862988 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2499029961500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36885.832563 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 46.221263 # Average occupied blocks per requestor +system.cpu.l2cache.replacements 64402 # number of replacements +system.cpu.l2cache.tagsinuse 51349.814622 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1928941 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129796 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.861329 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2499028808000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36883.442332 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 42.609278 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000238 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8173.888273 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6245.999155 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.562833 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000705 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 8182.264424 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6241.498349 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.562797 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000650 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.124724 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.095306 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783568 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 82917 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11882 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 976616 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 388806 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1460221 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 609206 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 609206 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 42 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112940 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112940 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 82917 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 11882 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 976616 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 501746 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1573161 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 82917 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 11882 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 976616 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 501746 # number of overall hits -system.cpu.l2cache.overall_hits::total 1573161 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 57 # number of ReadReq misses +system.cpu.l2cache.occ_percent::cpu.inst 0.124851 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.095238 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.783536 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 83718 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11792 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 976445 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 388833 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1460788 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 609265 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 609265 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 11 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 112992 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112992 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 83718 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 11792 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 976445 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 501825 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1573780 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 83718 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 11792 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 976445 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 501825 # number of overall hits +system.cpu.l2cache.overall_hits::total 1573780 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 52 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 12351 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10715 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23124 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2929 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2929 # number of UpgradeReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10724 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23128 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2917 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2917 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133216 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133216 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 57 # number of demand (read+write) misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133197 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133197 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 52 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 12351 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143931 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156340 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 57 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.data 143921 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156325 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 52 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 12351 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143931 # number of overall misses -system.cpu.l2cache.overall_misses::total 156340 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2991000 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.data 143921 # number of overall misses +system.cpu.l2cache.overall_misses::total 156325 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2722500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 657846996 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 563988998 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1224886994 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1254000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 1254000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7004496993 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7004496993 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2991000 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 657732500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 564471998 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1224986998 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1042500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 1042500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7003431498 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7003431498 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2722500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 657846996 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7568485991 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8229383987 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2991000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 657732500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7567903496 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8228418496 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2722500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 60000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 657846996 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7568485991 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8229383987 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 82974 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11883 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 988967 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 399521 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1483345 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 609206 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 609206 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2971 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2971 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 19 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246156 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246156 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 82974 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 11883 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 988967 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 645677 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1729501 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 82974 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 11883 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 988967 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 645677 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1729501 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000687 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000084 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012489 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026820 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015589 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985863 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985863 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.157895 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.157895 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541185 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541185 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000687 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000084 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012489 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.222915 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.090396 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000687 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000084 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012489 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.222915 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.090396 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52473.684211 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_latency::cpu.inst 657732500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7567903496 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8228418496 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 83770 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11793 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 988796 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 399557 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1483916 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 609265 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 609265 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2956 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2956 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 14 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 14 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246189 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246189 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 83770 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 11793 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 988796 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 645746 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1730105 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 83770 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 11793 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 988796 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 645746 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1730105 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000621 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000085 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012491 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026840 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015586 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986806 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986806 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541036 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541036 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000621 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000085 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012491 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.222876 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.090356 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000621 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000085 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012491 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.222876 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.090356 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52355.769231 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 60000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53262.650474 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52635.464116 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52970.376838 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 428.132468 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 428.132468 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52579.997846 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52579.997846 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52473.684211 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53253.380293 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52636.329541 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52965.539519 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 357.387727 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 357.387727 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52579.498772 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52579.498772 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52355.769231 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53262.650474 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52584.127054 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52637.738180 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52473.684211 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53253.380293 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52583.733409 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52636.612800 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52355.769231 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53262.650474 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52584.127054 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52637.738180 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53253.380293 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52583.733409 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52636.612800 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -833,8 +833,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59129 # number of writebacks -system.cpu.l2cache.writebacks::total 59129 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 59134 # number of writebacks +system.cpu.l2cache.writebacks::total 59134 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits @@ -844,98 +844,98 @@ system.cpu.l2cache.demand_mshr_hits::total 69 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 69 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 57 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 52 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12343 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10654 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23055 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2929 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2929 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10663 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23059 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2917 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2917 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133216 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133216 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 57 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133197 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133197 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 52 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 12343 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143870 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156271 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 57 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143860 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156256 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 52 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 12343 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143870 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156271 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2295000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 143860 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156256 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2087500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 48000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 506735998 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 431013999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 940092997 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 117171500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 117171500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 506591500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 431393998 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 940120998 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 116691500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 116691500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5362815995 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5362815995 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2295000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5361943498 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5361943498 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2087500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 48000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 506735998 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5793829994 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6302908992 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2295000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 506591500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5793337496 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6302064496 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2087500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 48000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 506735998 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5793829994 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6302908992 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 506591500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5793337496 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6302064496 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5292000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166730274500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166735566500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32529244761 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32529244761 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166730210500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166735502500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32612370999 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32612370999 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5292000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 199259519261 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 199264811261 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026667 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015543 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985863 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985863 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541185 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541185 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222820 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.090356 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222820 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.090356 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 199342581499 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 199347873499 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000621 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012483 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026687 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015539 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986806 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986806 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541036 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541036 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000621 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012483 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222781 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.090316 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000621 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012483 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222781 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.090316 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40144.230769 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41054.524670 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40455.603435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40776.100499 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40003.926255 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40003.926255 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41042.817791 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40457.094439 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40770.241468 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40003.942407 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40003.942407 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40256.545723 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40256.545723 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40255.737727 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40255.737727 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40144.230769 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41054.524670 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40271.286536 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40333.196767 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41042.817791 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40270.662422 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40331.664039 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40144.230769 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41054.524670 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40271.286536 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40333.196767 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41042.817791 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40270.662422 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40331.664039 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -959,16 +959,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307054297856 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1307054297856 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307054297856 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1307054297856 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307562103462 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1307562103462 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307562103462 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1307562103462 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88034 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88032 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 8459be5ac..820ef6b3e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,71 +1,71 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.616879 # Number of seconds simulated -sim_ticks 2616878893500 # Number of ticks simulated -final_tick 2616878893500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.004001 # Number of seconds simulated +sim_ticks 1004001369000 # Number of ticks simulated +final_tick 1004001369000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63327 # Simulator instruction rate (inst/s) -host_op_rate 81506 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2627232906 # Simulator tick rate (ticks/s) -host_mem_usage 387740 # Number of bytes of host memory used -host_seconds 996.06 # Real time elapsed on the host -sim_insts 63077499 # Number of instructions simulated -sim_ops 81184436 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 397632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4358324 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 424512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5245616 # Number of bytes read from this memory -system.physmem.bytes_read::total 131538596 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 397632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 424512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 822144 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4254848 # Number of bytes written to this memory +host_inst_rate 89245 # Simulator instruction rate (inst/s) +host_op_rate 114826 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1450204701 # Simulator tick rate (ticks/s) +host_mem_usage 385792 # Number of bytes of host memory used +host_seconds 692.32 # Real time elapsed on the host +sim_insts 61785538 # Number of instructions simulated +sim_ops 79495701 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 44040192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 411712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4381300 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 403392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5239536 # Number of bytes read from this memory +system.physmem.bytes_read::total 54478052 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 411712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 403392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4277248 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7283984 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6213 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68171 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6633 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81989 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15301853 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66482 # Number of write requests responded to by this memory +system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory +system.physmem.bytes_written::total 7304336 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 5505024 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6433 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68530 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6303 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81894 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5668214 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66832 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823766 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46280525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 73 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 151949 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1665466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 465 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 162221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2004531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50265450 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 151949 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 162221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1625925 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6496 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1151041 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2783462 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1625925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46280525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 73 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 151949 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1671963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 162221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3155573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53048913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory +system.physmem.num_writes::total 823604 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43864673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 410071 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 4363839 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 401784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5218654 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54260934 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 410071 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 401784 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 811855 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4260201 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 16932 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2998092 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7275225 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4260201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43864673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 410071 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 4380771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 401784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 8216746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 61536159 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -75,246 +75,246 @@ system.realview.nvmem.bytes_inst_read::total 448 system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 24 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 171 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 24 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 171 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 24 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 171 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72648 # number of replacements -system.l2c.tagsinuse 53148.103120 # Cycle average of tags in use -system.l2c.total_refs 1925510 # Total number of references to valid blocks. -system.l2c.sampled_refs 137845 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.968660 # Average number of references to valid blocks. +system.realview.nvmem.bw_read::cpu0.inst 64 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 382 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 446 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 64 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 382 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 446 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 64 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 382 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 446 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 72797 # number of replacements +system.l2c.tagsinuse 53893.248657 # Cycle average of tags in use +system.l2c.total_refs 1879341 # Total number of references to valid blocks. +system.l2c.sampled_refs 137955 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.622855 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37769.007236 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 3.653962 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.872957 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4238.981277 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2955.984743 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 14.025683 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4027.816705 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4137.760558 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.576309 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 39653.380215 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 3.693619 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000676 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4026.678241 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2797.052262 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 11.937877 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3656.015551 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3744.490216 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.605063 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000056 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.064682 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.045105 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000214 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061460 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.063137 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.810976 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 34723 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5721 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 398866 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166115 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 54785 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6733 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 615111 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 202597 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1484651 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 585034 # number of Writeback hits -system.l2c.Writeback_hits::total 585034 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1035 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 803 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1838 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 166 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 376 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48272 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58996 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107268 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 34723 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5721 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 398866 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214387 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 54785 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6733 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 615111 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 261593 # number of demand (read+write) hits -system.l2c.demand_hits::total 1591919 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 34723 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5721 # number of overall hits -system.l2c.overall_hits::cpu0.inst 398866 # number of overall hits -system.l2c.overall_hits::cpu0.data 214387 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 54785 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6733 # number of overall hits -system.l2c.overall_hits::cpu1.inst 615111 # number of overall hits -system.l2c.overall_hits::cpu1.data 261593 # number of overall hits -system.l2c.overall_hits::total 1591919 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 9 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6086 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6313 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 19 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6595 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6354 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25379 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5710 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4349 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 10059 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 787 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 589 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1376 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63248 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 76888 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140136 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 9 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6086 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69561 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 19 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6595 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 83242 # number of demand (read+write) misses -system.l2c.demand_misses::total 165515 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 9 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6086 # number of overall misses -system.l2c.overall_misses::cpu0.data 69561 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 19 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6595 # number of overall misses -system.l2c.overall_misses::cpu1.data 83242 # number of overall misses -system.l2c.overall_misses::total 165515 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 469500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 164500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 324649999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 331479497 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 999000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 350737499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 334001499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1342501494 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 20494467 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 27361999 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 47856466 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1618500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6981500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 8600000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3367787487 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4076466989 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7444254476 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 469500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 164500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 324649999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3699266984 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 999000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 350737499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4410468488 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8786755970 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 469500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 164500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 324649999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3699266984 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 999000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 350737499 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4410468488 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8786755970 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 34732 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 5724 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 404952 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 172428 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 54804 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6733 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 621706 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 208951 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1510030 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 585034 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 585034 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6745 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5152 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 11897 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 997 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 755 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1752 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111520 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 135884 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247404 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 34732 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 5724 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 404952 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 283948 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 54804 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6733 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 621706 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 344835 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1757434 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 34732 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 5724 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 404952 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 283948 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 54804 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6733 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 621706 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 344835 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1757434 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000259 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000524 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015029 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036612 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000347 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010608 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.030409 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016807 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.846553 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.844138 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.845507 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.789368 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.780132 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.785388 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.567145 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.565836 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.566426 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000259 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000524 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015029 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.244978 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000347 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010608 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.241397 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.094180 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000259 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000524 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015029 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.244978 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000347 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010608 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.241397 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.094180 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52166.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 54833.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53343.739566 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52507.444480 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52578.947368 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53182.334951 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52565.549103 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52898.124197 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3589.223643 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6291.561049 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 4757.576896 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2056.543837 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11853.140917 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 6250 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53247.335679 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53018.247178 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53121.642376 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52166.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 54833.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 53343.739566 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 53180.186944 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52578.947368 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 53182.334951 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52983.691982 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 53087.369544 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52166.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 54833.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 53343.739566 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 53180.186944 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52578.947368 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 53182.334951 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52983.691982 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 53087.369544 # average overall miss latency +system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.061442 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.042680 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000182 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.055786 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.057136 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.822346 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 32914 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 5095 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 390213 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166351 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 51484 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5864 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 597704 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 198321 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1447946 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 581607 # number of Writeback hits +system.l2c.Writeback_hits::total 581607 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1028 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 797 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1825 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 197 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 161 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 358 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48089 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58157 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106246 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 32914 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 5095 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 390213 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 214440 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 51484 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5864 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 597704 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 256478 # number of demand (read+write) hits +system.l2c.demand_hits::total 1554192 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 32914 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 5095 # number of overall hits +system.l2c.overall_hits::cpu0.inst 390213 # number of overall hits +system.l2c.overall_hits::cpu0.data 214440 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 51484 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5864 # number of overall hits +system.l2c.overall_hits::cpu1.inst 597704 # number of overall hits +system.l2c.overall_hits::cpu1.data 256478 # number of overall hits +system.l2c.overall_hits::total 1554192 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 10 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6309 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6299 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 18 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 6265 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 6179 # number of ReadReq misses +system.l2c.ReadReq_misses::total 25082 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5132 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3726 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8858 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 658 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 399 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1057 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63592 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 76934 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140526 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 10 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6309 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69891 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 18 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6265 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 83113 # number of demand (read+write) misses +system.l2c.demand_misses::total 165608 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 10 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6309 # number of overall misses +system.l2c.overall_misses::cpu0.data 69891 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 18 # number of overall misses +system.l2c.overall_misses::cpu1.inst 6265 # number of overall misses +system.l2c.overall_misses::cpu1.data 83113 # number of overall misses +system.l2c.overall_misses::total 165608 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 521500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 112000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 336617000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 331223999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 949000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 333434500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 325052500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1327910499 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 20016979 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 27954998 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 47971977 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1517000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 7957998 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 9474998 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3416178492 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4069563497 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7485741989 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 521500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 112000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 336617000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3747402491 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 949000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 333434500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4394615997 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8813652488 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 521500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 112000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 336617000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3747402491 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 949000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 333434500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4394615997 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8813652488 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 32924 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 5097 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 396522 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 172650 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 51502 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 5864 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 603969 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 204500 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1473028 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 581607 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 581607 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6160 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4523 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10683 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 855 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 560 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1415 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111681 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 135091 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246772 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 32924 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 5097 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 396522 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 284331 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 51502 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5864 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 603969 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 339591 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1719800 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 32924 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 5097 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 396522 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 284331 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 51502 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5864 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 603969 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 339591 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1719800 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000304 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000392 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015911 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036484 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000350 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010373 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.030215 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.017028 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.833117 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.823790 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.829168 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.769591 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.712500 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.746996 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.569408 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.569498 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.569457 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000304 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000392 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015911 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.245809 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000350 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010373 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.244744 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.096295 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000304 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000392 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015911 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.245809 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000350 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010373 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.244744 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.096295 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52150 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 56000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53355.048344 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52583.584537 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52722.222222 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53221.787709 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52606.004208 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52942.767682 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3900.424591 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7502.683306 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5415.666855 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2305.471125 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 19944.857143 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 8964.047304 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53720.255567 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52896.814113 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53269.444722 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52150 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 56000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 53355.048344 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 53617.811893 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52722.222222 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 53221.787709 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52875.193977 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 53219.968166 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52150 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 56000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 53355.048344 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 53617.811893 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52722.222222 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 53221.787709 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52875.193977 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 53219.968166 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -323,168 +323,168 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 66482 # number of writebacks -system.l2c.writebacks::total 66482 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 66832 # number of writebacks +system.l2c.writebacks::total 66832 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 37 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 37 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 37 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 9 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6081 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6275 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 19 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6588 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 6330 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25305 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 5710 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 4349 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 10059 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 787 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 589 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1376 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 63248 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 76888 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140136 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 9 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6081 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 69523 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 19 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6588 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 83218 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 165441 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 9 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6081 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 69523 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 19 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6588 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 83218 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 165441 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 360000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 128000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 250196499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 253577000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 768500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 270011999 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 255801000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1030842998 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 228550000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 174127500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 402677500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 31488000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23619500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 55107500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2598832997 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3131766991 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5730599988 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 360000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 128000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 250196499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2852409997 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 768500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 270011999 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3387567991 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6761442986 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 360000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 128000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 250196499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2852409997 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 768500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 270011999 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3387567991 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6761442986 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5530000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12326566000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2170500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154699599000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167033865500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1153697499 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31138895772 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32292593271 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5530000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13480263499 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2170500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185838494772 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 199326458771 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000259 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000524 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015017 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036392 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000347 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010597 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030294 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016758 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.846553 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.844138 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.845507 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.789368 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.780132 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.785388 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.567145 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.565836 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.566426 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000259 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000524 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015017 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.244844 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000347 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010597 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.241327 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.094138 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000259 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000524 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015017 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.244844 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000347 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010597 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.241327 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.094138 # mshr miss rate for overall accesses +system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 10 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6302 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6262 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 18 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6258 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 6155 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25007 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 5132 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3726 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8858 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 658 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 399 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1057 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 63592 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 76934 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140526 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 10 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6302 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 69854 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 18 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6258 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 83089 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 165533 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 10 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 6302 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 69854 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 18 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 6258 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 83089 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 165533 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 400000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 88000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 259390500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 253074999 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 729000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 256738000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 248671000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1019091499 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 205375466 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 149167996 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 354543462 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 26341496 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 15988493 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 42329989 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2637739492 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3117564497 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5755303989 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 400000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 88000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 259390500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2890814491 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 729000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 256738000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3366235497 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6774395488 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 400000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 88000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 259390500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2890814491 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 729000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 256738000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3366235497 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6774395488 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5539000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12385867978 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2149000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154396291480 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166789847458 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1090238997 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31486348998 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32576587995 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5539000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13476106975 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2149000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185882640478 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 199366435453 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000304 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000392 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015893 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036270 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000350 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010361 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030098 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016977 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.833117 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.823790 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.829168 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.769591 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.712500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.746996 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569408 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.569498 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.569457 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000304 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000392 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015893 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.245678 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000350 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010361 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244674 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.096251 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000304 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000392 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015893 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.245678 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000350 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010361 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244674 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.096251 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 42666.666667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41143.972866 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40410.677291 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40447.368421 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40985.427899 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40410.900474 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40736.731792 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40026.269702 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40038.514601 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40031.563774 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40010.165184 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40101.018676 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40049.055233 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41089.568002 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40731.544467 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40893.132300 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41160.028562 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40414.404184 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41025.567274 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40401.462226 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40752.249330 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40018.602104 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40034.352120 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40025.227139 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40032.668693 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40071.411028 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40047.293283 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41479.108882 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40522.584254 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40955.438773 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 42666.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41143.972866 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41028.292752 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40447.368421 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40985.427899 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40707.154594 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40869.210087 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41160.028562 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41383.664371 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41025.567274 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40513.611874 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40924.743030 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 42666.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41143.972866 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41028.292752 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40447.368421 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40985.427899 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40707.154594 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40869.210087 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41160.028562 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41383.664371 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41025.567274 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40513.611874 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40924.743030 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -507,27 +507,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9084291 # DTB read hits -system.cpu0.dtb.read_misses 36586 # DTB read misses -system.cpu0.dtb.write_hits 5291622 # DTB write hits -system.cpu0.dtb.write_misses 6420 # DTB write misses +system.cpu0.dtb.read_hits 8992964 # DTB read hits +system.cpu0.dtb.read_misses 35495 # DTB read misses +system.cpu0.dtb.write_hits 5204763 # DTB write hits +system.cpu0.dtb.write_misses 6364 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2157 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1431 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 301 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2149 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1250 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 357 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 545 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9120877 # DTB read accesses -system.cpu0.dtb.write_accesses 5298042 # DTB write accesses +system.cpu0.dtb.perms_faults 536 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9028459 # DTB read accesses +system.cpu0.dtb.write_accesses 5211127 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14375913 # DTB hits -system.cpu0.dtb.misses 43006 # DTB misses -system.cpu0.dtb.accesses 14418919 # DTB accesses -system.cpu0.itb.inst_hits 4432740 # ITB inst hits -system.cpu0.itb.inst_misses 5766 # ITB inst misses +system.cpu0.dtb.hits 14197727 # DTB hits +system.cpu0.dtb.misses 41859 # DTB misses +system.cpu0.dtb.accesses 14239586 # DTB accesses +system.cpu0.itb.inst_hits 4345219 # ITB inst hits +system.cpu0.itb.inst_misses 5468 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -536,542 +536,538 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1406 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1393 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1571 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1660 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4438506 # ITB inst accesses -system.cpu0.itb.hits 4432740 # DTB hits -system.cpu0.itb.misses 5766 # DTB misses -system.cpu0.itb.accesses 4438506 # DTB accesses -system.cpu0.numCycles 73427885 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4350687 # ITB inst accesses +system.cpu0.itb.hits 4345219 # DTB hits +system.cpu0.itb.misses 5468 # DTB misses +system.cpu0.itb.accesses 4350687 # DTB accesses +system.cpu0.numCycles 69454344 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 6227156 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4741082 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 330435 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3793257 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 3054809 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6140299 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4680843 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 325697 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3967848 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 3011514 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 703344 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 32160 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 12941361 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 33277959 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6227156 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3758153 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7819599 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1599392 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 82441 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 23494459 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5895 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 62047 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 92342 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 197 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4430967 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 174323 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2958 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 45648361 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.940627 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.320252 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 689087 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 31971 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 11903950 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32719278 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6140299 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3700601 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7697719 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1567081 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 66811 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 21663795 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4784 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 55267 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 90495 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4343360 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 170443 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2579 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 42607741 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.991445 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.370542 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 37836918 82.89% 82.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 627349 1.37% 84.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 824369 1.81% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 703980 1.54% 87.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 786046 1.72% 89.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 579188 1.27% 90.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 721067 1.58% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 372009 0.81% 93.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3197435 7.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34918154 81.95% 81.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 615023 1.44% 83.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 811777 1.91% 85.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 689946 1.62% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 788421 1.85% 88.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 570027 1.34% 90.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 709248 1.66% 91.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 365635 0.86% 92.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3139510 7.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 45648361 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.084806 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.453206 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 13430389 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 23511343 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 7018661 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 602696 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1085272 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 979924 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 65913 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 41505511 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 215463 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1085272 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 14040409 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6748642 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14460031 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6960379 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2353628 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 40289777 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2418 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 473813 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1332712 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 81 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 40678861 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 182059364 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 182024641 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34723 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31700311 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8978549 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 462421 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 418498 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5663645 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7939186 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5895346 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1154000 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1239736 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 38066358 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 944329 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 38270432 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 91181 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6810597 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 14485199 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 255192 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 45648361 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.838375 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.464052 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 42607741 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088408 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.471090 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12410407 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21637687 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6924723 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 574768 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1060156 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 960041 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 65781 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40808812 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 215037 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1060156 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12993427 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5870248 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13615125 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6864393 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2204392 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39624437 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2198 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 433654 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1244123 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 41 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39987634 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 178950817 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 178916692 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34125 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31114791 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8872842 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 451750 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 410482 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5405254 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7790925 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5788375 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1121917 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1222446 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37402937 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 939151 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37702557 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 87742 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6716452 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 14173286 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 260083 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 42607741 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.884876 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.498206 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 29755811 65.18% 65.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6343756 13.90% 79.08% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3236490 7.09% 86.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2520305 5.52% 91.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2106581 4.61% 96.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 935116 2.05% 98.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 513948 1.13% 99.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 183643 0.40% 99.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 52711 0.12% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 27166804 63.76% 63.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5957097 13.98% 77.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3214078 7.54% 85.28% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2477962 5.82% 91.10% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2111115 4.95% 96.06% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 940986 2.21% 98.26% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 497762 1.17% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 188040 0.44% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53897 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 45648361 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 42607741 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27042 2.53% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 464 0.04% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 835512 78.03% 80.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 207702 19.40% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 24897 2.34% 2.34% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 455 0.04% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 841667 79.11% 81.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 196890 18.51% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22977707 60.04% 60.18% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 50299 0.13% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9565645 24.99% 85.31% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5623724 14.69% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52279 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22610692 59.97% 60.11% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48707 0.13% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 696 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9470500 25.12% 85.36% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5519656 14.64% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 38270432 # Type of FU issued -system.cpu0.iq.rate 0.521198 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1070720 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.027978 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 123385364 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 45829388 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 35329971 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8465 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4764 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3918 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 39284390 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4418 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 323676 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37702557 # Type of FU issued +system.cpu0.iq.rate 0.542839 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1063909 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028218 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 119197860 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 45066260 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34725350 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8284 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4664 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3878 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38709880 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4307 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 311315 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1511954 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3775 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13508 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 616210 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1483597 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3551 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13024 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 603760 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149507 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5450 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2189792 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5367 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1085272 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4652854 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 126877 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 39130245 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 91852 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7939186 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5895346 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 610877 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 49621 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 17387 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13508 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 175421 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 130280 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 305701 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37846246 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9402583 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 424186 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1060156 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4217100 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 98020 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38461133 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 95338 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7790925 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5788375 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 610075 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39436 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2994 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13024 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 172050 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 129143 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 301193 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37281122 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9309198 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 421435 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 119558 # number of nop insts executed -system.cpu0.iew.exec_refs 14967440 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4996145 # Number of branches executed -system.cpu0.iew.exec_stores 5564857 # Number of stores executed -system.cpu0.iew.exec_rate 0.515421 # Inst execution rate -system.cpu0.iew.wb_sent 37628600 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 35333889 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18696932 # num instructions producing a value -system.cpu0.iew.wb_consumers 35648829 # num instructions consuming a value +system.cpu0.iew.exec_nop 119045 # number of nop insts executed +system.cpu0.iew.exec_refs 14772448 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4922535 # Number of branches executed +system.cpu0.iew.exec_stores 5463250 # Number of stores executed +system.cpu0.iew.exec_rate 0.536772 # Inst execution rate +system.cpu0.iew.wb_sent 37065432 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34729228 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18441672 # num instructions producing a value +system.cpu0.iew.wb_consumers 35371865 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.481205 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.524475 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.500030 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.521366 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6705821 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 689137 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 265687 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 44599494 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.717911 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.673991 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6577828 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 679068 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 261125 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 41583448 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.756316 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.712971 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 32451965 72.76% 72.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6077972 13.63% 86.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1948934 4.37% 90.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1034999 2.32% 93.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 805126 1.81% 94.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 506776 1.14% 96.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 402342 0.90% 96.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 201836 0.45% 97.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1169544 2.62% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 29716852 71.46% 71.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5893148 14.17% 85.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1935709 4.65% 90.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 983715 2.37% 92.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 787040 1.89% 94.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 514741 1.24% 95.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 394337 0.95% 96.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 216625 0.52% 97.26% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1141281 2.74% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 44599494 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24278814 # Number of instructions committed -system.cpu0.commit.committedOps 32018477 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 41583448 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23837222 # Number of instructions committed +system.cpu0.commit.committedOps 31450221 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11706368 # Number of memory references committed -system.cpu0.commit.loads 6427232 # Number of loads committed -system.cpu0.commit.membars 234590 # Number of memory barriers committed -system.cpu0.commit.branches 4349138 # Number of branches committed +system.cpu0.commit.refs 11491943 # Number of memory references committed +system.cpu0.commit.loads 6307328 # Number of loads committed +system.cpu0.commit.membars 231960 # Number of memory barriers committed +system.cpu0.commit.branches 4279027 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28284672 # Number of committed integer instructions. -system.cpu0.commit.function_calls 500279 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1169544 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27769802 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489719 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1141281 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 81269635 # The number of ROB reads -system.cpu0.rob.rob_writes 78536158 # The number of ROB writes -system.cpu0.timesIdled 427323 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27779524 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5160286096 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 24198072 # Number of Instructions Simulated -system.cpu0.committedOps 31937735 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 24198072 # Number of Instructions Simulated -system.cpu0.cpi 3.034452 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.034452 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.329549 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.329549 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 176614966 # number of integer regfile reads -system.cpu0.int_regfile_writes 35097459 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3370 # number of floating regfile reads -system.cpu0.fp_regfile_writes 922 # number of floating regfile writes -system.cpu0.misc_regfile_reads 47564974 # number of misc regfile reads -system.cpu0.misc_regfile_writes 527822 # number of misc regfile writes -system.cpu0.icache.replacements 405114 # number of replacements -system.cpu0.icache.tagsinuse 511.561657 # Cycle average of tags in use -system.cpu0.icache.total_refs 3991755 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 405626 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.840974 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 7272099000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.561657 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999144 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999144 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3991755 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3991755 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3991755 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3991755 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3991755 # number of overall hits -system.cpu0.icache.overall_hits::total 3991755 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 439070 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 439070 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 439070 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 439070 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 439070 # number of overall misses -system.cpu0.icache.overall_misses::total 439070 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7078203996 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7078203996 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7078203996 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7078203996 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7078203996 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7078203996 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4430825 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4430825 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4430825 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4430825 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4430825 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4430825 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099094 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.099094 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099094 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.099094 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099094 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.099094 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16120.900986 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 16120.900986 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16120.900986 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 16120.900986 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16120.900986 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 16120.900986 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1491997 # number of cycles access was blocked +system.cpu0.rob.rob_reads 77601886 # The number of ROB reads +system.cpu0.rob.rob_writes 77118702 # The number of ROB writes +system.cpu0.timesIdled 360842 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26846603 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 1938505291 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23756480 # Number of Instructions Simulated +system.cpu0.committedOps 31369479 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23756480 # Number of Instructions Simulated +system.cpu0.cpi 2.923596 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.923596 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.342045 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.342045 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 173851540 # number of integer regfile reads +system.cpu0.int_regfile_writes 34503400 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3265 # number of floating regfile reads +system.cpu0.fp_regfile_writes 914 # number of floating regfile writes +system.cpu0.misc_regfile_reads 46745590 # number of misc regfile reads +system.cpu0.misc_regfile_writes 520572 # number of misc regfile writes +system.cpu0.icache.replacements 396597 # number of replacements +system.cpu0.icache.tagsinuse 510.934010 # Cycle average of tags in use +system.cpu0.icache.total_refs 3914161 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 397109 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.856641 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 7097415000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.934010 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.997918 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.997918 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3914161 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3914161 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3914161 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3914161 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3914161 # number of overall hits +system.cpu0.icache.overall_hits::total 3914161 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 429060 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 429060 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 429060 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 429060 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 429060 # number of overall misses +system.cpu0.icache.overall_misses::total 429060 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5859924996 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5859924996 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5859924996 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5859924996 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5859924996 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5859924996 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4343221 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4343221 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4343221 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4343221 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4343221 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4343221 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.098788 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.098788 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.098788 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.098788 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.098788 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.098788 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13657.588673 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13657.588673 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13657.588673 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13657.588673 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13657.588673 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13657.588673 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2603 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 170 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 172 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 8776.452941 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.133721 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33429 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 33429 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 33429 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 33429 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 33429 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 33429 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 405641 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 405641 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 405641 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 405641 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 405641 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 405641 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5425368997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5425368997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5425368997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5425368997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5425368997 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5425368997 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8328000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8328000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8328000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8328000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.091550 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.091550 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.091550 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.091550 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.091550 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.091550 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13374.804315 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13374.804315 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13374.804315 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13374.804315 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13374.804315 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13374.804315 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31940 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 31940 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 31940 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 31940 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 31940 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 31940 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 397120 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 397120 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 397120 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 397120 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 397120 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 397120 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4781055496 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4781055496 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4781055496 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4781055496 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4781055496 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4781055496 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8271000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8271000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8271000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8271000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.091434 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.091434 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.091434 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.091434 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.091434 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.091434 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12039.321857 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12039.321857 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12039.321857 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12039.321857 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12039.321857 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12039.321857 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 275935 # number of replacements -system.cpu0.dcache.tagsinuse 476.765535 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9559328 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276447 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.579243 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 51426000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 476.765535 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.931183 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.931183 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5939119 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5939119 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3227738 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3227738 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174834 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 174834 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171593 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 171593 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9166857 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9166857 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9166857 # number of overall hits -system.cpu0.dcache.overall_hits::total 9166857 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 401304 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 401304 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1595717 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1595717 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8980 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8980 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7781 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7781 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1997021 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1997021 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1997021 # number of overall misses -system.cpu0.dcache.overall_misses::total 1997021 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7282608500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 7282608500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71716653343 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 71716653343 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 113510500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 113510500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 89966000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 89966000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 78999261843 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 78999261843 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 78999261843 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 78999261843 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6340423 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6340423 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4823455 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4823455 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183814 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183814 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179374 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 179374 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11163878 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11163878 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11163878 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11163878 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063293 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063293 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330824 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.330824 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048854 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048854 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043379 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043379 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178882 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.178882 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178882 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.178882 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18147.360854 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 18147.360854 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44943.215710 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44943.215710 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12640.367483 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12640.367483 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11562.267061 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11562.267061 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39558.553387 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39558.553387 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39558.553387 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39558.553387 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7775987 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1662000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1508 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 96 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 5156.490053 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 17312.500000 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 275715 # number of replacements +system.cpu0.dcache.tagsinuse 460.505640 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9383873 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276227 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.971599 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 50121000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 460.505640 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.899425 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.899425 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5832717 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5832717 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3162819 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3162819 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174349 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 174349 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171411 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 171411 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8995536 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8995536 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8995536 # number of overall hits +system.cpu0.dcache.overall_hits::total 8995536 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 389324 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 389324 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1581862 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1581862 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8809 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8809 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7464 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7464 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1971186 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1971186 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1971186 # number of overall misses +system.cpu0.dcache.overall_misses::total 1971186 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5380617500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5380617500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 64543979864 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 64543979864 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88840500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88840500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 65914500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 65914500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 69924597364 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 69924597364 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 69924597364 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 69924597364 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6222041 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6222041 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744681 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4744681 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183158 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 183158 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 178875 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 178875 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10966722 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10966722 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10966722 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10966722 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062572 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.062572 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333397 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333397 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048095 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048095 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.041727 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.041727 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.179742 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.179742 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.179742 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.179742 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13820.410506 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13820.410506 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40802.535154 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40802.535154 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10085.196958 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10085.196958 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8830.988746 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8830.988746 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35473.363429 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35473.363429 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35473.363429 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35473.363429 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 7710 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3643 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 580 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 95 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.293103 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 38.347368 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256111 # number of writebacks -system.cpu0.dcache.writebacks::total 256111 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 211639 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 211639 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1464558 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1464558 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 529 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 529 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1676197 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1676197 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1676197 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1676197 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189665 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189665 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131159 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131159 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8451 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8451 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7774 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7774 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 320824 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 320824 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 320824 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 320824 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2812273446 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2812273446 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4676498504 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4676498504 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79208005 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79208005 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 65545528 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 65545528 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7488771950 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7488771950 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7488771950 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7488771950 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13454662000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13454662000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1295219899 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1295219899 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14749881899 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14749881899 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029914 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029914 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027192 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027192 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045976 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045976 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043340 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043340 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028738 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028738 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028738 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028738 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14827.582559 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14827.582559 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35655.185721 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35655.185721 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9372.619217 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9372.619217 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8431.377412 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8431.377412 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23342.305906 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23342.305906 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23342.305906 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23342.305906 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256563 # number of writebacks +system.cpu0.dcache.writebacks::total 256563 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 201019 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 201019 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451459 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1451459 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 444 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 444 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1652478 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1652478 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1652478 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1652478 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188305 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188305 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130403 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130403 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8365 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8365 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7460 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7460 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 318708 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 318708 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 318708 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 318708 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2330576500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2330576500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4457768490 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4457768490 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67402500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 67402500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50994500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50994500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6788344990 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6788344990 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6788344990 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6788344990 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13509879500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13509879500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1216585395 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1216585395 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14726464895 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14726464895 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030264 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030264 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027484 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027484 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045671 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045671 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.041705 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.041705 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029061 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029061 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029061 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029061 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12376.604445 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12376.604445 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34184.554727 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34184.554727 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8057.680813 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8057.680813 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6835.723861 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6835.723861 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21299.575128 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21299.575128 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21299.575128 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21299.575128 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1081,27 +1077,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43437526 # DTB read hits -system.cpu1.dtb.read_misses 44897 # DTB read misses -system.cpu1.dtb.write_hits 7020721 # DTB write hits -system.cpu1.dtb.write_misses 11707 # DTB write misses +system.cpu1.dtb.read_hits 43128318 # DTB read hits +system.cpu1.dtb.read_misses 43709 # DTB read misses +system.cpu1.dtb.write_hits 6848528 # DTB write hits +system.cpu1.dtb.write_misses 11704 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2363 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 4220 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 316 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2308 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3032 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 376 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 641 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43482423 # DTB read accesses -system.cpu1.dtb.write_accesses 7032428 # DTB write accesses +system.cpu1.dtb.perms_faults 614 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43172027 # DTB read accesses +system.cpu1.dtb.write_accesses 6860232 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50458247 # DTB hits -system.cpu1.dtb.misses 56604 # DTB misses -system.cpu1.dtb.accesses 50514851 # DTB accesses -system.cpu1.itb.inst_hits 9182577 # ITB inst hits -system.cpu1.itb.inst_misses 6227 # ITB inst misses +system.cpu1.dtb.hits 49976846 # DTB hits +system.cpu1.dtb.misses 55413 # DTB misses +system.cpu1.dtb.accesses 50032259 # DTB accesses +system.cpu1.itb.inst_hits 9000425 # ITB inst hits +system.cpu1.itb.inst_misses 6008 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1110,538 +1106,542 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1587 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1553 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1649 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1639 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 9188804 # ITB inst accesses -system.cpu1.itb.hits 9182577 # DTB hits -system.cpu1.itb.misses 6227 # DTB misses -system.cpu1.itb.accesses 9188804 # DTB accesses -system.cpu1.numCycles 420121858 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 9006433 # ITB inst accesses +system.cpu1.itb.hits 9000425 # DTB hits +system.cpu1.itb.misses 6008 # DTB misses +system.cpu1.itb.accesses 9006433 # DTB accesses +system.cpu1.numCycles 411196854 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9688118 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 7965440 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 469703 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 6737081 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5659691 # Number of BTB hits +system.cpu1.BPredUnit.lookups 9419862 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 7750034 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 456519 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 6563236 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5515830 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 834304 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 51249 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 22081738 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 71759711 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9688118 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6493995 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 15294978 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4586075 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 88967 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 80951772 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5897 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 52783 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 142728 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 134 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 9180482 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 856181 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3761 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 121742103 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.711584 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.060066 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 808543 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 49558 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 20407169 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 70137907 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9419862 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6324373 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14954252 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4469714 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 69962 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 78537497 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4608 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 48031 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 137349 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 105 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8998373 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 846947 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3472 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 117207584 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.722166 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.072596 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 106455334 87.44% 87.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 840434 0.69% 88.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1014558 0.83% 88.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2075766 1.71% 90.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1622971 1.33% 92.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 608124 0.50% 92.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2270082 1.86% 94.37% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 458736 0.38% 94.75% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 6396098 5.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 102261187 87.25% 87.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 819653 0.70% 87.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 985556 0.84% 88.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2033886 1.74% 90.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1605966 1.37% 91.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 588504 0.50% 92.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2242580 1.91% 94.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 432923 0.37% 94.68% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 6237329 5.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 121742103 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.023060 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.170807 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 23726811 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 80682083 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 13746238 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 564864 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3022107 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1180909 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 102849 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 80937245 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 340282 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3022107 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 25270664 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33976360 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 42200569 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 12677087 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4595316 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 74576204 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 20275 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 711120 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3286160 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 33636 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 79110058 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 343673709 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 343614714 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 58995 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50196787 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 28913271 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 480316 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 419400 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8402630 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 14031046 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8540774 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1078770 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1484758 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 67259946 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1207834 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 91753969 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 112690 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 18841154 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 53684147 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 287920 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 121742103 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.753675 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.492082 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 117207584 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022908 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.170570 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 22086254 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 78170196 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 13474165 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 527031 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2949938 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1142917 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 100567 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 79224649 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 333390 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2949938 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 23604711 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 32726720 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 41122515 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 12389079 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4414621 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 72870010 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 19270 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 676690 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3162757 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 33999 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 77285870 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 335898709 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 335839792 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 58917 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49079142 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 28206728 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 460869 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 403889 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7994466 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13706939 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8341114 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1036889 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1489334 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 65799753 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1184242 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 90434427 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 105475 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 18495331 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 52692216 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 284904 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 117207584 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.771575 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.509324 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 89993106 73.92% 73.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 9114072 7.49% 81.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4553910 3.74% 85.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 4000568 3.29% 88.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10707495 8.80% 97.23% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1970764 1.62% 98.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1044074 0.86% 99.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 282783 0.23% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 75331 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 86216438 73.56% 73.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8629120 7.36% 80.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4443515 3.79% 84.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3900369 3.33% 88.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10705508 9.13% 97.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1918417 1.64% 98.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1028985 0.88% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 292713 0.25% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 72519 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 121742103 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 117207584 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 28572 0.36% 0.36% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 997 0.01% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7569076 95.94% 96.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 290938 3.69% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 27077 0.34% 0.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 994 0.01% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7551420 96.03% 96.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 284170 3.61% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 313802 0.34% 0.34% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 39340328 42.88% 43.22% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61412 0.07% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 6 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 3 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1696 0.00% 43.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 43.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.29% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 44630775 48.64% 91.93% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7405942 8.07% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 313737 0.35% 0.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 38536009 42.61% 42.96% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59463 0.07% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 3 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1448 0.00% 43.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 43.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.03% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 44313821 49.00% 92.03% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7209923 7.97% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 91753969 # Type of FU issued -system.cpu1.iq.rate 0.218398 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7889583 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.085986 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 313294010 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 87318397 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 55594578 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14739 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8070 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6796 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 99322053 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7697 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 360033 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 90434427 # Type of FU issued +system.cpu1.iq.rate 0.219930 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7863661 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.086954 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 306085964 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 85487883 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54343960 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14808 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8052 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6813 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 97976579 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7772 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 344186 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4037305 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 4422 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 18147 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1519259 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3955729 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 4256 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17131 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1493245 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31965400 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1049364 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31918877 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1021818 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3022107 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25590166 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 410250 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 68573370 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 132853 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 14031046 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8540774 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 897358 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 85617 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 14991 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 18147 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 245880 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 172266 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 418146 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 88914677 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43821187 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2839292 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2949938 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24820563 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 368762 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 67089139 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 132396 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13706939 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8341114 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 882128 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 65563 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3455 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17131 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 238596 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 168339 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 406935 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87595702 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43496570 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2838725 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 105590 # number of nop insts executed -system.cpu1.iew.exec_refs 51148287 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7278596 # Number of branches executed -system.cpu1.iew.exec_stores 7327100 # Number of stores executed -system.cpu1.iew.exec_rate 0.211640 # Inst execution rate -system.cpu1.iew.wb_sent 87750200 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 55601374 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30754041 # num instructions producing a value -system.cpu1.iew.wb_consumers 54503523 # num instructions consuming a value +system.cpu1.iew.exec_nop 105144 # number of nop insts executed +system.cpu1.iew.exec_refs 50630638 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7094868 # Number of branches executed +system.cpu1.iew.exec_stores 7134068 # Number of stores executed +system.cpu1.iew.exec_rate 0.213026 # Inst execution rate +system.cpu1.iew.wb_sent 86451134 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54350773 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30183399 # num instructions producing a value +system.cpu1.iew.wb_consumers 53726330 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.132346 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.564258 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.132177 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.561799 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 18816555 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 919914 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 368704 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 118768431 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.415231 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.371949 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 18453809 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 899338 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 357846 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 114304625 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.421644 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.382099 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 101503583 85.46% 85.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8523872 7.18% 92.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2201888 1.85% 94.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1303888 1.10% 95.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1288434 1.08% 96.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 587085 0.49% 97.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 997227 0.84% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 495127 0.42% 98.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1867327 1.57% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 97479553 85.28% 85.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8276936 7.24% 92.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2163829 1.89% 94.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1249082 1.09% 95.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1246649 1.09% 96.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 573488 0.50% 97.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1001794 0.88% 97.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 527131 0.46% 98.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1786163 1.56% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 118768431 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38949066 # Number of instructions committed -system.cpu1.commit.committedOps 49316340 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 114304625 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38098697 # Number of instructions committed +system.cpu1.commit.committedOps 48195861 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 17015256 # Number of memory references committed -system.cpu1.commit.loads 9993741 # Number of loads committed -system.cpu1.commit.membars 202364 # Number of memory barriers committed -system.cpu1.commit.branches 6138465 # Number of branches committed +system.cpu1.commit.refs 16599079 # Number of memory references committed +system.cpu1.commit.loads 9751210 # Number of loads committed +system.cpu1.commit.membars 196398 # Number of memory barriers committed +system.cpu1.commit.branches 5978782 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43706861 # Number of committed integer instructions. -system.cpu1.commit.function_calls 556456 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1867327 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42713997 # Number of committed integer instructions. +system.cpu1.commit.function_calls 536442 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1786163 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 183919327 # The number of ROB reads -system.cpu1.rob.rob_writes 139377269 # The number of ROB writes -system.cpu1.timesIdled 1519096 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 298379755 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4813097636 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38879427 # Number of Instructions Simulated -system.cpu1.committedOps 49246701 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38879427 # Number of Instructions Simulated -system.cpu1.cpi 10.805763 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.805763 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092543 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092543 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 397952991 # number of integer regfile reads -system.cpu1.int_regfile_writes 58412580 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4851 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2298 # number of floating regfile writes -system.cpu1.misc_regfile_reads 91535746 # number of misc regfile reads -system.cpu1.misc_regfile_writes 429838 # number of misc regfile writes -system.cpu1.icache.replacements 621848 # number of replacements -system.cpu1.icache.tagsinuse 498.728003 # Cycle average of tags in use -system.cpu1.icache.total_refs 8507924 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 622360 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.670422 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 75775782000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.728003 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974078 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974078 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 8507924 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 8507924 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 8507924 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 8507924 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 8507924 # number of overall hits -system.cpu1.icache.overall_hits::total 8507924 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 672506 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 672506 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 672506 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 672506 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 672506 # number of overall misses -system.cpu1.icache.overall_misses::total 672506 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10595189995 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 10595189995 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 10595189995 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 10595189995 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 10595189995 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 10595189995 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 9180430 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 9180430 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 9180430 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 9180430 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 9180430 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 9180430 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073254 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.073254 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073254 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.073254 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073254 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.073254 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15754.788797 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15754.788797 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15754.788797 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15754.788797 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15754.788797 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15754.788797 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1171995 # number of cycles access was blocked +system.cpu1.rob.rob_reads 178079063 # The number of ROB reads +system.cpu1.rob.rob_writes 136331127 # The number of ROB writes +system.cpu1.timesIdled 1409981 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 293989270 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1596154251 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38029058 # Number of Instructions Simulated +system.cpu1.committedOps 48126222 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38029058 # Number of Instructions Simulated +system.cpu1.cpi 10.812702 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.812702 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092484 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092484 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 391789649 # number of integer regfile reads +system.cpu1.int_regfile_writes 57184516 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4895 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes +system.cpu1.misc_regfile_reads 89371872 # number of misc regfile reads +system.cpu1.misc_regfile_writes 414539 # number of misc regfile writes +system.cpu1.icache.replacements 604043 # number of replacements +system.cpu1.icache.tagsinuse 477.396851 # Cycle average of tags in use +system.cpu1.icache.total_refs 8346622 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 604555 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.806224 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74944474500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 477.396851 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.932416 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.932416 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 8346622 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 8346622 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 8346622 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 8346622 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 8346622 # number of overall hits +system.cpu1.icache.overall_hits::total 8346622 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 651698 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 651698 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 651698 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 651698 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 651698 # number of overall misses +system.cpu1.icache.overall_misses::total 651698 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8706583495 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8706583495 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8706583495 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8706583495 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8706583495 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8706583495 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8998320 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8998320 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8998320 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8998320 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8998320 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8998320 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.072424 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.072424 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.072424 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.072424 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.072424 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.072424 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13359.843816 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13359.843816 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13359.843816 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13359.843816 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13359.843816 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13359.843816 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1860 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 180 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 164 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6511.083333 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.341463 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50115 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 50115 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 50115 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 50115 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 50115 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 50115 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 622391 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 622391 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 622391 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 622391 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 622391 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 622391 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8107387995 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8107387995 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8107387995 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8107387995 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8107387995 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8107387995 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3209000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3209000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3209000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3209000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067795 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067795 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067795 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.067795 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067795 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.067795 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13026.197350 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13026.197350 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13026.197350 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13026.197350 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13026.197350 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13026.197350 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 47118 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 47118 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 47118 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 47118 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 47118 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 47118 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 604580 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 604580 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 604580 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 604580 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 604580 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 604580 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7117577996 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7117577996 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7117577996 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7117577996 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7117577996 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7117577996 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3208500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3208500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3208500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 3208500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067188 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067188 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067188 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.067188 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067188 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.067188 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11772.764557 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11772.764557 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11772.764557 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11772.764557 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11772.764557 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11772.764557 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 364389 # number of replacements -system.cpu1.dcache.tagsinuse 487.304887 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13108660 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 364763 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 35.937472 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 71473892000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 487.304887 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.951767 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.951767 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8608527 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8608527 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4253626 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4253626 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105088 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 105088 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100770 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 100770 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12862153 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12862153 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12862153 # number of overall hits -system.cpu1.dcache.overall_hits::total 12862153 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 413506 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 413506 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1597634 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1597634 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14294 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14294 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10915 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10915 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 2011140 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 2011140 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 2011140 # number of overall misses -system.cpu1.dcache.overall_misses::total 2011140 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8210381000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 8210381000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 66162469729 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 66162469729 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 166851000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 166851000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 95119500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 95119500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 74372850729 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 74372850729 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 74372850729 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 74372850729 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9022033 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9022033 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5851260 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5851260 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 119382 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 119382 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111685 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 111685 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14873293 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14873293 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14873293 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14873293 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045833 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045833 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273041 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.273041 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119733 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119733 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097730 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097730 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135218 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135218 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135218 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135218 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19855.530512 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19855.530512 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41412.782733 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41412.782733 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11672.799776 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11672.799776 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8714.567109 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8714.567109 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 36980.444290 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 36980.444290 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 36980.444290 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 36980.444290 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 29857004 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5566500 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6768 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4411.495863 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 33133.928571 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 360631 # number of replacements +system.cpu1.dcache.tagsinuse 472.241123 # Cycle average of tags in use +system.cpu1.dcache.total_refs 12789913 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 361011 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.428042 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 71012585000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 472.241123 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.922346 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.922346 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8401496 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8401496 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4150430 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4150430 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 102060 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 102060 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 98301 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 98301 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12551926 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12551926 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12551926 # number of overall hits +system.cpu1.dcache.overall_hits::total 12551926 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 394540 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 394540 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1551061 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1551061 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14054 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14054 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10582 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10582 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1945601 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1945601 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1945601 # number of overall misses +system.cpu1.dcache.overall_misses::total 1945601 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5828870500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 5828870500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 56343693023 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 56343693023 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129108000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 129108000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 64979500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 64979500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 62172563523 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 62172563523 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 62172563523 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 62172563523 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8796036 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8796036 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5701491 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5701491 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 116114 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 116114 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 108883 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 108883 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14497527 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14497527 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14497527 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14497527 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044854 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.044854 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.272045 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.272045 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.121036 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.121036 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097187 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097187 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134202 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.134202 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134202 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.134202 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14773.839154 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14773.839154 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36325.904025 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 36325.904025 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9186.566102 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9186.566102 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6140.568891 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6140.568891 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31955.454136 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 31955.454136 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31955.454136 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 31955.454136 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 23777 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 10847 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3216 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 162 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.393346 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 66.956790 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 328923 # number of writebacks -system.cpu1.dcache.writebacks::total 328923 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 180962 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 180962 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1434656 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1434656 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1453 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1615618 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1615618 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1615618 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1615618 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 232544 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 232544 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162978 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 162978 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12841 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12841 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10909 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10909 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 395522 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 395522 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 395522 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 395522 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3583215887 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3583215887 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5542320073 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5542320073 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 104521007 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 104521007 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 61064509 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 61064509 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9125535960 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9125535960 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9125535960 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9125535960 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169307109000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169307109000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40930247169 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40930247169 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210237356169 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210237356169 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025775 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025775 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027853 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027853 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107562 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107562 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097677 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097677 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026593 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026593 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026593 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026593 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15408.765167 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15408.765167 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34006.553480 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34006.553480 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8139.631415 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8139.631415 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5597.626639 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5597.626639 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23072.132422 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23072.132422 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23072.132422 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23072.132422 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 325044 # number of writebacks +system.cpu1.dcache.writebacks::total 325044 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 165979 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 165979 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1389692 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1389692 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1430 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1430 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1555671 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1555671 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1555671 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1555671 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228561 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228561 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161369 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161369 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12624 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12624 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10579 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10579 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389930 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389930 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389930 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389930 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2788566500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2788566500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5142243728 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5142243728 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88146000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88146000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43823500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43823500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7930810228 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7930810228 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7930810228 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7930810228 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168983572500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168983572500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40847570579 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40847570579 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 209831143079 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 209831143079 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025985 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025985 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028303 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028303 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.108721 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.108721 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097159 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097159 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026896 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026896 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026896 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026896 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12200.535087 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12200.535087 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31866.366700 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31866.366700 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6982.414449 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6982.414449 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4142.499291 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4142.499291 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20339.061442 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20339.061442 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20339.061442 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20339.061442 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1663,18 +1663,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1322950372611 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1322950372611 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1322950372611 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1322950372611 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 479854932995 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 479854932995 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 479854932995 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 479854932995 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 43807 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 43104 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 53930 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 52217 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 2d955a00e..9bc6eb181 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.534231 # Number of seconds simulated -sim_ticks 2534231333000 # Number of ticks simulated -final_tick 2534231333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.534230 # Number of seconds simulated +sim_ticks 2534229746000 # Number of ticks simulated +final_tick 2534229746000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58448 # Simulator instruction rate (inst/s) -host_op_rate 75181 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2444289303 # Simulator tick rate (ticks/s) -host_mem_usage 386996 # Number of bytes of host memory used -host_seconds 1036.80 # Real time elapsed on the host -sim_insts 60598653 # Number of instructions simulated -sim_ops 77947265 # Number of ops (including micro ops) simulated +host_inst_rate 72788 # Simulator instruction rate (inst/s) +host_op_rate 93626 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3043970352 # Simulator tick rate (ticks/s) +host_mem_usage 380668 # Number of bytes of host memory used +host_seconds 832.54 # Real time elapsed on the host +sim_insts 60598794 # Number of instructions simulated +sim_ops 77947430 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 798016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094928 # Number of bytes read from this memory -system.physmem.bytes_read::total 129434320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9095568 # Number of bytes read from this memory +system.physmem.bytes_read::total 129434640 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 798016 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 798016 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784256 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 3784576 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800328 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800648 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 57 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 12469 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142142 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096877 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59129 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.data 142152 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096882 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59134 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813147 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47169200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1439 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813152 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47169229 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1313 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 314895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3588831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51074390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51074548 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 314895 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 314895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493256 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190133 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683389 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47169200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493383 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190134 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683517 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47169229 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1313 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 314895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4778964 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53757779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4779219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53758065 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -69,27 +69,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51729232 # DTB read hits -system.cpu.dtb.read_misses 76957 # DTB read misses -system.cpu.dtb.write_hits 11808980 # DTB write hits -system.cpu.dtb.write_misses 17307 # DTB write misses +system.cpu.dtb.read_hits 51729015 # DTB read hits +system.cpu.dtb.read_misses 77642 # DTB read misses +system.cpu.dtb.write_hits 11810988 # DTB write hits +system.cpu.dtb.write_misses 17459 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4248 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2685 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 493 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4269 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2642 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 530 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1359 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51806189 # DTB read accesses -system.cpu.dtb.write_accesses 11826287 # DTB write accesses +system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51806657 # DTB read accesses +system.cpu.dtb.write_accesses 11828447 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63538212 # DTB hits -system.cpu.dtb.misses 94264 # DTB misses -system.cpu.dtb.accesses 63632476 # DTB accesses -system.cpu.itb.inst_hits 13079160 # ITB inst hits -system.cpu.itb.inst_misses 12175 # ITB inst misses +system.cpu.dtb.hits 63540003 # DTB hits +system.cpu.dtb.misses 95101 # DTB misses +system.cpu.dtb.accesses 63635104 # DTB accesses +system.cpu.itb.inst_hits 13083995 # ITB inst hits +system.cpu.itb.inst_misses 12083 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -98,121 +98,121 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2600 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2591 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3091 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3112 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13091335 # ITB inst accesses -system.cpu.itb.hits 13079160 # DTB hits -system.cpu.itb.misses 12175 # DTB misses -system.cpu.itb.accesses 13091335 # DTB accesses -system.cpu.numCycles 475963827 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13096078 # ITB inst accesses +system.cpu.itb.hits 13083995 # DTB hits +system.cpu.itb.misses 12083 # DTB misses +system.cpu.itb.accesses 13096078 # DTB accesses +system.cpu.numCycles 475967538 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15173200 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12164115 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 783934 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10408500 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8322467 # Number of BTB hits +system.cpu.BPredUnit.lookups 15172784 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12163693 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 783478 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10392072 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8320250 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1454459 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 82493 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31372709 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 100925223 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15173200 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9776926 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22188702 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5931906 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 131502 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 97682240 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2742 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 97772 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 209251 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 367 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13075329 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1015161 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6456 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 155760556 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.799528 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.166845 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1454874 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 82640 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 31374160 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 100930999 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15172784 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9775124 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22189039 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5936170 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 131560 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 97680943 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2725 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 99805 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208737 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 364 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13080141 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1016234 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6355 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 155765235 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.799529 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.166844 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 133588722 85.77% 85.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1382794 0.89% 86.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1756872 1.13% 87.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2657278 1.71% 89.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2325995 1.49% 90.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1138064 0.73% 91.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2914708 1.87% 93.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 785042 0.50% 94.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9211081 5.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 133592933 85.77% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1382764 0.89% 86.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1755577 1.13% 87.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2658359 1.71% 89.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2327487 1.49% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1136384 0.73% 91.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2915896 1.87% 93.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 784165 0.50% 94.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9211670 5.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 155760556 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031879 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.212044 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 33510183 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 97305420 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20012915 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1028503 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3903535 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2022769 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174789 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 117637896 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 576974 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3903535 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 35608044 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37583370 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53602713 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18875511 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6187383 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110135538 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21282 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1015019 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4145584 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 32208 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 114982743 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 504362437 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 504271413 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 91024 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78733155 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36249587 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 891770 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797348 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12515452 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21000461 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13838053 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1958528 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2462024 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 100930109 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2057680 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126222278 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 188912 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24421115 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65012350 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 513116 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 155760556 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.810361 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.523302 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 155765235 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031878 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.212054 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33515539 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 97301422 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20013824 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1028268 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3906182 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2022458 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174763 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 117645711 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 578390 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3906182 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 35614317 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37590587 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53594123 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18875472 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6184554 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110140296 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21341 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1015182 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4143290 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 32170 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 114983026 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 504387694 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 504296628 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91066 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78733405 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36249620 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 891466 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797109 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12509806 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21006076 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13841580 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1961226 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2453000 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 100941360 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2057614 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126221061 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 189445 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24437015 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65086313 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 513058 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 155765235 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.810329 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.523325 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 110556788 70.98% 70.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13998731 8.99% 79.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7311876 4.69% 84.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6076948 3.90% 88.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12739380 8.18% 96.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2787527 1.79% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1678652 1.08% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 483348 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127306 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 110569920 70.98% 70.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13988875 8.98% 79.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7307591 4.69% 84.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6076063 3.90% 88.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12752921 8.19% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2780626 1.79% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1679008 1.08% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 481895 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128336 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 155760556 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 155765235 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57641 0.65% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 57759 0.65% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 2 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available @@ -241,13 +241,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8370517 94.61% 95.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 419308 4.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8370724 94.64% 95.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 416242 4.71% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59916595 47.47% 47.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95459 0.08% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59912166 47.47% 47.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95497 0.08% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued @@ -260,10 +260,10 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued @@ -271,365 +271,365 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53391379 42.30% 90.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12453015 9.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53392141 42.30% 90.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12455427 9.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126222278 # Type of FU issued -system.cpu.iq.rate 0.265193 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8847468 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070094 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 417312006 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 127425546 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87185779 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12560 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10301 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134693654 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12426 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624535 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126221061 # Type of FU issued +system.cpu.iq.rate 0.265188 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8844727 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070073 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 417312910 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 127452442 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87180232 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23310 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12552 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10294 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134689743 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12379 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 626582 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5283990 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7463 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30379 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2039233 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5289586 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7312 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30140 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2042757 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34106900 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1029053 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34106883 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1034668 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3903535 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28661313 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 449961 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103213314 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 232487 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21000461 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13838053 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1466210 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113940 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30379 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 409944 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 293507 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 703451 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 122976352 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52416933 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3245926 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3906182 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28670725 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 450645 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103223935 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 233802 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21006076 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13841580 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1466072 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 114504 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3680 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30140 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 409816 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 293009 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 702825 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 122971529 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52416599 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3249532 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 225525 # number of nop insts executed -system.cpu.iew.exec_refs 64738243 # number of memory reference insts executed -system.cpu.iew.exec_branches 11734992 # Number of branches executed -system.cpu.iew.exec_stores 12321310 # Number of stores executed -system.cpu.iew.exec_rate 0.258373 # Inst execution rate -system.cpu.iew.wb_sent 121627349 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87196080 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47712496 # num instructions producing a value -system.cpu.iew.wb_consumers 88865437 # num instructions consuming a value +system.cpu.iew.exec_nop 224961 # number of nop insts executed +system.cpu.iew.exec_refs 64739842 # number of memory reference insts executed +system.cpu.iew.exec_branches 11733959 # Number of branches executed +system.cpu.iew.exec_stores 12323243 # Number of stores executed +system.cpu.iew.exec_rate 0.258361 # Inst execution rate +system.cpu.iew.wb_sent 121621677 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87190526 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47712664 # num instructions producing a value +system.cpu.iew.wb_consumers 88871095 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.183199 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536907 # average fanout of values written-back +system.cpu.iew.wb_rate 0.183186 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536875 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24286652 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544564 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 612198 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151939453 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.514005 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.494998 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24296365 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544556 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 611758 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151941485 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.513999 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.495079 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 124139967 81.70% 81.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13583489 8.94% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3975420 2.62% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2135851 1.41% 94.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1949883 1.28% 95.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 999128 0.66% 96.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1578626 1.04% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 727876 0.48% 98.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2849213 1.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 124150656 81.71% 81.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13572481 8.93% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3978264 2.62% 93.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2132059 1.40% 94.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1949397 1.28% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 999089 0.66% 96.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1584839 1.04% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 727042 0.48% 98.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2847658 1.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151939453 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60749034 # Number of instructions committed -system.cpu.commit.committedOps 78097646 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151941485 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60749175 # Number of instructions committed +system.cpu.commit.committedOps 78097811 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27515291 # Number of memory references committed -system.cpu.commit.loads 15716471 # Number of loads committed +system.cpu.commit.refs 27515313 # Number of memory references committed +system.cpu.commit.loads 15716490 # Number of loads committed system.cpu.commit.membars 413125 # Number of memory barriers committed -system.cpu.commit.branches 10023270 # Number of branches committed +system.cpu.commit.branches 10023277 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69135938 # Number of committed integer instructions. +system.cpu.commit.int_insts 69136099 # Number of committed integer instructions. system.cpu.commit.function_calls 996018 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2849213 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 2847658 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 249559242 # The number of ROB reads -system.cpu.rob.rob_writes 208759201 # The number of ROB writes -system.cpu.timesIdled 1773088 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320203271 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4592410806 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60598653 # Number of Instructions Simulated -system.cpu.committedOps 77947265 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60598653 # Number of Instructions Simulated -system.cpu.cpi 7.854363 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.854363 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127318 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127318 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 556742712 # number of integer regfile reads -system.cpu.int_regfile_writes 89972066 # number of integer regfile writes +system.cpu.rob.rob_reads 249572720 # The number of ROB reads +system.cpu.rob.rob_writes 208783952 # The number of ROB writes +system.cpu.timesIdled 1774345 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320202303 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4592403923 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60598794 # Number of Instructions Simulated +system.cpu.committedOps 77947430 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60598794 # Number of Instructions Simulated +system.cpu.cpi 7.854406 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.854406 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127317 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127317 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 556725625 # number of integer regfile reads +system.cpu.int_regfile_writes 89967060 # number of integer regfile writes system.cpu.fp_regfile_reads 8371 # number of floating regfile reads -system.cpu.fp_regfile_writes 2922 # number of floating regfile writes -system.cpu.misc_regfile_reads 133101437 # number of misc regfile reads -system.cpu.misc_regfile_writes 912914 # number of misc regfile writes -system.cpu.icache.replacements 989669 # number of replacements -system.cpu.icache.tagsinuse 511.593818 # Cycle average of tags in use -system.cpu.icache.total_refs 12001618 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 990181 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.120630 # Average number of references to valid blocks. +system.cpu.fp_regfile_writes 2914 # number of floating regfile writes +system.cpu.misc_regfile_reads 133111894 # number of misc regfile reads +system.cpu.misc_regfile_writes 912902 # number of misc regfile writes +system.cpu.icache.replacements 989535 # number of replacements +system.cpu.icache.tagsinuse 511.594104 # Cycle average of tags in use +system.cpu.icache.total_refs 12006884 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 990047 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.127590 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6924990000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.593818 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 511.594104 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999207 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999207 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12001618 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12001618 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12001618 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12001618 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12001618 # number of overall hits -system.cpu.icache.overall_hits::total 12001618 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1073577 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1073577 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1073577 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1073577 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1073577 # number of overall misses -system.cpu.icache.overall_misses::total 1073577 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14108104991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14108104991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14108104991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14108104991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14108104991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14108104991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13075195 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13075195 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13075195 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13075195 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13075195 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13075195 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082108 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.082108 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.082108 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.082108 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.082108 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.082108 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13141.213896 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13141.213896 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13141.213896 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13141.213896 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13141.213896 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13141.213896 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2357994 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 12006884 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12006884 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12006884 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12006884 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12006884 # number of overall hits +system.cpu.icache.overall_hits::total 12006884 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1073125 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1073125 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1073125 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1073125 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1073125 # number of overall misses +system.cpu.icache.overall_misses::total 1073125 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14103457490 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14103457490 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14103457490 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14103457490 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14103457490 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14103457490 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13080009 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13080009 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13080009 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13080009 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13080009 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13080009 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082043 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.082043 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.082043 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.082043 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.082043 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.082043 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13142.418162 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13142.418162 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13142.418162 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13142.418162 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13142.418162 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13142.418162 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4497 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 295 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7993.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.244068 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 83350 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 83350 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 83350 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 83350 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 83350 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 83350 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 990227 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 990227 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 990227 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 990227 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 990227 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 990227 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11450107511 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11450107511 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11450107511 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11450107511 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11450107511 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11450107511 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 83043 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 83043 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 83043 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 83043 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 83043 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 83043 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 990082 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 990082 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 990082 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 990082 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 990082 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 990082 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11447874492 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11447874492 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11447874492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11447874492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11447874492 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11447874492 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7934000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7934000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7934000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7934000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075733 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075733 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075733 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075733 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075733 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075733 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11563.113822 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11563.113822 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11563.113822 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11563.113822 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11563.113822 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11563.113822 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075694 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075694 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075694 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075694 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075694 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075694 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11562.551882 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11562.551882 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11562.551882 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11562.551882 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11562.551882 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11562.551882 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 645165 # number of replacements +system.cpu.dcache.replacements 645234 # number of replacements system.cpu.dcache.tagsinuse 511.991712 # Cycle average of tags in use -system.cpu.dcache.total_refs 21796404 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 645677 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.757442 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 21791132 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 645746 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.745671 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 48877000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.991712 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13934718 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13934718 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7288473 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7288473 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 284342 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 284342 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285730 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285730 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21223191 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21223191 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21223191 # number of overall hits -system.cpu.dcache.overall_hits::total 21223191 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 726725 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 726725 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2962478 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2962478 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13561 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13561 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3689203 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3689203 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3689203 # number of overall misses -system.cpu.dcache.overall_misses::total 3689203 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9436874000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9436874000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104178007737 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104178007737 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180640000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 180640000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 370500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 370500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 113614881737 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 113614881737 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 113614881737 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 113614881737 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14661443 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14661443 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10250951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10250951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297903 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 297903 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285749 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285749 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24912394 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24912394 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24912394 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24912394 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049567 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049567 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288995 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288995 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045522 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045522 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000066 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000066 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148087 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.148087 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.148087 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.148087 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12985.481441 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12985.481441 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35165.833379 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35165.833379 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13320.551582 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13320.551582 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19500 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30796.592580 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30796.592580 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30796.592580 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30796.592580 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12775922 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7850000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2526 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5057.768013 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 27738.515901 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13929737 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13929737 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7288383 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7288383 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 284164 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 284164 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21218120 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21218120 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21218120 # number of overall hits +system.cpu.dcache.overall_hits::total 21218120 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 727325 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 727325 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2962578 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2962578 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13599 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13599 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3689903 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3689903 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3689903 # number of overall misses +system.cpu.dcache.overall_misses::total 3689903 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9441506500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9441506500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104195765238 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104195765238 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181224000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 181224000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 305500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 305500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 113637271738 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 113637271738 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 113637271738 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 113637271738 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14657062 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14657062 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10250961 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10250961 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297763 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 297763 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285742 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285742 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24908023 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24908023 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24908023 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24908023 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049623 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.049623 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289005 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289005 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045671 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045671 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000049 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000049 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148141 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148141 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148141 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148141 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12981.138418 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12981.138418 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35170.640313 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35170.640313 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13326.273991 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13326.273991 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21821.428571 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21821.428571 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30796.818165 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30796.818165 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30796.818165 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30796.818165 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 25623 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15683 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2532 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.119668 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 56.211470 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 609206 # number of writebacks -system.cpu.dcache.writebacks::total 609206 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 339325 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 339325 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713436 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713436 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1355 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1355 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3052761 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3052761 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3052761 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3052761 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387400 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 387400 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249042 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249042 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12206 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12206 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636442 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636442 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636442 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636442 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4757620458 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4757620458 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8541364957 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8541364957 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141415500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141415500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 332500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 332500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13298985415 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13298985415 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13298985415 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13298985415 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182407548000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182407548000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41944273253 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41944273253 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224351821253 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 224351821253 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026423 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026423 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024295 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024295 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040973 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040973 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000066 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000066 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025547 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025547 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025547 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12280.899479 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12280.899479 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34296.885493 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34296.885493 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11585.736523 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11585.736523 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17500 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20895.832480 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20895.832480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20895.832480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20895.832480 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 609265 # number of writebacks +system.cpu.dcache.writebacks::total 609265 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 339927 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 339927 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713517 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2713517 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1356 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1356 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3053444 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3053444 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3053444 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3053444 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387398 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 387398 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249061 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249061 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12243 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12243 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 636459 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 636459 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 636459 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 636459 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4758834000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4758834000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8540298916 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8540298916 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141913000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141913000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 277500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 277500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13299132916 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13299132916 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13299132916 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13299132916 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182407357500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182407357500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42045203371 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42045203371 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224452560871 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 224452560871 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024296 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024296 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041117 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041117 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000049 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000049 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025552 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025552 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025552 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025552 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12284.095426 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12284.095426 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34289.988862 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34289.988862 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11591.358327 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11591.358327 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19821.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19821.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20895.506099 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20895.506099 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20895.506099 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20895.506099 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -637,149 +637,149 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64397 # number of replacements -system.cpu.l2cache.tagsinuse 51351.941492 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1929097 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129792 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.862988 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2499029961500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36885.832563 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 46.221263 # Average occupied blocks per requestor +system.cpu.l2cache.replacements 64402 # number of replacements +system.cpu.l2cache.tagsinuse 51349.814622 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1928941 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129796 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.861329 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2499028808000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36883.442332 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 42.609278 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000238 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8173.888273 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6245.999155 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.562833 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000705 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 8182.264424 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6241.498349 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.562797 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000650 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.124724 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.095306 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783568 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 82917 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11882 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 976616 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 388806 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1460221 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 609206 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 609206 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 42 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112940 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112940 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 82917 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 11882 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 976616 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 501746 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1573161 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 82917 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 11882 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 976616 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 501746 # number of overall hits -system.cpu.l2cache.overall_hits::total 1573161 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 57 # number of ReadReq misses +system.cpu.l2cache.occ_percent::cpu.inst 0.124851 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.095238 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.783536 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 83718 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11792 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 976445 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 388833 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1460788 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 609265 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 609265 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 11 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 112992 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112992 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 83718 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 11792 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 976445 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 501825 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1573780 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 83718 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 11792 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 976445 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 501825 # number of overall hits +system.cpu.l2cache.overall_hits::total 1573780 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 52 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 12351 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10715 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23124 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2929 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2929 # number of UpgradeReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10724 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23128 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2917 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2917 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133216 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133216 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 57 # number of demand (read+write) misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133197 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133197 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 52 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 12351 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143931 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156340 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 57 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.data 143921 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156325 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 52 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 12351 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143931 # number of overall misses -system.cpu.l2cache.overall_misses::total 156340 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2991000 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.data 143921 # number of overall misses +system.cpu.l2cache.overall_misses::total 156325 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2722500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 657846996 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 563988998 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1224886994 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1254000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 1254000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7004496993 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7004496993 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2991000 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 657732500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 564471998 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1224986998 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1042500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 1042500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7003431498 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7003431498 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2722500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 657846996 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7568485991 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8229383987 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2991000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 657732500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7567903496 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8228418496 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2722500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 60000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 657846996 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7568485991 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8229383987 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 82974 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11883 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 988967 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 399521 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1483345 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 609206 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 609206 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2971 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2971 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 19 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246156 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246156 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 82974 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 11883 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 988967 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 645677 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1729501 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 82974 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 11883 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 988967 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 645677 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1729501 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000687 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000084 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012489 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026820 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015589 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985863 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985863 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.157895 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.157895 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541185 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541185 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000687 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000084 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012489 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.222915 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.090396 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000687 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000084 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012489 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.222915 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.090396 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52473.684211 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_latency::cpu.inst 657732500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7567903496 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8228418496 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 83770 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11793 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 988796 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 399557 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1483916 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 609265 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 609265 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2956 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2956 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 14 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 14 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246189 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246189 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 83770 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 11793 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 988796 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 645746 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1730105 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 83770 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 11793 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 988796 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 645746 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1730105 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000621 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000085 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012491 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026840 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015586 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986806 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986806 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541036 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541036 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000621 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000085 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012491 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.222876 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.090356 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000621 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000085 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012491 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.222876 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.090356 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52355.769231 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 60000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53262.650474 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52635.464116 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52970.376838 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 428.132468 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 428.132468 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52579.997846 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52579.997846 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52473.684211 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53253.380293 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52636.329541 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52965.539519 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 357.387727 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 357.387727 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52579.498772 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52579.498772 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52355.769231 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53262.650474 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52584.127054 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52637.738180 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52473.684211 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53253.380293 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52583.733409 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52636.612800 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52355.769231 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53262.650474 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52584.127054 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52637.738180 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53253.380293 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52583.733409 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52636.612800 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -788,8 +788,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59129 # number of writebacks -system.cpu.l2cache.writebacks::total 59129 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 59134 # number of writebacks +system.cpu.l2cache.writebacks::total 59134 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits @@ -799,98 +799,98 @@ system.cpu.l2cache.demand_mshr_hits::total 69 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 69 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 57 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 52 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12343 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10654 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23055 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2929 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2929 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10663 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23059 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2917 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2917 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133216 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133216 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 57 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133197 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133197 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 52 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 12343 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143870 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156271 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 57 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143860 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156256 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 52 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 12343 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143870 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156271 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2295000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 143860 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156256 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2087500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 48000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 506735998 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 431013999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 940092997 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 117171500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 117171500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 506591500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 431393998 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 940120998 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 116691500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 116691500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5362815995 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5362815995 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2295000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5361943498 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5361943498 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2087500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 48000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 506735998 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5793829994 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6302908992 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2295000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 506591500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5793337496 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6302064496 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2087500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 48000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 506735998 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5793829994 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6302908992 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 506591500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5793337496 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6302064496 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5292000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166730274500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166735566500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32529244761 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32529244761 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166730210500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166735502500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32612370999 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32612370999 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5292000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 199259519261 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 199264811261 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026667 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015543 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985863 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985863 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541185 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541185 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222820 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.090356 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222820 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.090356 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 199342581499 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 199347873499 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000621 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012483 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026687 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015539 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986806 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986806 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541036 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541036 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000621 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012483 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222781 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.090316 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000621 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012483 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222781 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.090316 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40144.230769 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41054.524670 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40455.603435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40776.100499 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40003.926255 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40003.926255 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41042.817791 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40457.094439 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40770.241468 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40003.942407 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40003.942407 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40256.545723 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40256.545723 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40255.737727 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40255.737727 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40144.230769 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41054.524670 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40271.286536 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40333.196767 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41042.817791 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40270.662422 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40331.664039 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40144.230769 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41054.524670 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40271.286536 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40333.196767 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41042.817791 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40270.662422 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40331.664039 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -914,16 +914,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307054297856 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1307054297856 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307054297856 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1307054297856 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307562103462 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1307562103462 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307562103462 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1307562103462 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88034 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88032 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 978d3ed52..908c82993 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,60 +1,60 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.125295 # Number of seconds simulated -sim_ticks 5125295451000 # Number of ticks simulated -final_tick 5125295451000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.133289 # Number of seconds simulated +sim_ticks 5133289198000 # Number of ticks simulated +final_tick 5133289198000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133696 # Simulator instruction rate (inst/s) -host_op_rate 264282 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1679641336 # Simulator tick rate (ticks/s) -host_mem_usage 368820 # Number of bytes of host memory used -host_seconds 3051.42 # Real time elapsed on the host -sim_insts 407963822 # Number of instructions simulated -sim_ops 806434654 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2463488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory +host_inst_rate 170996 # Simulator instruction rate (inst/s) +host_op_rate 338013 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2151657827 # Simulator tick rate (ticks/s) +host_mem_usage 361992 # Number of bytes of host memory used +host_seconds 2385.74 # Real time elapsed on the host +sim_insts 407952579 # Number of instructions simulated +sim_ops 806410876 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2466560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2496 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1076608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10836416 # Number of bytes read from this memory -system.physmem.bytes_read::total 14379776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1076608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1076608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9553280 # Number of bytes written to this memory -system.physmem.bytes_written::total 9553280 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38492 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1078720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10839424 # Number of bytes read from this memory +system.physmem.bytes_read::total 14387648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1078720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1078720 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9551232 # Number of bytes written to this memory +system.physmem.bytes_written::total 9551232 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38540 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 39 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16822 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 169319 # Number of read requests responded to by this memory -system.physmem.num_reads::total 224684 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149270 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149270 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 480653 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 549 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16855 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 169366 # Number of read requests responded to by this memory +system.physmem.num_reads::total 224807 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149238 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149238 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 480503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 486 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 210058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2114301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2805648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 210058 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 210058 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1863947 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1863947 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1863947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 480653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 210142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2111594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2802813 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 210142 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 210142 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1860646 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1860646 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1860646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 480503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 486 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 210058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2114301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4669595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 210142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2111594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4663458 # Total bandwidth to/from this memory (bytes/s) system.iocache.replacements 47577 # number of replacements -system.iocache.tagsinuse 0.091712 # Cycle average of tags in use +system.iocache.tagsinuse 0.116486 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 47593 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 4992311644000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.091712 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.005732 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.005732 # Average percentage of cache occupancy +system.iocache.occ_blocks::pc.south_bridge.ide 0.116486 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.007280 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.007280 # Average percentage of cache occupancy system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses system.iocache.ReadReq_misses::total 912 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses @@ -63,14 +63,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47632 system.iocache.demand_misses::total 47632 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses system.iocache.overall_misses::total 47632 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 138301932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 138301932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9924152160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9924152160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10062454092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10062454092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10062454092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10062454092 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 138482932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 138482932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9931610160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9931610160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10070093092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10070093092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10070093092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10070093092 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) @@ -87,19 +87,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 151646.855263 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 151646.855263 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212417.640411 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 212417.640411 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211254.074824 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 211254.074824 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211254.074824 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 211254.074824 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 71289012 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 151845.320175 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 151845.320175 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212577.272260 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 212577.272260 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211414.450202 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 211414.450202 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211414.450202 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 211414.450202 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 71516 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 8825 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 8861 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8078.075014 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.070872 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -113,14 +113,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90847000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 90847000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7494384978 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7494384978 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7585231978 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7585231978 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7585231978 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7585231978 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 91058932 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 91058932 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7502170160 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7502170160 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7593229092 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7593229092 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7593229092 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7593229092 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -129,14 +129,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 99612.938596 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 99612.938596 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160410.637372 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 160410.637372 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159246.556475 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 159246.556475 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159246.556475 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 159246.556475 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 99845.320175 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 99845.320175 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160577.272260 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 160577.272260 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159414.450202 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 159414.450202 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159414.450202 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 159414.450202 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -150,141 +150,141 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 448616710 # number of cpu cycles simulated +system.cpu.numCycles 448600431 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 86513922 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 86513922 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1185612 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 81821696 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79447101 # Number of BTB hits +system.cpu.BPredUnit.lookups 86509944 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86509944 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1185802 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 81830934 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79445705 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27982708 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 427301680 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86513922 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79447101 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 164025545 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5056665 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 120243 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 63002299 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36683 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 57009 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 294 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9269960 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 518545 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3708 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 259058563 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.256074 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.417846 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27983612 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 427293864 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86509944 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79445705 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 164022517 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5056605 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 118707 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 62987614 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36438 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 56602 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 319 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9268852 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 518204 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3676 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 259039385 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.256241 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.417856 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95463641 36.85% 36.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1593246 0.62% 37.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71955070 27.78% 65.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 970468 0.37% 65.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1621274 0.63% 66.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2451045 0.95% 67.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1124441 0.43% 67.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1422902 0.55% 68.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82456476 31.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95447322 36.85% 36.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1594478 0.62% 37.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71953209 27.78% 65.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 971457 0.38% 65.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1620147 0.63% 66.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2451072 0.95% 67.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1123457 0.43% 67.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1423255 0.55% 68.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82454988 31.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 259058563 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192846 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.952487 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31703593 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60473195 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159750936 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3297057 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3833782 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 840221922 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1208 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3833782 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34472569 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37379630 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10860587 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159949927 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12562068 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 836350803 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21427 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5922094 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4820401 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 7659 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 998159477 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1816297556 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1816296596 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 960 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964421570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33737900 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 466538 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 473424 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 28941579 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17313500 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10257423 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1154419 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 952791 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 829902104 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1256068 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824407567 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167070 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23703242 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36101298 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 203347 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 259058563 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.182321 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.385461 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 259039385 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192844 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.952504 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31701157 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60460157 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159747770 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3296725 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3833576 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 840199157 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1214 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3833576 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34469655 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37373675 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10858241 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159947646 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12556592 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 836331491 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21404 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5918645 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4820353 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 7887 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 998118157 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1816257155 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1816256355 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 800 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964383755 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33734395 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 466799 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 473697 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 28937943 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17313250 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10261817 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1158356 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 954062 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829878064 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1256439 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824382236 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167222 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23705426 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36106397 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 203573 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 259039385 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.182459 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.385421 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 72075437 27.82% 27.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15729256 6.07% 33.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10360511 4.00% 37.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7565386 2.92% 40.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75947592 29.32% 70.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3904357 1.51% 71.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72537575 28.00% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 784064 0.30% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 154385 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 72064876 27.82% 27.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15723846 6.07% 33.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10360482 4.00% 37.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7566572 2.92% 40.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75946167 29.32% 70.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3904049 1.51% 71.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72535410 28.00% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 783527 0.30% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 154456 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 259058563 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 259039385 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 356821 33.57% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 553408 52.07% 85.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 152587 14.36% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 355366 33.47% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 553588 52.14% 85.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 152800 14.39% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 305253 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796599749 96.63% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 305432 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 796570576 96.63% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued @@ -313,246 +313,246 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18032887 2.19% 98.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9469678 1.15% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18033245 2.19% 98.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9472983 1.15% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824407567 # Type of FU issued -system.cpu.iq.rate 1.837666 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1062816 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001289 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1909237330 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 854871180 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819733271 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 242 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 448 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 64 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 825165021 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 109 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1650397 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 824382236 # Type of FU issued +system.cpu.iq.rate 1.837676 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1061754 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001288 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1909166354 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 854849744 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819707401 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 374 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 65 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 825138441 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 117 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1650685 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3332196 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26785 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11385 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1841480 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3332850 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26850 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11358 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1844760 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932351 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 11661 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932315 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11695 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3833782 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26055488 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2116129 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 831158172 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 342184 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17313500 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10257423 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 725671 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1616608 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15691 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11385 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 710592 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 622404 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1332996 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822394271 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17607905 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2013295 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3833576 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26046353 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2116686 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 831134503 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 342849 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17313250 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10261817 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 725973 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1616805 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 16237 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11358 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 710415 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 622755 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1333170 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822369106 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17608498 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2013129 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26830923 # number of memory reference insts executed -system.cpu.iew.exec_branches 83287562 # Number of branches executed -system.cpu.iew.exec_stores 9223018 # Number of stores executed -system.cpu.iew.exec_rate 1.833178 # Inst execution rate -system.cpu.iew.wb_sent 821886032 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819733335 # cumulative count of insts written-back -system.cpu.iew.wb_producers 640537929 # num instructions producing a value -system.cpu.iew.wb_consumers 1046481965 # num instructions consuming a value +system.cpu.iew.exec_refs 26834247 # number of memory reference insts executed +system.cpu.iew.exec_branches 83283502 # Number of branches executed +system.cpu.iew.exec_stores 9225749 # Number of stores executed +system.cpu.iew.exec_rate 1.833188 # Inst execution rate +system.cpu.iew.wb_sent 821860005 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819707466 # cumulative count of insts written-back +system.cpu.iew.wb_producers 640500741 # num instructions producing a value +system.cpu.iew.wb_consumers 1046431080 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.827247 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.612087 # average fanout of values written-back +system.cpu.iew.wb_rate 1.827255 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.612081 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24617298 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1052719 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1189640 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255240182 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.159513 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.852385 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24617133 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1052864 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1189777 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 255221218 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.159655 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.852368 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 83212701 32.60% 32.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11927297 4.67% 37.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4018442 1.57% 38.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74971615 29.37% 68.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2476707 0.97% 69.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1494205 0.59% 69.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1000959 0.39% 70.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70934027 27.79% 97.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5204229 2.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 83203030 32.60% 32.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11920052 4.67% 37.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4017826 1.57% 38.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74972744 29.38% 68.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2476508 0.97% 69.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1494072 0.59% 69.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1000652 0.39% 70.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70934036 27.79% 97.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5202298 2.04% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255240182 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407963822 # Number of instructions committed -system.cpu.commit.committedOps 806434654 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 255221218 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407952579 # Number of instructions committed +system.cpu.commit.committedOps 806410876 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22397244 # Number of memory references committed -system.cpu.commit.loads 13981301 # Number of loads committed -system.cpu.commit.membars 473469 # Number of memory barriers committed -system.cpu.commit.branches 82197284 # Number of branches committed +system.cpu.commit.refs 22397454 # Number of memory references committed +system.cpu.commit.loads 13980397 # Number of loads committed +system.cpu.commit.membars 473477 # Number of memory barriers committed +system.cpu.commit.branches 82193415 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735369790 # Number of committed integer instructions. +system.cpu.commit.int_insts 735346024 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5204229 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5202298 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1081009655 # The number of ROB reads -system.cpu.rob.rob_writes 1665958243 # The number of ROB writes -system.cpu.timesIdled 1218536 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 189558147 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9801971615 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407963822 # Number of Instructions Simulated -system.cpu.committedOps 806434654 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407963822 # Number of Instructions Simulated -system.cpu.cpi 1.099648 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.099648 # CPI: Total CPI of All Threads -system.cpu.ipc 0.909382 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.909382 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1508373932 # number of integer regfile reads -system.cpu.int_regfile_writes 977906784 # number of integer regfile writes -system.cpu.fp_regfile_reads 64 # number of floating regfile reads -system.cpu.misc_regfile_reads 265175533 # number of misc regfile reads -system.cpu.misc_regfile_writes 402332 # number of misc regfile writes -system.cpu.icache.replacements 1068558 # number of replacements -system.cpu.icache.tagsinuse 510.894483 # Cycle average of tags in use -system.cpu.icache.total_refs 8130546 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1069070 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.605251 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 1080968615 # The number of ROB reads +system.cpu.rob.rob_writes 1665910047 # The number of ROB writes +system.cpu.timesIdled 1218526 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 189561046 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9817975385 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407952579 # Number of Instructions Simulated +system.cpu.committedOps 806410876 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407952579 # Number of Instructions Simulated +system.cpu.cpi 1.099639 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.099639 # CPI: Total CPI of All Threads +system.cpu.ipc 0.909390 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.909390 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1508324148 # number of integer regfile reads +system.cpu.int_regfile_writes 977861305 # number of integer regfile writes +system.cpu.fp_regfile_reads 65 # number of floating regfile reads +system.cpu.misc_regfile_reads 265169626 # number of misc regfile reads +system.cpu.misc_regfile_writes 402500 # number of misc regfile writes +system.cpu.icache.replacements 1068646 # number of replacements +system.cpu.icache.tagsinuse 510.896112 # Cycle average of tags in use +system.cpu.icache.total_refs 8129454 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1069158 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.603604 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 56547532000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.894483 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997841 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997841 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8130546 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8130546 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8130546 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8130546 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8130546 # number of overall hits -system.cpu.icache.overall_hits::total 8130546 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1139410 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1139410 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1139410 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1139410 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1139410 # number of overall misses -system.cpu.icache.overall_misses::total 1139410 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15243937992 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15243937992 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15243937992 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15243937992 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15243937992 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15243937992 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9269956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9269956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9269956 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9269956 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9269956 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9269956 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122914 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.122914 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.122914 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.122914 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.122914 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.122914 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13378.799547 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13378.799547 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13378.799547 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13378.799547 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13378.799547 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13378.799547 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2477494 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 510.896112 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997844 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997844 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8129454 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8129454 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8129454 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8129454 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8129454 # number of overall hits +system.cpu.icache.overall_hits::total 8129454 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1139394 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1139394 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1139394 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1139394 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1139394 # number of overall misses +system.cpu.icache.overall_misses::total 1139394 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15246811490 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15246811490 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15246811490 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15246811490 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15246811490 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15246811490 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9268848 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9268848 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9268848 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9268848 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9268848 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9268848 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122927 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.122927 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.122927 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.122927 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.122927 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.122927 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13381.509373 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13381.509373 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13381.509373 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13381.509373 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13381.509373 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13381.509373 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5114 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 254 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 262 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 9753.913386 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.519084 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68152 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68152 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68152 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68152 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68152 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68152 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1071258 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1071258 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1071258 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1071258 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1071258 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1071258 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12539776496 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12539776496 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12539776496 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12539776496 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12539776496 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12539776496 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115562 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115562 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115562 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.115562 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115562 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.115562 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11705.654937 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11705.654937 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11705.654937 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11705.654937 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11705.654937 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11705.654937 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68044 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 68044 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 68044 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 68044 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 68044 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 68044 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1071350 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1071350 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1071350 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1071350 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1071350 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1071350 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12542463990 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12542463990 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12542463990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12542463990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12542463990 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12542463990 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115586 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115586 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115586 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.115586 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115586 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.115586 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11707.158249 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11707.158249 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11707.158249 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11707.158249 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11707.158249 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11707.158249 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 9803 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.028064 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 28000 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 9816 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.852486 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5098956249000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.028064 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376754 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.376754 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 28010 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 28010 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 9707 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.043772 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 27693 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 9719 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.849367 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5100157918000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.043772 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.377736 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.377736 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 27843 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 27843 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 28013 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 28013 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 28013 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 28013 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10692 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 10692 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10692 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 10692 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10692 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 10692 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 117857500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 117857500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 117857500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 117857500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 117857500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 117857500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38702 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 38702 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 27846 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 27846 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 27846 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 27846 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10592 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 10592 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10592 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 10592 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10592 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 10592 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 116124000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 116124000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 116124000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 116124000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 116124000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 116124000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38435 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 38435 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38705 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 38705 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38705 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 38705 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.276265 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.276265 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.276243 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.276243 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.276243 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.276243 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11022.961092 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11022.961092 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11022.961092 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11022.961092 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11022.961092 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11022.961092 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38438 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 38438 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38438 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 38438 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.275582 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.275582 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.275561 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.275561 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.275561 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.275561 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10963.368580 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10963.368580 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10963.368580 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10963.368580 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10963.368580 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10963.368580 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -561,78 +561,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1616 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1616 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10692 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10692 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10692 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10692 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10692 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 10692 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 96471005 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 96471005 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 96471005 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 96471005 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 96471005 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 96471005 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.276265 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.276265 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.276243 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.276243 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.276243 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.276243 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9022.727740 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9022.727740 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9022.727740 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9022.727740 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9022.727740 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9022.727740 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1540 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1540 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10592 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10592 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10592 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10592 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10592 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 10592 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 94940000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 94940000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 94940000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 94940000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 94940000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 94940000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.275582 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.275582 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.275561 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.275561 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.275561 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.275561 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8963.368580 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8963.368580 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8963.368580 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8963.368580 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8963.368580 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8963.368580 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 109091 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 11.986906 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 138731 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 109107 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.271513 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.replacements 107637 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 11.991971 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 139374 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 107653 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.294660 # Average number of references to valid blocks. system.cpu.dtb_walker_cache.warmup_cycle 5096875914000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 11.986906 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.749182 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.749182 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 138731 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 138731 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 138731 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 138731 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 138731 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 138731 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110113 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 110113 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110113 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 110113 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110113 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 110113 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1378090500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1378090500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1378090500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1378090500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1378090500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1378090500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 248844 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 248844 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 248844 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 248844 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 248844 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 248844 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.442498 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.442498 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.442498 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.442498 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.442498 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.442498 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12515.238891 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12515.238891 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12515.238891 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12515.238891 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12515.238891 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12515.238891 # average overall miss latency +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 11.991971 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.749498 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.749498 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 139374 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 139374 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 139374 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 139374 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 139374 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 139374 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 108671 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 108671 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 108671 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 108671 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 108671 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 108671 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1362724500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1362724500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1362724500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1362724500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1362724500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1362724500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 248045 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 248045 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 248045 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 248045 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 248045 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 248045 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.438110 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.438110 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.438110 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.438110 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.438110 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.438110 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12539.909451 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12539.909451 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12539.909451 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12539.909451 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12539.909451 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12539.909451 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,146 +641,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 32856 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 32856 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110113 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110113 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110113 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 110113 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110113 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 110113 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1157860508 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1157860508 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1157860508 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1157860508 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1157860508 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1157860508 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.442498 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.442498 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.442498 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.442498 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.442498 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.442498 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10515.202637 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10515.202637 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10515.202637 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10515.202637 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10515.202637 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10515.202637 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 32720 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 32720 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 108671 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 108671 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 108671 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 108671 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 108671 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 108671 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1145382500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1145382500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1145382500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1145382500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1145382500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1145382500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.438110 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.438110 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.438110 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.438110 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.438110 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.438110 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10539.909451 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10539.909451 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10539.909451 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10539.909451 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10539.909451 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10539.909451 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1673200 # number of replacements -system.cpu.dcache.tagsinuse 511.995281 # Cycle average of tags in use -system.cpu.dcache.total_refs 19218602 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1673712 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.482622 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1673658 # number of replacements +system.cpu.dcache.tagsinuse 511.992942 # Cycle average of tags in use +system.cpu.dcache.total_refs 19220297 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1674170 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.480493 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 32836000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.995281 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11125713 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11125713 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8087784 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8087784 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19213497 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19213497 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19213497 # number of overall hits -system.cpu.dcache.overall_hits::total 19213497 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2270273 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2270273 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318926 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318926 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2589199 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2589199 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2589199 # number of overall misses -system.cpu.dcache.overall_misses::total 2589199 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31735107000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31735107000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9818389991 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9818389991 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41553496991 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41553496991 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41553496991 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41553496991 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13395986 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13395986 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8406710 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8406710 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21802696 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21802696 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21802696 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21802696 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169474 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.169474 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037937 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037937 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118756 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118756 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118756 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118756 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13978.542228 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13978.542228 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30785.793541 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30785.793541 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16048.784582 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16048.784582 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16048.784582 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16048.784582 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 182917491 # number of cycles access was blocked +system.cpu.dcache.occ_blocks::cpu.data 511.992942 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 11126575 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11126575 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8088656 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8088656 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19215231 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19215231 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19215231 # number of overall hits +system.cpu.dcache.overall_hits::total 19215231 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2269640 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2269640 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 319173 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 319173 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2588813 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2588813 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2588813 # number of overall misses +system.cpu.dcache.overall_misses::total 2588813 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31726602500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31726602500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9823121491 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9823121491 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41549723991 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41549723991 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41549723991 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41549723991 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13396215 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13396215 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8407829 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8407829 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21804044 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21804044 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21804044 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21804044 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169424 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.169424 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037961 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037961 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118731 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118731 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118731 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118731 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13978.693758 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13978.693758 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30776.793435 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30776.793435 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16049.720081 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16049.720081 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16049.720081 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16049.720081 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 366322 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42914 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42954 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4262.419979 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.528240 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1573634 # number of writebacks -system.cpu.dcache.writebacks::total 1573634 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 885029 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 885029 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26052 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 26052 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 911081 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 911081 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 911081 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 911081 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1385244 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1385244 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292874 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 292874 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1678118 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1678118 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1678118 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1678118 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17081753038 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17081753038 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8984344493 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8984344493 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26066097531 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26066097531 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26066097531 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26066097531 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296526000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296526000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469883000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469883000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99766409000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99766409000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103407 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103407 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034838 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034838 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076968 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076968 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076968 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076968 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12331.223263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12331.223263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30676.483720 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30676.483720 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15532.934830 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15532.934830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15532.934830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15532.934830 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1573837 # number of writebacks +system.cpu.dcache.writebacks::total 1573837 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 884183 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 884183 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26057 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 26057 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 910240 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 910240 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 910240 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 910240 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1385457 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1385457 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 293116 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 293116 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1678573 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1678573 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1678573 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1678573 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17084942000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17084942000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8988357491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8988357491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26073299491 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26073299491 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26073299491 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26073299491 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296962500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296962500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470375500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470375500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767338000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767338000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103422 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103422 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034862 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034862 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076984 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076984 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076984 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076984 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12331.629202 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12331.629202 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30664.847675 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30664.847675 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15533.014942 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15533.014942 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15533.014942 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15533.014942 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -788,141 +788,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 113744 # number of replacements -system.cpu.l2cache.tagsinuse 64832.774955 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3973830 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 177660 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.367612 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 113860 # number of replacements +system.cpu.l2cache.tagsinuse 64830.724160 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3973813 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 177772 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.353425 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 50148.563193 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 11.721741 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.159900 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3217.931386 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 11454.398735 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.765206 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 50128.354504 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 11.733619 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.162766 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3228.532252 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 11461.941019 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.764898 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000179 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.049102 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.174780 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989270 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 102638 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8131 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1052204 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1346999 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2509972 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1608106 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1608106 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 331 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 331 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 155908 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 155908 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 102638 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 8131 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1052204 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1502907 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2665880 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 102638 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 8131 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1052204 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1502907 # number of overall hits -system.cpu.l2cache.overall_hits::total 2665880 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 44 # number of ReadReq misses +system.cpu.l2cache.occ_percent::cpu.inst 0.049263 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.174895 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.989238 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 101628 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7965 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1052257 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1347205 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2509055 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1608097 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1608097 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 328 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 328 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 156120 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 156120 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 101628 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 7965 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1052257 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1503325 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2665175 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 101628 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 7965 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1052257 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1503325 # number of overall hits +system.cpu.l2cache.overall_hits::total 2665175 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 39 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16823 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 37139 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 54013 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3584 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3584 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133122 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133122 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 44 # number of demand (read+write) misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 16857 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 37156 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 54059 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 3590 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 3590 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133151 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133151 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 39 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16823 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 170261 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 187135 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 44 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 16857 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 170307 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 187210 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 39 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16823 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 170261 # number of overall misses -system.cpu.l2cache.overall_misses::total 187135 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2320000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 364500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 893498997 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1994669499 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2890852996 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 37408500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 37408500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6938452500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6938452500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2320000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 364500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 893498997 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8933121999 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9829305496 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2320000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 364500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 893498997 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8933121999 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9829305496 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 102682 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8138 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1069027 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1384138 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2563985 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1608106 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1608106 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3915 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 3915 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 289030 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 289030 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 102682 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 8138 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1069027 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1673168 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2853015 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 102682 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 8138 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1069027 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1673168 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2853015 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000429 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000860 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.015737 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026832 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021066 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.915453 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.915453 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.460582 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.460582 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000429 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000860 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.015737 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.101760 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.065592 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000429 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000860 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.015737 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.101760 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.065592 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52727.272727 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52071.428571 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53111.751590 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53708.217750 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53521.429952 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 10437.639509 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 10437.639509 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52121.005544 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52121.005544 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52727.272727 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52071.428571 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53111.751590 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52467.223845 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52525.211724 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52727.272727 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52071.428571 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53111.751590 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52467.223845 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52525.211724 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.inst 16857 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 170307 # number of overall misses +system.cpu.l2cache.overall_misses::total 187210 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2058500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 371500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 895435000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1995543998 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2893408998 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 37772999 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 37772999 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6939920000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6939920000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2058500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 371500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 895435000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8935463998 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9833328998 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2058500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 371500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 895435000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8935463998 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9833328998 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 101667 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7972 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1069114 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1384361 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2563114 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1608097 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1608097 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3918 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 3918 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 289271 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 289271 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 101667 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 7972 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1069114 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1673632 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2852385 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 101667 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 7972 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1069114 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1673632 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2852385 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000384 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000878 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.015767 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026840 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021091 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.916284 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.916284 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.460298 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.460298 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000384 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000878 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.015767 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.101759 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.065633 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000384 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000878 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.015767 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.101759 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.065633 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52782.051282 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 53071.428571 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53119.475589 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53707.180482 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53523.169093 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 10521.726741 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 10521.726741 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52120.675023 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52120.675023 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52782.051282 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 53071.428571 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53119.475589 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52466.804054 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52525.661012 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52782.051282 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 53071.428571 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53119.475589 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52466.804054 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52525.661012 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -931,99 +931,99 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 102603 # number of writebacks -system.cpu.l2cache.writebacks::total 102603 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 102571 # number of writebacks +system.cpu.l2cache.writebacks::total 102571 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 44 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 39 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16822 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 37137 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 54010 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3584 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 3584 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133122 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133122 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 44 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16855 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 37154 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 54055 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3590 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 3590 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133151 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133151 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 39 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16822 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 170259 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 187132 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 44 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16855 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 170305 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 187206 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 39 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16822 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 170259 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 187132 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1782000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 688158999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1540337500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2230558499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 143814000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 143814000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5332275500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5332275500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1782000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 688158999 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6872613000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7562833999 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1782000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 688158999 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6872613000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7562833999 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89185334000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89185334000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2304322500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2304322500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91489656500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91489656500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000429 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000860 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015736 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026830 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021065 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.915453 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.915453 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.460582 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.460582 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000429 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000860 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015736 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16855 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 170305 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 187206 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1582000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 287000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 689639500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1541128498 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2232636998 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 144031499 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 144031499 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5333340000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5333340000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1582000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 287000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 689639500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6874468498 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7565976998 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1582000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 287000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 689639500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6874468498 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7565976998 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89185727000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89185727000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2304773500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2304773500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91490500500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91490500500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000384 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000878 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015765 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026838 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021090 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.916284 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.916284 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.460298 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.460298 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000384 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000878 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015765 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101758 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.065591 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000429 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000860 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015736 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.065631 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000384 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000878 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015765 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101758 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.065591 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40908.274819 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41477.165630 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41298.990909 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40126.674107 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40126.674107 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40055.554304 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40055.554304 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40908.274819 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40365.637059 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40414.434725 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40908.274819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40365.637059 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40414.434725 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.065631 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40564.102564 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40916.018985 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41479.477257 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41303.061659 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40120.194708 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40120.194708 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40054.824973 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40054.824973 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40564.102564 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40916.018985 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40365.629300 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40415.248432 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40564.102564 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40916.018985 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40365.629300 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40415.248432 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt index 80abd3d9c..e69de29bb 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt @@ -1,133 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.116889 # Number of seconds simulated -sim_ticks 2233777512 # Number of ticks simulated -final_tick 2233777512 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 2000000000 # Frequency of simulated ticks -host_inst_rate 3140005 # Simulator instruction rate (inst/s) -host_op_rate 3141240 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3147745 # Simulator tick rate (ticks/s) -host_mem_usage 511524 # Number of bytes of host memory used -host_seconds 709.64 # Real time elapsed on the host -sim_insts 2228284650 # Number of instructions simulated -sim_ops 2229160714 # Number of ops (including micro ops) simulated -system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory -system.hypervisor_desc.bytes_read::total 16792 # Number of bytes read from this memory -system.hypervisor_desc.num_reads::cpu.data 9024 # Number of read requests responded to by this memory -system.hypervisor_desc.num_reads::total 9024 # Number of read requests responded to by this memory -system.hypervisor_desc.bw_read::cpu.data 15035 # Total read bandwidth from this memory (bytes/s) -system.hypervisor_desc.bw_read::total 15035 # Total read bandwidth from this memory (bytes/s) -system.hypervisor_desc.bw_total::cpu.data 15035 # Total bandwidth to/from this memory (bytes/s) -system.hypervisor_desc.bw_total::total 15035 # Total bandwidth to/from this memory (bytes/s) -system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory -system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory -system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory -system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory -system.partition_desc.bw_read::cpu.data 4339 # Total read bandwidth from this memory (bytes/s) -system.partition_desc.bw_read::total 4339 # Total read bandwidth from this memory (bytes/s) -system.partition_desc.bw_total::cpu.data 4339 # Total bandwidth to/from this memory (bytes/s) -system.partition_desc.bw_total::total 4339 # Total bandwidth to/from this memory (bytes/s) -system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory -system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory -system.rom.bytes_read::total 1128688 # Number of bytes read from this memory -system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory -system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory -system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory -system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory -system.rom.num_reads::total 195123 # Number of read requests responded to by this memory -system.rom.bw_read::cpu.inst 387054 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_read::cpu.data 623511 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_read::total 1010564 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_inst_read::cpu.inst 387054 # Instruction read bandwidth from this memory (bytes/s) -system.rom.bw_inst_read::total 387054 # Instruction read bandwidth from this memory (bytes/s) -system.rom.bw_total::cpu.inst 387054 # Total bandwidth to/from this memory (bytes/s) -system.rom.bw_total::cpu.data 623511 # Total bandwidth to/from this memory (bytes/s) -system.rom.bw_total::total 1010564 # Total bandwidth to/from this memory (bytes/s) -system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory -system.nvram.bytes_read::total 284 # Number of bytes read from this memory -system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory -system.nvram.bytes_written::total 92 # Number of bytes written to this memory -system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory -system.nvram.num_reads::total 284 # Number of read requests responded to by this memory -system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory -system.nvram.num_writes::total 92 # Number of write requests responded to by this memory -system.nvram.bw_read::cpu.data 254 # Total read bandwidth from this memory (bytes/s) -system.nvram.bw_read::total 254 # Total read bandwidth from this memory (bytes/s) -system.nvram.bw_write::cpu.data 82 # Write bandwidth from this memory (bytes/s) -system.nvram.bw_write::total 82 # Write bandwidth from this memory (bytes/s) -system.nvram.bw_total::cpu.data 337 # Total bandwidth to/from this memory (bytes/s) -system.nvram.bw_total::total 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 97534024 # Number of bytes read from this memory -system.physmem.bytes_read::total 709825348 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 612291324 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 612291324 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 15400223 # Number of bytes written to this memory -system.physmem.bytes_written::total 15400223 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 153072831 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 12152054 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165224885 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 1927067 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1927067 # Number of write requests responded to by this memory -system.physmem.num_other::cpu.data 14 # Number of other requests responded to by this memory -system.physmem.num_other::total 14 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 548211557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 87326534 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 635538091 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 548211557 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 548211557 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 13788502 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13788502 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 548211557 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 101115036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 649326593 # Total bandwidth to/from this memory (bytes/s) -system.physmem2.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory -system.physmem2.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory -system.physmem2.bytes_read::total 9813991967 # Number of bytes read from this memory -system.physmem2.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory -system.physmem2.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory -system.physmem2.bytes_written::cpu.data 897268422 # Number of bytes written to this memory -system.physmem2.bytes_written::total 897268422 # Number of bytes written to this memory -system.physmem2.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory -system.physmem2.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory -system.physmem2.num_reads::total 2403489130 # Number of read requests responded to by this memory -system.physmem2.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory -system.physmem2.num_writes::total 187387796 # Number of write requests responded to by this memory -system.physmem2.num_other::cpu.data 5403067 # Number of other requests responded to by this memory -system.physmem2.num_other::total 5403067 # Number of other requests responded to by this memory -system.physmem2.bw_read::cpu.inst 7447569684 # Total read bandwidth from this memory (bytes/s) -system.physmem2.bw_read::cpu.data 1339332247 # Total read bandwidth from this memory (bytes/s) -system.physmem2.bw_read::total 8786901931 # Total read bandwidth from this memory (bytes/s) -system.physmem2.bw_inst_read::cpu.inst 7447569684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem2.bw_inst_read::total 7447569684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem2.bw_write::cpu.data 803364182 # Write bandwidth from this memory (bytes/s) -system.physmem2.bw_write::total 803364182 # Write bandwidth from this memory (bytes/s) -system.physmem2.bw_total::cpu.inst 7447569684 # Total bandwidth to/from this memory (bytes/s) -system.physmem2.bw_total::cpu.data 2142696429 # Total bandwidth to/from this memory (bytes/s) -system.physmem2.bw_total::total 9590266113 # Total bandwidth to/from this memory (bytes/s) -system.cpu.numCycles 2233777513 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2228284650 # Number of instructions committed -system.cpu.committedOps 2229160714 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1839325658 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses -system.cpu.num_func_calls 44037246 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 316367761 # number of instructions that are conditional controls -system.cpu.num_int_insts 1839325658 # number of integer instructions -system.cpu.num_fp_insts 14608322 # number of float instructions -system.cpu.num_int_register_reads 4305540407 # number of times the integer registers were read -system.cpu.num_int_register_writes 2100562807 # number of times the integer registers were written -system.cpu.num_fp_register_reads 35401841 # number of times the floating registers were read -system.cpu.num_fp_register_writes 22917558 # number of times the floating registers were written -system.cpu.num_mem_refs 547951940 # number of memory refs -system.cpu.num_load_insts 349807670 # Number of load instructions -system.cpu.num_store_insts 198144270 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2233777513 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 011acdd4e..182ad7ea2 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.271545 # Nu sim_ticks 271544682500 # Number of ticks simulated final_tick 271544682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105483 # Simulator instruction rate (inst/s) -host_op_rate 105483 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47591638 # Simulator tick rate (ticks/s) -host_mem_usage 219440 # Number of bytes of host memory used -host_seconds 5705.72 # Real time elapsed on the host +host_inst_rate 142205 # Simulator instruction rate (inst/s) +host_op_rate 142205 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64159611 # Simulator tick rate (ticks/s) +host_mem_usage 212920 # Number of bytes of host memory used +host_seconds 4232.33 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -181,11 +181,11 @@ system.cpu.icache.demand_avg_miss_latency::total 55134.540117 system.cpu.icache.overall_avg_miss_latency::cpu.inst 55134.540117 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 55134.540117 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 175 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 58.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits @@ -276,12 +276,12 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 14281.915545 system.cpu.dcache.demand_avg_miss_latency::total 14281.915545 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 14281.915545 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 14281.915545 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21072500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2046602500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 42145 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4093205 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3164 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 211457 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6660.082174 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9678.575313 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.320164 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19.357151 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks @@ -410,11 +410,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 56646.117674 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54104.637337 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56730.545900 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 56646.117674 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 108500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 217 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 13562.500000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 27.125000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 73ec0cee6..66988a872 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.133202 # Nu sim_ticks 133202081500 # Number of ticks simulated final_tick 133202081500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 189557 # Simulator instruction rate (inst/s) -host_op_rate 189557 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44645563 # Simulator tick rate (ticks/s) -host_mem_usage 220464 # Number of bytes of host memory used -host_seconds 2983.55 # Real time elapsed on the host +host_inst_rate 258977 # Simulator instruction rate (inst/s) +host_op_rate 258977 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60995759 # Simulator tick rate (ticks/s) +host_mem_usage 213944 # Number of bytes of host memory used +host_seconds 2183.79 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory @@ -480,12 +480,12 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 7340.245420 system.cpu.dcache.demand_avg_miss_latency::total 7340.245420 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 7340.245420 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 7340.245420 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 483496 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 206500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 963 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 413 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 102 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4740.156863 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18772.727273 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.441176 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 37.545455 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 444931 # number of writebacks @@ -571,14 +571,14 @@ system.cpu.l2cache.overall_misses::total 26388 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 34437000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 148748500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 183185500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 844656996 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 844656996 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 844655000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 844655000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 34437000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 993405496 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1027842496 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 993403500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1027840500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 34437000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 993405496 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1027842496 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 993403500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1027840500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 979 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 210276 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 211255 # number of ReadReq accesses(hits+misses) @@ -606,19 +606,19 @@ system.cpu.l2cache.overall_miss_rate::total 0.056655 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35946.764092 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34657.152842 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 34892.476190 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39959.172864 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39959.172864 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39959.078437 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39959.078437 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35946.764092 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39064.313645 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 38951.132939 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39064.235155 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 38951.057299 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35946.764092 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39064.313645 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 38951.132939 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 100996 # number of cycles access was blocked +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39064.235155 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 38951.057299 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 198 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 81 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1246.864198 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2.444444 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed @@ -638,14 +638,14 @@ system.cpu.l2cache.overall_mshr_misses::total 26388 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31379500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 135795500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 167175000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 778051996 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 778051996 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 778050000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 778050000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31379500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 913847496 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 945226996 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 913845500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 945225000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31379500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 913847496 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 945226996 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 913845500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 945225000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.978550 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020411 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024851 # mshr miss rate for ReadReq accesses @@ -660,14 +660,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.056655 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32755.219207 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31639.212488 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31842.857143 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36808.212508 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36808.212508 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36808.118081 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36808.118081 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32755.219207 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35935.804011 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35820.334849 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35935.725521 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35820.259209 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32755.219207 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35935.804011 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35820.334849 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35935.725521 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35820.259209 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 20eccd335..c6b30ffc7 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.163008 # Nu sim_ticks 163008222000 # Number of ticks simulated final_tick 163008222000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104701 # Simulator instruction rate (inst/s) -host_op_rate 110635 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29939476 # Simulator tick rate (ticks/s) -host_mem_usage 234836 # Number of bytes of host memory used -host_seconds 5444.59 # Real time elapsed on the host +host_inst_rate 178133 # Simulator instruction rate (inst/s) +host_op_rate 188229 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50937760 # Simulator tick rate (ticks/s) +host_mem_usage 228580 # Number of bytes of host memory used +host_seconds 3200.15 # Real time elapsed on the host sim_insts 570052710 # Number of instructions simulated sim_ops 602360916 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory @@ -502,12 +502,12 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 8537.033204 system.cpu.dcache.demand_avg_miss_latency::total 8537.033204 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 8537.033204 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 8537.033204 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28514592 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 54626 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3014 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9460.714001 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 1000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.124088 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 2 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 421091 # number of writebacks @@ -595,14 +595,14 @@ system.cpu.l2cache.overall_misses::total 28446 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27249500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 189324500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 216574000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 974455801 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 974455801 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 974356500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 974356500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 27249500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1163780301 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1191029801 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1163681000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1190930500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 27249500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1163780301 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1191029801 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1163681000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1190930500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 818 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 197352 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 198170 # number of ReadReq accesses(hits+misses) @@ -630,19 +630,19 @@ system.cpu.l2cache.overall_miss_rate::total 0.063881 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36092.052980 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34403.870616 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 34607.542346 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43918.144988 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43918.144988 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43913.669551 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43913.669551 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36092.052980 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42027.384385 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 41869.851684 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42023.798346 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 41866.360824 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36092.052980 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42027.384385 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 41869.851684 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 13672801 # number of cycles access was blocked +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42023.798346 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 41866.360824 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 27147 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 2920 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 4682.466096 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 9.296918 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed @@ -671,14 +671,14 @@ system.cpu.l2cache.overall_mshr_misses::total 28433 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24797500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 172259500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 197057000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 900047801 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 900047801 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899948500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899948500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24797500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1072307301 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1097104801 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1072208000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1097005500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24797500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1072307301 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1097104801 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1072208000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1097005500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.918093 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027839 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031513 # mshr miss rate for ReadReq accesses @@ -693,14 +693,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.063852 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33019.307590 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31354.113578 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31554.363491 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40564.620561 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40564.620561 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40560.145123 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40560.145123 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33019.307590 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38736.626725 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38585.615341 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38733.039520 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38582.122885 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33019.307590 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38736.626725 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38585.615341 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38733.039520 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38582.122885 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index b8b444d29..293c634b6 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.386987 # Nu sim_ticks 386986985000 # Number of ticks simulated final_tick 386986985000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135169 # Simulator instruction rate (inst/s) -host_op_rate 135595 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37331500 # Simulator tick rate (ticks/s) -host_mem_usage 223688 # Number of bytes of host memory used -host_seconds 10366.23 # Real time elapsed on the host +host_inst_rate 190632 # Simulator instruction rate (inst/s) +host_op_rate 191233 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52649747 # Simulator tick rate (ticks/s) +host_mem_usage 217240 # Number of bytes of host memory used +host_seconds 7350.22 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 78784 # Number of bytes read from this memory @@ -453,11 +453,11 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 6577.376711 system.cpu.dcache.demand_avg_miss_latency::total 6577.376711 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 6577.376711 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 6577.376711 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index b0555a54b..0c2881972 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.025432 # Nu sim_ticks 25432499000 # Number of ticks simulated final_tick 25432499000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141358 # Simulator instruction rate (inst/s) -host_op_rate 142373 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39681246 # Simulator tick rate (ticks/s) -host_mem_usage 367916 # Number of bytes of host memory used -host_seconds 640.92 # Real time elapsed on the host +host_inst_rate 191631 # Simulator instruction rate (inst/s) +host_op_rate 193007 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53793580 # Simulator tick rate (ticks/s) +host_mem_usage 361656 # Number of bytes of host memory used +host_seconds 472.78 # Real time elapsed on the host sim_insts 90599358 # Number of instructions simulated sim_ops 91249911 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 45440 # Number of bytes read from this memory @@ -494,11 +494,11 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 7044.800890 system.cpu.dcache.demand_avg_miss_latency::total 7044.800890 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 7044.800890 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 7044.800890 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 8960217 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 12648 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6519 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 1374.477220 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.940175 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 5a3a68b8e..b5e0cf470 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.201852 # Nu sim_ticks 201852280500 # Number of ticks simulated final_tick 201852280500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114620 # Simulator instruction rate (inst/s) -host_op_rate 129121 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45458575 # Simulator tick rate (ticks/s) -host_mem_usage 239092 # Number of bytes of host memory used -host_seconds 4440.36 # Real time elapsed on the host +host_inst_rate 135871 # Simulator instruction rate (inst/s) +host_op_rate 153059 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53886430 # Simulator tick rate (ticks/s) +host_mem_usage 232836 # Number of bytes of host memory used +host_seconds 3745.88 # Real time elapsed on the host sim_insts 508955133 # Number of instructions simulated sim_ops 573341693 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 218816 # Number of bytes read from this memory @@ -162,9 +162,9 @@ system.cpu.iq.issued_per_cycle::samples 402291353 # Nu system.cpu.iq.issued_per_cycle::mean 1.671200 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.739620 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 143645817 35.71% 35.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 74204584 18.45% 54.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 68520883 17.03% 71.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143645798 35.71% 35.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 74204622 18.45% 54.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 68520864 17.03% 71.19% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 53274856 13.24% 84.43% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 32167138 8.00% 92.42% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 16325737 4.06% 96.48% # Number of insts issued each cycle @@ -503,11 +503,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 12757.829762 system.cpu.dcache.overall_avg_miss_latency::cpu.data 12757.829762 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 12757.829762 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3322000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6644 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 557 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5964.093357 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 11.928187 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1101507 # number of writebacks diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index eb9886f3f..8ceb40825 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.427481 # Number of seconds simulated -sim_ticks 427481057500 # Number of ticks simulated -final_tick 427481057500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 427481054500 # Number of ticks simulated +final_tick 427481054500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54913 # Simulator instruction rate (inst/s) -host_op_rate 101540 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28388930 # Simulator tick rate (ticks/s) -host_mem_usage 267916 # Number of bytes of host memory used -host_seconds 15058.02 # Real time elapsed on the host +host_inst_rate 86006 # Simulator instruction rate (inst/s) +host_op_rate 159036 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44463827 # Simulator tick rate (ticks/s) +host_mem_usage 261156 # Number of bytes of host memory used +host_seconds 9614.13 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988699 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 222080 # Number of bytes read from this memory @@ -24,18 +24,18 @@ system.physmem.num_reads::total 434860 # Nu system.physmem.num_writes::writebacks 324977 # Number of write requests responded to by this memory system.physmem.num_writes::total 324977 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 519508 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 64585224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 64585225 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 65104733 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 519508 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 519508 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 48653683 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 48653683 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 48653683 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 48653684 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 48653684 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 48653684 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 519508 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 64585224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 113758416 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 64585225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 113758417 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 854962116 # number of cpu cycles simulated +system.cpu.numCycles 854962110 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.BPredUnit.lookups 221542687 # Number of BP lookups @@ -52,16 +52,16 @@ system.cpu.fetch.Branches 221542687 # Nu system.cpu.fetch.predictedBranches 152734220 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 382634785 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 91865959 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 200356871 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 200356865 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 29611 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 292723 # Number of stall cycles due to pending traps system.cpu.fetch.CacheLines 179385748 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 4126859 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 847490251 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 847490245 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.698073 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.416409 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 469274174 55.37% 55.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 469274168 55.37% 55.37% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 25456463 3.00% 58.38% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 28089429 3.31% 61.69% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 29452206 3.48% 65.17% # Number of instructions fetched each cycle (Total) @@ -73,11 +73,11 @@ system.cpu.fetch.rateDist::8 188811034 22.28% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 847490251 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 847490245 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.259126 # Number of branch fetches per cycle system.cpu.fetch.rate 1.440493 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 242064219 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 159033013 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 159033007 # Number of cycles decode is blocked system.cpu.decode.RunCycles 325519019 # Number of cycles decode is running system.cpu.decode.UnblockCycles 43678013 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 77195987 # Number of cycles decode is squashing @@ -85,7 +85,7 @@ system.cpu.decode.DecodedInsts 2233248714 # Nu system.cpu.decode.SquashedInsts 3 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 77195987 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 275570857 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 34110312 # Number of cycles rename is blocking +system.cpu.rename.BlockCycles 34110306 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 14758 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 334015692 # Number of cycles rename is running system.cpu.rename.UnblockCycles 126582645 # Number of cycles rename is unblocking @@ -114,11 +114,11 @@ system.cpu.iq.iqSquashedInstsIssued 951947 # Nu system.cpu.iq.iqSquashedInstsExamined 551393168 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 912351431 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 32844 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 847490251 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 847490245 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.164950 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.897317 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 226384740 26.71% 26.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 226384734 26.71% 26.71% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 141456799 16.69% 43.40% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 133569524 15.76% 59.16% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 133051620 15.70% 74.86% # Number of insts issued each cycle @@ -130,7 +130,7 @@ system.cpu.iq.issued_per_cycle::8 1920111 0.23% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 847490251 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 847490245 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 5020198 29.82% 29.82% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 29.82% # attempts to use FU when none available @@ -203,7 +203,7 @@ system.cpu.iq.FU_type_0::total 1834774344 # Ty system.cpu.iq.rate 2.146030 # Inst issue rate system.cpu.iq.fu_busy_cnt 16833252 # FU busy when requested system.cpu.iq.fu_busy_rate 0.009175 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4534784465 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 4534784459 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 2638023268 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 1791909670 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 39673 # Number of floating instruction queue reads @@ -223,7 +223,7 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 10593 # system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 77195987 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3929046 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 3929040 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 530860 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 2086453895 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 2572498 # Number of squashed instructions skipped by dispatch @@ -256,11 +256,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 557495358 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 14453256 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 770294264 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 770294258 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.984941 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.459206 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 276893916 35.95% 35.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 276893910 35.95% 35.95% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 195328257 25.36% 61.30% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 61767064 8.02% 69.32% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 90267747 11.72% 81.04% # Number of insts commited each cycle @@ -272,7 +272,7 @@ system.cpu.commit.committed_per_cycle::8 68515952 8.89% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 770294264 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 770294258 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -285,7 +285,7 @@ system.cpu.commit.int_insts 1528317557 # Nu system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.bw_lim_events 68515952 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2788262369 # The number of ROB reads +system.cpu.rob.rob_reads 2788262363 # The number of ROB reads system.cpu.rob.rob_writes 4250388650 # The number of ROB writes system.cpu.timesIdled 191112 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 7471865 # Total number of cycles that the CPU has spent unscheduled due to idling @@ -302,12 +302,12 @@ system.cpu.fp_regfile_reads 9183 # nu system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 992828832 # number of misc regfile reads system.cpu.icache.replacements 5688 # number of replacements -system.cpu.icache.tagsinuse 1035.102627 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1035.102624 # Cycle average of tags in use system.cpu.icache.total_refs 179169407 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 7297 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 24553.845005 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1035.102627 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1035.102624 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.505421 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.505421 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 179186003 # number of ReadReq hits @@ -322,12 +322,12 @@ system.cpu.icache.demand_misses::cpu.inst 199745 # n system.cpu.icache.demand_misses::total 199745 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 199745 # number of overall misses system.cpu.icache.overall_misses::total 199745 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1237682000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1237682000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1237682000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1237682000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1237682000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1237682000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1237681000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1237681000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1237681000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1237681000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1237681000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1237681000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 179385748 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 179385748 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 179385748 # number of demand (read+write) accesses @@ -340,12 +340,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001113 system.cpu.icache.demand_miss_rate::total 0.001113 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001113 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001113 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6196.310296 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6196.310296 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6196.310296 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6196.310296 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6196.310296 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6196.310296 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6196.305289 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6196.305289 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6196.305289 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6196.305289 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6196.305289 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6196.305289 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -366,24 +366,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 198172 system.cpu.icache.demand_mshr_misses::total 198172 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 198172 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 198172 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804804500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 804804500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804804500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 804804500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804804500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 804804500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804803500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 804803500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804803500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 804803500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804803500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 804803500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001105 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001105 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001105 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001105 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001105 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001105 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4061.141332 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4061.141332 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4061.141332 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4061.141332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4061.141332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4061.141332 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4061.136286 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4061.136286 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4061.136286 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4061.136286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4061.136286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4061.136286 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2529003 # number of replacements system.cpu.dcache.tagsinuse 4087.729607 # Cycle average of tags in use @@ -410,14 +410,14 @@ system.cpu.dcache.demand_misses::cpu.data 3725145 # n system.cpu.dcache.demand_misses::total 3725145 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 3725145 # number of overall misses system.cpu.dcache.overall_misses::total 3725145 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29892922500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29892922500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16960185000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16960185000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46853107500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46853107500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46853107500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46853107500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29892904500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29892904500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16960182000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16960182000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46853086500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46853086500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46853086500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46853086500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 264751521 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 264751521 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) @@ -434,14 +434,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.009000 system.cpu.dcache.demand_miss_rate::total 0.009000 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009000 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009000 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10827.054087 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 10827.054087 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17589.940033 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17589.940033 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12577.525841 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12577.525841 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12577.525841 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12577.525841 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10827.047567 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 10827.047567 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17589.936922 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17589.936922 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12577.520204 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12577.520204 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12577.520204 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12577.520204 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -468,14 +468,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2723946 system.cpu.dcache.demand_mshr_misses::total 2723946 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2723946 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2723946 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10993049600 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10993049600 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14994697002 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14994697002 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25987746602 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25987746602 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25987746602 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25987746602 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10993099500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10993099500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14994695000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14994695000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25987794500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25987794500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25987794500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25987794500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006658 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006658 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006445 # mshr miss rate for WriteReq accesses @@ -484,24 +484,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006581 system.cpu.dcache.demand_mshr_miss_rate::total 0.006581 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006581 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006581 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 6236.759555 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 6236.759555 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15597.963852 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15597.963852 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9540.477896 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 9540.477896 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9540.477896 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 9540.477896 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 6236.787865 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 6236.787865 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15597.961769 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15597.961769 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9540.495480 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 9540.495480 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9540.495480 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 9540.495480 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 408687 # number of replacements -system.cpu.l2cache.tagsinuse 29306.187052 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29306.187032 # Cycle average of tags in use system.cpu.l2cache.total_refs 3611934 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 441022 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 8.189918 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 209697302000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21100.579663 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 21100.579684 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 146.976593 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8058.630796 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 8058.630755 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.643939 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.004485 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.245930 # Average percentage of cache occupancy @@ -612,18 +612,18 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 3470 system.cpu.l2cache.overall_mshr_misses::cpu.data 431420 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 434890 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111424500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6957189466 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7068613966 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5872774499 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5872774499 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6957207430 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7068631930 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5878812896 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5878812896 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6488320000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6488320000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111424500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13445509466 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13556933966 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13445527430 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13556951930 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111424500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13445509466 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13556933966 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13445527430 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13556951930 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.478885 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126143 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127588 # mshr miss rate for ReadReq accesses @@ -638,18 +638,18 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.478885 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170313 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.171193 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32110.806916 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31310.201825 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31322.512168 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31004.637934 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31004.637934 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31310.282671 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31322.591770 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31036.516957 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31036.516957 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31012.245600 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31012.245600 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32110.806916 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31165.707352 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31173.248329 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31165.748992 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31173.289636 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32110.806916 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31165.707352 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31173.248329 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31165.748992 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31173.289636 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 63bbc9ea5..c1850cccb 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.141181 # Nu sim_ticks 141180939500 # Number of ticks simulated final_tick 141180939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88431 # Simulator instruction rate (inst/s) -host_op_rate 88431 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31316360 # Simulator tick rate (ticks/s) -host_mem_usage 225476 # Number of bytes of host memory used -host_seconds 4508.22 # Real time elapsed on the host +host_inst_rate 139974 # Simulator instruction rate (inst/s) +host_op_rate 139974 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49569488 # Simulator tick rate (ticks/s) +host_mem_usage 218836 # Number of bytes of host memory used +host_seconds 2848.14 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory @@ -174,11 +174,11 @@ system.cpu.icache.demand_avg_miss_latency::total 49040.669856 system.cpu.icache.overall_avg_miss_latency::cpu.inst 49040.669856 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 49040.669856 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 90 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 45000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 90 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 488 # number of ReadReq MSHR hits @@ -270,11 +270,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 52755.480984 system.cpu.dcache.overall_avg_miss_latency::cpu.data 52755.480984 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 52755.480984 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 85964000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 171928 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1907 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 45078.133193 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 90.156266 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 649 # number of writebacks diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 9ec4bfca0..f5e3faa91 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.080354 # Nu sim_ticks 80354154000 # Number of ticks simulated final_tick 80354154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172564 # Simulator instruction rate (inst/s) -host_op_rate 172564 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36920064 # Simulator tick rate (ticks/s) -host_mem_usage 226504 # Number of bytes of host memory used -host_seconds 2176.44 # Real time elapsed on the host +host_inst_rate 221188 # Simulator instruction rate (inst/s) +host_op_rate 221188 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47323038 # Simulator tick rate (ticks/s) +host_mem_usage 219864 # Number of bytes of host memory used +host_seconds 1697.99 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 222976 # Number of bytes read from this memory @@ -473,11 +473,11 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 31189.659864 system.cpu.dcache.demand_avg_miss_latency::total 31189.659864 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 31189.659864 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 31189.659864 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -607,11 +607,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 38052.307692 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35664.466131 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40136.807818 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 38052.307692 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 3500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3500 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 8292ba84e..908860e43 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.070882 # Nu sim_ticks 70882487500 # Number of ticks simulated final_tick 70882487500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119635 # Simulator instruction rate (inst/s) -host_op_rate 152946 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31056895 # Simulator tick rate (ticks/s) -host_mem_usage 243232 # Number of bytes of host memory used -host_seconds 2282.34 # Real time elapsed on the host +host_inst_rate 146290 # Simulator instruction rate (inst/s) +host_op_rate 187023 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37976354 # Simulator tick rate (ticks/s) +host_mem_usage 236976 # Number of bytes of host memory used +host_seconds 1866.49 # Real time elapsed on the host sim_insts 273048441 # Number of instructions simulated sim_ops 349076165 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 194880 # Number of bytes read from this memory @@ -497,11 +497,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 32843.594242 system.cpu.dcache.overall_avg_miss_latency::cpu.data 32843.594242 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 32843.594242 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 313000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 626 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19562.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 39.125000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1041 # number of writebacks diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 1c7f4cd18..76fb7aa81 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.644314 # Nu sim_ticks 644314104000 # Number of ticks simulated final_tick 644314104000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127860 # Simulator instruction rate (inst/s) -host_op_rate 127860 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45189117 # Simulator tick rate (ticks/s) -host_mem_usage 230524 # Number of bytes of host memory used -host_seconds 14258.17 # Real time elapsed on the host +host_inst_rate 164548 # Simulator instruction rate (inst/s) +host_op_rate 164548 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58155841 # Simulator tick rate (ticks/s) +host_mem_usage 223896 # Number of bytes of host memory used +host_seconds 11079.10 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 190848 # Number of bytes read from this memory @@ -488,12 +488,12 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 33793.696324 system.cpu.dcache.demand_avg_miss_latency::total 33793.696324 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 33793.696324 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 33793.696324 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 167000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 21500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 334 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 43 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7952.380952 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.904762 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 43 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 109393 # number of writebacks @@ -624,11 +624,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 35105.146381 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35724.010731 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35103.896073 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 35105.146381 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 105500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 211 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5275 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10.550000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 70391a345..c008b73ab 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.659244 # Nu sim_ticks 659244465000 # Number of ticks simulated final_tick 659244465000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88407 # Simulator instruction rate (inst/s) -host_op_rate 120399 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42099861 # Simulator tick rate (ticks/s) -host_mem_usage 243836 # Number of bytes of host memory used -host_seconds 15659.07 # Real time elapsed on the host +host_inst_rate 153116 # Simulator instruction rate (inst/s) +host_op_rate 208523 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72914339 # Simulator tick rate (ticks/s) +host_mem_usage 237584 # Number of bytes of host memory used +host_seconds 9041.36 # Real time elapsed on the host sim_insts 1384375635 # Number of instructions simulated sim_ops 1885330387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 199616 # Number of bytes read from this memory @@ -504,11 +504,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 33900.527612 system.cpu.dcache.overall_avg_miss_latency::cpu.data 33900.527612 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 33900.527612 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 52500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 105 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 17500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 35 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 108430 # number of writebacks diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 1f592bc6b..7d4bfa05d 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.046793 # Nu sim_ticks 46793182500 # Number of ticks simulated final_tick 46793182500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59681 # Simulator instruction rate (inst/s) -host_op_rate 59681 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31612654 # Simulator tick rate (ticks/s) -host_mem_usage 227600 # Number of bytes of host memory used -host_seconds 1480.20 # Real time elapsed on the host +host_inst_rate 131801 # Simulator instruction rate (inst/s) +host_op_rate 131801 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69813482 # Simulator tick rate (ticks/s) +host_mem_usage 220956 # Number of bytes of host memory used +host_seconds 670.26 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 514880 # Number of bytes read from this memory @@ -181,11 +181,11 @@ system.cpu.icache.demand_avg_miss_latency::total 15833.265655 system.cpu.icache.overall_avg_miss_latency::cpu.inst 15833.265655 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 15833.265655 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1025000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 2050 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 94 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 10904.255319 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 21.808511 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30939 # number of ReadReq MSHR hits @@ -277,11 +277,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 50319.544394 system.cpu.dcache.overall_avg_miss_latency::cpu.data 50319.544394 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 50319.544394 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6260683500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 12521367 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 124119 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50440.975999 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 100.881952 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 165811 # number of writebacks diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index dcb5671a4..9eadbf92f 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.021083 # Nu sim_ticks 21083079000 # Number of ticks simulated final_tick 21083079000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 162660 # Simulator instruction rate (inst/s) -host_op_rate 162660 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43087037 # Simulator tick rate (ticks/s) -host_mem_usage 228624 # Number of bytes of host memory used -host_seconds 489.31 # Real time elapsed on the host +host_inst_rate 198104 # Simulator instruction rate (inst/s) +host_op_rate 198104 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52475767 # Simulator tick rate (ticks/s) +host_mem_usage 221996 # Number of bytes of host memory used +host_seconds 401.77 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 559552 # Number of bytes read from this memory @@ -480,12 +480,12 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 36802.050170 system.cpu.dcache.demand_avg_miss_latency::total 36802.050170 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 36802.050170 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 36802.050170 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 90500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 25500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 181 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 51 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6033.333333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 25500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.066667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 51 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 166256 # number of writebacks @@ -614,11 +614,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 39898.128604 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35626.787144 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40130.278560 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 39898.128604 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 75 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3409.090909 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6.818182 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 3a7d388e3..fe9fd6111 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.023747 # Nu sim_ticks 23747395500 # Number of ticks simulated final_tick 23747395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 107822 # Simulator instruction rate (inst/s) -host_op_rate 153002 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36101670 # Simulator tick rate (ticks/s) -host_mem_usage 242616 # Number of bytes of host memory used -host_seconds 657.79 # Real time elapsed on the host +host_inst_rate 142184 # Simulator instruction rate (inst/s) +host_op_rate 201762 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47606944 # Simulator tick rate (ticks/s) +host_mem_usage 237384 # Number of bytes of host memory used +host_seconds 498.82 # Real time elapsed on the host sim_insts 70924309 # Number of instructions simulated sim_ops 100643556 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 325888 # Number of bytes read from this memory @@ -504,11 +504,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 33713.205595 system.cpu.dcache.overall_avg_miss_latency::cpu.data 33713.205595 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 33713.205595 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 197000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 394 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19700 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 39.400000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 128103 # number of writebacks diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 9df6e0f0a..0c8fe7df6 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.983203 # Nu sim_ticks 983202553500 # Number of ticks simulated final_tick 983202553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94547 # Simulator instruction rate (inst/s) -host_op_rate 94547 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51082649 # Simulator tick rate (ticks/s) -host_mem_usage 219392 # Number of bytes of host memory used -host_seconds 19247.29 # Real time elapsed on the host +host_inst_rate 119503 # Simulator instruction rate (inst/s) +host_op_rate 119503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64565869 # Simulator tick rate (ticks/s) +host_mem_usage 212872 # Number of bytes of host memory used +host_seconds 15227.90 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory @@ -181,11 +181,11 @@ system.cpu.icache.demand_avg_miss_latency::total 54537.140204 system.cpu.icache.overall_avg_miss_latency::cpu.inst 54537.140204 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 54537.140204 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 105000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 210 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 26250 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 52.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 218 # number of ReadReq MSHR hits @@ -276,12 +276,12 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 25004.469885 system.cpu.dcache.demand_avg_miss_latency::total 25004.469885 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 25004.469885 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 25004.469885 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 26428500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7896367000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 52857 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15792734 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4352 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 208446 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6072.725184 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 37882.074974 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.145450 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 75.764150 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3389692 # number of writebacks @@ -407,11 +407,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 52782.351713 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53849.243306 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52781.925390 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 52782.351713 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 540500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 1081 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 42 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 12869.047619 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 25.738095 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index b5afab091..d7e4bc3be 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.601884 # Number of seconds simulated -sim_ticks 601884201500 # Number of ticks simulated -final_tick 601884201500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.601742 # Number of seconds simulated +sim_ticks 601741522500 # Number of ticks simulated +final_tick 601741522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130981 # Simulator instruction rate (inst/s) -host_op_rate 130981 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45411041 # Simulator tick rate (ticks/s) -host_mem_usage 220420 # Number of bytes of host memory used -host_seconds 13254.14 # Real time elapsed on the host +host_inst_rate 165987 # Simulator instruction rate (inst/s) +host_op_rate 165987 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57533745 # Simulator tick rate (ticks/s) +host_mem_usage 213900 # Number of bytes of host memory used +host_seconds 10458.93 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138169152 # Number of bytes read from this memory -system.physmem.bytes_read::total 138230976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67208000 # Number of bytes written to this memory -system.physmem.bytes_written::total 67208000 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 966 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2158893 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2159859 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050125 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050125 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 102717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 229561021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 229663739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 102717 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 102717 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 111662675 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 111662675 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 111662675 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 102717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 229561021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 341326414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138172352 # Number of bytes read from this memory +system.physmem.bytes_read::total 138234112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67207424 # Number of bytes written to this memory +system.physmem.bytes_written::total 67207424 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2158943 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2159908 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050116 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050116 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 102635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 229620770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 229723406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 102635 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 102635 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 111688194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 111688194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 111688194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 102635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 229620770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 341411600 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 610881152 # DTB read hits -system.cpu.dtb.read_misses 10794363 # DTB read misses +system.cpu.dtb.read_hits 610863506 # DTB read hits +system.cpu.dtb.read_misses 10801691 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 621675515 # DTB read accesses -system.cpu.dtb.write_hits 207421516 # DTB write hits -system.cpu.dtb.write_misses 6613595 # DTB write misses +system.cpu.dtb.read_accesses 621665197 # DTB read accesses +system.cpu.dtb.write_hits 207455295 # DTB write hits +system.cpu.dtb.write_misses 6623437 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 214035111 # DTB write accesses -system.cpu.dtb.data_hits 818302668 # DTB hits -system.cpu.dtb.data_misses 17407958 # DTB misses +system.cpu.dtb.write_accesses 214078732 # DTB write accesses +system.cpu.dtb.data_hits 818318801 # DTB hits +system.cpu.dtb.data_misses 17425128 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 835710626 # DTB accesses -system.cpu.itb.fetch_hits 399285601 # ITB hits -system.cpu.itb.fetch_misses 63 # ITB misses +system.cpu.dtb.data_accesses 835743929 # DTB accesses +system.cpu.itb.fetch_hits 399244233 # ITB hits +system.cpu.itb.fetch_misses 57 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 399285664 # ITB accesses +system.cpu.itb.fetch_accesses 399244290 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,146 +67,146 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1203768404 # number of cpu cycles simulated +system.cpu.numCycles 1203483046 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 378661928 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 290874773 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18850616 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 264881962 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 260540807 # Number of BTB hits +system.cpu.BPredUnit.lookups 378630674 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 290853975 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 18842896 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 264245889 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 260518236 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 25136701 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6159 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 410735894 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3138932224 # Number of instructions fetch has processed -system.cpu.fetch.Branches 378661928 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 285677508 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 572729793 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 132567804 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 108566970 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1302 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 399285601 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10259418 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1199047347 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.617855 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.169243 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 25134989 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6201 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 410689836 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3138690905 # Number of instructions fetch has processed +system.cpu.fetch.Branches 378630674 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 285653225 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 572677806 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 132533954 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 108403122 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1285 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 399244233 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10255002 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1198760050 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.618281 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.169328 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 626317554 52.23% 52.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42572057 3.55% 55.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22209930 1.85% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 40806426 3.40% 61.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 126340363 10.54% 71.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 63640386 5.31% 76.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40565082 3.38% 80.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30197237 2.52% 82.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 206398312 17.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 626082244 52.23% 52.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42560367 3.55% 55.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22212227 1.85% 57.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 40796625 3.40% 61.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 126320083 10.54% 71.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 63645436 5.31% 76.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40565089 3.38% 80.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30205669 2.52% 82.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 206372310 17.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1199047347 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.314564 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.607588 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 438876145 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95310008 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542739947 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 15108786 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 107012461 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 60159953 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 978 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3060008107 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 1198760050 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.314612 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.608006 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 438814843 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95153182 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542714056 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 15090918 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 106987051 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 60150241 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1010 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3059802509 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 2177 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 107012461 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 459450274 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50562010 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5044 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 536182540 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 45835018 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2978218339 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 422353 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1724352 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 41499068 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2227532255 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3846059420 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3844664884 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1394536 # Number of floating rename lookups +system.cpu.rename.SquashCycles 106987051 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 459387866 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50448288 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5147 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 536142849 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 45788849 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2978016816 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 421943 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1715322 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 41464029 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2227365150 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3845813324 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3844419965 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1393359 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 851329292 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 212 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 209 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 95534350 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 674543157 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 250165929 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 60031674 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 34641501 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2674307937 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 181 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2477606155 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3178446 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 927538702 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 394492556 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1199047347 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.066312 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.969260 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 851162187 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 215 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 214 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 95471202 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 674494217 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 250159031 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59771171 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 34263403 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2674166611 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 189 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2477607357 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3173205 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 927397839 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 394299937 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 160 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1198760050 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.066808 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.969624 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 374590988 31.24% 31.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 190702947 15.90% 47.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 181537142 15.14% 62.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153695699 12.82% 75.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 136730734 11.40% 86.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80190081 6.69% 93.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 61698536 5.15% 98.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14532490 1.21% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5368730 0.45% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 374466356 31.24% 31.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 190640446 15.90% 47.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 181417957 15.13% 62.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153622544 12.82% 75.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 136730069 11.41% 86.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80254846 6.69% 93.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 61695164 5.15% 98.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14563469 1.21% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5369199 0.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1199047347 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1198760050 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2248592 11.88% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12188219 64.39% 76.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4492341 23.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2251857 11.87% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12201284 64.32% 76.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4515049 23.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1617099394 65.27% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 98 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1617068630 65.27% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 94 0.00% 65.27% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 284 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 297 0.00% 65.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 17 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 161 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 32 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 171 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 41 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.27% # Type of FU issued @@ -228,84 +228,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.27% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 639262195 25.80% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 221243949 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 639258763 25.80% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 221279320 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2477606155 # Type of FU issued -system.cpu.iq.rate 2.058208 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18929152 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007640 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6174384179 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3600600502 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2375948293 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1983076 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1349305 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 869249 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2495560681 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 974626 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 56273066 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2477607357 # Type of FU issued +system.cpu.iq.rate 2.058697 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18968190 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007656 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6174132781 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3600319262 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2375945234 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1983378 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1347629 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 869060 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2495600765 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 974782 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 56278777 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 229947494 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 250240 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 104617 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 89437427 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 229898554 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 250139 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 103830 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 89430529 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 223 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 81293 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 234 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 81236 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 107012461 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18493719 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 964338 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2816222496 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 17539215 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 674543157 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 250165929 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 181 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 222443 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13054 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 104617 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 13266110 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8853005 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 22119115 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2426782897 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 621677051 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 50823258 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 106987051 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18488263 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 963433 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2816062244 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 17529415 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 674494217 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 250159031 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 189 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 221508 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12923 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 103830 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 13260228 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8848776 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 22109004 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2426798028 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 621666775 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 50809329 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 141914378 # number of nop insts executed -system.cpu.iew.exec_refs 835712197 # number of memory reference insts executed -system.cpu.iew.exec_branches 297017404 # Number of branches executed -system.cpu.iew.exec_stores 214035146 # Number of stores executed -system.cpu.iew.exec_rate 2.015988 # Inst execution rate -system.cpu.iew.wb_sent 2405357276 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2376817542 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1361466858 # num instructions producing a value -system.cpu.iew.wb_consumers 1724557006 # num instructions consuming a value +system.cpu.iew.exec_nop 141895444 # number of nop insts executed +system.cpu.iew.exec_refs 835745555 # number of memory reference insts executed +system.cpu.iew.exec_branches 297016780 # Number of branches executed +system.cpu.iew.exec_stores 214078780 # Number of stores executed +system.cpu.iew.exec_rate 2.016479 # Inst execution rate +system.cpu.iew.wb_sent 2405369179 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2376814294 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1361493757 # num instructions producing a value +system.cpu.iew.wb_consumers 1724612513 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.974481 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.789459 # average fanout of values written-back +system.cpu.iew.wb_rate 1.974946 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.789449 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 756599351 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 756436478 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 18849719 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1092034886 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.666412 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.514594 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 18841975 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1091772999 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.666812 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.514787 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 565812226 51.81% 51.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 181963708 16.66% 68.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 91431923 8.37% 76.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53287438 4.88% 81.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36685843 3.36% 85.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28834990 2.64% 87.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22491649 2.06% 89.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22994830 2.11% 91.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 88532279 8.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 565636558 51.81% 51.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 181878211 16.66% 68.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 91372107 8.37% 76.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53285897 4.88% 81.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36714852 3.36% 85.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28908245 2.65% 87.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22459323 2.06% 89.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22999009 2.11% 91.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 88518797 8.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1092034886 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1091772999 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +316,70 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 88532279 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 88518797 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3494102884 # The number of ROB reads -system.cpu.rob.rob_writes 5259875951 # The number of ROB writes -system.cpu.timesIdled 272602 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 4721057 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3493691606 # The number of ROB reads +system.cpu.rob.rob_writes 5259524652 # The number of ROB writes +system.cpu.timesIdled 273067 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 4722996 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.693397 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.693397 # CPI: Total CPI of All Threads -system.cpu.ipc 1.442174 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.442174 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3262431101 # number of integer regfile reads -system.cpu.int_regfile_writes 1906790236 # number of integer regfile writes -system.cpu.fp_regfile_reads 51143 # number of floating regfile reads -system.cpu.fp_regfile_writes 554 # number of floating regfile writes +system.cpu.cpi 0.693233 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.693233 # CPI: Total CPI of All Threads +system.cpu.ipc 1.442516 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.442516 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3262496367 # number of integer regfile reads +system.cpu.int_regfile_writes 1906751993 # number of integer regfile writes +system.cpu.fp_regfile_reads 51073 # number of floating regfile reads +system.cpu.fp_regfile_writes 575 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 770.355491 # Cycle average of tags in use -system.cpu.icache.total_refs 399284112 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 966 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 413337.590062 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 769.815211 # Cycle average of tags in use +system.cpu.icache.total_refs 399242763 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 965 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 413723.070466 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 770.355491 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.376150 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.376150 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 399284112 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 399284112 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 399284112 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 399284112 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 399284112 # number of overall hits -system.cpu.icache.overall_hits::total 399284112 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1489 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1489 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1489 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1489 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1489 # number of overall misses -system.cpu.icache.overall_misses::total 1489 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 51254000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 51254000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 51254000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 51254000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 51254000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 51254000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 399285601 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 399285601 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 399285601 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 399285601 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 399285601 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 399285601 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 769.815211 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.375886 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.375886 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 399242763 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 399242763 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 399242763 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 399242763 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 399242763 # number of overall hits +system.cpu.icache.overall_hits::total 399242763 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1470 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1470 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1470 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1470 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1470 # number of overall misses +system.cpu.icache.overall_misses::total 1470 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 50742000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 50742000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 50742000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 50742000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 50742000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 50742000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 399244233 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 399244233 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 399244233 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 399244233 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 399244233 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 399244233 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34421.759570 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34421.759570 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34421.759570 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34421.759570 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34421.759570 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34421.759570 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34518.367347 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34518.367347 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34518.367347 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34518.367347 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34518.367347 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34518.367347 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,299 +388,299 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 523 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 523 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 523 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 523 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 523 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 523 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 966 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 966 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36312000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36312000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36312000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36312000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36312000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36312000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 505 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 505 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 505 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 505 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 505 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 505 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 965 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 965 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 965 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36236500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36236500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36236500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36236500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36236500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36236500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37590.062112 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37590.062112 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37590.062112 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37590.062112 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37590.062112 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37590.062112 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37550.777202 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37550.777202 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37550.777202 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37550.777202 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37550.777202 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37550.777202 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9176158 # number of replacements -system.cpu.dcache.tagsinuse 4085.718246 # Cycle average of tags in use -system.cpu.dcache.total_refs 700542179 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9180254 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 76.309673 # Average number of references to valid blocks. +system.cpu.dcache.replacements 9176269 # number of replacements +system.cpu.dcache.tagsinuse 4085.715808 # Cycle average of tags in use +system.cpu.dcache.total_refs 700520059 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9180365 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 76.306341 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 5701764000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4085.718246 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997490 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997490 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 544702732 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 544702732 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155839442 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155839442 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 700542174 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 700542174 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 700542174 # number of overall hits -system.cpu.dcache.overall_hits::total 700542174 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9892344 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9892344 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4889060 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4889060 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 4085.715808 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997489 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997489 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 544680569 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 544680569 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155839486 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155839486 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 700520055 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 700520055 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 700520055 # number of overall hits +system.cpu.dcache.overall_hits::total 700520055 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9891173 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9891173 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4889016 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4889016 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 14781404 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 14781404 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 14781404 # number of overall misses -system.cpu.dcache.overall_misses::total 14781404 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 135375372000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 135375372000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 128493017298 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 128493017298 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 14780189 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 14780189 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 14780189 # number of overall misses +system.cpu.dcache.overall_misses::total 14780189 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 135366568000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 135366568000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 128487056395 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 128487056395 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 42500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 42500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 263868389298 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 263868389298 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 263868389298 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 263868389298 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 554595076 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 554595076 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 263853624395 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 263853624395 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 263853624395 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 263853624395 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 554571742 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 554571742 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 715323578 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 715323578 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 715323578 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 715323578 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017837 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.017837 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 715300244 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 715300244 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 715300244 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 715300244 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017836 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.017836 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030418 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.030418 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.020664 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.020664 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.020664 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.020664 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13684.862961 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13684.862961 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26281.742768 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26281.742768 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.020663 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.020663 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.020663 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.020663 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13685.593003 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13685.593003 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26280.760054 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26280.760054 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 42500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 42500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17851.375235 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17851.375235 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17851.375235 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17851.375235 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 54186258 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2148410500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 10025 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65117 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5405.113017 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 32993.081684 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17851.843735 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17851.843735 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17851.843735 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17851.843735 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 105233 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4296872 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9989 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65119 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.534888 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 65.984920 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3416507 # number of writebacks -system.cpu.dcache.writebacks::total 3416507 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2595838 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2595838 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3005313 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3005313 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 5601151 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 5601151 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 5601151 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 5601151 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296506 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296506 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883747 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883747 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3416489 # number of writebacks +system.cpu.dcache.writebacks::total 3416489 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2594561 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2594561 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3005264 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3005264 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 5599825 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 5599825 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 5599825 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 5599825 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296612 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296612 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883752 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883752 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180253 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180253 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180253 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180253 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63651885000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 63651885000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 32596175026 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 32596175026 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9180364 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180364 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180364 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180364 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63655163500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 63655163500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 32590773423 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 32590773423 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 40500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 40500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 96248060026 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 96248060026 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 96248060026 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 96248060026 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013156 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 96245936923 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 96245936923 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 96245936923 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 96245936923 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013157 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013157 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011720 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011720 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.166667 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.166667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012834 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.012834 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012834 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012834 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8723.611685 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8723.611685 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17303.902820 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17303.902820 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8723.934273 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8723.934273 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17300.989421 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17300.989421 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 40500 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 40500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10484.249184 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10484.249184 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10484.249184 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10484.249184 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10483.891153 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10483.891153 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10483.891153 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10483.891153 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2143403 # number of replacements -system.cpu.l2cache.tagsinuse 30886.044156 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8540338 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2173098 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.930029 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 106236291500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14425.723577 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 30.926005 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16429.394573 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.440238 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000944 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.501385 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.942567 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5920206 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5920206 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3416507 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3416507 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1101155 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1101155 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7021361 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7021361 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7021361 # number of overall hits -system.cpu.l2cache.overall_hits::total 7021361 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 966 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1376292 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1377258 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 782601 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 782601 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 966 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2158893 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2159859 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 966 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2158893 # number of overall misses -system.cpu.l2cache.overall_misses::total 2159859 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35332000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49455599500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 49490931500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 28985235156 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 28985235156 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 35332000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 78440834656 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 78476166656 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 35332000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 78440834656 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 78476166656 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 966 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7296498 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7297464 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3416507 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3416507 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883756 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1883756 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 966 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9180254 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9181220 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 966 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9180254 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9181220 # number of overall (read+write) accesses +system.cpu.l2cache.replacements 2143480 # number of replacements +system.cpu.l2cache.tagsinuse 30885.644548 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8540352 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2173177 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 3.929893 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 106255777500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14426.759191 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 30.810977 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16428.074381 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.440270 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000940 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.501345 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.942555 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 5920172 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5920172 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3416489 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3416489 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1101250 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1101250 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7021422 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7021422 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7021422 # number of overall hits +system.cpu.l2cache.overall_hits::total 7021422 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 965 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1376432 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1377397 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 782511 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 782511 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 965 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2158943 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2159908 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 965 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2158943 # number of overall misses +system.cpu.l2cache.overall_misses::total 2159908 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35260500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49459767000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 49495027500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 28979186500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 28979186500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 35260500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 78438953500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 78474214000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 35260500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 78438953500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 78474214000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 965 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7296604 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7297569 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3416489 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3416489 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883761 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1883761 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 965 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9180365 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9181330 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 965 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9180365 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9181330 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188624 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.188731 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.415447 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.415447 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188640 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.188747 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.415398 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.415398 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.235167 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.235247 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.235170 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.235250 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.235167 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.235247 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36575.569358 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35933.943887 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35934.393919 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 37037.053564 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 37037.053564 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36575.569358 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 36333.822314 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 36333.930435 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36575.569358 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 36333.822314 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 36333.930435 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 23861689 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.235170 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.235250 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36539.378238 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35933.316720 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35933.741325 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 37033.583553 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 37033.583553 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36539.378238 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 36332.109509 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 36332.202112 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36539.378238 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 36332.109509 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 36332.202112 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 47300 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 3922 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 3906 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6084.061448 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 12.109575 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1050125 # number of writebacks -system.cpu.l2cache.writebacks::total 1050125 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1376292 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1377258 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782601 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 782601 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2158893 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2159859 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2158893 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2159859 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32266500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 45051953000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 45084219500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 26472928656 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 26472928656 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32266500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 71524881656 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 71557148156 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32266500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 71524881656 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 71557148156 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1050116 # number of writebacks +system.cpu.l2cache.writebacks::total 1050116 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1376432 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1377397 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782511 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 782511 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2158943 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2159908 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2158943 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2159908 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32204000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 45055642500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 45087846500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 26467073000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 26467073000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32204000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 71522715500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 71554919500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32204000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 71522715500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 71554919500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188624 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188731 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415447 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415447 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188640 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188747 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415398 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415398 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235167 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.235247 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235170 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.235250 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235167 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.235247 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33402.173913 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32734.298390 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32734.766834 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33826.852580 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33826.852580 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33402.173913 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33130.350442 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33130.472015 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33402.173913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33130.350442 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33130.472015 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235170 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.235250 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33372.020725 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32733.649392 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32734.096633 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33823.259993 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33823.259993 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33372.020725 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33128.579819 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33128.688583 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33372.020725 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33128.579819 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33128.688583 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 620901a70..2519af40e 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.454220 # Number of seconds simulated -sim_ticks 454219906500 # Number of ticks simulated -final_tick 454219906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.454149 # Number of seconds simulated +sim_ticks 454149445000 # Number of ticks simulated +final_tick 454149445000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 138720 # Simulator instruction rate (inst/s) -host_op_rate 154753 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40794382 # Simulator tick rate (ticks/s) -host_mem_usage 234840 # Number of bytes of host memory used -host_seconds 11134.37 # Real time elapsed on the host +host_inst_rate 251011 # Simulator instruction rate (inst/s) +host_op_rate 280022 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73805166 # Simulator tick rate (ticks/s) +host_mem_usage 228580 # Number of bytes of host memory used +host_seconds 6153.36 # Real time elapsed on the host sim_insts 1544563043 # Number of instructions simulated sim_ops 1723073855 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 47808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 156313408 # Number of bytes read from this memory -system.physmem.bytes_read::total 156361216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47808 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 71943232 # Number of bytes written to this memory -system.physmem.bytes_written::total 71943232 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 747 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2442397 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2443144 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1124113 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1124113 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 105253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 344135970 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 344241223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 105253 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 105253 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 158388549 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 158388549 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 158388549 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 105253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 344135970 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 502629772 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 48256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 156265984 # Number of bytes read from this memory +system.physmem.bytes_read::total 156314240 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48256 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 71930048 # Number of bytes written to this memory +system.physmem.bytes_written::total 71930048 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 754 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2441656 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2442410 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1123907 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1123907 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 106256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 344084939 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 344191195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 106256 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 106256 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 158384093 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 158384093 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 158384093 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 106256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 344084939 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 502575288 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,140 +77,140 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 908439814 # number of cpu cycles simulated +system.cpu.numCycles 908298891 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 299293350 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 245165786 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16042294 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 167415927 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 155291115 # Number of BTB hits +system.cpu.BPredUnit.lookups 299221505 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 245089393 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16036207 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 167476566 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 155260747 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18349808 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 218 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 291155231 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2147464853 # Number of instructions fetch has processed -system.cpu.fetch.Branches 299293350 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 173640923 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 427083963 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 82022952 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 117971766 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 18353715 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 235 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 291143927 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2147541842 # Number of instructions fetch has processed +system.cpu.fetch.Branches 299221505 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 173614462 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 427042376 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 81995589 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 117912816 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 81 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 282205512 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5329978 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 901954385 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.649183 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.246512 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 94 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 282188311 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5315637 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 901821520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.649341 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.246532 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 474870538 52.65% 52.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 22740626 2.52% 55.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38702218 4.29% 59.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 47644255 5.28% 64.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 40322718 4.47% 69.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46782649 5.19% 74.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38980366 4.32% 78.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18009770 2.00% 80.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 173901245 19.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 474779291 52.65% 52.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 22710427 2.52% 55.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38716038 4.29% 59.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 47664478 5.29% 64.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 40313573 4.47% 69.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46765093 5.19% 74.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38987797 4.32% 78.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 17988591 1.99% 80.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 173896232 19.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 901954385 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.329459 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.363904 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 319244517 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 99044104 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 402843645 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 15079439 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 65742680 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46017167 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 685 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2336575701 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2448 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 65742680 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 340277658 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 45082178 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13877 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 395714637 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 55123355 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2280505483 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 18602 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4635517 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 42073464 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2255238182 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10526656383 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10526652098 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4285 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 901821520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.329431 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.364356 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 319221723 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 98997420 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 402809489 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 15071254 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 65721634 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46024947 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 700 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2336308946 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2514 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 65721634 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 340227863 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 45083280 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12690 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 395699548 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 55076505 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2280327240 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 18280 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4628387 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 42035635 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2254967875 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10525732443 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10525728121 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4322 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319962 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 548918220 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1694 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1690 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 127506095 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 622196847 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 217942695 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 85227601 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 65382931 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2181344295 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1719 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2010119502 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4796816 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 454085036 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1056260113 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1545 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 901954385 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.228627 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.927984 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 548647913 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1655 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1650 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 127333779 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 622133622 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 217936550 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 85018666 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 64907509 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2181155194 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1636 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2010118619 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4778350 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 453891413 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1054915735 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1462 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 901821520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.228954 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.928169 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 241738453 26.80% 26.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 133353594 14.78% 41.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 156367006 17.34% 58.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 115954647 12.86% 71.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 125581942 13.92% 85.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 75899476 8.42% 94.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 39722592 4.40% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10686145 1.18% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2650530 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 241649201 26.80% 26.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 133398569 14.79% 41.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 156277076 17.33% 58.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 115862389 12.85% 71.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 125673548 13.94% 85.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 75895678 8.42% 94.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 39700475 4.40% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10713373 1.19% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2651211 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 901954385 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 901821520 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 695241 2.77% 2.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4797 0.02% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19085015 76.16% 78.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5273410 21.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 707951 2.82% 2.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4768 0.02% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19054904 75.97% 78.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5315511 21.19% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1230459115 61.21% 61.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 930103 0.05% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1230445204 61.21% 61.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 929764 0.05% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued @@ -234,88 +234,88 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 72 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 33 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 15 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 31 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 14 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 585119298 29.11% 90.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193610861 9.63% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 585105545 29.11% 90.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193637984 9.63% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2010119502 # Type of FU issued -system.cpu.iq.rate 2.212716 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25058463 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012466 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4952048213 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2635615257 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1952750313 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 455 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 782 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 169 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2035177734 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 231 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63595770 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2010118619 # Type of FU issued +system.cpu.iq.rate 2.213059 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25083134 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012478 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4951919807 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2635232712 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1952804452 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 435 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 778 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 167 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2035201532 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 221 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63665905 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 136270074 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 285522 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 187812 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 43095646 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 136206849 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 286531 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 188011 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 43089501 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 118212 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 117367 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 65742680 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 20161039 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1080033 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2181346094 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 5536242 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 622196847 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 217942695 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1653 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 177278 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 42353 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 187812 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8595145 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10187661 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18782806 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1980860321 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 570725685 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29259181 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 65721634 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 20156212 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1080802 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2181156911 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 5548348 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 622133622 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 217936550 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1571 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 177848 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 42316 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 188011 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8591764 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10177079 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18768843 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1980852010 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 570685009 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29266609 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 80 # number of nop insts executed -system.cpu.iew.exec_refs 761335906 # number of memory reference insts executed -system.cpu.iew.exec_branches 237528825 # Number of branches executed -system.cpu.iew.exec_stores 190610221 # Number of stores executed -system.cpu.iew.exec_rate 2.180508 # Inst execution rate -system.cpu.iew.wb_sent 1961779173 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1952750482 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1293463699 # num instructions producing a value -system.cpu.iew.wb_consumers 2065510739 # num instructions consuming a value +system.cpu.iew.exec_nop 81 # number of nop insts executed +system.cpu.iew.exec_refs 761345389 # number of memory reference insts executed +system.cpu.iew.exec_branches 237537296 # Number of branches executed +system.cpu.iew.exec_stores 190660380 # Number of stores executed +system.cpu.iew.exec_rate 2.180837 # Inst execution rate +system.cpu.iew.wb_sent 1961817327 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1952804619 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1293399468 # num instructions producing a value +system.cpu.iew.wb_consumers 2065182627 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.149565 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.626220 # average fanout of values written-back +system.cpu.iew.wb_rate 2.149958 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.626288 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 458335863 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 458146610 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 174 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16041632 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 836211706 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.060571 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.763665 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16035536 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 836099887 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.060847 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.764107 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 346444317 41.43% 41.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193987468 23.20% 64.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73877669 8.83% 73.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35342489 4.23% 77.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18524109 2.22% 79.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30984795 3.71% 83.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19692342 2.35% 85.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10738999 1.28% 87.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106619518 12.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 346421369 41.43% 41.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193942009 23.20% 64.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73849330 8.83% 73.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35339477 4.23% 77.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18485791 2.21% 79.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30991807 3.71% 83.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19654660 2.35% 85.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10738938 1.28% 87.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106676506 12.76% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 836211706 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 836099887 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563061 # Number of instructions committed system.cpu.commit.committedOps 1723073873 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -326,70 +326,70 @@ system.cpu.commit.branches 213462430 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106619518 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106676506 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2911001325 # The number of ROB reads -system.cpu.rob.rob_writes 4428720797 # The number of ROB writes -system.cpu.timesIdled 678798 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6485429 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2910643265 # The number of ROB reads +system.cpu.rob.rob_writes 4428322151 # The number of ROB writes +system.cpu.timesIdled 678500 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6477371 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563043 # Number of Instructions Simulated system.cpu.committedOps 1723073855 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563043 # Number of Instructions Simulated -system.cpu.cpi 0.588153 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.588153 # CPI: Total CPI of All Threads -system.cpu.ipc 1.700237 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.700237 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9924440864 # number of integer regfile reads -system.cpu.int_regfile_writes 1932829114 # number of integer regfile writes -system.cpu.fp_regfile_reads 176 # number of floating regfile reads -system.cpu.fp_regfile_writes 197 # number of floating regfile writes -system.cpu.misc_regfile_reads 2885564305 # number of misc regfile reads +system.cpu.cpi 0.588062 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.588062 # CPI: Total CPI of All Threads +system.cpu.ipc 1.700501 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.700501 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9924419417 # number of integer regfile reads +system.cpu.int_regfile_writes 1932830839 # number of integer regfile writes +system.cpu.fp_regfile_reads 180 # number of floating regfile reads +system.cpu.fp_regfile_writes 196 # number of floating regfile writes +system.cpu.misc_regfile_reads 2885680755 # number of misc regfile reads system.cpu.misc_regfile_writes 132 # number of misc regfile writes -system.cpu.icache.replacements 18 # number of replacements -system.cpu.icache.tagsinuse 627.769502 # Cycle average of tags in use -system.cpu.icache.total_refs 282204371 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 777 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 363197.388674 # Average number of references to valid blocks. +system.cpu.icache.replacements 25 # number of replacements +system.cpu.icache.tagsinuse 628.471657 # Cycle average of tags in use +system.cpu.icache.total_refs 282187157 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 785 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 359474.085350 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 627.769502 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.306528 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.306528 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 282204371 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 282204371 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 282204371 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 282204371 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 282204371 # number of overall hits -system.cpu.icache.overall_hits::total 282204371 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1141 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1141 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1141 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1141 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1141 # number of overall misses -system.cpu.icache.overall_misses::total 1141 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 38891500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 38891500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 38891500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 38891500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 38891500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 38891500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 282205512 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 282205512 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 282205512 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 282205512 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 282205512 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 282205512 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 628.471657 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.306871 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.306871 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 282187157 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 282187157 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 282187157 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 282187157 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 282187157 # number of overall hits +system.cpu.icache.overall_hits::total 282187157 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses +system.cpu.icache.overall_misses::total 1154 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39417000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39417000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39417000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39417000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39417000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39417000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 282188311 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 282188311 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 282188311 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 282188311 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 282188311 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 282188311 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34085.451358 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34085.451358 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34085.451358 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34085.451358 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34085.451358 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34085.451358 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34156.845754 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34156.845754 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34156.845754 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34156.845754 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34156.845754 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34156.845754 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -398,313 +398,309 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 363 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 363 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 363 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 363 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 363 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 363 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 778 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 778 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 778 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 778 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 778 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 778 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28274000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28274000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28274000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28274000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28274000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28274000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 369 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 369 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 369 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 369 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 369 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 785 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 785 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 785 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 785 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28514500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 28514500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28514500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 28514500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28514500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28514500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36341.902314 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36341.902314 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36341.902314 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36341.902314 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36341.902314 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36341.902314 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36324.203822 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36324.203822 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36324.203822 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36324.203822 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36324.203822 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36324.203822 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9617276 # number of replacements -system.cpu.dcache.tagsinuse 4087.426616 # Cycle average of tags in use -system.cpu.dcache.total_refs 660019994 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9621372 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.599363 # Average number of references to valid blocks. +system.cpu.dcache.replacements 9616145 # number of replacements +system.cpu.dcache.tagsinuse 4087.425286 # Cycle average of tags in use +system.cpu.dcache.total_refs 659915514 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9620241 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.596568 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 3361698000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.426616 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4087.425286 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.997907 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.997907 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 492609527 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 492609527 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167410308 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167410308 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 93 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 93 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 492504705 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 492504705 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167410650 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167410650 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 94 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 94 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 65 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 65 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 660019835 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 660019835 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 660019835 # number of overall hits -system.cpu.dcache.overall_hits::total 660019835 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 10110221 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 10110221 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5175739 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5175739 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 659915355 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 659915355 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 659915355 # number of overall hits +system.cpu.dcache.overall_hits::total 659915355 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10104493 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10104493 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5175397 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5175397 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 15285960 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 15285960 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 15285960 # number of overall misses -system.cpu.dcache.overall_misses::total 15285960 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 152096766000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 152096766000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 119863517075 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 119863517075 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 78000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 78000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 271960283075 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 271960283075 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 271960283075 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 271960283075 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 502719748 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 502719748 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 15279890 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 15279890 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 15279890 # number of overall misses +system.cpu.dcache.overall_misses::total 15279890 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 151975224500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 151975224500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 119867822584 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 119867822584 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 111500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 111500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 271843047084 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 271843047084 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 271843047084 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 271843047084 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 502609198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 502609198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 96 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 96 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 97 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 97 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 65 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 65 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 675305795 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 675305795 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 675305795 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 675305795 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020111 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020111 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029989 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029989 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.031250 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.031250 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.022636 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.022636 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.022636 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.022636 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15043.861652 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15043.861652 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23158.725174 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23158.725174 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 26000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 26000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17791.508226 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17791.508226 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17791.508226 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17791.508226 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 277962262 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 153500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 60300 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 675195245 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 675195245 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 675195245 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 675195245 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020104 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020104 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029987 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029987 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.030928 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.030928 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.022630 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.022630 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.022630 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.022630 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15040.361204 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15040.361204 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23161.087465 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23161.087465 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17790.903409 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17790.903409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17790.903409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17790.903409 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 547911 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 306 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 59951 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4609.656086 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 17055.555556 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.139314 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 34 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3473158 # number of writebacks -system.cpu.dcache.writebacks::total 3473158 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2383078 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2383078 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3281509 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3281509 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3473179 # number of writebacks +system.cpu.dcache.writebacks::total 3473179 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2378385 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2378385 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3281264 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3281264 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 5664587 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 5664587 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 5664587 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 5664587 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7727143 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7727143 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894230 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1894230 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9621373 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9621373 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9621373 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9621373 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75156431500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75156431500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 39462683260 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 39462683260 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114619114760 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 114619114760 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114619114760 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 114619114760 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015371 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015371 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010976 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010976 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014247 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014247 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014247 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014247 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9726.289717 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9726.289717 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20833.100130 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20833.100130 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11912.968633 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11912.968633 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11912.968633 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11912.968633 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 5659649 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 5659649 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 5659649 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 5659649 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7726108 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7726108 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894133 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1894133 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9620241 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9620241 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9620241 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9620241 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75134366500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75134366500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 39443717607 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 39443717607 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114578084107 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 114578084107 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114578084107 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 114578084107 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015372 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015372 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010975 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010975 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014248 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014248 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9724.736763 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9724.736763 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20824.154168 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20824.154168 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11910.105382 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11910.105382 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11910.105382 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11910.105382 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2427555 # number of replacements -system.cpu.l2cache.tagsinuse 31133.152617 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8743299 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2457267 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.558140 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 77440728000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14066.626463 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 15.622946 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 17050.903208 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.429279 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000477 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.520352 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.950108 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6115762 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6115791 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3473158 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3473158 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1063205 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1063205 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7178967 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7178996 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7178967 # number of overall hits -system.cpu.l2cache.overall_hits::total 7178996 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 749 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1611381 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1612130 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 831024 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 831024 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 749 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2442405 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2443154 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 749 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2442405 # number of overall misses -system.cpu.l2cache.overall_misses::total 2443154 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27440500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 59348934500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 59376375000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 35714709005 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 35714709005 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27440500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 95063643505 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 95091084005 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27440500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 95063643505 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 95091084005 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7727143 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7727921 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3473158 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3473158 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1894229 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1894229 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9621372 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9622150 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 778 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9621372 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9622150 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.962725 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.208535 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.208611 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.438714 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.438714 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.962725 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.253852 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.253909 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.962725 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.253852 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.253909 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36636.181575 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36831.099845 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 36831.009286 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42976.747970 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42976.747970 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36636.181575 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38922.145797 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 38921.444987 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36636.181575 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38922.145797 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 38921.444987 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 115700122 # number of cycles access was blocked +system.cpu.l2cache.replacements 2426778 # number of replacements +system.cpu.l2cache.tagsinuse 31133.069432 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8743063 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2456493 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 3.559165 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 77443387000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14066.378954 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 15.908545 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 17050.781934 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.429272 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000485 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.520349 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.950106 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6115252 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6115280 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3473179 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3473179 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1063326 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1063326 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7178578 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7178606 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7178578 # number of overall hits +system.cpu.l2cache.overall_hits::total 7178606 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 757 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1610856 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1611613 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 830807 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 830807 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 757 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2441663 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2442420 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 757 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2441663 # number of overall misses +system.cpu.l2cache.overall_misses::total 2442420 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27670500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 59328864000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 59356534500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 35694611500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 35694611500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27670500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 95023475500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 95051146000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27670500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 95023475500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 95051146000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 785 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7726108 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7726893 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3473179 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3473179 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1894133 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1894133 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 785 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9620241 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9621026 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 785 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9620241 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9621026 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964331 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.208495 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.208572 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.438621 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.438621 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964331 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.253805 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.253863 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964331 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.253805 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.253863 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36552.840159 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36830.644080 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36830.513591 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42963.782804 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42963.782804 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36552.840159 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38917.522811 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 38916.789905 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36552.840159 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38917.522811 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 38916.789905 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 229442 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 21086 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 20875 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5487.058807 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10.991234 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1124113 # number of writebacks -system.cpu.l2cache.writebacks::total 1124113 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 1123907 # number of writebacks +system.cpu.l2cache.writebacks::total 1123907 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 747 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1611373 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1612120 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 831024 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 831024 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 747 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2442397 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2443144 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 747 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2442397 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2443144 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25029000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54213758000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54238787000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33085952005 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33085952005 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25029000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87299710005 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 87324739005 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25029000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87299710005 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 87324739005 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960154 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208534 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208610 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960154 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253851 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.253908 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960154 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253851 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.253908 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33506.024096 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33644.449795 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33644.385654 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39813.473504 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39813.473504 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33506.024096 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35743.456123 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35742.772020 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33506.024096 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35743.456123 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35742.772020 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 754 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1610849 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1611603 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 830807 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 830807 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 754 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2441656 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2442410 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 754 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2441656 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2442410 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25220000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54195045500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54220265500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33065264000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33065264000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25220000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87260309500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 87285529500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25220000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87260309500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 87285529500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960510 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208494 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208571 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438621 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438621 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960510 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253804 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.253862 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960510 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253804 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.253862 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33448.275862 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33643.777598 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33643.686131 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39798.971362 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39798.971362 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33448.275862 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35738.166843 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35737.459927 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33448.275862 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35738.166843 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35737.459927 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index aad21c6d0..feb13ce30 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.042001 # Nu sim_ticks 42001440000 # Number of ticks simulated final_tick 42001440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75192 # Simulator instruction rate (inst/s) -host_op_rate 75192 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34364250 # Simulator tick rate (ticks/s) -host_mem_usage 223172 # Number of bytes of host memory used -host_seconds 1222.24 # Real time elapsed on the host +host_inst_rate 134131 # Simulator instruction rate (inst/s) +host_op_rate 134131 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61300636 # Simulator tick rate (ticks/s) +host_mem_usage 216520 # Number of bytes of host memory used +host_seconds 685.17 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -174,11 +174,11 @@ system.cpu.icache.demand_avg_miss_latency::total 24215.288412 system.cpu.icache.overall_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 24215.288412 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 92000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 184 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 15333.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 30.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1742 # number of ReadReq MSHR hits @@ -270,11 +270,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 54653.714005 system.cpu.dcache.overall_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 54653.714005 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 41228500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 82457 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 827 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 49853.083434 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 99.706167 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 4339a22dc..c18f0c43e 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.023660 # Nu sim_ticks 23659827000 # Number of ticks simulated final_tick 23659827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114539 # Simulator instruction rate (inst/s) -host_op_rate 114539 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32192844 # Simulator tick rate (ticks/s) -host_mem_usage 224192 # Number of bytes of host memory used -host_seconds 734.94 # Real time elapsed on the host +host_inst_rate 188397 # Simulator instruction rate (inst/s) +host_op_rate 188397 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52951506 # Simulator tick rate (ticks/s) +host_mem_usage 217548 # Number of bytes of host memory used +host_seconds 446.82 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 197632 # Number of bytes read from this memory @@ -481,11 +481,11 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 35694.911504 system.cpu.dcache.demand_avg_miss_latency::total 35694.911504 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 35694.911504 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 35694.911504 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -623,11 +623,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 36749.952390 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35341.806995 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38760.286639 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 36749.952390 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 3 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index e11bd02ec..a5a9d98b7 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.075929 # Nu sim_ticks 75929256000 # Number of ticks simulated final_tick 75929256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99785 # Simulator instruction rate (inst/s) -host_op_rate 109254 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43964821 # Simulator tick rate (ticks/s) -host_mem_usage 238132 # Number of bytes of host memory used -host_seconds 1727.05 # Real time elapsed on the host +host_inst_rate 126863 # Simulator instruction rate (inst/s) +host_op_rate 138901 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55895176 # Simulator tick rate (ticks/s) +host_mem_usage 231880 # Number of bytes of host memory used +host_seconds 1358.42 # Real time elapsed on the host sim_insts 172333091 # Number of instructions simulated sim_ops 188686573 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 132864 # Number of bytes read from this memory @@ -497,11 +497,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 31016.696141 system.cpu.dcache.overall_avg_miss_latency::cpu.data 31016.696141 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 31016.696141 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 9 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 9 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 98f92d27e..b9451bcf6 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,170 +1,170 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.870336 # Number of seconds simulated -sim_ticks 1870335522500 # Number of ticks simulated -final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.870325 # Number of seconds simulated +sim_ticks 1870325497500 # Number of ticks simulated +final_tick 1870325497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3051606 # Simulator instruction rate (inst/s) -host_op_rate 3051604 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90374561583 # Simulator tick rate (ticks/s) -host_mem_usage 305448 # Number of bytes of host memory used -host_seconds 20.70 # Real time elapsed on the host -sim_insts 63154034 # Number of instructions simulated -sim_ops 63154034 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory +host_inst_rate 2529303 # Simulator instruction rate (inst/s) +host_op_rate 2529302 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 74909435310 # Simulator tick rate (ticks/s) +host_mem_usage 298360 # Number of bytes of host memory used +host_seconds 24.97 # Real time elapsed on the host +sim_insts 63151114 # Number of instructions simulated +sim_ops 63151114 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 760896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 66666560 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 668672 # Number of bytes read from this memory -system.physmem.bytes_read::total 70883520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 761216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7861504 # Number of bytes written to this memory -system.physmem.bytes_written::total 7861504 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11894 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1042079 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 111168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 681792 # Number of bytes read from this memory +system.physmem.bytes_read::total 70870016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 760896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 111168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 872064 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7852480 # Number of bytes written to this memory +system.physmem.bytes_written::total 7852480 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11889 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1041665 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10448 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1107555 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122836 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122836 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 406994 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35658338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 357514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37898826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 406994 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4203259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4203259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4203259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 406994 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35658338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42102084 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 1000626 # number of replacements -system.l2c.tagsinuse 65381.922680 # Cycle average of tags in use -system.l2c.total_refs 2464737 # Total number of references to valid blocks. -system.l2c.sampled_refs 1065768 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.312639 # Average number of references to valid blocks. +system.physmem.num_reads::cpu1.inst 1737 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10653 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1107344 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122695 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122695 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 406825 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35644362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1416652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 364531 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37891809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 406825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 466263 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4198456 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4198456 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4198456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 406825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35644362 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1416652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 364531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42090265 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 1000406 # number of replacements +system.l2c.tagsinuse 65381.817479 # Cycle average of tags in use +system.l2c.total_refs 2465974 # Total number of references to valid blocks. +system.l2c.sampled_refs 1065550 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.314273 # Average number of references to valid blocks. system.l2c.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 56158.702580 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4894.236968 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4134.601551 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 174.423287 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 19.958294 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 56158.126687 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4894.240577 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4135.004263 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 174.436812 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 20.009142 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.856905 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.063095 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.002662 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.997649 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 873086 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 763077 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 101896 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 36734 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1774793 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 816653 # number of Writeback hits -system.l2c.Writeback_hits::total 816653 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits +system.l2c.occ_percent::total 0.997647 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 872724 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 763058 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 102911 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 36889 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1775582 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 816811 # number of Writeback hits +system.l2c.Writeback_hits::total 816811 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 138 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 175 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 166234 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 14285 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 180519 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 873086 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 929311 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 101896 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 51019 # number of demand (read+write) hits -system.l2c.demand_hits::total 1955312 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 873086 # number of overall hits -system.l2c.overall_hits::cpu0.data 929311 # number of overall hits -system.l2c.overall_hits::cpu1.inst 101896 # number of overall hits -system.l2c.overall_hits::cpu1.data 51019 # number of overall hits -system.l2c.overall_hits::total 1955312 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11894 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 908 # number of ReadReq misses -system.l2c.ReadReq_misses::total 941297 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 570 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3012 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 65 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 165 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 115706 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9662 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 125368 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 11894 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1042467 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1734 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses -system.l2c.demand_misses::total 1066665 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11894 # number of overall misses -system.l2c.overall_misses::cpu0.data 1042467 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1734 # number of overall misses -system.l2c.overall_misses::cpu1.data 10570 # number of overall misses -system.l2c.overall_misses::total 1066665 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.inst 884980 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1689838 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 103630 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 37642 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2716090 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 816653 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 816653 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 281940 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 23947 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 305887 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 884980 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1971778 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 103630 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 61589 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3021977 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 884980 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1971778 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 103630 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 61589 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3021977 # number of overall (read+write) accesses +system.l2c.ReadExReq_hits::cpu0.data 166434 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 14300 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 180734 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 872724 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 929492 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 102911 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 51189 # number of demand (read+write) hits +system.l2c.demand_hits::total 1956316 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 872724 # number of overall hits +system.l2c.overall_hits::cpu0.data 929492 # number of overall hits +system.l2c.overall_hits::cpu1.inst 102911 # number of overall hits +system.l2c.overall_hits::cpu1.data 51189 # number of overall hits +system.l2c.overall_hits::total 1956316 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 11889 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 926770 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1737 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 918 # number of ReadReq misses +system.l2c.ReadReq_misses::total 941314 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2441 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 575 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3016 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 67 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 103 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 170 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 115282 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9862 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 125144 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 11889 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 1042052 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1737 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10780 # number of demand (read+write) misses +system.l2c.demand_misses::total 1066458 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11889 # number of overall misses +system.l2c.overall_misses::cpu0.data 1042052 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1737 # number of overall misses +system.l2c.overall_misses::cpu1.data 10780 # number of overall misses +system.l2c.overall_misses::total 1066458 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.inst 884613 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1689828 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 104648 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 37807 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2716896 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 816811 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 816811 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2579 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 612 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3191 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 81 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 112 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 193 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 281716 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 24162 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 305878 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 884613 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1971544 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 104648 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 61969 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3022774 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 884613 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1971544 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 104648 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 61969 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3022774 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.548432 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.016733 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024122 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.346563 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.410392 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.403474 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.409851 # miss rate for ReadExReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.548440 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.016599 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024281 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.346467 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.946491 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939542 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.945158 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.827160 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.919643 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.880829 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.409214 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.408162 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.409130 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.528694 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.016733 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.171622 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.352969 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.528546 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.016599 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.173958 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.352808 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.528694 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.016733 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.171622 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.352969 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.528546 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.016599 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.173958 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.352808 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,34 +173,34 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 81316 # number of writebacks -system.l2c.writebacks::total 81316 # number of writebacks +system.l2c.writebacks::writebacks 81175 # number of writebacks +system.l2c.writebacks::total 81175 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41695 # number of replacements -system.iocache.tagsinuse 0.435437 # Cycle average of tags in use +system.iocache.replacements 41694 # number of replacements +system.iocache.tagsinuse 0.435353 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.435437 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.027215 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.warmup_cycle 1685787105067 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.435353 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.027210 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.027210 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses -system.iocache.demand_misses::total 41727 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses -system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -236,22 +236,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9154530 # DTB read hits +system.cpu0.dtb.read_hits 9148429 # DTB read hits system.cpu0.dtb.read_misses 7079 # DTB read misses system.cpu0.dtb.read_acv 152 # DTB read access violations system.cpu0.dtb.read_accesses 508987 # DTB read accesses -system.cpu0.dtb.write_hits 5936899 # DTB write hits +system.cpu0.dtb.write_hits 5932048 # DTB write hits system.cpu0.dtb.write_misses 726 # DTB write misses system.cpu0.dtb.write_acv 99 # DTB write access violations system.cpu0.dtb.write_accesses 189050 # DTB write accesses -system.cpu0.dtb.data_hits 15091429 # DTB hits +system.cpu0.dtb.data_hits 15080477 # DTB hits system.cpu0.dtb.data_misses 7805 # DTB misses system.cpu0.dtb.data_acv 251 # DTB access violations system.cpu0.dtb.data_accesses 698037 # DTB accesses -system.cpu0.itb.fetch_hits 3855556 # ITB hits +system.cpu0.itb.fetch_hits 3854196 # ITB hits system.cpu0.itb.fetch_misses 3485 # ITB misses system.cpu0.itb.fetch_acv 127 # ITB acv -system.cpu0.itb.fetch_accesses 3859041 # ITB accesses +system.cpu0.itb.fetch_accesses 3857681 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -264,55 +264,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3740670933 # number of cpu cycles simulated +system.cpu0.numCycles 3740650883 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 57222076 # Number of instructions committed -system.cpu0.committedOps 57222076 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses -system.cpu0.num_func_calls 1399585 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls -system.cpu0.num_int_insts 53249924 # number of integer instructions -system.cpu0.num_fp_insts 299810 # number of float instructions -system.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written -system.cpu0.num_mem_refs 15135515 # number of memory refs -system.cpu0.num_load_insts 9184477 # Number of load instructions -system.cpu0.num_store_insts 5951038 # Number of store instructions -system.cpu0.num_idle_cycles 3683437089.313678 # Number of idle cycles -system.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles -system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles +system.cpu0.committedInsts 57184467 # Number of instructions committed +system.cpu0.committedOps 57184467 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 53214865 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 299670 # Number of float alu accesses +system.cpu0.num_func_calls 1398025 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6803964 # number of instructions that are conditional controls +system.cpu0.num_int_insts 53214865 # number of integer instructions +system.cpu0.num_fp_insts 299670 # number of float instructions +system.cpu0.num_int_register_reads 73271755 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39802131 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 147658 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 150767 # number of times the floating registers were written +system.cpu0.num_mem_refs 15124548 # number of memory refs +system.cpu0.num_load_insts 9178366 # Number of load instructions +system.cpu0.num_store_insts 5946182 # Number of store instructions +system.cpu0.num_idle_cycles 3683454679.572560 # Number of idle cycles +system.cpu0.num_busy_cycles 57196203.427440 # Number of busy cycles +system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6280 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 196965 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 70940 40.60% 40.60% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 101705 58.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 101631 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 174730 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 69573 49.24% 49.24% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1852989766500 99.07% 99.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 69565 49.23% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 141297 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1852985718000 99.07% 99.07% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_ticks::31 17236468500 0.92% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1870325290000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.980730 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684486 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808659 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed @@ -345,37 +345,37 @@ system.cpu0.kern.syscall::144 2 0.88% 99.12% # nu system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 226 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 110 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wripir 111 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3760 2.05% 2.12% # number of callpals executed system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal::swpipl 168035 91.68% 93.82% # number of callpals executed -system.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed +system.cpu0.kern.callpal::swpipl 167897 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal::rdps 6134 3.35% 97.17% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.00% 97.18% # number of callpals executed +system.cpu0.kern.callpal::rdusp 7 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 183291 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches +system.cpu0.kern.callpal::total 183136 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7089 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1156 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1157 -system.cpu0.kern.mode_good::user 1158 +system.cpu0.kern.mode_good::kernel 1155 +system.cpu0.kern.mode_good::user 1156 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.162928 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.280291 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1869368290000 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 956999000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3763 # number of times the context was actually changed +system.cpu0.kern.swap_context 3761 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -407,39 +407,39 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 884404 # number of replacements -system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use -system.cpu0.icache.total_refs 56345132 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 884916 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks. +system.cpu0.icache.replacements 883989 # number of replacements +system.cpu0.icache.tagsinuse 511.244895 # Cycle average of tags in use +system.cpu0.icache.total_refs 56307893 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 884501 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 63.660632 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.244754 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 511.244895 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.998525 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 56345132 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 56345132 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 56345132 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 56345132 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 56345132 # number of overall hits -system.cpu0.icache.overall_hits::total 56345132 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 885000 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 885000 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 885000 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 885000 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 885000 # number of overall misses -system.cpu0.icache.overall_misses::total 885000 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230132 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 57230132 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 56307893 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 56307893 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 56307893 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 56307893 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 56307893 # number of overall hits +system.cpu0.icache.overall_hits::total 56307893 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 884630 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 884630 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 884630 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 884630 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 884630 # number of overall misses +system.cpu0.icache.overall_misses::total 884630 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 57192523 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 57192523 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 57192523 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 57192523 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 57192523 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 57192523 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015468 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.015468 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015468 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.015468 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015468 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.015468 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,63 +449,63 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1978686 # number of replacements -system.cpu0.dcache.tagsinuse 507.129778 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13123753 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1979198 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 6.630844 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1978242 # number of replacements +system.cpu0.dcache.tagsinuse 507.129590 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13113201 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1978754 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 6.626999 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 507.129778 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.990488 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7298337 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7298337 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5462263 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5462263 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186624 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 186624 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12760600 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12760600 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12760600 # number of overall hits -system.cpu0.dcache.overall_hits::total 12760600 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1683332 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1683332 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 285998 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 285998 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 714 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1969330 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1969330 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1969330 # number of overall misses -system.cpu0.dcache.overall_misses::total 1969330 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14729930 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187419 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.187419 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003811 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003811 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses +system.cpu0.dcache.occ_blocks::cpu0.data 507.129590 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.990487 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.990487 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7292600 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7292600 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5457787 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5457787 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 171977 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 171977 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186443 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 186443 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12750387 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12750387 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12750387 # number of overall hits +system.cpu0.dcache.overall_hits::total 12750387 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1683130 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1683130 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 285798 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 285798 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16152 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16152 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 726 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 726 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1968928 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1968928 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1968928 # number of overall misses +system.cpu0.dcache.overall_misses::total 1968928 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8975730 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8975730 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5743585 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5743585 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188129 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 188129 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187169 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 187169 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14719315 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14719315 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14719315 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14719315 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187520 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.187520 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049760 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049760 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085856 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085856 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003879 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003879 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133765 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.133765 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133765 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.133765 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -514,29 +514,29 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 775641 # number of writebacks -system.cpu0.dcache.writebacks::total 775641 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 775494 # number of writebacks +system.cpu0.dcache.writebacks::total 775494 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1163439 # DTB read hits +system.cpu1.dtb.read_hits 1169160 # DTB read hits system.cpu1.dtb.read_misses 3277 # DTB read misses system.cpu1.dtb.read_acv 58 # DTB read access violations system.cpu1.dtb.read_accesses 220342 # DTB read accesses -system.cpu1.dtb.write_hits 751446 # DTB write hits +system.cpu1.dtb.write_hits 755883 # DTB write hits system.cpu1.dtb.write_misses 415 # DTB write misses system.cpu1.dtb.write_acv 58 # DTB write access violations system.cpu1.dtb.write_accesses 103280 # DTB write accesses -system.cpu1.dtb.data_hits 1914885 # DTB hits +system.cpu1.dtb.data_hits 1925043 # DTB hits system.cpu1.dtb.data_misses 3692 # DTB misses system.cpu1.dtb.data_acv 116 # DTB access violations system.cpu1.dtb.data_accesses 323622 # DTB accesses -system.cpu1.itb.fetch_hits 1468399 # ITB hits +system.cpu1.itb.fetch_hits 1469677 # ITB hits system.cpu1.itb.fetch_misses 1539 # ITB misses system.cpu1.itb.fetch_acv 57 # ITB acv -system.cpu1.itb.fetch_accesses 1469938 # ITB accesses +system.cpu1.itb.fetch_accesses 1471216 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -549,51 +549,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3740248881 # number of cpu cycles simulated +system.cpu1.numCycles 3740237218 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5931958 # Number of instructions committed -system.cpu1.committedOps 5931958 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses -system.cpu1.num_func_calls 182742 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls -system.cpu1.num_int_insts 5550578 # number of integer instructions -system.cpu1.num_fp_insts 28590 # number of float instructions -system.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read -system.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written -system.cpu1.num_mem_refs 1926244 # number of memory refs -system.cpu1.num_load_insts 1170888 # Number of load instructions -system.cpu1.num_store_insts 755356 # Number of store instructions -system.cpu1.num_idle_cycles 3734312190.077655 # Number of idle cycles -system.cpu1.num_busy_cycles 5936690.922345 # Number of busy cycles -system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles +system.cpu1.committedInsts 5966647 # Number of instructions committed +system.cpu1.committedOps 5966647 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 5582916 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 28730 # Number of float alu accesses +system.cpu1.num_func_calls 184190 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 581489 # number of instructions that are conditional controls +system.cpu1.num_int_insts 5582916 # number of integer instructions +system.cpu1.num_fp_insts 28730 # number of float instructions +system.cpu1.num_int_register_reads 7700123 # number of times the integer registers were read +system.cpu1.num_int_register_writes 4186358 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 17955 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 17751 # number of times the floating registers were written +system.cpu1.num_mem_refs 1936419 # number of memory refs +system.cpu1.num_load_insts 1176619 # Number of load instructions +system.cpu1.num_store_insts 759800 # Number of store instructions +system.cpu1.num_idle_cycles 3734265828.606121 # Number of idle cycles +system.cpu1.num_busy_cycles 5971389.393879 # Number of busy cycles +system.cpu1.not_idle_fraction 0.001597 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.998403 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.inst.quiesce 2208 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 39691 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 10388 33.53% 33.53% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1907 6.15% 39.68% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 111 0.36% 40.04% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 18579 59.96% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 30985 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 10378 45.79% 45.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1907 8.41% 54.21% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 111 0.49% 54.70% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 10267 45.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 22663 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1859112376500 99.41% 99.41% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1870124427000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_ticks::30 14176500 0.00% 99.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 10910041500 0.58% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1870118595500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.999037 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.552613 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.731418 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed @@ -616,67 +616,67 @@ system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 470 1.46% 1.50% # number of callpals executed +system.cpu1.kern.callpal::swpctx 472 1.46% 1.50% # number of callpals executed system.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26238 81.66% 83.22% # number of callpals executed -system.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed -system.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed +system.cpu1.kern.callpal::swpipl 26358 81.69% 83.25% # number of callpals executed +system.cpu1.kern.callpal::rdps 2589 8.02% 91.28% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.28% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 91.29% # number of callpals executed +system.cpu1.kern.callpal::rdusp 2 0.01% 91.30% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.31% # number of callpals executed +system.cpu1.kern.callpal::rti 2608 8.08% 99.39% # number of callpals executed system.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed system.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 32131 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches +system.cpu1.kern.callpal::total 32267 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1034 # number of protection mode switches system.cpu1.kern.mode_switch::user 580 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 612 +system.cpu1.kern.mode_switch::idle 2048 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 613 system.cpu1.kern.mode_good::user 580 -system.cpu1.kern.mode_good::idle 32 -system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 33 +system.cpu1.kern.mode_switch_good::kernel 0.592843 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::idle 0.016113 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.334790 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 1393260500 0.07% 0.07% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 471 # number of times the context was actually changed -system.cpu1.icache.replacements 103091 # number of replacements -system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use -system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 427.126317 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.834231 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 5832136 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5832136 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5832136 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5832136 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5832136 # number of overall hits -system.cpu1.icache.overall_hits::total 5832136 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 103630 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 103630 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 103630 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 103630 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 103630 # number of overall misses -system.cpu1.icache.overall_misses::total 103630 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5935766 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.017459 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.017459 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.017459 # miss rate for overall accesses +system.cpu1.kern.mode_ticks::idle 1867980072500 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 473 # number of times the context was actually changed +system.cpu1.icache.replacements 104103 # number of replacements +system.cpu1.icache.tagsinuse 427.138444 # Cycle average of tags in use +system.cpu1.icache.total_refs 5865807 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 104615 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 56.070420 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1868930362000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 427.138444 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.834255 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.834255 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 5865807 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5865807 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 5865807 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5865807 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 5865807 # number of overall hits +system.cpu1.icache.overall_hits::total 5865807 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 104648 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 104648 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 104648 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 104648 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 104648 # number of overall misses +system.cpu1.icache.overall_misses::total 104648 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 5970455 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5970455 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 5970455 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5970455 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 5970455 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5970455 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017528 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.017528 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017528 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.017528 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017528 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.017528 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -686,63 +686,63 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 62044 # number of replacements -system.cpu1.dcache.tagsinuse 421.562730 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1836054 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 62382 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 29.432432 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1851115552500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 421.562730 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.823365 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.823365 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1109521 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1109521 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 707457 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 707457 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1816978 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1816978 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1816978 # number of overall hits -system.cpu1.dcache.overall_hits::total 1816978 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 41444 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 41444 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 25848 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 25848 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 67292 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 67292 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 67292 # number of overall misses -system.cpu1.dcache.overall_misses::total 67292 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036008 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036008 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035249 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.035249 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035713 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.035713 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035713 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035713 # miss rate for overall accesses +system.cpu1.dcache.replacements 62444 # number of replacements +system.cpu1.dcache.tagsinuse 421.660465 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1845254 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 62784 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 29.390514 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1851113732500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 421.660465 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.823556 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.823556 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1114890 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1114890 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 711494 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 711494 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15278 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 15278 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15743 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 15743 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1826384 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1826384 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1826384 # number of overall hits +system.cpu1.dcache.overall_hits::total 1826384 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 41651 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 41651 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 26091 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 26091 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1291 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1291 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 751 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 751 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 67742 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 67742 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 67742 # number of overall misses +system.cpu1.dcache.overall_misses::total 67742 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1156541 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1156541 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 737585 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 737585 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16569 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 16569 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16494 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 16494 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1894126 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1894126 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1894126 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1894126 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036013 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036013 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035374 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.035374 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.077917 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.077917 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.045532 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.045532 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035764 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.035764 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035764 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035764 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -751,8 +751,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 41012 # number of writebacks -system.cpu1.dcache.writebacks::total 41012 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 41317 # number of writebacks +system.cpu1.dcache.writebacks::total 41317 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index a50f49017..cf5c30619 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,132 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.829332 # Number of seconds simulated -sim_ticks 1829332258000 # Number of ticks simulated -final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.829331 # Number of seconds simulated +sim_ticks 1829330593000 # Number of ticks simulated +final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2962809 # Simulator instruction rate (inst/s) -host_op_rate 2962806 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90274916526 # Simulator tick rate (ticks/s) -host_mem_usage 302384 # Number of bytes of host memory used -host_seconds 20.26 # Real time elapsed on the host -sim_insts 60038305 # Number of instructions simulated -sim_ops 60038305 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory +host_inst_rate 2569577 # Simulator instruction rate (inst/s) +host_op_rate 2569575 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78294086451 # Simulator tick rate (ticks/s) +host_mem_usage 295292 # Number of bytes of host memory used +host_seconds 23.37 # Real time elapsed on the host +sim_insts 60037737 # Number of instructions simulated +sim_ops 60037737 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66839296 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 70349696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7411392 # Number of bytes written to this memory -system.physmem.bytes_written::total 7411392 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044366 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 70349440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 857856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 857856 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7411136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7411136 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13404 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044364 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1099214 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115803 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115803 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36537607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1449867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 38456489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 992301 # number of replacements -system.cpu.l2cache.tagsinuse 65424.374305 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2433239 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1057464 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.301014 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 4247.922119 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.998297 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 811229 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1718026 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187229 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187229 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906797 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998458 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905255 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906797 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998458 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905255 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 117117 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1044757 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1058163 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1044757 # number of overall misses -system.cpu.l2cache.overall_misses::total 1058163 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1738869 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2659072 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2043215 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2963418 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2043215 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2963418 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.353900 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384815 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384815 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511330 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511330 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks -system.cpu.l2cache.writebacks::total 74291 # number of writebacks -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.physmem.num_reads::total 1099210 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115799 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115799 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 468945 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36537571 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1449868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 38456384 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 468945 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 468945 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4051283 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4051283 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4051283 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 468945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36537571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1449868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42507667 # Total bandwidth to/from this memory (bytes/s) system.iocache.replacements 41686 # number of replacements -system.iocache.tagsinuse 1.225570 # Cycle average of tags in use +system.iocache.tagsinuse 1.225558 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41702 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.076598 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1685780599067 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.225558 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.076597 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.076597 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -178,22 +98,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9710427 # DTB read hits +system.cpu.dtb.read_hits 9710417 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6352498 # DTB write hits +system.cpu.dtb.write_hits 6352487 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 16062925 # DTB hits +system.cpu.dtb.data_hits 16062904 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974648 # ITB hits +system.cpu.itb.fetch_hits 4974615 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979654 # ITB accesses +system.cpu.itb.fetch_accesses 4979621 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -206,51 +126,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3658664408 # number of cpu cycles simulated +system.cpu.numCycles 3658661078 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60038305 # Number of instructions committed -system.cpu.committedOps 60038305 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses +system.cpu.committedInsts 60037737 # Number of instructions committed +system.cpu.committedOps 60037737 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 55912968 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses -system.cpu.num_func_calls 1484182 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls -system.cpu.num_int_insts 55913521 # number of integer instructions +system.cpu.num_func_calls 1484174 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7110641 # number of instructions that are conditional controls +system.cpu.num_int_insts 55912968 # number of integer instructions system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read -system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written +system.cpu.num_int_register_reads 76953007 # number of times the integer registers were read +system.cpu.num_int_register_writes 41739788 # number of times the integer registers were written system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 16115709 # number of memory refs -system.cpu.num_load_insts 9747513 # Number of load instructions -system.cpu.num_store_insts 6368196 # Number of store instructions -system.cpu.num_idle_cycles 3598608979.180807 # Number of idle cycles -system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles -system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.983585 # Percentage of idle cycles +system.cpu.num_mem_refs 16115688 # number of memory refs +system.cpu.num_load_insts 9747503 # Number of load instructions +system.cpu.num_store_insts 6368185 # Number of store instructions +system.cpu.num_idle_cycles 3598606247.544791 # Number of idle cycles +system.cpu.num_busy_cycles 60054830.455209 # Number of busy cycles +system.cpu.not_idle_fraction 0.016414 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.983586 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 211316 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105620 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182559 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1811925911500 99.05% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1829332050500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 17304126000 0.95% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1829330385500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.695541 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.816366 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -289,7 +209,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal::swpipl 175246 91.19% 93.40% # number of callpals executed system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed @@ -298,20 +218,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192180 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1738 +system.cpu.kern.callpal::total 192177 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5948 # number of protection mode switches +system.cpu.kern.mode_switch::user 1735 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1906 +system.cpu.kern.mode_good::user 1735 system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320444 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081506 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.389735 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 26832734500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 1465059000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1801032591000 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -344,33 +264,33 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 919594 # number of replacements -system.cpu.icache.tagsinuse 511.215243 # Cycle average of tags in use -system.cpu.icache.total_refs 59129922 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks. +system.cpu.icache.replacements 919577 # number of replacements +system.cpu.icache.tagsinuse 511.215229 # Cycle average of tags in use +system.cpu.icache.total_refs 59129371 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 920089 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 64.264839 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.215243 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 511.215229 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.998467 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 59129922 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59129922 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59129922 # number of overall hits -system.cpu.icache.overall_hits::total 59129922 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 920221 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 920221 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 920221 # number of overall misses -system.cpu.icache.overall_misses::total 920221 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 60050143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60050143 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 59129371 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59129371 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59129371 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59129371 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59129371 # number of overall hits +system.cpu.icache.overall_hits::total 59129371 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 920204 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 920204 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 920204 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 920204 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 920204 # number of overall misses +system.cpu.icache.overall_misses::total 920204 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 60049575 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60049575 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60049575 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60049575 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60049575 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60049575 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses @@ -386,55 +306,55 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2042702 # number of replacements +system.cpu.dcache.replacements 2042708 # number of replacements system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.total_refs 14038431 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2043214 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 6.870759 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 14038404 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2043220 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 6.870726 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7807780 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807780 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655992 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655992 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655992 # number of overall hits -system.cpu.dcache.overall_hits::total 13655992 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721707 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721707 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 7807768 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807768 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13655967 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655967 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655967 # number of overall hits +system.cpu.dcache.overall_hits::total 13655967 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721710 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721710 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026069 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026069 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026069 # number of overall misses -system.cpu.dcache.overall_misses::total 2026069 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15682061 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses +system.cpu.dcache.demand_misses::cpu.data 2026075 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026075 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026075 # number of overall misses +system.cpu.dcache.overall_misses::total 2026075 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses @@ -450,5 +370,85 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks system.cpu.dcache.writebacks::total 833491 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 992297 # number of replacements +system.cpu.l2cache.tagsinuse 65424.375500 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2433229 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1057460 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.301013 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 56309.097195 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 4867.351144 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 4247.927161 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.998297 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 906782 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 811232 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1718014 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187234 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187234 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906782 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998466 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1905248 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 906782 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998466 # number of overall hits +system.cpu.l2cache.overall_hits::total 1905248 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 13404 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 941044 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 117115 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 117115 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13404 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1044755 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1058159 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13404 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1044755 # number of overall misses +system.cpu.l2cache.overall_misses::total 1058159 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 920186 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1738872 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2659058 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304349 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304349 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 920186 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2043221 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2963407 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 920186 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2043221 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2963407 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014567 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.353901 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384805 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.384805 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014567 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511327 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014567 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511327 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 74287 # number of writebacks +system.cpu.l2cache.writebacks::total 74287 # number of writebacks +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 181c5df24..ba361e6db 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962058 # Number of seconds simulated -sim_ticks 1962057812000 # Number of ticks simulated -final_tick 1962057812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.955746 # Number of seconds simulated +sim_ticks 1955746240500 # Number of ticks simulated +final_tick 1955746240500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1235183 # Simulator instruction rate (inst/s) -host_op_rate 1235183 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40819911602 # Simulator tick rate (ticks/s) -host_mem_usage 297060 # Number of bytes of host memory used -host_seconds 48.07 # Real time elapsed on the host -sim_insts 59370518 # Number of instructions simulated -sim_ops 59370518 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 834432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24593280 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 29312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 572992 # Number of bytes read from this memory -system.physmem.bytes_read::total 28680832 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 834432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 29312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7715456 # Number of bytes written to this memory -system.physmem.bytes_written::total 7715456 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13038 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 384270 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 458 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8953 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448138 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120554 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120554 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 425284 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12534432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1351039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14939 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 292036 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14617730 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 425284 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14939 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3932329 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3932329 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3932329 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 425284 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12534432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1351039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14939 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 292036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18550059 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 341238 # number of replacements -system.l2c.tagsinuse 65290.171288 # Cycle average of tags in use -system.l2c.total_refs 2492514 # Total number of references to valid blocks. -system.l2c.sampled_refs 406253 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.135374 # Average number of references to valid blocks. -system.l2c.warmup_cycle 7854344000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55481.148199 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4824.640956 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4855.323185 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 116.032373 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 13.026576 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.846575 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.073618 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.074086 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001771 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000199 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996249 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 902430 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 773977 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 86748 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 31919 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1795074 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 820361 # number of Writeback hits -system.l2c.Writeback_hits::total 820361 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 161 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 57 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 218 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 21 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 42 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 172410 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 12341 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 184751 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 902430 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 946387 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 86748 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 44260 # number of demand (read+write) hits -system.l2c.demand_hits::total 1979825 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 902430 # number of overall hits -system.l2c.overall_hits::cpu0.data 946387 # number of overall hits -system.l2c.overall_hits::cpu1.inst 86748 # number of overall hits -system.l2c.overall_hits::cpu1.data 44260 # number of overall hits -system.l2c.overall_hits::total 1979825 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13038 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271462 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 469 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 326 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285295 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2435 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 490 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2925 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 34 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 73 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 107 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113176 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8669 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121845 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13038 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 384638 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 469 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8995 # number of demand (read+write) misses -system.l2c.demand_misses::total 407140 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13038 # number of overall misses -system.l2c.overall_misses::cpu0.data 384638 # number of overall misses -system.l2c.overall_misses::cpu1.inst 469 # number of overall misses -system.l2c.overall_misses::cpu1.data 8995 # number of overall misses -system.l2c.overall_misses::total 407140 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 678189500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 14120883000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 24328000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 17368000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 14840768500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1412000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1560000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 2972000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 156000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 208000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 364000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5885512000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 450808000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6336320000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 678189500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 20006395000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 24328000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 468176000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21177088500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 678189500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 20006395000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 24328000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 468176000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21177088500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 915468 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1045439 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 87217 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 32245 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2080369 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 820361 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 820361 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2596 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 547 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3143 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 55 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 94 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 149 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 285586 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 21010 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 306596 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 915468 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1331025 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 87217 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 53255 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2386965 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 915468 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1331025 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 87217 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 53255 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2386965 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014242 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.259663 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.005377 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.010110 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.137137 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.937982 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.895795 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.930640 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.618182 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.776596 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.718121 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.396294 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.412613 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.397412 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014242 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.288979 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.005377 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.168904 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.170568 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014242 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.288979 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.005377 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.168904 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.170568 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52016.375211 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52017.899374 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51872.068230 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 53276.073620 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52019.027673 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 579.876797 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3183.673469 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1016.068376 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4588.235294 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2849.315068 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3401.869159 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52003.180886 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52002.307071 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52003.118716 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52016.375211 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52013.568602 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 51872.068230 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52048.471373 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52014.266591 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52016.375211 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52013.568602 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 51872.068230 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52048.471373 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52014.266591 # average overall miss latency +host_inst_rate 1240365 # Simulator instruction rate (inst/s) +host_op_rate 1240364 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39831169965 # Simulator tick rate (ticks/s) +host_mem_usage 291792 # Number of bytes of host memory used +host_seconds 49.10 # Real time elapsed on the host +sim_insts 60902973 # Number of instructions simulated +sim_ops 60902973 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 830080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24726528 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 35200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 438464 # Number of bytes read from this memory +system.physmem.bytes_read::total 28681152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 830080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 35200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 865280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7699072 # Number of bytes written to this memory +system.physmem.bytes_written::total 7699072 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12970 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386352 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 550 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6851 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448143 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120298 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120298 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 424431 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12643014 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1355431 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 17998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 224193 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14665068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 424431 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 17998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442430 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3936642 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3936642 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3936642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 424431 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12643014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1355431 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 17998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 224193 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18601710 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 341281 # number of replacements +system.l2c.tagsinuse 65229.882617 # Cycle average of tags in use +system.l2c.total_refs 2441318 # Total number of references to valid blocks. +system.l2c.sampled_refs 406256 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.009309 # Average number of references to valid blocks. +system.l2c.warmup_cycle 7648586000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 55341.365970 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4865.877793 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4868.452553 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 116.161458 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 38.024844 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.844442 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.074247 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.074287 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.001772 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000580 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.995329 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 685804 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 664321 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 316190 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 108937 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1775252 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 793334 # number of Writeback hits +system.l2c.Writeback_hits::total 793334 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 183 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 549 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 732 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 35 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 22 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 57 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 126580 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 47318 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 173898 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 685804 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 790901 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 316190 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 156255 # number of demand (read+write) hits +system.l2c.demand_hits::total 1949150 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 685804 # number of overall hits +system.l2c.overall_hits::cpu0.data 790901 # number of overall hits +system.l2c.overall_hits::cpu1.inst 316190 # number of overall hits +system.l2c.overall_hits::cpu1.data 156255 # number of overall hits +system.l2c.overall_hits::total 1949150 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 12970 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 271621 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 561 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 244 # number of ReadReq misses +system.l2c.ReadReq_misses::total 285396 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2948 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1741 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4689 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 892 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 895 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1787 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 115480 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 6627 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 122107 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 12970 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 387101 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 561 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 6871 # number of demand (read+write) misses +system.l2c.demand_misses::total 407503 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 12970 # number of overall misses +system.l2c.overall_misses::cpu0.data 387101 # number of overall misses +system.l2c.overall_misses::cpu1.inst 561 # number of overall misses +system.l2c.overall_misses::cpu1.data 6871 # number of overall misses +system.l2c.overall_misses::total 407503 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 679344500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 14131444000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 29382500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 12805500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 14852976500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 2720000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 22059498 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 24779498 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2047000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 521500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2568500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6014286500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 347569000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6361855500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 679344500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 20145730500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 29382500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 360374500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21214832000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 679344500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 20145730500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 29382500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 360374500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21214832000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 698774 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 935942 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 316751 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 109181 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2060648 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 793334 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 793334 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3131 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 2290 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5421 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 927 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 917 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1844 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 242060 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 53945 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 296005 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 698774 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1178002 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 316751 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 163126 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2356653 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 698774 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1178002 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 316751 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 163126 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2356653 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.018561 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.290211 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.001771 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.002235 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.138498 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941552 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.760262 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.864970 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.962244 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.976009 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.969089 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.477072 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.122847 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.412517 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018561 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.328608 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.001771 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.042121 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.172916 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018561 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.328608 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.001771 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.042121 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.172916 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52378.141866 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52026.330807 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52375.222816 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52481.557377 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52043.394091 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 922.659430 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12670.590465 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5284.601834 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2294.843049 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 582.681564 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1437.325126 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52080.762903 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52447.412102 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52100.661715 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52378.141866 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52042.568994 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52375.222816 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52448.624654 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52060.554155 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52378.141866 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52042.568994 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52375.222816 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52448.624654 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52060.554155 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -221,119 +221,119 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 79034 # number of writebacks -system.l2c.writebacks::total 79034 # number of writebacks +system.l2c.writebacks::writebacks 78778 # number of writebacks +system.l2c.writebacks::total 78778 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 13038 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 271462 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 458 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 326 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 285284 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2435 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 490 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2925 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 34 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 73 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 107 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 113176 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 8669 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 121845 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13038 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 384638 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 458 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 8995 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 407129 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13038 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 384638 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 458 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 8995 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 407129 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 521730000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10863339000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 18343000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 13456000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 11416868000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 97460000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 19615000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 117075000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1360000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2920000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 4280000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4527400000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 346780000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4874180000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 521730000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 15390739000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 18343000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 360236000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16291048000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 521730000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 15390739000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 18343000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 360236000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16291048000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1369455000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 19250000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1388705000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1966544000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 505236000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2471780000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3335999000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 524486000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 3860485000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014242 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.259663 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005251 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.010110 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.137131 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.937982 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.895795 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.930640 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.618182 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.776596 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.718121 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.396294 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.412613 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.397412 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014242 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.288979 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005251 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.168904 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.170563 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014242 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.288979 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005251 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.168904 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.170563 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40016.106765 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.899374 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40050.218341 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41276.073620 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40019.307076 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.640657 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40030.612245 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40025.641026 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 12970 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 271621 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 550 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 244 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 285385 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2948 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1741 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4689 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 892 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 895 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1787 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 115480 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 6627 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 122107 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 12970 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 387101 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 550 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 6871 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 407492 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 12970 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 387101 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 550 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 6871 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 407492 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 519097000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10870382000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 22042500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 9816500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 11421338000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 117985500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 69640998 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 187626498 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 35714975 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 35800000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 71514975 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4619582000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 265544000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4885126000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 519097000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 15489964000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 22042500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 275360500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16306464000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 519097000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 15489964000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 22042500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 275360500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16306464000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1370272000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18137500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1388409500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2141921500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 673752500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2815674000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3512193500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 691890000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4204083500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018561 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.290211 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001736 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002235 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.138493 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941552 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.760262 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.864970 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.962244 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.976009 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969089 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477072 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122847 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.412517 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018561 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.328608 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001736 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.042121 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.172911 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018561 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.328608 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001736 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.042121 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.172911 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40022.898998 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40020.403430 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40077.272727 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40231.557377 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.806980 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40022.218453 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000.573234 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40014.181702 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40039.209641 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40003.180886 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40002.307071 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40003.118716 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40016.106765 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.568602 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40050.218341 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40048.471373 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40014.462247 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40016.106765 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.568602 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40050.218341 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40048.471373 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40014.462247 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40019.571908 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40003.307932 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40070.016599 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40006.928350 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40022.898998 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40015.303500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40077.272727 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40075.753165 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40016.648180 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40022.898998 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40015.303500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40077.272727 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40075.753165 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40016.648180 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -344,39 +344,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41698 # number of replacements -system.iocache.tagsinuse 0.566822 # Cycle average of tags in use +system.iocache.replacements 41696 # number of replacements +system.iocache.tagsinuse 0.569930 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1754521474000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.566822 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.035426 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.035426 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses -system.iocache.ReadReq_misses::total 178 # number of ReadReq misses +system.iocache.warmup_cycle 1749614950000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.569930 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.035621 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.035621 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses +system.iocache.ReadReq_misses::total 176 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses -system.iocache.demand_misses::total 41730 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses -system.iocache.overall_misses::total 41730 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21239998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21239998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 11448106806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11448106806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 11469346804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11469346804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 11469346804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11469346804 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses +system.iocache.demand_misses::total 41728 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses +system.iocache.overall_misses::total 41728 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21013998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21013998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 11453563806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11453563806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 11474577804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11474577804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 11474577804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11474577804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -385,40 +385,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119325.831461 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119325.831461 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275512.774499 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 275512.774499 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 274846.556530 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 274846.556530 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 274846.556530 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 274846.556530 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 199371000 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119397.715909 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119397.715909 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275644.103918 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 275644.103918 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 274985.089245 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 274985.089245 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 274985.089245 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 274985.089245 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 199825 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 24657 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 24712 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8085.776858 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.086152 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11983000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11983000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9287247000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9287247000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9299230000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9299230000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9299230000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9299230000 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11861998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11861998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9292859806 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9292859806 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9304721804 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9304721804 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9304721804 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9304721804 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -427,14 +427,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67320.224719 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67320.224719 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223509.024836 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 223509.024836 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222842.798946 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 222842.798946 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222842.798946 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 222842.798946 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67397.715909 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67397.715909 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223644.103918 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 223644.103918 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222985.089245 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 222985.089245 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222985.089245 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 222985.089245 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -452,22 +452,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8658368 # DTB read hits -system.cpu0.dtb.read_misses 7687 # DTB read misses -system.cpu0.dtb.read_acv 174 # DTB read access violations -system.cpu0.dtb.read_accesses 524201 # DTB read accesses -system.cpu0.dtb.write_hits 6036843 # DTB write hits -system.cpu0.dtb.write_misses 798 # DTB write misses -system.cpu0.dtb.write_acv 115 # DTB write access violations -system.cpu0.dtb.write_accesses 195659 # DTB write accesses -system.cpu0.dtb.data_hits 14695211 # DTB hits -system.cpu0.dtb.data_misses 8485 # DTB misses -system.cpu0.dtb.data_acv 289 # DTB access violations -system.cpu0.dtb.data_accesses 719860 # DTB accesses -system.cpu0.itb.fetch_hits 3948323 # ITB hits -system.cpu0.itb.fetch_misses 3841 # ITB misses -system.cpu0.itb.fetch_acv 143 # ITB acv -system.cpu0.itb.fetch_accesses 3952164 # ITB accesses +system.cpu0.dtb.read_hits 7486542 # DTB read hits +system.cpu0.dtb.read_misses 7443 # DTB read misses +system.cpu0.dtb.read_acv 210 # DTB read access violations +system.cpu0.dtb.read_accesses 490673 # DTB read accesses +system.cpu0.dtb.write_hits 5063820 # DTB write hits +system.cpu0.dtb.write_misses 813 # DTB write misses +system.cpu0.dtb.write_acv 134 # DTB write access violations +system.cpu0.dtb.write_accesses 187452 # DTB write accesses +system.cpu0.dtb.data_hits 12550362 # DTB hits +system.cpu0.dtb.data_misses 8256 # DTB misses +system.cpu0.dtb.data_acv 344 # DTB access violations +system.cpu0.dtb.data_accesses 678125 # DTB accesses +system.cpu0.itb.fetch_hits 3500956 # ITB hits +system.cpu0.itb.fetch_misses 3871 # ITB misses +system.cpu0.itb.fetch_acv 184 # ITB acv +system.cpu0.itb.fetch_accesses 3504827 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -480,118 +480,117 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3924115624 # number of cpu cycles simulated +system.cpu0.numCycles 3910167080 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 54116505 # Number of instructions committed -system.cpu0.committedOps 54116505 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 50087098 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 302903 # Number of float alu accesses -system.cpu0.num_func_calls 1426970 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6243728 # number of instructions that are conditional controls -system.cpu0.num_int_insts 50087098 # number of integer instructions -system.cpu0.num_fp_insts 302903 # number of float instructions -system.cpu0.num_int_register_reads 68610814 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37122288 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 149298 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 152355 # number of times the floating registers were written -system.cpu0.num_mem_refs 14741096 # number of memory refs -system.cpu0.num_load_insts 8689646 # Number of load instructions -system.cpu0.num_store_insts 6051450 # Number of store instructions -system.cpu0.num_idle_cycles 3676817171.998126 # Number of idle cycles -system.cpu0.num_busy_cycles 247298452.001874 # Number of busy cycles -system.cpu0.not_idle_fraction 0.063020 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.936980 # Percentage of idle cycles +system.cpu0.committedInsts 47719039 # Number of instructions committed +system.cpu0.committedOps 47719039 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44257119 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 210954 # Number of float alu accesses +system.cpu0.num_func_calls 1200899 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5607083 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44257119 # number of integer instructions +system.cpu0.num_fp_insts 210954 # number of float instructions +system.cpu0.num_int_register_reads 60839484 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32982631 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102466 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104326 # number of times the floating registers were written +system.cpu0.num_mem_refs 12590587 # number of memory refs +system.cpu0.num_load_insts 7513713 # Number of load instructions +system.cpu0.num_store_insts 5076874 # Number of store instructions +system.cpu0.num_idle_cycles 3701181001.496715 # Number of idle cycles +system.cpu0.num_busy_cycles 208986078.503285 # Number of busy cycles +system.cpu0.not_idle_fraction 0.053447 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.946553 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 202757 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 72604 40.61% 40.61% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.07% 40.69% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1979 1.11% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 104050 58.20% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 178770 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71235 49.27% 49.27% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1979 1.37% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71229 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 144580 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1900688314000 96.87% 96.87% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 102511500 0.01% 96.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 795126500 0.04% 96.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 5572000 0.00% 96.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 60465450000 3.08% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1962056974000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981144 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6789 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 164868 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56806 40.18% 40.18% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1972 1.39% 41.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 420 0.30% 41.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82040 58.03% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141369 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56268 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1972 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 420 0.37% 51.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55848 48.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114639 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1899887304000 97.18% 97.18% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 92906000 0.00% 97.18% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 760170500 0.04% 97.22% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 309335500 0.02% 97.24% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 54033794000 2.76% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1955083510000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990529 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684565 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808749 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 6 2.68% 2.68% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.48% 11.16% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.34% 12.50% # number of syscalls executed -system.cpu0.kern.syscall::6 30 13.39% 25.89% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.45% 26.34% # number of syscalls executed -system.cpu0.kern.syscall::15 1 0.45% 26.79% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.46% 31.25% # number of syscalls executed -system.cpu0.kern.syscall::19 6 2.68% 33.93% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.79% 35.71% # number of syscalls executed -system.cpu0.kern.syscall::23 2 0.89% 36.61% # number of syscalls executed -system.cpu0.kern.syscall::24 4 1.79% 38.39% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.57% 41.96% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.89% 42.86% # number of syscalls executed -system.cpu0.kern.syscall::45 39 17.41% 60.27% # number of syscalls executed -system.cpu0.kern.syscall::47 4 1.79% 62.05% # number of syscalls executed -system.cpu0.kern.syscall::48 7 3.12% 65.18% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.02% 69.20% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.45% 69.64% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.23% 71.88% # number of syscalls executed -system.cpu0.kern.syscall::71 32 14.29% 86.16% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.34% 87.50% # number of syscalls executed -system.cpu0.kern.syscall::74 9 4.02% 91.52% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.45% 91.96% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.89% 92.86% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.12% 95.98% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.89% 96.87% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.89% 97.77% # number of syscalls executed -system.cpu0.kern.syscall::132 2 0.89% 98.66% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.45% 99.11% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 224 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.680741 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810920 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed +system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed +system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed +system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 91 0.05% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3872 2.06% 2.11% # number of callpals executed -system.cpu0.kern.callpal::tbi 44 0.02% 2.13% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal::swpipl 171948 91.52% 93.66% # number of callpals executed -system.cpu0.kern.callpal::rdps 6691 3.56% 97.22% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.00% 97.23% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.23% # number of callpals executed -system.cpu0.kern.callpal::rti 4705 2.50% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 356 0.19% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 149 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 187881 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7233 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1235 # number of protection mode switches +system.cpu0.kern.callpal::wripir 503 0.34% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3070 2.05% 2.39% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.43% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134512 89.86% 92.29% # number of callpals executed +system.cpu0.kern.callpal::rdps 6676 4.46% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed +system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 149688 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6889 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1285 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1234 -system.cpu0.kern.mode_good::user 1235 +system.cpu0.kern.mode_good::kernel 1285 +system.cpu0.kern.mode_good::user 1285 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.170607 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186529 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.291568 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958395542000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3661425000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.314412 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1951516113500 99.83% 99.83% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3347061000 0.17% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3873 # number of times the context was actually changed +system.cpu0.kern.swap_context 3071 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -623,51 +622,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 914851 # number of replacements -system.cpu0.icache.tagsinuse 508.781994 # Cycle average of tags in use -system.cpu0.icache.total_refs 53209789 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 915362 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 58.129777 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 36528993000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 508.781994 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.993715 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.993715 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 53209789 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 53209789 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 53209789 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 53209789 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 53209789 # number of overall hits -system.cpu0.icache.overall_hits::total 53209789 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 915491 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 915491 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 915491 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 915491 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 915491 # number of overall misses -system.cpu0.icache.overall_misses::total 915491 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13646549000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13646549000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13646549000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13646549000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13646549000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13646549000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 54125280 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 54125280 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 54125280 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 54125280 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 54125280 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 54125280 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016914 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.016914 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016914 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.016914 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016914 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.016914 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14906.262323 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14906.262323 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14906.262323 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14906.262323 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14906.262323 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14906.262323 # average overall miss latency +system.cpu0.icache.replacements 698187 # number of replacements +system.cpu0.icache.tagsinuse 508.830635 # Cycle average of tags in use +system.cpu0.icache.total_refs 47028847 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 698699 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 67.309166 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 35739052000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 508.830635 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.993810 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.993810 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 47028847 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47028847 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47028847 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47028847 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47028847 # number of overall hits +system.cpu0.icache.overall_hits::total 47028847 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 698792 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 698792 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 698792 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 698792 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 698792 # number of overall misses +system.cpu0.icache.overall_misses::total 698792 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9694162500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9694162500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9694162500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9694162500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9694162500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9694162500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47727639 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47727639 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47727639 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47727639 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47727639 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47727639 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014641 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014641 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014641 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014641 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014641 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014641 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13872.743964 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13872.743964 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13872.743964 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13872.743964 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13872.743964 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13872.743964 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -676,112 +675,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915491 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 915491 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 915491 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 915491 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 915491 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 915491 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10899382500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10899382500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10899382500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10899382500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10899382500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10899382500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016914 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016914 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016914 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016914 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016914 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016914 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11905.504806 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11905.504806 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11905.504806 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11905.504806 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11905.504806 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11905.504806 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 698792 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 698792 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 698792 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 698792 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 698792 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 698792 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8296578500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8296578500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8296578500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8296578500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8296578500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8296578500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014641 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014641 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014641 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014641 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014641 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014641 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11872.743964 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11872.743964 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11872.743964 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11872.743964 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11872.743964 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11872.743964 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1337819 # number of replacements -system.cpu0.dcache.tagsinuse 506.532892 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13370103 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1338331 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.990132 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 101834000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 506.532892 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.989322 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.989322 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7444463 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7444463 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5554933 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5554933 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 175817 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 175817 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191182 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 191182 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12999396 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12999396 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12999396 # number of overall hits -system.cpu0.dcache.overall_hits::total 12999396 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1037635 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1037635 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 289296 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 289296 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16772 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16772 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 445 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 445 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1326931 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1326931 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1326931 # number of overall misses -system.cpu0.dcache.overall_misses::total 1326931 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26113637000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 26113637000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8963228000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8963228000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 238633000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 238633000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4867000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4867000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 35076865000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 35076865000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 35076865000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 35076865000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8482098 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8482098 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5844229 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5844229 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 192589 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 192589 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191627 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 191627 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14326327 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14326327 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14326327 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14326327 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122332 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.122332 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049501 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049501 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087087 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087087 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002322 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002322 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092622 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.092622 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092622 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092622 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25166.495926 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25166.495926 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30982.896411 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 30982.896411 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14228.058669 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14228.058669 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10937.078652 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10937.078652 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26434.580999 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26434.580999 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26434.580999 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 26434.580999 # average overall miss latency +system.cpu0.dcache.replacements 1180402 # number of replacements +system.cpu0.dcache.tagsinuse 505.183019 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11360683 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1180820 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.621012 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 99461000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 505.183019 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.986686 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.986686 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6406782 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6406782 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4655760 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4655760 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140286 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140286 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147915 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 147915 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11062542 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11062542 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11062542 # number of overall hits +system.cpu0.dcache.overall_hits::total 11062542 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 938249 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 938249 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 251643 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 251643 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13638 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13638 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5458 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5458 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1189892 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1189892 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1189892 # number of overall misses +system.cpu0.dcache.overall_misses::total 1189892 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 23522563000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 23522563000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8201327000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8201327000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 147906000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 147906000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 67796500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 67796500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 31723890000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 31723890000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 31723890000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 31723890000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7345031 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7345031 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4907403 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4907403 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 153924 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 153924 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153373 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153373 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12252434 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12252434 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12252434 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12252434 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127739 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127739 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051278 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051278 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088602 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088602 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035586 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035586 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097115 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097115 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097115 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097115 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25070.704046 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25070.704046 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 32591.119165 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 32591.119165 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10845.138583 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10845.138583 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12421.491389 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12421.491389 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26661.150760 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26661.150760 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26661.150760 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 26661.150760 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -790,62 +789,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 785166 # number of writebacks -system.cpu0.dcache.writebacks::total 785166 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1037635 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1037635 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 289296 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 289296 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16772 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16772 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 445 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 445 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326931 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1326931 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326931 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1326931 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23000669022 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23000669022 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8095339001 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8095339001 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 188317000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 188317000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3531001 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3531001 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31096008023 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 31096008023 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31096008023 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 31096008023 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1461823000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1461823000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2088243000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2088243000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3550066000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3550066000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122332 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122332 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049501 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049501 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087087 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087087 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002322 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002322 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092622 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092622 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092622 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092622 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22166.435232 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22166.435232 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27982.892957 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27982.892957 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11228.058669 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11228.058669 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7934.833708 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7934.833708 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23434.532785 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23434.532785 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23434.532785 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23434.532785 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 679069 # number of writebacks +system.cpu0.dcache.writebacks::total 679069 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938249 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 938249 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251643 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251643 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13638 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13638 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5458 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5458 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1189892 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1189892 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1189892 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1189892 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21646065000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21646065000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7698041000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7698041000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 120630000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 120630000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 56880500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 56880500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29344106000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 29344106000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29344106000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 29344106000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465334500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465334500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2275733500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2275733500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3741068000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3741068000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127739 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127739 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051278 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051278 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088602 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088602 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035586 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035586 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097115 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097115 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097115 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097115 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 23070.704046 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 23070.704046 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30591.119165 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30591.119165 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8845.138583 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8845.138583 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 10421.491389 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 10421.491389 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24661.150760 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24661.150760 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24661.150760 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24661.150760 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -857,22 +856,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1027530 # DTB read hits -system.cpu1.dtb.read_misses 2750 # DTB read misses -system.cpu1.dtb.read_acv 36 # DTB read access violations -system.cpu1.dtb.read_accesses 205838 # DTB read accesses -system.cpu1.dtb.write_hits 663193 # DTB write hits -system.cpu1.dtb.write_misses 356 # DTB write misses -system.cpu1.dtb.write_acv 48 # DTB write access violations -system.cpu1.dtb.write_accesses 97040 # DTB write accesses -system.cpu1.dtb.data_hits 1690723 # DTB hits -system.cpu1.dtb.data_misses 3106 # DTB misses -system.cpu1.dtb.data_acv 84 # DTB access violations -system.cpu1.dtb.data_accesses 302878 # DTB accesses -system.cpu1.itb.fetch_hits 1394871 # ITB hits -system.cpu1.itb.fetch_misses 1246 # ITB misses -system.cpu1.itb.fetch_acv 41 # ITB acv -system.cpu1.itb.fetch_accesses 1396117 # ITB accesses +system.cpu1.dtb.read_hits 2425080 # DTB read hits +system.cpu1.dtb.read_misses 2992 # DTB read misses +system.cpu1.dtb.read_acv 0 # DTB read access violations +system.cpu1.dtb.read_accesses 239363 # DTB read accesses +system.cpu1.dtb.write_hits 1761000 # DTB write hits +system.cpu1.dtb.write_misses 341 # DTB write misses +system.cpu1.dtb.write_acv 29 # DTB write access violations +system.cpu1.dtb.write_accesses 105247 # DTB write accesses +system.cpu1.dtb.data_hits 4186080 # DTB hits +system.cpu1.dtb.data_misses 3333 # DTB misses +system.cpu1.dtb.data_acv 29 # DTB access violations +system.cpu1.dtb.data_accesses 344610 # DTB accesses +system.cpu1.itb.fetch_hits 1964871 # ITB hits +system.cpu1.itb.fetch_misses 1216 # ITB misses +system.cpu1.itb.fetch_acv 0 # ITB acv +system.cpu1.itb.fetch_accesses 1966087 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -885,150 +884,141 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3923836552 # number of cpu cycles simulated +system.cpu1.numCycles 3911492481 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5254013 # Number of instructions committed -system.cpu1.committedOps 5254013 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 4921025 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 25430 # Number of float alu accesses -system.cpu1.num_func_calls 157600 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 506865 # number of instructions that are conditional controls -system.cpu1.num_int_insts 4921025 # number of integer instructions -system.cpu1.num_fp_insts 25430 # number of float instructions -system.cpu1.num_int_register_reads 6827399 # number of times the integer registers were read -system.cpu1.num_int_register_writes 3700117 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 16282 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 16129 # number of times the floating registers were written -system.cpu1.num_mem_refs 1700348 # number of memory refs -system.cpu1.num_load_insts 1033584 # Number of load instructions -system.cpu1.num_store_insts 666764 # Number of store instructions -system.cpu1.num_idle_cycles 3903107404.303190 # Number of idle cycles -system.cpu1.num_busy_cycles 20729147.696810 # Number of busy cycles -system.cpu1.not_idle_fraction 0.005283 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.994717 # Percentage of idle cycles +system.cpu1.committedInsts 13183934 # Number of instructions committed +system.cpu1.committedOps 13183934 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12160396 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 172922 # Number of float alu accesses +system.cpu1.num_func_calls 412685 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1307407 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12160396 # number of integer instructions +system.cpu1.num_fp_insts 172922 # number of float instructions +system.cpu1.num_int_register_reads 16740645 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8924669 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 90471 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 92344 # number of times the floating registers were written +system.cpu1.num_mem_refs 4209624 # number of memory refs +system.cpu1.num_load_insts 2439377 # Number of load instructions +system.cpu1.num_store_insts 1770247 # Number of store instructions +system.cpu1.num_idle_cycles 3861803254.998025 # Number of idle cycles +system.cpu1.num_busy_cycles 49689226.001975 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012703 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987297 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2331 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 35942 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 9143 31.85% 31.85% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1973 6.87% 38.72% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 91 0.32% 39.04% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17499 60.96% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 28706 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 9135 45.13% 45.13% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1973 9.75% 54.87% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 9044 44.68% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 20243 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1920766593500 97.90% 97.90% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 726074500 0.04% 97.94% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 67017000 0.00% 97.94% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 40358561000 2.06% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1961918246000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999125 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78634 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26575 38.36% 38.36% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1967 2.84% 41.20% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 503 0.73% 41.93% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40225 58.07% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69270 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25736 48.16% 48.16% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1967 3.68% 51.84% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 503 0.94% 52.78% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25233 47.22% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53439 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909053778500 97.61% 97.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 705460500 0.04% 97.65% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 351339000 0.02% 97.67% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 45634904500 2.33% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1955745482500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968429 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.516830 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.705184 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 2 1.96% 1.96% # number of syscalls executed -system.cpu1.kern.syscall::3 11 10.78% 12.75% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.98% 13.73% # number of syscalls executed -system.cpu1.kern.syscall::6 12 11.76% 25.49% # number of syscalls executed -system.cpu1.kern.syscall::17 5 4.90% 30.39% # number of syscalls executed -system.cpu1.kern.syscall::19 4 3.92% 34.31% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.96% 36.27% # number of syscalls executed -system.cpu1.kern.syscall::23 2 1.96% 38.24% # number of syscalls executed -system.cpu1.kern.syscall::24 2 1.96% 40.20% # number of syscalls executed -system.cpu1.kern.syscall::33 3 2.94% 43.14% # number of syscalls executed -system.cpu1.kern.syscall::45 15 14.71% 57.84% # number of syscalls executed -system.cpu1.kern.syscall::47 2 1.96% 59.80% # number of syscalls executed -system.cpu1.kern.syscall::48 3 2.94% 62.75% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.98% 63.73% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.96% 65.69% # number of syscalls executed -system.cpu1.kern.syscall::71 22 21.57% 87.25% # number of syscalls executed -system.cpu1.kern.syscall::74 7 6.86% 94.12% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.98% 95.10% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.96% 97.06% # number of syscalls executed -system.cpu1.kern.syscall::132 2 1.96% 99.02% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.98% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 102 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.627296 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771460 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed +system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed +system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed +system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 365 1.24% 1.27% # number of callpals executed -system.cpu1.kern.callpal::tbi 10 0.03% 1.31% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.33% # number of callpals executed -system.cpu1.kern.callpal::swpipl 24054 81.82% 83.15% # number of callpals executed -system.cpu1.kern.callpal::rdps 2165 7.36% 90.51% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 90.52% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 90.53% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.01% 90.53% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 90.54% # number of callpals executed -system.cpu1.kern.callpal::rti 2587 8.80% 99.34% # number of callpals executed -system.cpu1.kern.callpal::callsys 161 0.55% 99.89% # number of callpals executed -system.cpu1.kern.callpal::imb 31 0.11% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 420 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1995 2.79% 3.38% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed +system.cpu1.kern.callpal::swpipl 63027 88.05% 91.44% # number of callpals executed +system.cpu1.kern.callpal::rdps 2168 3.03% 94.47% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.47% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.47% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.48% # number of callpals executed +system.cpu1.kern.callpal::rti 3772 5.27% 99.75% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 29399 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 879 # number of protection mode switches -system.cpu1.kern.mode_switch::user 515 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2075 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 531 -system.cpu1.kern.mode_good::user 515 -system.cpu1.kern.mode_good::idle 16 -system.cpu1.kern.mode_switch_good::kernel 0.604096 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 71584 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2065 # number of protection mode switches +system.cpu1.kern.mode_switch::user 464 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2874 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 891 +system.cpu1.kern.mode_good::user 464 +system.cpu1.kern.mode_good::idle 427 +system.cpu1.kern.mode_switch_good::kernel 0.431477 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.007711 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.306140 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4075179000 0.21% 0.21% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1593973000 0.08% 0.29% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1955466537000 99.71% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 366 # number of times the context was actually changed -system.cpu1.icache.replacements 86678 # number of replacements -system.cpu1.icache.tagsinuse 419.761864 # Cycle average of tags in use -system.cpu1.icache.total_refs 5169985 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 87190 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 59.295619 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1958463060000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 419.761864 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.819847 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.819847 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 5169985 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5169985 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5169985 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5169985 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5169985 # number of overall hits -system.cpu1.icache.overall_hits::total 5169985 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 87218 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 87218 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 87218 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 87218 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 87218 # number of overall misses -system.cpu1.icache.overall_misses::total 87218 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1315004000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1315004000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1315004000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1315004000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1315004000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1315004000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5257203 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5257203 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5257203 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5257203 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5257203 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5257203 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016590 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.016590 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016590 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.016590 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016590 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.016590 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15077.208833 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15077.208833 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15077.208833 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15077.208833 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15077.208833 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15077.208833 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.148573 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.329817 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17893399500 0.91% 0.91% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1709951500 0.09% 1.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1936142128000 99.00% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1996 # number of times the context was actually changed +system.cpu1.icache.replacements 316204 # number of replacements +system.cpu1.icache.tagsinuse 447.456269 # Cycle average of tags in use +system.cpu1.icache.total_refs 12870545 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 316716 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 40.637495 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1953875803000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 447.456269 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.873938 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.873938 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 12870545 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12870545 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12870545 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12870545 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12870545 # number of overall hits +system.cpu1.icache.overall_hits::total 12870545 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 316752 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 316752 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 316752 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 316752 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 316752 # number of overall misses +system.cpu1.icache.overall_misses::total 316752 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4179857000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4179857000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4179857000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4179857000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4179857000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4179857000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13187297 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13187297 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13187297 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13187297 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13187297 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13187297 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024019 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024019 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024019 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024019 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024019 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024019 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13195.992448 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13195.992448 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13195.992448 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13195.992448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13195.992448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13195.992448 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1037,112 +1027,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 87218 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 87218 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 87218 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 87218 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 87218 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 87218 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1053316500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1053316500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1053316500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1053316500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1053316500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1053316500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016590 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.016590 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.016590 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12076.824738 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12076.824738 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12076.824738 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12076.824738 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12076.824738 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12076.824738 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316752 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 316752 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 316752 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 316752 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 316752 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 316752 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3546353000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3546353000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3546353000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3546353000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3546353000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3546353000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024019 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024019 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024019 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11195.992448 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11195.992448 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11195.992448 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 53530 # number of replacements -system.cpu1.dcache.tagsinuse 416.811223 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1627239 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 53938 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 30.168694 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1941569871000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 416.811223 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.814084 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.814084 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 982758 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 982758 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 626472 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 626472 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 11310 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 11310 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11707 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 11707 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1609230 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1609230 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1609230 # number of overall hits -system.cpu1.dcache.overall_hits::total 1609230 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 35626 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 35626 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 22614 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 22614 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1003 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1003 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 544 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 544 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 58240 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 58240 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 58240 # number of overall misses -system.cpu1.dcache.overall_misses::total 58240 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 484494000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 484494000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 694414000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 694414000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 12192000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 12192000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 7087000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 7087000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 1178908000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 1178908000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 1178908000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 1178908000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1018384 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1018384 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 649086 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 649086 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 12313 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 12313 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 12251 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 12251 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1667470 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1667470 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1667470 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1667470 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034983 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.034983 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034840 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034840 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081459 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.081459 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044405 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044405 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034927 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.034927 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034927 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.034927 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13599.449840 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13599.449840 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30707.260989 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 30707.260989 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12155.533400 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12155.533400 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13027.573529 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13027.573529 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20242.239011 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20242.239011 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20242.239011 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20242.239011 # average overall miss latency +system.cpu1.dcache.replacements 166318 # number of replacements +system.cpu1.dcache.tagsinuse 487.121043 # Cycle average of tags in use +system.cpu1.dcache.total_refs 4017452 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 166830 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 24.081113 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 63885131000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 487.121043 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.951408 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.951408 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2260833 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2260833 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1643465 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1643465 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48243 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 48243 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50839 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50839 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3904298 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3904298 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3904298 # number of overall hits +system.cpu1.dcache.overall_hits::total 3904298 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 118301 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 118301 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 62725 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 62725 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8915 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8915 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5846 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5846 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 181026 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 181026 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 181026 # number of overall misses +system.cpu1.dcache.overall_misses::total 181026 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1440550500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1440550500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1113565500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1113565500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81445500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 81445500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 69062000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 69062000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2554116000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2554116000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2554116000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2554116000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2379134 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2379134 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1706190 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1706190 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57158 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 57158 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56685 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 56685 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4085324 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4085324 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4085324 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4085324 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049724 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049724 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036763 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.036763 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155971 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155971 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103131 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103131 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044311 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044311 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044311 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044311 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12176.993432 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12176.993432 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17753.136708 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17753.136708 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9135.782389 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9135.782389 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11813.547725 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11813.547725 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14109.111398 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14109.111398 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14109.111398 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14109.111398 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1151,62 +1141,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 35195 # number of writebacks -system.cpu1.dcache.writebacks::total 35195 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 35626 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 35626 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 22614 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 22614 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1003 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1003 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 544 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 544 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 58240 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 58240 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 58240 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 58240 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 377607005 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 377607005 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 626568004 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 626568004 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9183000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 9183000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5455000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5455000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1004175009 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1004175009 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1004175009 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1004175009 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 20565000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 20565000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 534647000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 534647000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 555212000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 555212000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.034983 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.034983 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034840 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034840 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.081459 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.081459 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.044405 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.044405 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034927 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.034927 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034927 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034927 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10599.197356 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10599.197356 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27707.084284 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27707.084284 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9155.533400 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9155.533400 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10027.573529 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10027.573529 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17242.015951 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17242.015951 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17242.015951 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17242.015951 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 114265 # number of writebacks +system.cpu1.dcache.writebacks::total 114265 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118301 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 118301 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62725 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 62725 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8915 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8915 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5846 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5846 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 181026 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 181026 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 181026 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 181026 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1203948500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1203948500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 988115500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 988115500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63615500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 63615500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57370000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57370000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2192064000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2192064000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2192064000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2192064000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19387500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19387500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713392500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713392500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732780000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732780000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049724 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049724 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036763 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036763 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155971 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155971 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103131 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103131 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044311 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044311 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044311 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044311 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10176.993432 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10176.993432 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15753.136708 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15753.136708 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7135.782389 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7135.782389 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9813.547725 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9813.547725 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12109.111398 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12109.111398 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12109.111398 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12109.111398 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 23658f386..369a1e336 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.914421 # Nu sim_ticks 1914420945000 # Number of ticks simulated final_tick 1914420945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1284205 # Simulator instruction rate (inst/s) -host_op_rate 1284205 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43773036105 # Simulator tick rate (ticks/s) -host_mem_usage 295308 # Number of bytes of host memory used -host_seconds 43.74 # Real time elapsed on the host +host_inst_rate 1299276 # Simulator instruction rate (inst/s) +host_op_rate 1299275 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44286723014 # Simulator tick rate (ticks/s) +host_mem_usage 288696 # Number of bytes of host memory used +host_seconds 43.23 # Real time elapsed on the host sim_insts 56164879 # Number of instructions simulated sim_ops 56164879 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory @@ -87,11 +87,11 @@ system.iocache.demand_avg_miss_latency::tsunami.ide 274768.790989 system.iocache.demand_avg_miss_latency::total 274768.790989 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency system.iocache.overall_avg_miss_latency::total 274768.790989 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 199052000 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 199052 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 24614 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8086.942391 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.086942 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -105,14 +105,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9283200000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9283200000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9294876000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9294876000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9294876000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9294876000 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11676998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9283350806 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9283350806 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9295027804 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9295027804 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9295027804 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9295027804 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -121,14 +121,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223411.628802 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 223411.628802 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222765.152786 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 222765.152786 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222765.152786 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 222765.152786 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67497.098266 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67497.098266 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223415.258134 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 223415.258134 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222768.790989 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 222768.790989 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222768.790989 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 222768.790989 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -649,14 +649,14 @@ system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10884274000 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11416158000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675219000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675219000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675219500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675219500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 531884000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559493000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16091377000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559493500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16091377500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 531884000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559493000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16091377000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559493500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16091377500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1332180000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1332180000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892328500 # number of WriteReq MSHR uncacheable cycles @@ -681,14 +681,14 @@ system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40020.127220 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40020.185094 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.350739 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.350739 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.355018 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.355018 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40016.287365 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40016.455328 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40016.288651 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40016.456571 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40016.287365 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40016.455328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40016.288651 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40016.456571 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 0ffcacbe4..0a013f420 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,75 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.207291 # Number of seconds simulated -sim_ticks 1207290627000 # Number of ticks simulated -final_tick 1207290627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.203695 # Number of seconds simulated +sim_ticks 1203694548000 # Number of ticks simulated +final_tick 1203694548000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 648322 # Simulator instruction rate (inst/s) -host_op_rate 826248 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12731770448 # Simulator tick rate (ticks/s) -host_mem_usage 380152 # Number of bytes of host memory used -host_seconds 94.83 # Real time elapsed on the host -sim_insts 61477134 # Number of instructions simulated -sim_ops 78349023 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 52642784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 394084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4718772 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 323100 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4791152 # Number of bytes read from this memory -system.physmem.bytes_read::total 62870404 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 394084 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 323100 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4105920 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7133264 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 6580348 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12376 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5130 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74888 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6746553 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64155 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 820991 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43604069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 106 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 326420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3908563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 267624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3968516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52075617 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 326420 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 267624 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 594044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3400938 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14081 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2493471 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5908490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3400938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43604069 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 326420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3922645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 212 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 267624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6461987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57984106 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 610810 # Simulator instruction rate (inst/s) +host_op_rate 778429 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11963163223 # Simulator tick rate (ticks/s) +host_mem_usage 383784 # Number of bytes of host memory used +host_seconds 100.62 # Real time elapsed on the host +sim_insts 61457649 # Number of instructions simulated +sim_ops 78322983 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -88,251 +29,292 @@ system.realview.nvmem.bw_inst_read::total 56 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 69267 # number of replacements -system.l2c.tagsinuse 52917.687101 # Cycle average of tags in use -system.l2c.total_refs 1645693 # Total number of references to valid blocks. -system.l2c.sampled_refs 134464 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.238912 # Average number of references to valid blocks. +system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 354404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4259252 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 364636 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5307760 # Number of bytes read from this memory +system.physmem.bytes_read::total 62191012 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 354404 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 364636 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 719040 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4163840 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory +system.physmem.bytes_written::total 7191184 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11756 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 66623 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5779 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82960 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6655189 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 65060 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory +system.physmem.num_writes::total 821896 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43120999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 294430 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3538482 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 302931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4409557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51666772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 294430 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 302931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 597361 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3459216 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14123 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2500920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5974260 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3459216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43120999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 294430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3552606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 302931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6910477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57641032 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 70187 # number of replacements +system.l2c.tagsinuse 53228.642974 # Cycle average of tags in use +system.l2c.total_refs 1643789 # Total number of references to valid blocks. +system.l2c.sampled_refs 135350 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.144728 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40124.661917 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000403 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001466 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3720.854167 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4213.259554 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.746626 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.001732 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2800.295591 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2055.865645 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.612254 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 40454.040636 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 0.000402 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.003088 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3394.914064 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2735.381228 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 2.669984 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3118.851455 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3522.782116 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.617280 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056776 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.064289 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.042729 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.031370 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.807460 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4114 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1841 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 402307 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 205875 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5723 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1959 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 449970 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 144091 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1215880 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 572580 # number of Writeback hits -system.l2c.Writeback_hits::total 572580 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1130 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 572 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1702 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 212 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 316 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56723 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 53017 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109740 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4114 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1841 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 402307 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 262598 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5723 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1959 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 449970 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 197108 # number of demand (read+write) hits -system.l2c.demand_hits::total 1325620 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4114 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1841 # number of overall hits -system.l2c.overall_hits::cpu0.inst 402307 # number of overall hits -system.l2c.overall_hits::cpu0.data 262598 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5723 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1959 # number of overall hits -system.l2c.overall_hits::cpu1.inst 449970 # number of overall hits -system.l2c.overall_hits::cpu1.data 197108 # number of overall hits -system.l2c.overall_hits::total 1325620 # number of overall hits +system.l2c.occ_percent::cpu0.inst 0.051802 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.041739 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.047590 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.053753 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.812205 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 2523 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1490 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 278283 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 124654 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5208 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1502 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 576279 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 223386 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1213325 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 571443 # number of Writeback hits +system.l2c.Writeback_hits::total 571443 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 992 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 888 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1880 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 191 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 95 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 286 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 39230 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 70245 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 109475 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 2523 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1490 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 278283 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 163884 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5208 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1502 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 576279 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 293631 # number of demand (read+write) hits +system.l2c.demand_hits::total 1322800 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 2523 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1490 # number of overall hits +system.l2c.overall_hits::cpu0.inst 278283 # number of overall hits +system.l2c.overall_hits::cpu0.data 163884 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5208 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1502 # number of overall hits +system.l2c.overall_hits::cpu1.inst 576279 # number of overall hits +system.l2c.overall_hits::cpu1.data 293631 # number of overall hits +system.l2c.overall_hits::total 1322800 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 5744 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 7874 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5043 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 3639 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22308 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4704 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3584 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8288 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 569 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 485 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1054 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 67193 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 72340 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139533 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 5124 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6001 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 5692 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 5607 # number of ReadReq misses +system.l2c.ReadReq_misses::total 22431 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 4012 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4909 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8921 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 655 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 388 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1043 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 61449 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 78839 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140288 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 5744 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 75067 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5043 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 75979 # number of demand (read+write) misses -system.l2c.demand_misses::total 161841 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 5124 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 67450 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 5692 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 84446 # number of demand (read+write) misses +system.l2c.demand_misses::total 162719 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 5744 # number of overall misses -system.l2c.overall_misses::cpu0.data 75067 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 5043 # number of overall misses -system.l2c.overall_misses::cpu1.data 75979 # number of overall misses -system.l2c.overall_misses::total 161841 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu0.inst 5124 # number of overall misses +system.l2c.overall_misses::cpu0.data 67450 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu1.inst 5692 # number of overall misses +system.l2c.overall_misses::cpu1.data 84446 # number of overall misses +system.l2c.overall_misses::total 162719 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 104000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 298939500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 409670500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 208500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 263172000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 189494500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1161693500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 30053000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 27343000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 57396000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3692000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6036000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 9728000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3494513965 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3764719994 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7259233959 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 156500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 268094000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 313174000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 160000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 298650000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 293295000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1173581500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 15964999 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 31408500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 47373499 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1462500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6173000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 7635500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3221682991 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4131389996 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7353072987 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 104000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 298939500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3904184465 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 208500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 52500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 263172000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3954214494 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8420927459 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 156500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 268094000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3534856991 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 160000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 298650000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4424684996 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8526654487 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 104000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 298939500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3904184465 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 208500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 52500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 263172000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3954214494 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8420927459 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4115 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 1843 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 408051 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 213749 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5727 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1960 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 455013 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 147730 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1238188 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 572580 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 572580 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 5834 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4156 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 9990 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 781 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 589 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1370 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 123916 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 125357 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 249273 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4115 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 1843 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 408051 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 337665 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5727 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1960 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 455013 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 273087 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1487461 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4115 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 1843 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 408051 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 337665 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5727 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1960 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 455013 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 273087 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1487461 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000243 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001085 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014077 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036838 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000510 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.011083 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024633 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.018017 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.806308 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.862368 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.829630 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.728553 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.823430 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.769343 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.542246 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.577072 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.559760 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000243 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.001085 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014077 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.222312 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000510 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.011083 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.278223 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.108804 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000243 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.001085 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014077 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.222312 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000510 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.011083 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.278223 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.108804 # miss rate for overall accesses +system.l2c.overall_miss_latency::cpu0.itb.walker 156500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 268094000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3534856991 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 160000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 298650000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4424684996 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8526654487 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 2524 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1493 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 283407 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 130655 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5211 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1502 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 581971 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 228993 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1235756 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 571443 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 571443 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 5004 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5797 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10801 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 846 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 483 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1329 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 100679 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 149084 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 249763 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 2524 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1493 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 283407 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 231334 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5211 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1502 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 581971 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 378077 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1485519 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 2524 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1493 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 283407 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 231334 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5211 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1502 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 581971 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 378077 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1485519 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.002009 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.018080 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.045930 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000576 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009781 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024485 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.018152 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.801759 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.846817 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.825942 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.774232 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.803313 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.784801 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.610346 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.528823 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.561684 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.002009 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018080 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.291570 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000576 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009781 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.223357 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.109537 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.002009 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018080 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.291570 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000576 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009781 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.223357 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.109537 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52043.784819 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52028.257557 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52125 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52185.603807 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52073.234405 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52075.197239 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6388.818027 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7629.185268 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 6925.193050 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6488.576450 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12445.360825 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 9229.601518 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52007.113315 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52042.023694 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52025.212380 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52166.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52321.233411 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52186.968839 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 53333.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52468.376669 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52308.721241 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52319.624627 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3979.311815 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6398.146262 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5310.335052 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2232.824427 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15909.793814 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 7320.709492 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52428.566632 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52402.871624 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52414.126561 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52043.784819 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52009.331197 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52185.603807 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52043.518525 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52032.102242 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52166.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52321.233411 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52407.071772 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 53333.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52468.376669 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52396.620278 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52401.099361 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52043.784819 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52009.331197 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52185.603807 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52043.518525 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52032.102242 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52166.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52321.233411 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52407.071772 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 53333.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52468.376669 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52396.620278 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52401.099361 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,8 +323,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 64155 # number of writebacks -system.l2c.writebacks::total 64155 # number of writebacks +system.l2c.writebacks::writebacks 65060 # number of writebacks +system.l2c.writebacks::total 65060 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits @@ -350,162 +332,150 @@ system.l2c.demand_mshr_hits::total 1 # nu system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 5743 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 7874 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 5043 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 3639 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 22307 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 4704 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3584 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8288 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 569 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 485 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1054 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 67193 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 72340 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 139533 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 5123 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6001 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 5692 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 5607 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 22430 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 4012 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 4909 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8921 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 655 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 388 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1043 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 61449 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 78839 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140288 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 5743 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 75067 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 5043 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 75979 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 161840 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 5123 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 67450 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 5692 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 84446 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 162718 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 5743 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 75067 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 5043 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 75979 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 161840 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 5123 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 67450 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 5692 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 84446 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 162718 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 80000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 229995000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 315180000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 160000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 202652000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 145824000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 893971000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 188550000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 143713000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 332263000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22778000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 19436000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 42214000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2688153000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2896625000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5584778000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 120000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 204994000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 240097000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 124000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 228616000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 224783500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 898774500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 160670998 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 196506499 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 357177497 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 26201999 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 15527999 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 41729998 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2458624491 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3165174496 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5623798987 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 40000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 80000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 229995000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 3003333000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 40000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 202652000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3042449000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6478749000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 120000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 204994000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2698721491 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 124000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 228616000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3389957996 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6522573487 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 40000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 229995000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 3003333000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 160000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 40000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 202652000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3042449000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6478749000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 120000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 204994000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2698721491 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 124000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 228616000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3389957996 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6522573487 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12448669498 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154365762499 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167083912997 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1128303000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30843801500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 31972104500 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 11136775500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155704815500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167111072500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1070730500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30910255000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31980985500 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13576972498 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185209563999 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 199056017497 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036838 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024633 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.018016 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.806308 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.862368 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.829630 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.728553 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.823430 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.769343 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.542246 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577072 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.559760 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.222312 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.278223 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.108803 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.222312 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.278223 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.108803 # mshr miss rate for overall accesses +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12207506000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 186615070500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 199092058000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018076 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.045930 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000576 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009781 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024485 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.018151 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.801759 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.846817 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.825942 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.774232 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.803313 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.784801 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.610346 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.528823 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.561684 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018076 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.291570 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000576 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009781 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.223357 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.109536 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018076 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.291570 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000576 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009781 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.223357 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.109536 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40027.940056 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40072.547403 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40075.805801 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40082.908163 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40098.493304 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40089.647683 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.634446 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40074.226804 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.233397 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40006.444124 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40041.816422 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40024.782668 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40009.498417 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40089.798466 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40070.196166 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40047.606680 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40029.842942 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.831745 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40003.051908 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40020.615979 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40009.585810 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40010.813699 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40147.319169 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40087.526994 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40010.696679 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40143.499941 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40085.138012 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40010.696679 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40143.499941 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40085.138012 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -528,27 +498,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7076084 # DTB read hits -system.cpu0.dtb.read_misses 3743 # DTB read misses -system.cpu0.dtb.write_hits 5660386 # DTB write hits -system.cpu0.dtb.write_misses 804 # DTB write misses +system.cpu0.dtb.read_hits 4800541 # DTB read hits +system.cpu0.dtb.read_misses 2116 # DTB read misses +system.cpu0.dtb.write_hits 4101169 # DTB write hits +system.cpu0.dtb.write_misses 405 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1539 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7079827 # DTB read accesses -system.cpu0.dtb.write_accesses 5661190 # DTB write accesses +system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 4802657 # DTB read accesses +system.cpu0.dtb.write_accesses 4101574 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12736470 # DTB hits -system.cpu0.dtb.misses 4547 # DTB misses -system.cpu0.dtb.accesses 12741017 # DTB accesses -system.cpu0.itb.inst_hits 29574655 # ITB inst hits -system.cpu0.itb.inst_misses 2205 # ITB inst misses +system.cpu0.dtb.hits 8901710 # DTB hits +system.cpu0.dtb.misses 2521 # DTB misses +system.cpu0.dtb.accesses 8904231 # DTB accesses +system.cpu0.itb.inst_hits 19425295 # ITB inst hits +system.cpu0.itb.inst_misses 1350 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -557,86 +527,86 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29576860 # ITB inst accesses -system.cpu0.itb.hits 29574655 # DTB hits -system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29576860 # DTB accesses -system.cpu0.numCycles 2414581254 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 19426645 # ITB inst accesses +system.cpu0.itb.hits 19425295 # DTB hits +system.cpu0.itb.misses 1350 # DTB misses +system.cpu0.itb.accesses 19426645 # DTB accesses +system.cpu0.numCycles 2405961611 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28876799 # Number of instructions committed -system.cpu0.committedOps 37228975 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33114839 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241592 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4373527 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33114839 # number of integer instructions -system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 190147140 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36238708 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13404188 # number of memory refs -system.cpu0.num_load_insts 7413537 # Number of load instructions -system.cpu0.num_store_insts 5990651 # Number of store instructions -system.cpu0.num_idle_cycles 2267023582.330122 # Number of idle cycles -system.cpu0.num_busy_cycles 147557671.669878 # Number of busy cycles -system.cpu0.not_idle_fraction 0.061111 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.938889 # Percentage of idle cycles +system.cpu0.committedInsts 19048182 # Number of instructions committed +system.cpu0.committedOps 25051772 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 22684080 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses +system.cpu0.num_func_calls 868675 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 2620305 # number of instructions that are conditional controls +system.cpu0.num_int_insts 22684080 # number of integer instructions +system.cpu0.num_fp_insts 4364 # number of float instructions +system.cpu0.num_int_register_reads 128950966 # number of times the integer registers were read +system.cpu0.num_int_register_writes 23731370 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written +system.cpu0.num_mem_refs 9388163 # number of memory refs +system.cpu0.num_load_insts 5047859 # Number of load instructions +system.cpu0.num_store_insts 4340304 # Number of store instructions +system.cpu0.num_idle_cycles 2301502404.823749 # Number of idle cycles +system.cpu0.num_busy_cycles 104459206.176251 # Number of busy cycles +system.cpu0.not_idle_fraction 0.043417 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.956583 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46683 # number of quiesce instructions executed -system.cpu0.icache.replacements 408135 # number of replacements -system.cpu0.icache.tagsinuse 509.469782 # Cycle average of tags in use -system.cpu0.icache.total_refs 29165991 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 408647 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 71.372091 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 75845657000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.469782 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995058 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995058 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29165991 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29165991 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29165991 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29165991 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29165991 # number of overall hits -system.cpu0.icache.overall_hits::total 29165991 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 408647 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 408647 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 408647 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 408647 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 408647 # number of overall misses -system.cpu0.icache.overall_misses::total 408647 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6096279000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6096279000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6096279000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6096279000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6096279000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6096279000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29574638 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29574638 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29574638 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29574638 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29574638 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29574638 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013817 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013817 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013817 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013817 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013817 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013817 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.203241 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.203241 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14918.203241 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14918.203241 # average overall miss latency +system.cpu0.kern.inst.quiesce 34020 # number of quiesce instructions executed +system.cpu0.icache.replacements 283184 # number of replacements +system.cpu0.icache.tagsinuse 509.502628 # Cycle average of tags in use +system.cpu0.icache.total_refs 19141582 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 283696 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 67.472160 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 75588601000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.502628 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995122 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995122 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 19141582 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 19141582 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 19141582 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 19141582 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 19141582 # number of overall hits +system.cpu0.icache.overall_hits::total 19141582 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 283696 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 283696 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 283696 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 283696 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 283696 # number of overall misses +system.cpu0.icache.overall_misses::total 283696 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 3929923500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 3929923500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 3929923500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 3929923500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 3929923500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 3929923500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 19425278 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 19425278 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 19425278 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 19425278 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 19425278 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 19425278 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014604 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014604 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014604 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014604 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014604 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014604 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13852.586924 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13852.586924 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13852.586924 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13852.586924 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13852.586924 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13852.586924 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -645,120 +615,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408647 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 408647 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 408647 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 408647 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 408647 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 408647 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869493500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4869493500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869493500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4869493500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869493500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4869493500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013817 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.013817 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.013817 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11916.136666 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 283696 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 283696 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 283696 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 283696 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 283696 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 283696 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 3362531500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 3362531500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 3362531500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 3362531500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 3362531500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 3362531500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 353907000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 353907000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 353907000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 353907000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014604 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014604 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014604 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014604 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014604 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014604 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11852.586924 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11852.586924 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11852.586924 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11852.586924 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11852.586924 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11852.586924 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 330734 # number of replacements -system.cpu0.dcache.tagsinuse 459.649702 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12280871 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 331246 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.074775 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 664264000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 459.649702 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.897753 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.897753 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6605687 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6605687 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5355220 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5355220 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147939 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 147939 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149683 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 149683 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11960907 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11960907 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11960907 # number of overall hits -system.cpu0.dcache.overall_hits::total 11960907 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 228053 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 228053 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 141722 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 141722 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9325 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9325 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7497 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7497 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 369775 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 369775 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 369775 # number of overall misses -system.cpu0.dcache.overall_misses::total 369775 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3443058000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3443058000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4918727500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4918727500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100897000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 100897000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74611000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 74611000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8361785500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 8361785500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8361785500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 8361785500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6833740 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6833740 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5496942 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5496942 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157264 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 157264 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157180 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 157180 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12330682 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12330682 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12330682 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12330682 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033372 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033372 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025782 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.025782 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059295 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059295 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047697 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047697 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029988 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029988 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029988 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029988 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15097.622044 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15097.622044 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34706.873315 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 34706.873315 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10820.053619 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10820.053619 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9952.114179 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9952.114179 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22613.171523 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 22613.171523 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.171523 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 22613.171523 # average overall miss latency +system.cpu0.dcache.replacements 220187 # number of replacements +system.cpu0.dcache.tagsinuse 456.524851 # Cycle average of tags in use +system.cpu0.dcache.total_refs 8560144 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 220557 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 38.811482 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 656029000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 456.524851 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.891650 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.891650 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 4452407 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 4452407 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3852535 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3852535 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117731 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 117731 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 117849 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 117849 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8304942 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8304942 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8304942 # number of overall hits +system.cpu0.dcache.overall_hits::total 8304942 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 146461 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 146461 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 116958 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 116958 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7880 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 7880 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7697 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7697 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 263419 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 263419 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 263419 # number of overall misses +system.cpu0.dcache.overall_misses::total 263419 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 1991314500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 1991314500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4199641500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4199641500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 70263500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 70263500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 66334500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 66334500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 6190956000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 6190956000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 6190956000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 6190956000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 4598868 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 4598868 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3969493 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 3969493 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125611 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 125611 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125546 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 125546 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 8568361 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 8568361 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8568361 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 8568361 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031847 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.031847 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.029464 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.029464 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062733 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062733 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061308 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.061308 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030743 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.030743 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030743 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.030743 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13596.209913 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13596.209913 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35907.261581 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 35907.261581 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 8916.687817 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8916.687817 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8618.227881 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8618.227881 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23502.313804 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 23502.313804 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23502.313804 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23502.313804 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -767,66 +737,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306480 # number of writebacks -system.cpu0.dcache.writebacks::total 306480 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228053 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 228053 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141722 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141722 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9325 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9325 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7489 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7489 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369775 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369775 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369775 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369775 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758303642 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758303642 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4493366071 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4493366071 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72896006 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72896006 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52131016 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52131016 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1001 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1001 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7251669713 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7251669713 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7251669713 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7251669713 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559876000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559876000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253192500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253192500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14813068500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14813068500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033372 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033372 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025782 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025782 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059295 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059295 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047646 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047646 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029988 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029988 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12095.011432 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12095.011432 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.494355 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.494355 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7817.266059 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.266059 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6961.011617 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6961.011617 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 204960 # number of writebacks +system.cpu0.dcache.writebacks::total 204960 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 146461 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 146461 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 116958 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 116958 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7880 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7880 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7695 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7695 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 263419 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 263419 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 263419 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 263419 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1698392500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1698392500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3965725500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3965725500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 54503500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 54503500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50946500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50946500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5664118000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5664118000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5664118000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5664118000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12130688000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12130688000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1193496500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1193496500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13324184500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13324184500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031847 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031847 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029464 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029464 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062733 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062733 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.061292 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.061292 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030743 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030743 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11596.209913 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11596.209913 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33907.261581 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33907.261581 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 6916.687817 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6916.687817 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6620.727745 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6620.727745 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21502.313804 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21502.313804 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21502.313804 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21502.313804 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -836,27 +806,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8318170 # DTB read hits -system.cpu1.dtb.read_misses 3663 # DTB read misses -system.cpu1.dtb.write_hits 5832653 # DTB write hits -system.cpu1.dtb.write_misses 1435 # DTB write misses +system.cpu1.dtb.read_hits 10590618 # DTB read hits +system.cpu1.dtb.read_misses 5230 # DTB read misses +system.cpu1.dtb.write_hits 7384755 # DTB write hits +system.cpu1.dtb.write_misses 1835 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1968 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2257 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8321833 # DTB read accesses -system.cpu1.dtb.write_accesses 5834088 # DTB write accesses +system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10595848 # DTB read accesses +system.cpu1.dtb.write_accesses 7386590 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14150823 # DTB hits -system.cpu1.dtb.misses 5098 # DTB misses -system.cpu1.dtb.accesses 14155921 # DTB accesses -system.cpu1.itb.inst_hits 33211066 # ITB inst hits -system.cpu1.itb.inst_misses 2171 # ITB inst misses +system.cpu1.dtb.hits 17975373 # DTB hits +system.cpu1.dtb.misses 7065 # DTB misses +system.cpu1.dtb.accesses 17982438 # DTB accesses +system.cpu1.itb.inst_hits 43340388 # ITB inst hits +system.cpu1.itb.inst_misses 3017 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -865,86 +835,86 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33213237 # ITB inst accesses -system.cpu1.itb.hits 33211066 # DTB hits -system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33213237 # DTB accesses -system.cpu1.numCycles 2413083038 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 43343405 # ITB inst accesses +system.cpu1.itb.hits 43340388 # DTB hits +system.cpu1.itb.misses 3017 # DTB misses +system.cpu1.itb.accesses 43343405 # DTB accesses +system.cpu1.numCycles 2407389096 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32600335 # Number of instructions committed -system.cpu1.committedOps 41120048 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37342001 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 963082 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3735102 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37342001 # number of integer instructions -system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 213831809 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39482622 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14689113 # number of memory refs -system.cpu1.num_load_insts 8640454 # Number of load instructions -system.cpu1.num_store_insts 6048659 # Number of store instructions -system.cpu1.num_idle_cycles 1863361359.722463 # Number of idle cycles -system.cpu1.num_busy_cycles 549721678.277537 # Number of busy cycles -system.cpu1.not_idle_fraction 0.227809 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.772191 # Percentage of idle cycles +system.cpu1.committedInsts 42409467 # Number of instructions committed +system.cpu1.committedOps 53271211 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 47739499 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses +system.cpu1.num_func_calls 1335008 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5483103 # number of instructions that are conditional controls +system.cpu1.num_int_insts 47739499 # number of integer instructions +system.cpu1.num_fp_insts 5457 # number of float instructions +system.cpu1.num_int_register_reads 274842107 # number of times the integer registers were read +system.cpu1.num_int_register_writes 51975033 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written +system.cpu1.num_mem_refs 18684058 # number of memory refs +system.cpu1.num_load_insts 11000639 # Number of load instructions +system.cpu1.num_store_insts 7683419 # Number of store instructions +system.cpu1.num_idle_cycles 1827105047.254482 # Number of idle cycles +system.cpu1.num_busy_cycles 580284048.745518 # Number of busy cycles +system.cpu1.not_idle_fraction 0.241043 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.758957 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43948 # number of quiesce instructions executed -system.cpu1.icache.replacements 455071 # number of replacements -system.cpu1.icache.tagsinuse 479.019014 # Cycle average of tags in use -system.cpu1.icache.total_refs 32755479 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 455583 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 71.897940 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 94151388000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 479.019014 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935584 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935584 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 32755479 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32755479 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32755479 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32755479 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32755479 # number of overall hits -system.cpu1.icache.overall_hits::total 32755479 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 455583 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 455583 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 455583 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 455583 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 455583 # number of overall misses -system.cpu1.icache.overall_misses::total 455583 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6728250000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6728250000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6728250000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6728250000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6728250000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6728250000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33211062 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33211062 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33211062 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33211062 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33211062 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33211062 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013718 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.013718 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013718 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.013718 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013718 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.013718 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.439560 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.439560 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14768.439560 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14768.439560 # average overall miss latency +system.cpu1.kern.inst.quiesce 56706 # number of quiesce instructions executed +system.cpu1.icache.replacements 582628 # number of replacements +system.cpu1.icache.tagsinuse 479.068937 # Cycle average of tags in use +system.cpu1.icache.total_refs 42757244 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 583140 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 73.322434 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 92849627500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 479.068937 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.935682 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.935682 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 42757244 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 42757244 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 42757244 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 42757244 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 42757244 # number of overall hits +system.cpu1.icache.overall_hits::total 42757244 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 583140 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 583140 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 583140 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 583140 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 583140 # number of overall misses +system.cpu1.icache.overall_misses::total 583140 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7853505000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7853505000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7853505000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7853505000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7853505000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7853505000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 43340384 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 43340384 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 43340384 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 43340384 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 43340384 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 43340384 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013455 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.013455 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013455 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.013455 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013455 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.013455 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13467.614981 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13467.614981 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13467.614981 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13467.614981 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13467.614981 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13467.614981 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -953,120 +923,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 455583 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 455583 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 455583 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 455583 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 455583 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 455583 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5360597500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5360597500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5360597500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5360597500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5360597500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5360597500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013718 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.013718 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.013718 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.456387 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.456387 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.456387 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 583140 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 583140 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 583140 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 583140 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 583140 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 583140 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6687225000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6687225000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6687225000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6687225000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6687225000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6687225000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5251000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5251000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5251000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 5251000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013455 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013455 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013455 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.013455 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013455 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.013455 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11467.614981 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11467.614981 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11467.614981 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11467.614981 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11467.614981 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11467.614981 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 292605 # number of replacements -system.cpu1.dcache.tagsinuse 473.034237 # Cycle average of tags in use -system.cpu1.dcache.total_refs 11973075 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 292945 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 40.871409 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 85130110000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 473.034237 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.923895 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.923895 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 6952995 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6952995 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4831955 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4831955 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81928 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 81928 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82891 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 82891 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11784950 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11784950 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11784950 # number of overall hits -system.cpu1.dcache.overall_hits::total 11784950 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 170988 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 170988 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 150171 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 150171 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11121 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11121 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10078 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10078 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 321159 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 321159 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 321159 # number of overall misses -system.cpu1.dcache.overall_misses::total 321159 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2374362000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2374362000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5137708000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 5137708000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106370500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 106370500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87843000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 87843000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 7512070000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 7512070000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 7512070000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 7512070000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 7123983 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7123983 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4982126 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4982126 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93049 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 93049 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92969 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 92969 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 12106109 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 12106109 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 12106109 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 12106109 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024002 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.024002 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030142 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030142 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119518 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119518 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108402 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108402 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026529 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026529 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026529 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.026529 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13886.132360 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13886.132360 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34212.384548 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34212.384548 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9564.832299 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9564.832299 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8716.312760 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8716.312760 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23390.501278 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23390.501278 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23390.501278 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23390.501278 # average overall miss latency +system.cpu1.dcache.replacements 401361 # number of replacements +system.cpu1.dcache.tagsinuse 473.304740 # Cycle average of tags in use +system.cpu1.dcache.total_refs 15681919 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 401873 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 39.022077 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 84382221000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 473.304740 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.924423 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.924423 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 9101949 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9101949 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6323711 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6323711 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 111853 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 111853 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 114473 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 114473 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 15425660 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 15425660 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 15425660 # number of overall hits +system.cpu1.dcache.overall_hits::total 15425660 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 253200 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 253200 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 178129 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 178129 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13100 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13100 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10404 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10404 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 431329 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 431329 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 431329 # number of overall misses +system.cpu1.dcache.overall_misses::total 431329 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3278248500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3278248500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5660664500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 5660664500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 115759000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 115759000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 63020500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 63020500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8938913000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8938913000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8938913000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8938913000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9355149 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9355149 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6501840 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6501840 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 124953 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 124953 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 124877 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 124877 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 15856989 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 15856989 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 15856989 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 15856989 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027065 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.027065 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027397 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027397 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104839 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104839 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083314 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083314 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027201 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027201 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027201 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.027201 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12947.268957 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12947.268957 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31778.455501 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 31778.455501 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8836.564885 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8836.564885 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6057.333718 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6057.333718 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20724.117785 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20724.117785 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20724.117785 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20724.117785 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1075,62 +1045,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 266100 # number of writebacks -system.cpu1.dcache.writebacks::total 266100 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170988 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170988 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150171 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 150171 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11121 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11121 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10070 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10070 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 321159 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 321159 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 321159 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 321159 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1860790612 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1860790612 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4686951190 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4686951190 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72983005 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72983005 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57622011 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57622011 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6547741802 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6547741802 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6547741802 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6547741802 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686201000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686201000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39932204000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39932204000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618405000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618405000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024002 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024002 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030142 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030142 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119518 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119518 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108316 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108316 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026529 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026529 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10882.580134 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10882.580134 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.760999 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.760999 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6562.629710 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6562.629710 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.146077 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.146077 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 366483 # number of writebacks +system.cpu1.dcache.writebacks::total 366483 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 253200 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 253200 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 178129 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 178129 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13100 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13100 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10399 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10399 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 431329 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 431329 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 431329 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 431329 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2771848500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2771848500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5304406500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5304406500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89559000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89559000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 42226500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 42226500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8076255000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8076255000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8076255000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8076255000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170163530000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170163530000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40377042500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40377042500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210540572500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210540572500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027065 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027065 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027397 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027397 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104839 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104839 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083274 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083274 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027201 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027201 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027201 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027201 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10947.268957 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10947.268957 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29778.455501 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29778.455501 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6836.564885 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6836.564885 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4060.630830 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4060.630830 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18724.117785 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18724.117785 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18724.117785 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18724.117785 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1152,10 +1126,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574279130811 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 574279130811 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574279130811 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 574279130811 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 567076826640 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 567076826640 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 567076826640 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 567076826640 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 07e356a30..e07e69ea6 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,28 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.624688 # Number of seconds simulated -sim_ticks 2624688029000 # Number of ticks simulated -final_tick 2624688029000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2624688000000 # Number of ticks simulated +final_tick 2624688000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 388710 # Simulator instruction rate (inst/s) -host_op_rate 494628 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16947208284 # Simulator tick rate (ticks/s) -host_mem_usage 385844 # Number of bytes of host memory used -host_seconds 154.87 # Real time elapsed on the host +host_inst_rate 509092 # Simulator instruction rate (inst/s) +host_op_rate 647812 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22195691402 # Simulator tick rate (ticks/s) +host_mem_usage 379628 # Number of bytes of host memory used +host_seconds 118.25 # Real time elapsed on the host sim_insts 60201138 # Number of instructions simulated sim_ops 76605123 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory @@ -60,7 +48,19 @@ system.physmem.bw_total::cpu.dtb.walker 122 # To system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 268917 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4596999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53608355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53608356 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -109,7 +109,7 @@ system.cpu.itb.inst_accesses 61499578 # IT system.cpu.itb.hits 61495107 # DTB hits system.cpu.itb.misses 4471 # DTB misses system.cpu.itb.accesses 61499578 # DTB accesses -system.cpu.numCycles 5249376058 # number of cpu cycles simulated +system.cpu.numCycles 5249376000 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 60201138 # Number of instructions committed @@ -121,14 +121,14 @@ system.cpu.num_conditional_control_insts 7948064 # nu system.cpu.num_int_insts 68872510 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions system.cpu.num_int_register_reads 394780312 # number of times the integer registers were read -system.cpu.num_int_register_writes 74180713 # number of times the integer registers were written +system.cpu.num_int_register_writes 74180711 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written system.cpu.num_mem_refs 27395681 # number of memory refs system.cpu.num_load_insts 15660705 # Number of load instructions system.cpu.num_store_insts 11734976 # Number of store instructions -system.cpu.num_idle_cycles 4573668194.612258 # Number of idle cycles -system.cpu.num_busy_cycles 675707863.387743 # Number of busy cycles +system.cpu.num_idle_cycles 4573668198.612257 # Number of idle cycles +system.cpu.num_busy_cycles 675707801.387743 # Number of busy cycles system.cpu.not_idle_fraction 0.128722 # Percentage of non-idle cycles system.cpu.idle_fraction 0.871278 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed @@ -154,12 +154,12 @@ system.cpu.icache.demand_misses::cpu.inst 856390 # n system.cpu.icache.demand_misses::total 856390 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 856390 # number of overall misses system.cpu.icache.overall_misses::total 856390 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11565472500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11565472500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11565472500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11565472500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11565472500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11565472500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11565531500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11565531500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11565531500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11565531500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11565531500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11565531500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 61495107 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 61495107 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 61495107 # number of demand (read+write) accesses @@ -172,12 +172,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.913065 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13504.913065 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.913065 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13504.913065 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.913065 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13504.913065 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.981959 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13504.981959 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.981959 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13504.981959 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.981959 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13504.981959 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -192,12 +192,12 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 856390 system.cpu.icache.demand_mshr_misses::total 856390 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 856390 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 856390 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9852692500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9852692500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9852692500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9852692500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9852692500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9852692500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9852751500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9852751500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9852751500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9852751500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9852751500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9852751500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 353004500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 353004500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 353004500 # number of overall MSHR uncacheable cycles @@ -208,58 +208,58 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013926 system.cpu.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11504.913065 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11504.913065 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11504.913065 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11504.913065 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11504.913065 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11504.913065 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11504.981959 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11504.981959 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11504.981959 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11504.981959 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11504.981959 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11504.981959 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 627202 # number of replacements +system.cpu.dcache.replacements 627203 # number of replacements system.cpu.dcache.tagsinuse 511.878516 # Cycle average of tags in use -system.cpu.dcache.total_refs 23656924 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627714 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.687425 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 23656923 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 627715 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.687363 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 653137000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.878516 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999763 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999763 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13196261 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13196261 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 13196260 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13196260 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 9973783 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 9973783 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 236291 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 236291 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247690 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247690 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23170044 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23170044 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23170044 # number of overall hits -system.cpu.dcache.overall_hits::total 23170044 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368703 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368703 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 23170043 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23170043 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23170043 # number of overall hits +system.cpu.dcache.overall_hits::total 23170043 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368704 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368704 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 250510 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 250510 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 11400 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 11400 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 619213 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 619213 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 619213 # number of overall misses -system.cpu.dcache.overall_misses::total 619213 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5201080500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5201080500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8976707500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8976707500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 619214 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 619214 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 619214 # number of overall misses +system.cpu.dcache.overall_misses::total 619214 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5201105500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5201105500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8977284500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8977284500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154794000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 154794000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14177788000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14177788000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14177788000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14177788000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14178390000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14178390000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14178390000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14178390000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 13564964 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13564964 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 10224293 # number of WriteReq accesses(hits+misses) @@ -282,16 +282,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.026029 system.cpu.dcache.demand_miss_rate::total 0.026029 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.026029 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.026029 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14106.423056 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14106.423056 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35833.729192 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35833.729192 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14106.452602 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14106.452602 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35836.032494 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35836.032494 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13578.421053 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13578.421053 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22896.463737 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22896.463737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22896.463737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22896.463737 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22897.398961 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22897.398961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22897.398961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22897.398961 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,32 +302,32 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 595968 # number of writebacks system.cpu.dcache.writebacks::total 595968 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368703 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368703 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368704 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368704 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250510 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11400 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 11400 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619213 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619213 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619213 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619213 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463674500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463674500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8475687500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8475687500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 619214 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619214 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619214 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619214 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463697500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463697500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8476264500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8476264500 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131994000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131994000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12939362000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12939362000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12939362000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12939362000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182162796000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182162796000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41387867000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41387867000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223550663000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 223550663000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12939962000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12939962000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12939962000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12939962000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182162296000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182162296000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41387676000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41387676000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223549972000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 223549972000 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027181 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027181 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024501 # mshr miss rate for WriteReq accesses @@ -338,16 +338,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026029 system.cpu.dcache.demand_mshr_miss_rate::total 0.026029 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026029 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.026029 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12106.423056 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12106.423056 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33833.729192 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33833.729192 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12106.452602 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12106.452602 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33836.032494 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33836.032494 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11578.421053 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11578.421053 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20896.463737 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20896.463737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20896.463737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20896.463737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20897.398961 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20897.398961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20897.398961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20897.398961 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -356,16 +356,16 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 61913 # number of replacements -system.cpu.l2cache.tagsinuse 50867.983375 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1683054 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 50867.983864 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1683055 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 127295 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 13.221682 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2574063802000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 37864.330216 # Average occupied blocks per requestor +system.cpu.l2cache.avg_refs 13.221690 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2574063892000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 37864.330390 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001416 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 6985.667758 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6014.098399 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 6985.667850 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6014.098622 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.577764 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -375,8 +375,8 @@ system.cpu.l2cache.occ_percent::total 0.776184 # Av system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8765 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3551 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 844136 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 370245 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226697 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 370246 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1226698 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 595968 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 595968 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits @@ -386,13 +386,13 @@ system.cpu.l2cache.ReadExReq_hits::total 114435 # nu system.cpu.l2cache.demand_hits::cpu.dtb.walker 8765 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3551 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 844136 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 484680 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1341132 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 484681 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1341133 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 8765 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3551 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 844136 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 484680 # number of overall hits -system.cpu.l2cache.overall_hits::total 1341132 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 484681 # number of overall hits +system.cpu.l2cache.overall_hits::total 1341133 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 10615 # number of ReadReq misses @@ -414,28 +414,28 @@ system.cpu.l2cache.overall_misses::cpu.data 143034 # system.cpu.l2cache.overall_misses::total 153657 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 261500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 156000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 553303500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 513115500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1066836500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 553362500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 513127500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1066907500 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6933900000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6933900000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6934471000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6934471000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 261500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 156000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 553303500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7447015500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8000736500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 553362500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7447598500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8001378500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 261500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 156000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 553303500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7447015500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8000736500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 553362500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7447598500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8001378500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8770 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3554 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 854751 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 380103 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1247178 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 380104 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1247179 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 595968 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 595968 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2899 # number of UpgradeReq accesses(hits+misses) @@ -445,13 +445,13 @@ system.cpu.l2cache.ReadExReq_accesses::total 247611 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8770 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3554 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 854751 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 627714 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1494789 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 627715 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1494790 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8770 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3554 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 854751 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 627714 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1494789 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 627715 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1494790 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000570 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000844 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012419 # miss rate for ReadReq accesses @@ -473,23 +473,23 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.227865 system.cpu.l2cache.overall_miss_rate::total 0.102795 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52300 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52124.682054 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52050.669507 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52089.082564 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52130.240226 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52051.886792 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52092.549192 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 361.990950 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 361.990950 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52065.687511 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52065.687511 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52069.975071 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52069.975071 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52124.682054 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52064.652460 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52068.805847 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52130.240226 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52068.728414 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52072.983984 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52124.682054 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52064.652460 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52068.805847 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52130.240226 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52068.728414 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52072.983984 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -521,31 +521,31 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 143034 system.cpu.l2cache.overall_mshr_misses::total 153657 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 200000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 425853000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 394738000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 820911000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 115017000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 115017000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5335717000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5335717000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 425912000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 394750500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 820982500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 115023000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 115023000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5336288000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5336288000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 200000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425853000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5730455000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6156628000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425912000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5731038500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6157270500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 200000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425853000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5730455000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6156628000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425912000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5731038500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6157270500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166763732500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167028572500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31856780000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31856780000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166763232500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167028072500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31856015000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31856015000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198620512500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198885352500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198619247500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198884087500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for ReadReq accesses @@ -567,23 +567,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227865 system.cpu.l2cache.overall_mshr_miss_rate::total 0.102795 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.040509 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40042.402110 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40081.587813 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40033.762617 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40033.762617 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40065.154382 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40065.154382 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40123.598681 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40043.670116 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40085.078854 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40035.851027 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40035.851027 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40069.441941 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40069.441941 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40123.598681 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40067.665730 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40071.526191 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40123.598681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40067.665730 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40071.526191 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -607,10 +607,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1358750753218 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1358750753218 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1359273920420 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1359273920420 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1359273920420 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1359273920420 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 5a613cfa1..551274795 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,184 +1,76 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.112043 # Number of seconds simulated -sim_ticks 5112043255000 # Number of ticks simulated -final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.112041 # Number of seconds simulated +sim_ticks 5112040968500 # Number of ticks simulated +final_tick 5112040968500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1011485 # Simulator instruction rate (inst/s) -host_op_rate 2071087 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25877843451 # Simulator tick rate (ticks/s) -host_mem_usage 397304 # Number of bytes of host memory used -host_seconds 197.55 # Real time elapsed on the host -sim_insts 199813914 # Number of instructions simulated -sim_ops 409133298 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2464768 # Number of bytes read from this memory +host_inst_rate 923075 # Simulator instruction rate (inst/s) +host_op_rate 1890063 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23616389220 # Simulator tick rate (ticks/s) +host_mem_usage 353316 # Number of bytes of host memory used +host_seconds 216.46 # Real time elapsed on the host +sim_insts 199810236 # Number of instructions simulated +sim_ops 409125915 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10600192 # Number of bytes read from this memory -system.physmem.bytes_read::total 13919232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10600128 # Number of bytes read from this memory +system.physmem.bytes_read::total 13919040 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9292800 # Number of bytes written to this memory -system.physmem.bytes_written::total 9292800 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38512 # Number of read requests responded to by this memory +system.physmem.bytes_written::writebacks 9292608 # Number of bytes written to this memory +system.physmem.bytes_written::total 9292608 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38510 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165628 # Number of read requests responded to by this memory -system.physmem.num_reads::total 217488 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 145200 # Number of write requests responded to by this memory -system.physmem.num_writes::total 145200 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 482149 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.data 165627 # Number of read requests responded to by this memory +system.physmem.num_reads::total 217485 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 145197 # Number of write requests responded to by this memory +system.physmem.num_writes::total 145197 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 482124 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2073572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2722831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2073561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2722795 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1817825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1817825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1817825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 482149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 1817788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1817788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1817788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 482124 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2073572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 106561 # number of replacements -system.cpu.l2cache.tagsinuse 64822.143261 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3456533 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 170680 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 20.251541 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2434.983596 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 10405.560614 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989107 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2062630 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1538130 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1538130 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 179208 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 777957 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1454603 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2241838 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 777957 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1454603 # number of overall hits -system.cpu.l2cache.overall_hits::total 2241838 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 32184 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 45533 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 134377 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 134377 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 166561 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 179910 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 166561 # number of overall misses -system.cpu.l2cache.overall_misses::total 179910 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1538130 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1538130 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 313585 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 791299 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1621164 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2421748 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 791299 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1621164 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2421748 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016861 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024613 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021598 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428519 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.428519 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016861 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102742 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.074289 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016861 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102742 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.074289 # miss rate for overall accesses -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 98533 # number of writebacks -system.cpu.l2cache.writebacks::total 98533 # number of writebacks -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47570 # number of replacements -system.iocache.tagsinuse 0.042409 # Cycle average of tags in use +system.physmem.bw_total::cpu.data 2073561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4540583 # Total bandwidth to/from this memory (bytes/s) +system.iocache.replacements 47569 # number of replacements +system.iocache.tagsinuse 0.042402 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47586 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47585 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.042409 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.002651 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.002651 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses -system.iocache.ReadReq_misses::total 905 # number of ReadReq misses +system.iocache.warmup_cycle 4994776680059 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.042402 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.002650 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.002650 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses +system.iocache.ReadReq_misses::total 904 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses -system.iocache.demand_misses::total 47625 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses -system.iocache.overall_misses::total 47625 # number of overall misses -system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses +system.iocache.demand_misses::total 47624 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses +system.iocache.overall_misses::total 47624 # number of overall misses +system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -200,7 +92,7 @@ system.iocache.writebacks::total 46667 # nu system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -210,57 +102,57 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10224086531 # number of cpu cycles simulated +system.cpu.numCycles 10224081960 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 199813914 # Number of instructions committed -system.cpu.committedOps 409133298 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374297264 # Number of integer alu accesses +system.cpu.committedInsts 199810236 # Number of instructions committed +system.cpu.committedOps 409125915 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374289906 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39954974 # number of instructions that are conditional controls -system.cpu.num_int_insts 374297264 # number of integer instructions +system.cpu.num_conditional_control_insts 39954535 # number of instructions that are conditional controls +system.cpu.num_int_insts 374289906 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 915470380 # number of times the integer registers were read -system.cpu.num_int_register_writes 480331069 # number of times the integer registers were written +system.cpu.num_int_register_reads 915450684 # number of times the integer registers were read +system.cpu.num_int_register_writes 480322735 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 35626517 # number of memory refs -system.cpu.num_load_insts 27217782 # Number of load instructions -system.cpu.num_store_insts 8408735 # Number of store instructions -system.cpu.num_idle_cycles 9770605318.086651 # Number of idle cycles -system.cpu.num_busy_cycles 453481212.913350 # Number of busy cycles -system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.955646 # Percentage of idle cycles +system.cpu.num_mem_refs 35624588 # number of memory refs +system.cpu.num_load_insts 27216588 # Number of load instructions +system.cpu.num_store_insts 8408000 # Number of store instructions +system.cpu.num_idle_cycles 9770609605.299961 # Number of idle cycles +system.cpu.num_busy_cycles 453472354.700038 # Number of busy cycles +system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.955647 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 790793 # number of replacements +system.cpu.icache.replacements 790732 # number of replacements system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use -system.cpu.icache.total_refs 243365779 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791305 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 307.549907 # Average number of references to valid blocks. +system.cpu.icache.total_refs 243360722 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 791244 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 307.567226 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 148763110500 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 243365779 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243365779 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243365779 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243365779 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243365779 # number of overall hits -system.cpu.icache.overall_hits::total 243365779 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791312 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791312 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791312 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791312 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791312 # number of overall misses -system.cpu.icache.overall_misses::total 791312 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 243360722 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243360722 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243360722 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243360722 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243360722 # number of overall hits +system.cpu.icache.overall_hits::total 243360722 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791251 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791251 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791251 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791251 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791251 # number of overall misses +system.cpu.icache.overall_misses::total 791251 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 244151973 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244151973 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244151973 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244151973 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244151973 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244151973 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses @@ -277,14 +169,14 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.replacements 3335 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.026444 # Cycle average of tags in use +system.cpu.itb_walker_cache.tagsinuse 3.026483 # Cycle average of tags in use system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks. system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5102048603500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026444 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.189153 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.warmup_cycle 5102019603000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8031 # number of ReadReq hits system.cpu.itb_walker_cache.ReadReq_hits::total 8031 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits @@ -324,39 +216,39 @@ system.cpu.itb_walker_cache.cache_copies 0 # nu system.cpu.itb_walker_cache.writebacks::writebacks 593 # number of writebacks system.cpu.itb_walker_cache.writebacks::total 593 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7598 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.013733 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13014 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7612 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.709669 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5101231664000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013733 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313358 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.313358 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13016 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13016 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13016 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13016 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13016 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13016 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8792 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8792 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8792 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8792 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8792 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8792 # number of overall misses +system.cpu.dtb_walker_cache.replacements 7597 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5101206381500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13017 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13017 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13017 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13017 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13017 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13017 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8791 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8791 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8791 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8791 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8791 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8791 # number of overall misses system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403155 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403155 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403155 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403155 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403155 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403155 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403109 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403109 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403109 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403109 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403109 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403109 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -368,39 +260,39 @@ system.cpu.dtb_walker_cache.cache_copies 0 # nu system.cpu.dtb_walker_cache.writebacks::writebacks 2556 # number of writebacks system.cpu.dtb_walker_cache.writebacks::total 2556 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1621273 # number of replacements +system.cpu.dcache.replacements 1621135 # number of replacements system.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use -system.cpu.dcache.total_refs 20142222 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1621785 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.419786 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 20140429 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1621647 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.419737 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 12057024 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8082936 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8082936 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20139960 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20139960 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20139960 # number of overall hits -system.cpu.dcache.overall_hits::total 20139960 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308205 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308205 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315852 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315852 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1624057 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1624057 # number of overall misses -system.cpu.dcache.overall_misses::total 1624057 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 13365229 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13365229 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21764017 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21764017 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21764017 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21764017 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12055941 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12055941 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8082226 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8082226 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20138167 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20138167 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20138167 # number of overall hits +system.cpu.dcache.overall_hits::total 20138167 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308091 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308091 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315828 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315828 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1623919 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1623919 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1623919 # number of overall misses +system.cpu.dcache.overall_misses::total 1623919 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 13364032 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13364032 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8398054 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8398054 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21762086 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21762086 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21762086 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21762086 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses @@ -417,8 +309,116 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1534981 # number of writebacks -system.cpu.dcache.writebacks::total 1534981 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1534848 # number of writebacks +system.cpu.dcache.writebacks::total 1534848 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 106558 # number of replacements +system.cpu.l2cache.tagsinuse 64822.149249 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 51981.453140 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2434.994085 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 10405.564956 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.989108 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 777896 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1275281 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2062455 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1537997 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1537997 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 179183 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 179183 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 777896 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1454464 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2241638 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 777896 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1454464 # number of overall hits +system.cpu.l2cache.overall_hits::total 2241638 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 32182 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 45531 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 134378 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 134378 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 166560 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 179909 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 166560 # number of overall misses +system.cpu.l2cache.overall_misses::total 179909 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 791238 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1307463 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2107986 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1537997 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1537997 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 313561 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 313561 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 791238 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1621024 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2421547 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 791238 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1621024 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2421547 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016862 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024614 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428555 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.428555 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016862 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102750 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.074295 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016862 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102750 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.074295 # miss rate for overall accesses +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 98530 # number of writebacks +system.cpu.l2cache.writebacks::total 98530 # number of writebacks +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 358803d5d..b8216d15c 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.187896 # Nu sim_ticks 5187896410000 # Number of ticks simulated final_tick 5187896410000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 834857 # Simulator instruction rate (inst/s) -host_op_rate 1609393 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33766110220 # Simulator tick rate (ticks/s) -host_mem_usage 354356 # Number of bytes of host memory used -host_seconds 153.64 # Real time elapsed on the host +host_inst_rate 812782 # Simulator instruction rate (inst/s) +host_op_rate 1566838 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32873266023 # Simulator tick rate (ticks/s) +host_mem_usage 347504 # Number of bytes of host memory used +host_seconds 157.82 # Real time elapsed on the host sim_insts 128269216 # Number of instructions simulated sim_ops 247270559 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2867328 # Number of bytes read from this memory @@ -59,14 +59,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47558 system.iocache.demand_misses::total 47558 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses system.iocache.overall_misses::total 47558 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130045932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 130045932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130086932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 130086932 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10696163160 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 10696163160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10826209092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10826209092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10826209092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10826209092 # number of overall miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10826250092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10826250092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10826250092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10826250092 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 838 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) @@ -83,19 +83,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155186.076372 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 155186.076372 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155235.002387 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 155235.002387 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 228941.848459 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 228941.848459 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 227642.228269 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 227642.228269 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 90077012 # number of cycles access was blocked +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227643.090374 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 227643.090374 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227643.090374 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 227643.090374 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 90078 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 11025 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8170.250522 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.170340 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -109,14 +109,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47558 system.iocache.demand_mshr_misses::total 47558 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47558 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47558 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86439000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 86439000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8266468944 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8266468944 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8352907944 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8352907944 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86510932 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 86510932 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8266723160 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8266723160 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8353234092 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8353234092 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8353234092 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8353234092 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -125,14 +125,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103149.164678 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 103149.164678 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176936.407192 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176936.407192 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103235.002387 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 103235.002387 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176941.848459 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 176941.848459 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175643.090374 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 175643.090374 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175643.090374 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 175643.090374 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -437,14 +437,14 @@ system.cpu.dcache.demand_misses::cpu.data 1621067 # n system.cpu.dcache.demand_misses::total 1621067 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1621067 # number of overall misses system.cpu.dcache.overall_misses::total 1621067 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18175236500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18175236500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18175237000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18175237000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 8903442500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 8903442500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27078679000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27078679000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27078679000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27078679000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27078679500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27078679500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27078679500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27078679500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 13298830 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13298830 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 8353033 # number of WriteReq accesses(hits+misses) @@ -461,14 +461,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.074870 system.cpu.dcache.demand_miss_rate::total 0.074870 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074870 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.074870 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13913.843616 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13913.843616 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13913.843999 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13913.843999 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28283.123727 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 28283.123727 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16704.231842 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16704.231842 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16704.231842 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16704.231842 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16704.232151 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16704.232151 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16704.232151 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16704.232151 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -487,20 +487,20 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1621067 system.cpu.dcache.demand_mshr_misses::total 1621067 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1621067 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1621067 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15562696500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15562696500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15562697000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15562697000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8273848500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 8273848500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23836545000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23836545000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23836545000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23836545000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23836545500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23836545500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23836545500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23836545500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94146954000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94146954000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469435000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469435000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96616389000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96616389000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469434500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469434500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96616388500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96616388500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098224 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098224 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037687 # mshr miss rate for WriteReq accesses @@ -509,14 +509,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074870 system.cpu.dcache.demand_mshr_miss_rate::total 0.074870 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074870 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074870 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11913.843616 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11913.843616 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11913.843999 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11913.843999 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26283.123727 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26283.123727 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14704.231842 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14704.231842 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14704.231842 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14704.231842 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14704.232151 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14704.232151 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14704.232151 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14704.232151 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -672,21 +672,21 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 12922 system.cpu.l2cache.overall_mshr_misses::cpu.data 141498 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 154425 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 517329000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1144074500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1661603500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 517329500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1144100000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1661629500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 54186500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 54186500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4533030500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4533030500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 517329000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5677105000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6194634000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 517329500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5677130500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6194660000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 517329000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5677105000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6194634000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 517329500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5677130500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6194660000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86587561000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86587561000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305699000 # number of WriteReq MSHR uncacheable cycles @@ -710,21 +710,21 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016282 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087447 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.063788 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40034.746943 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40515.422480 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40364.472246 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40034.785637 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40516.325519 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40365.103850 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40287.360595 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40287.360595 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40023.225322 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40023.225322 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40034.785637 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40121.630694 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40114.359722 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40034.785637 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40121.630694 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40114.359722 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index ba49bebdd..062194e2a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 21628500 # Number of ticks simulated final_tick 21628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48865 # Simulator instruction rate (inst/s) -host_op_rate 48859 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 165354272 # Simulator tick rate (ticks/s) -host_mem_usage 218640 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 34038 # Simulator instruction rate (inst/s) +host_op_rate 34033 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 115179622 # Simulator tick rate (ticks/s) +host_mem_usage 212112 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory @@ -270,11 +270,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 56590.517241 system.cpu.dcache.overall_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 56590.517241 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1690000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3380 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 37 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 45675.675676 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 91.351351 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 1d71c4fe2..04aaa0ff5 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 20184000 # Number of ticks simulated final_tick 20184000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50290 # Simulator instruction rate (inst/s) -host_op_rate 50282 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174536927 # Simulator tick rate (ticks/s) -host_mem_usage 219492 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 91753 # Simulator instruction rate (inst/s) +host_op_rate 91718 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 318298211 # Simulator tick rate (ticks/s) +host_mem_usage 212944 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -160,11 +160,11 @@ system.cpu.icache.demand_avg_miss_latency::total 56098.837209 system.cpu.icache.overall_avg_miss_latency::cpu.inst 56098.837209 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 56098.837209 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 58 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 58 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits @@ -256,11 +256,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 57663.385827 system.cpu.dcache.overall_avg_miss_latency::cpu.data 57663.385827 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 57663.385827 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1194500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2389 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51934.782609 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 103.869565 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 9881f90a7..a6445a723 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18570500 # Number of ticks simulated final_tick 18570500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42410 # Simulator instruction rate (inst/s) -host_op_rate 42404 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 147804999 # Simulator tick rate (ticks/s) -host_mem_usage 221464 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 78205 # Simulator instruction rate (inst/s) +host_op_rate 78177 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 272440141 # Simulator tick rate (ticks/s) +host_mem_usage 214124 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -142,11 +142,11 @@ system.cpu.icache.demand_avg_miss_latency::total 55220 system.cpu.icache.overall_avg_miss_latency::cpu.inst 55220 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 55220 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 109000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 218 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 36333.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 72.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59 # number of ReadReq MSHR hits @@ -238,11 +238,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 55992.711370 system.cpu.dcache.overall_avg_miss_latency::cpu.data 55992.711370 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 55992.711370 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2307000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4614 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51266.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 102.533333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 2a32b08b0..c19d33801 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000015 # Nu sim_ticks 14818500 # Number of ticks simulated final_tick 14818500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71701 # Simulator instruction rate (inst/s) -host_op_rate 71694 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 83350191 # Simulator tick rate (ticks/s) -host_mem_usage 220256 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 95139 # Simulator instruction rate (inst/s) +host_op_rate 95123 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 110579898 # Simulator tick rate (ticks/s) +host_mem_usage 213740 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory @@ -736,11 +736,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 40780.102041 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 38918.400000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44057.746479 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 40780.102041 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 49000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 4083.333333 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8.166667 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index e278da8a8..c5840e3c9 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu sim_ticks 25317500 # Number of ticks simulated final_tick 25317500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 47783 # Simulator instruction rate (inst/s) -host_op_rate 47781 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79779918 # Simulator tick rate (ticks/s) -host_mem_usage 220364 # Number of bytes of host memory used -host_seconds 0.32 # Real time elapsed on the host +host_inst_rate 84248 # Simulator instruction rate (inst/s) +host_op_rate 84237 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 140641450 # Simulator tick rate (ticks/s) +host_mem_usage 214032 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -142,11 +142,11 @@ system.cpu.icache.demand_avg_miss_latency::total 54837.398374 system.cpu.icache.overall_avg_miss_latency::cpu.inst 54837.398374 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 54837.398374 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 65500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 131 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 32750 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 65.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits @@ -242,11 +242,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 56182.451253 system.cpu.dcache.overall_avg_miss_latency::cpu.data 56182.451253 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 56182.451253 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4519 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 100.422222 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 482a9e980..ff9862a27 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,953 +1,953 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000114 # Number of seconds simulated -sim_ticks 113910500 # Number of ticks simulated -final_tick 113910500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000110 # Number of seconds simulated +sim_ticks 109894000 # Number of ticks simulated +final_tick 109894000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141669 # Simulator instruction rate (inst/s) -host_op_rate 141669 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14682125 # Simulator tick rate (ticks/s) -host_mem_usage 244464 # Number of bytes of host memory used -host_seconds 7.76 # Real time elapsed on the host -sim_insts 1099129 # Number of instructions simulated -sim_ops 1099129 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 23168 # Number of bytes read from this memory +host_inst_rate 161995 # Simulator instruction rate (inst/s) +host_op_rate 161994 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16590549 # Simulator tick rate (ticks/s) +host_mem_usage 228988 # Number of bytes of host memory used +host_seconds 6.62 # Real time elapsed on the host +sim_insts 1073027 # Number of instructions simulated +sim_ops 1073027 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5632 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 23168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 29248 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 362 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 42880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 29184 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 84 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 88 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 671 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 203387747 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 94389894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 47194947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11236892 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 2809223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7303980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 3371068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7303980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 376997731 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 203387747 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 47194947 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 2809223 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 3371068 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 256762985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 203387747 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 94389894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 47194947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11236892 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 2809223 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7303980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 3371068 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7303980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 376997731 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 670 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 209656578 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 97839736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 51249386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11647588 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 2329518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7570932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 2329518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7570932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 390194187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 209656578 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 51249386 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 2329518 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 2329518 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 265564999 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 209656578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 97839736 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 51249386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11647588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 2329518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7570932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 2329518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7570932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 390194187 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 227822 # number of cpu cycles simulated +system.cpu0.numCycles 219789 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 88179 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 85929 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 1290 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 85894 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 83486 # Number of BTB hits +system.cpu0.BPredUnit.lookups 85747 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 83485 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 1265 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 83551 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 81101 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 517 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.usedRAS 507 # Number of times the RAS was used to get a target. system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 17727 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 523680 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 88179 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 84003 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 172095 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 4009 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 15408 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 17217 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 509162 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 85747 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 81608 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 167267 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3854 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13783 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1281 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 6036 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 519 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 209087 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.504603 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.209881 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1302 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 6029 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 502 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 202015 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.520417 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.209670 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 36992 17.69% 17.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 85294 40.79% 58.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 585 0.28% 58.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1000 0.48% 59.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 484 0.23% 59.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 81297 38.88% 98.36% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 665 0.32% 98.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 355 0.17% 98.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2415 1.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34748 17.20% 17.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 82895 41.03% 58.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 589 0.29% 58.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 956 0.47% 59.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 519 0.26% 59.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 78871 39.04% 98.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 675 0.33% 98.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 356 0.18% 98.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2406 1.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 209087 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.387052 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.298637 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18268 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 16880 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 171017 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 351 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2571 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 520658 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2571 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18993 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2288 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13870 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 170679 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 686 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 517484 # Number of instructions processed by rename -system.cpu0.rename.LSQFullEvents 297 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 353459 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1032335 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 1032335 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 339779 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13680 # Number of HB maps that are undone due to squashing +system.cpu0.fetch.rateDist::total 202015 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.390133 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.316595 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17805 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 15234 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 166234 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 301 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2441 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 506087 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2441 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18480 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 1523 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13039 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 165885 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 647 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 502881 # Number of instructions processed by rename +system.cpu0.rename.LSQFullEvents 252 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 343651 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1003098 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 1003098 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 330631 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13020 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 904 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 933 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4009 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 165974 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 83785 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 81138 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 80830 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 432592 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 951 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 429324 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 270 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11361 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 11323 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 392 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 209087 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.053327 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.097112 # Number of insts issued each cycle +system.cpu0.rename.tempSerializingInsts 932 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3938 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 161147 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 81377 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 78673 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 78441 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 420405 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 949 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 417702 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 122 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10651 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 9804 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 390 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 202015 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.067678 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.086169 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 36280 17.35% 17.35% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5325 2.55% 19.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 82668 39.54% 59.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 82134 39.28% 98.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1638 0.78% 99.50% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 661 0.32% 99.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 275 0.13% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 94 0.04% 99.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 12 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33785 16.72% 16.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5274 2.61% 19.33% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 80485 39.84% 59.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 79928 39.57% 98.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1527 0.76% 99.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 645 0.32% 99.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 270 0.13% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 14 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 209087 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 202015 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 52 18.77% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 113 40.79% 59.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 40.43% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 46 19.74% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 73 31.33% 51.07% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 114 48.93% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 180924 42.14% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 165296 38.50% 80.64% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 83104 19.36% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 176241 42.19% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 160662 38.46% 80.66% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 80799 19.34% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 429324 # Type of FU issued -system.cpu0.iq.rate 1.884471 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 277 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000645 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1068282 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 444960 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 427393 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 417702 # Type of FU issued +system.cpu0.iq.rate 1.900468 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 233 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000558 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1037774 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 432063 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 415867 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 429601 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 417935 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 80458 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 78173 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2495 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 56 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1539 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2242 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 58 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 20 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2571 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1789 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 88 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 515149 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 291 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 165974 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 83785 # Number of dispatched store instructions +system.cpu0.iew.iewSquashCycles 2441 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1114 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 500579 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 311 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 161147 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 81377 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 838 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 95 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 56 # Number of memory order violations +system.cpu0.iew.memOrderViolationEvents 58 # Number of memory order violations system.cpu0.iew.predictedTakenIncorrect 383 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1113 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1496 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 428216 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 164977 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1108 # Number of squashed instructions skipped in execute +system.cpu0.iew.predictedNotTakenIncorrect 1089 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1472 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 416616 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 160343 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1086 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 81606 # number of nop insts executed -system.cpu0.iew.exec_refs 247935 # number of memory reference insts executed -system.cpu0.iew.exec_branches 85106 # Number of branches executed -system.cpu0.iew.exec_stores 82958 # Number of stores executed -system.cpu0.iew.exec_rate 1.879608 # Inst execution rate -system.cpu0.iew.wb_sent 427739 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 427393 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 253334 # num instructions producing a value -system.cpu0.iew.wb_consumers 255736 # num instructions consuming a value +system.cpu0.iew.exec_nop 79225 # number of nop insts executed +system.cpu0.iew.exec_refs 241004 # number of memory reference insts executed +system.cpu0.iew.exec_branches 82800 # Number of branches executed +system.cpu0.iew.exec_stores 80661 # Number of stores executed +system.cpu0.iew.exec_rate 1.895527 # Inst execution rate +system.cpu0.iew.wb_sent 416200 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 415867 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 246464 # num instructions producing a value +system.cpu0.iew.wb_consumers 248856 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.875995 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.990608 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.892119 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.990388 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 13085 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 12251 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1290 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 206533 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.430701 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.136521 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1265 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 199591 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.446493 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.132962 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 36757 17.80% 17.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 84830 41.07% 58.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2489 1.21% 60.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 701 0.34% 60.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 579 0.28% 60.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 80093 38.78% 99.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 561 0.27% 99.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 222 0.11% 99.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 301 0.15% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34293 17.18% 17.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 82677 41.42% 58.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2432 1.22% 59.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 705 0.35% 60.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 565 0.28% 60.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 77961 39.06% 99.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 418 0.21% 99.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 251 0.13% 99.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 289 0.14% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 206533 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 502020 # Number of instructions committed -system.cpu0.commit.committedOps 502020 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 199591 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 488298 # Number of instructions committed +system.cpu0.commit.committedOps 488298 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 245725 # Number of memory references committed -system.cpu0.commit.loads 163479 # Number of loads committed +system.cpu0.commit.refs 238864 # Number of memory references committed +system.cpu0.commit.loads 158905 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 84133 # Number of branches committed +system.cpu0.commit.branches 81846 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 338110 # Number of committed integer instructions. +system.cpu0.commit.int_insts 328962 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 301 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 289 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 720176 # The number of ROB reads -system.cpu0.rob.rob_writes 1032801 # The number of ROB writes -system.cpu0.timesIdled 336 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 18735 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 421071 # Number of Instructions Simulated -system.cpu0.committedOps 421071 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 421071 # Number of Instructions Simulated -system.cpu0.cpi 0.541054 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.541054 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.848246 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.848246 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 766308 # number of integer regfile reads -system.cpu0.int_regfile_writes 345106 # number of integer regfile writes +system.cpu0.rob.rob_reads 698690 # The number of ROB reads +system.cpu0.rob.rob_writes 1003556 # The number of ROB writes +system.cpu0.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 17774 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 409636 # Number of Instructions Simulated +system.cpu0.committedOps 409636 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 409636 # Number of Instructions Simulated +system.cpu0.cpi 0.536547 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.536547 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.863769 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.863769 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 745424 # number of integer regfile reads +system.cpu0.int_regfile_writes 335847 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 249733 # number of misc regfile reads +system.cpu0.misc_regfile_reads 242810 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 302 # number of replacements -system.cpu0.icache.tagsinuse 247.706871 # Cycle average of tags in use -system.cpu0.icache.total_refs 5276 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 594 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.882155 # Average number of references to valid blocks. +system.cpu0.icache.replacements 299 # number of replacements +system.cpu0.icache.tagsinuse 247.576197 # Cycle average of tags in use +system.cpu0.icache.total_refs 5285 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 591 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.942470 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 247.706871 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.483802 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.483802 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5276 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5276 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5276 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5276 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5276 # number of overall hits -system.cpu0.icache.overall_hits::total 5276 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 760 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 760 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 760 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 760 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 760 # number of overall misses -system.cpu0.icache.overall_misses::total 760 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 29374500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 29374500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 29374500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 29374500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 29374500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 29374500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6036 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6036 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6036 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6036 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6036 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6036 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125911 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.125911 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125911 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.125911 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125911 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.125911 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38650.657895 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38650.657895 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38650.657895 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38650.657895 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38650.657895 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38650.657895 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 13500 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 247.576197 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.483547 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.483547 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5285 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5285 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5285 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5285 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5285 # number of overall hits +system.cpu0.icache.overall_hits::total 5285 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 744 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 744 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 744 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 744 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 744 # number of overall misses +system.cpu0.icache.overall_misses::total 744 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 28183000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 28183000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 28183000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 28183000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 28183000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 28183000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6029 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6029 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6029 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6029 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6029 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6029 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.123404 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.123404 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.123404 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.123404 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.123404 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.123404 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 37880.376344 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 37880.376344 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 37880.376344 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 37880.376344 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 37880.376344 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 37880.376344 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13500 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.500000 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 165 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 165 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 165 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 165 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 595 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 595 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 595 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 595 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 595 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 595 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22317000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 22317000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22317000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 22317000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22317000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 22317000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.098575 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.098575 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.098575 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.098575 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.098575 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.098575 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37507.563025 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37507.563025 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37507.563025 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 37507.563025 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37507.563025 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 37507.563025 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 152 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 152 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 152 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 152 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 152 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 152 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 592 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 592 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 592 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 592 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 592 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 592 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22043000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 22043000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22043000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 22043000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22043000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 22043000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.098192 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.098192 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.098192 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.098192 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.098192 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.098192 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37234.797297 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37234.797297 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37234.797297 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 37234.797297 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37234.797297 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 37234.797297 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 144.389455 # Cycle average of tags in use -system.cpu0.dcache.total_refs 165484 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 144.284283 # Cycle average of tags in use +system.cpu0.dcache.total_refs 160925 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 973.435294 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 946.617647 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 144.389455 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.282011 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.282011 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 83924 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 83924 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 81641 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 81641 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 17 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 17 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 165565 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 165565 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 165565 # number of overall hits -system.cpu0.dcache.overall_hits::total 165565 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 532 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 532 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 563 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 563 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 25 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 25 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1095 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1095 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1095 # number of overall misses -system.cpu0.dcache.overall_misses::total 1095 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16935000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 16935000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 28694494 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 28694494 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 516500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 516500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 45629494 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 45629494 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 45629494 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 45629494 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 84456 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 84456 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 82204 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 82204 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.occ_blocks::cpu0.data 144.284283 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.281805 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.281805 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 81643 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 81643 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 79364 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 79364 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 161007 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 161007 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 161007 # number of overall hits +system.cpu0.dcache.overall_hits::total 161007 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 465 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 465 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 553 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 553 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1018 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1018 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1018 # number of overall misses +system.cpu0.dcache.overall_misses::total 1018 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 14129000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 14129000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26395982 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 26395982 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 370000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 370000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 40524982 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 40524982 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 40524982 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 40524982 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 82108 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 82108 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 79917 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 79917 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 166660 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 166660 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 166660 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 166660 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006299 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006299 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006849 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006849 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.595238 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.595238 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006570 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006570 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006570 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006570 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31832.706767 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31832.706767 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50967.129663 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50967.129663 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 20660 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 20660 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41670.770776 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 41670.770776 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41670.770776 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 41670.770776 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 112000 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 162025 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 162025 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 162025 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 162025 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005663 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.005663 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006920 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006920 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006283 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006283 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006283 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006283 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30384.946237 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 30384.946237 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 47732.336347 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 47732.336347 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 17619.047619 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 17619.047619 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39808.430255 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39808.430255 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39808.430255 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39808.430255 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 319 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 24 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6222.222222 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.291667 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 351 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 351 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 394 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 394 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 745 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 745 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 745 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 745 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 181 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 169 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 169 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 25 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 25 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 350 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 350 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5844010 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5844010 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6652500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6652500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 438500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 438500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12496510 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12496510 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12496510 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12496510 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002143 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002143 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002056 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002056 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.595238 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.595238 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002100 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002100 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002100 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002100 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32287.348066 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32287.348066 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39363.905325 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39363.905325 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17540 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17540 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35704.314286 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35704.314286 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35704.314286 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35704.314286 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 276 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 381 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 381 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 657 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 657 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 657 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 657 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 172 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 172 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5343500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5343500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6330000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6330000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 328000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 328000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11673500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11673500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11673500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11673500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002302 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002302 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002152 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002228 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002228 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002228 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002228 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28272.486772 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28272.486772 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36802.325581 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36802.325581 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 15619.047619 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 15619.047619 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32336.565097 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32336.565097 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32336.565097 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32336.565097 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 191317 # number of cpu cycles simulated +system.cpu1.numCycles 184127 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 53059 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 50011 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 1521 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 46382 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 45427 # Number of BTB hits +system.cpu1.BPredUnit.lookups 48566 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 45425 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 1525 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 41634 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 40784 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 803 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.usedRAS 857 # Number of times the RAS was used to get a target. system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 31318 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 294530 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 53059 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 46230 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 104588 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4407 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 38684 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6733 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1070 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 21833 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 319 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 185209 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.590257 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.119058 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 32363 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 265611 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 48566 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 41641 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 96301 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4375 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 40077 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.NoActiveThreadStallCycles 6455 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 1055 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 23564 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 345 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 179027 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.483637 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.076927 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 80621 43.53% 43.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 53529 28.90% 72.43% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 6903 3.73% 76.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3276 1.77% 77.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 732 0.40% 78.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 34514 18.64% 96.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1160 0.63% 97.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 883 0.48% 98.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3591 1.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 82726 46.21% 46.21% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 49826 27.83% 74.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7772 4.34% 78.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3158 1.76% 80.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 709 0.40% 80.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 29207 16.31% 96.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1125 0.63% 97.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 886 0.49% 97.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3618 2.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 185209 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.277336 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.539487 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 37437 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 34588 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 97784 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 5856 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2811 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 290465 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2811 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 38251 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18737 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 14962 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 92242 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 11473 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 288015 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 15 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 60 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 201252 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 549512 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 549512 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 185544 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15708 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1231 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1359 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 14237 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 80834 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 37999 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 38862 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 32764 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 237666 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 7151 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 239902 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12973 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 11962 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 719 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 185209 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.295304 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.311031 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 179027 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.263764 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.442542 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 39330 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 35122 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 88807 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 6541 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2772 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 261671 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2772 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 40116 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 20114 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 14157 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 82544 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 12869 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 259082 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 41 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 180494 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 488461 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 488461 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 165372 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15122 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1240 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1383 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 15783 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 71004 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 32715 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 34344 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 27479 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 212625 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 7991 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 216005 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 69 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12464 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 11017 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 740 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 179027 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.206550 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.298788 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 78322 42.29% 42.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 24974 13.48% 55.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 38132 20.59% 76.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 38761 20.93% 97.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3339 1.80% 99.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1231 0.66% 99.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 341 0.18% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 48 0.03% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 80193 44.79% 44.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 27393 15.30% 60.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 32961 18.41% 78.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 33539 18.73% 97.24% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3241 1.81% 99.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1264 0.71% 99.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 324 0.18% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 185209 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 179027 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 21 6.44% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 95 29.14% 35.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 64.42% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 20 6.78% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 65 22.03% 28.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 116849 48.71% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 85748 35.74% 84.45% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 37305 15.55% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 107139 49.60% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 76812 35.56% 85.16% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 32054 14.84% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 239902 # Type of FU issued -system.cpu1.iq.rate 1.253950 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 326 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001359 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 665467 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 257831 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 237819 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 216005 # Type of FU issued +system.cpu1.iq.rate 1.173131 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 295 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001366 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 611401 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 233118 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 214044 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 240228 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 216300 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 32613 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 27354 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2758 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1567 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2609 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1525 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2811 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2340 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 107 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 284663 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 401 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 80834 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 37999 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1126 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 105 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2772 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 1710 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 255983 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 380 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 71004 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 32715 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1159 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 52 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 509 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1185 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1694 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 238552 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 79712 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1350 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 484 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1213 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1697 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 214708 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 69981 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1297 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 39846 # number of nop insts executed -system.cpu1.iew.exec_refs 116931 # number of memory reference insts executed -system.cpu1.iew.exec_branches 49232 # Number of branches executed -system.cpu1.iew.exec_stores 37219 # Number of stores executed -system.cpu1.iew.exec_rate 1.246894 # Inst execution rate -system.cpu1.iew.wb_sent 238105 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 237819 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 133762 # num instructions producing a value -system.cpu1.iew.wb_consumers 138617 # num instructions consuming a value +system.cpu1.iew.exec_nop 35367 # number of nop insts executed +system.cpu1.iew.exec_refs 101954 # number of memory reference insts executed +system.cpu1.iew.exec_branches 44806 # Number of branches executed +system.cpu1.iew.exec_stores 31973 # Number of stores executed +system.cpu1.iew.exec_rate 1.166086 # Inst execution rate +system.cpu1.iew.wb_sent 214321 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 214044 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 118861 # num instructions producing a value +system.cpu1.iew.wb_consumers 123754 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.243063 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.964975 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.162480 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.960462 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 14936 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 6432 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1521 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 175666 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.535334 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.989786 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 14492 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 7251 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1525 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 169801 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.422188 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.937267 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 78046 44.43% 44.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 47129 26.83% 71.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6230 3.55% 74.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 7351 4.18% 78.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1552 0.88% 79.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 32915 18.74% 98.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 634 0.36% 98.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 995 0.57% 99.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 814 0.46% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 80979 47.69% 47.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 42780 25.19% 72.88% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6215 3.66% 76.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 8147 4.80% 81.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1520 0.90% 82.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 27830 16.39% 98.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 515 0.30% 98.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1002 0.59% 99.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 813 0.48% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 175666 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 269706 # Number of instructions committed -system.cpu1.commit.committedOps 269706 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 169801 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 241489 # Number of instructions committed +system.cpu1.commit.committedOps 241489 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 114508 # Number of memory references committed -system.cpu1.commit.loads 78076 # Number of loads committed -system.cpu1.commit.membars 5720 # Number of memory barriers committed -system.cpu1.commit.branches 48115 # Number of branches committed +system.cpu1.commit.refs 99585 # Number of memory references committed +system.cpu1.commit.loads 68395 # Number of loads committed +system.cpu1.commit.membars 6536 # Number of memory barriers committed +system.cpu1.commit.branches 43685 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 184747 # Number of committed integer instructions. +system.cpu1.commit.int_insts 165393 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 814 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 813 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 458907 # The number of ROB reads -system.cpu1.rob.rob_writes 572109 # The number of ROB writes -system.cpu1.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 6108 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 36503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 225079 # Number of Instructions Simulated -system.cpu1.committedOps 225079 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 225079 # Number of Instructions Simulated -system.cpu1.cpi 0.849999 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.849999 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.176472 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.176472 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 410678 # number of integer regfile reads -system.cpu1.int_regfile_writes 191757 # number of integer regfile writes +system.cpu1.rob.rob_reads 424382 # The number of ROB reads +system.cpu1.rob.rob_writes 514748 # The number of ROB writes +system.cpu1.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 5100 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 35660 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 200479 # Number of Instructions Simulated +system.cpu1.committedOps 200479 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 200479 # Number of Instructions Simulated +system.cpu1.cpi 0.918435 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.918435 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.088808 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.088808 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 365766 # number of integer regfile reads +system.cpu1.int_regfile_writes 171568 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 118640 # number of misc regfile reads +system.cpu1.misc_regfile_reads 103658 # number of misc regfile reads system.cpu1.misc_regfile_writes 646 # number of misc regfile writes -system.cpu1.icache.replacements 322 # number of replacements -system.cpu1.icache.tagsinuse 90.918932 # Cycle average of tags in use -system.cpu1.icache.total_refs 21316 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 436 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 48.889908 # Average number of references to valid blocks. +system.cpu1.icache.replacements 321 # number of replacements +system.cpu1.icache.tagsinuse 92.890627 # Cycle average of tags in use +system.cpu1.icache.total_refs 23041 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 438 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 52.605023 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 90.918932 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.177576 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.177576 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 21316 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 21316 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 21316 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 21316 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 21316 # number of overall hits -system.cpu1.icache.overall_hits::total 21316 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 517 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 517 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 517 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 517 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 517 # number of overall misses -system.cpu1.icache.overall_misses::total 517 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11871000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 11871000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 11871000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 11871000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 11871000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 11871000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 21833 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 21833 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 21833 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 21833 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 21833 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 21833 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023680 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023680 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023680 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023680 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023680 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023680 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22961.315280 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 22961.315280 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22961.315280 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 22961.315280 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22961.315280 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 22961.315280 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 32000 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 92.890627 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.181427 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.181427 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 23041 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 23041 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 23041 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 23041 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 23041 # number of overall hits +system.cpu1.icache.overall_hits::total 23041 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 523 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 523 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 523 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 523 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 523 # number of overall misses +system.cpu1.icache.overall_misses::total 523 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10934000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 10934000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 10934000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 10934000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 10934000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 10934000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 23564 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 23564 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 23564 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 23564 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 23564 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 23564 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022195 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.022195 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022195 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.022195 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022195 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.022195 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20906.309751 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 20906.309751 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20906.309751 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 20906.309751 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20906.309751 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 20906.309751 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 66 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 32000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 66 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 81 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 81 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 81 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 81 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 436 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 436 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 436 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 436 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8857500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8857500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8857500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8857500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8857500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8857500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019970 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019970 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019970 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.019970 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019970 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.019970 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20315.366972 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 20315.366972 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 20315.366972 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 20315.366972 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 20315.366972 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 20315.366972 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 85 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 85 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 85 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 85 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 85 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 438 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 438 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 438 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 438 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 438 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 438 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8718000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8718000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8718000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8718000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8718000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8718000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018588 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018588 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018588 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.018588 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018588 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.018588 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19904.109589 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19904.109589 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19904.109589 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 19904.109589 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19904.109589 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 19904.109589 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 27.526466 # Cycle average of tags in use -system.cpu1.dcache.total_refs 42609 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 27.499718 # Cycle average of tags in use +system.cpu1.dcache.total_refs 37345 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1521.750000 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 1333.750000 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 27.526466 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.053763 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.053763 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 46637 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 46637 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 36226 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 36226 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 82863 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 82863 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 82863 # number of overall hits -system.cpu1.dcache.overall_hits::total 82863 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 446 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 446 # number of ReadReq misses +system.cpu1.dcache.occ_blocks::cpu1.data 27.499718 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.053710 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.053710 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 42212 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 42212 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 30981 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 30981 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 17 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 17 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 73193 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 73193 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 73193 # number of overall hits +system.cpu1.dcache.overall_hits::total 73193 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 398 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 398 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 140 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 140 # number of WriteReq misses system.cpu1.dcache.SwapReq_misses::cpu1.data 52 # number of SwapReq misses system.cpu1.dcache.SwapReq_misses::total 52 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 586 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 586 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 586 # number of overall misses -system.cpu1.dcache.overall_misses::total 586 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 12735500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 12735500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3574500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3574500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1329500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 1329500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 16310000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 16310000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 16310000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 16310000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 47083 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 47083 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 36366 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 36366 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 83449 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 83449 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 83449 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 83449 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009473 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.009473 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003850 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003850 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.787879 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.787879 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007022 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.007022 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007022 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.007022 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 28554.932735 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 28554.932735 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25532.142857 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25532.142857 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 25567.307692 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 25567.307692 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27832.764505 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 27832.764505 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27832.764505 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 27832.764505 # average overall miss latency +system.cpu1.dcache.demand_misses::cpu1.data 538 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 538 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 538 # number of overall misses +system.cpu1.dcache.overall_misses::total 538 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9898500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 9898500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3138500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3138500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1008000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 1008000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13037000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13037000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13037000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13037000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 42610 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 42610 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 31121 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 31121 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 73731 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 73731 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 73731 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 73731 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009341 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.009341 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004499 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004499 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.753623 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.753623 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007297 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.007297 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007297 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.007297 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 24870.603015 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 24870.603015 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22417.857143 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22417.857143 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 19384.615385 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 19384.615385 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24232.342007 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24232.342007 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24232.342007 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24232.342007 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -956,364 +956,364 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 286 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 286 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 320 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 320 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 320 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 320 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 238 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 238 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 37 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 37 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 275 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 275 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 275 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 275 # number of overall MSHR hits system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 160 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 52 # number of SwapReq MSHR misses system.cpu1.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 266 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 266 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3164503 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3164503 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1890000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1890000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 1168500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 1168500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5054503 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5054503 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5054503 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5054503 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003398 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003398 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002915 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002915 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.787879 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.787879 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003188 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003188 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003188 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003188 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 19778.143750 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 19778.143750 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17830.188679 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17830.188679 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 22471.153846 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 22471.153846 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19001.890977 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19001.890977 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19001.890977 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19001.890977 # average overall mshr miss latency +system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2446500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2446500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1653500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1653500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 904000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 904000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4100000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4100000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4100000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4100000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003755 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003755 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003310 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003310 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.753623 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.753623 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003567 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003567 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003567 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003567 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15290.625000 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15290.625000 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16053.398058 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16053.398058 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 17384.615385 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 17384.615385 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15589.353612 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15589.353612 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15589.353612 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15589.353612 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 191010 # number of cpu cycles simulated +system.cpu2.numCycles 183836 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.BPredUnit.lookups 57179 # Number of BP lookups -system.cpu2.BPredUnit.condPredicted 53988 # Number of conditional branches predicted -system.cpu2.BPredUnit.condIncorrect 1553 # Number of conditional branches incorrect -system.cpu2.BPredUnit.BTBLookups 50487 # Number of BTB lookups -system.cpu2.BPredUnit.BTBHits 49441 # Number of BTB hits +system.cpu2.BPredUnit.lookups 53962 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 50907 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 1502 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 47302 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 46374 # Number of BTB hits system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.usedRAS 815 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.usedRAS 814 # Number of times the RAS was used to get a target. system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.fetch.icacheStallCycles 29527 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 320031 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 57179 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 50256 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 111848 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 4474 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 35937 # Number of cycles fetch has spent blocked +system.cpu2.fetch.icacheStallCycles 29545 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 300535 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 53962 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 47188 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 106111 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 4305 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 35885 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6751 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1077 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 20539 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 333 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 187993 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.702356 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.156955 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.NoActiveThreadStallCycles 6446 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 1035 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 21240 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 181756 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.653508 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.139245 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 76145 40.50% 40.50% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 56782 30.20% 70.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 6165 3.28% 73.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3347 1.78% 75.77% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 731 0.39% 76.16% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 39077 20.79% 96.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1243 0.66% 97.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 913 0.49% 98.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3590 1.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 75645 41.62% 41.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 54116 29.77% 71.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 6682 3.68% 75.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3224 1.77% 76.84% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 665 0.37% 77.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 35775 19.68% 96.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1232 0.68% 97.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 880 0.48% 98.05% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3537 1.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 187993 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.299351 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.675467 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 35252 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 32290 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 105597 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5255 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2848 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 315625 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2848 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 36036 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 16472 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 14955 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 100655 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 10276 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 313299 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 22 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 57 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 219155 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 602465 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 602465 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 203359 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 15796 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1243 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1365 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 12944 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 89370 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 42679 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 42734 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 37374 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 259618 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6531 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 261379 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 134 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 13068 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11786 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 697 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 187993 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.390366 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.314588 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 181756 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.293533 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.634799 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 35633 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 31817 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 99530 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5601 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2729 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 296271 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2729 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 36405 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 17349 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13658 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 94174 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 10995 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 293755 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 37 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 205188 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 562117 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 562117 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 190142 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 15046 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1228 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1359 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 13734 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 82915 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 39246 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 39773 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 34011 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 242760 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 6943 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 245051 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 12414 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11373 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 664 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 181756 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.348242 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.310708 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 73641 39.17% 39.17% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 23139 12.31% 51.48% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 42800 22.77% 74.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 43353 23.06% 97.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3352 1.78% 99.09% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1252 0.67% 99.76% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 341 0.18% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 62 0.03% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 73115 40.23% 40.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 24368 13.41% 53.63% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 39333 21.64% 75.27% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 39995 22.00% 97.28% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3268 1.80% 99.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1268 0.70% 99.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 298 0.16% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 187993 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 181756 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 21 6.71% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 82 26.20% 32.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 67.09% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 20 6.83% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 63 21.50% 28.33% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 71.67% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 125670 48.08% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 93767 35.87% 83.95% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 41942 16.05% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 118754 48.46% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 87780 35.82% 84.28% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 38517 15.72% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 261379 # Type of FU issued -system.cpu2.iq.rate 1.368405 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 313 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001197 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 711198 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 279252 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 259224 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 245051 # Type of FU issued +system.cpu2.iq.rate 1.332987 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 293 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001196 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 672224 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 262158 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 243059 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 261692 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 245344 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 37218 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 33799 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2690 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1641 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2624 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1621 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2848 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 1926 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 75 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 309970 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 424 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 89370 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 42679 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1173 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 72 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2729 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 1758 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 40 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 290501 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 383 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 82915 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 39246 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1163 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 35 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 514 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1208 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1722 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 259980 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 88335 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1399 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 513 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1158 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1671 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 243729 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 81914 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1322 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 43821 # number of nop insts executed -system.cpu2.iew.exec_refs 130189 # number of memory reference insts executed -system.cpu2.iew.exec_branches 53302 # Number of branches executed -system.cpu2.iew.exec_stores 41854 # Number of stores executed -system.cpu2.iew.exec_rate 1.361081 # Inst execution rate -system.cpu2.iew.wb_sent 259524 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 259224 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 147020 # num instructions producing a value -system.cpu2.iew.wb_consumers 151915 # num instructions consuming a value +system.cpu2.iew.exec_nop 40798 # number of nop insts executed +system.cpu2.iew.exec_refs 120340 # number of memory reference insts executed +system.cpu2.iew.exec_branches 50195 # Number of branches executed +system.cpu2.iew.exec_stores 38426 # Number of stores executed +system.cpu2.iew.exec_rate 1.325796 # Inst execution rate +system.cpu2.iew.wb_sent 243343 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 243059 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 137174 # num instructions producing a value +system.cpu2.iew.wb_consumers 142058 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.357123 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.967778 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.322151 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.965620 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 15032 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 5834 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1553 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 178395 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.653241 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.030877 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 14265 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 6279 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1502 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 172582 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.600480 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.009191 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 72759 40.79% 40.79% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 51159 28.68% 69.46% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6241 3.50% 72.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6697 3.75% 76.72% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1549 0.87% 77.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 37557 21.05% 98.64% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 629 0.35% 98.99% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 989 0.55% 99.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 815 0.46% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 72897 42.24% 42.24% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 48196 27.93% 70.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6187 3.58% 73.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 7136 4.13% 77.89% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1545 0.90% 78.78% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 34295 19.87% 98.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 518 0.30% 98.95% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 991 0.57% 99.53% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 817 0.47% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 178395 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 294930 # Number of instructions committed -system.cpu2.commit.committedOps 294930 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 172582 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 276214 # Number of instructions committed +system.cpu2.commit.committedOps 276214 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 127718 # Number of memory references committed -system.cpu2.commit.loads 86680 # Number of loads committed -system.cpu2.commit.membars 5119 # Number of memory barriers committed -system.cpu2.commit.branches 52122 # Number of branches committed +system.cpu2.commit.refs 117916 # Number of memory references committed +system.cpu2.commit.loads 80291 # Number of loads committed +system.cpu2.commit.membars 5562 # Number of memory barriers committed +system.cpu2.commit.branches 49152 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 201960 # Number of committed integer instructions. +system.cpu2.commit.int_insts 189186 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 815 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 817 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 486955 # The number of ROB reads -system.cpu2.rob.rob_writes 622786 # The number of ROB writes -system.cpu2.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3017 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 36810 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 246900 # Number of Instructions Simulated -system.cpu2.committedOps 246900 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 246900 # Number of Instructions Simulated -system.cpu2.cpi 0.773633 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.773633 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.292602 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.292602 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 450556 # number of integer regfile reads -system.cpu2.int_regfile_writes 209704 # number of integer regfile writes +system.cpu2.rob.rob_reads 461657 # The number of ROB reads +system.cpu2.rob.rob_writes 583698 # The number of ROB writes +system.cpu2.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 2080 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 35951 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 230713 # Number of Instructions Simulated +system.cpu2.committedOps 230713 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 230713 # Number of Instructions Simulated +system.cpu2.cpi 0.796817 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.796817 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.254994 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.254994 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 420543 # number of integer regfile reads +system.cpu2.int_regfile_writes 196056 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 131893 # number of misc regfile reads +system.cpu2.misc_regfile_reads 121964 # number of misc regfile reads system.cpu2.misc_regfile_writes 646 # number of misc regfile writes -system.cpu2.icache.replacements 322 # number of replacements -system.cpu2.icache.tagsinuse 84.177245 # Cycle average of tags in use -system.cpu2.icache.total_refs 20042 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 438 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 45.757991 # Average number of references to valid blocks. +system.cpu2.icache.replacements 323 # number of replacements +system.cpu2.icache.tagsinuse 86.140818 # Cycle average of tags in use +system.cpu2.icache.total_refs 20746 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 436 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 47.582569 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 84.177245 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.164409 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.164409 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 20042 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 20042 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 20042 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 20042 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 20042 # number of overall hits -system.cpu2.icache.overall_hits::total 20042 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 497 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 497 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 497 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 497 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 497 # number of overall misses -system.cpu2.icache.overall_misses::total 497 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7614500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 7614500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 7614500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 7614500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 7614500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 7614500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 20539 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 20539 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 20539 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 20539 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 20539 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 20539 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024198 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.024198 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024198 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.024198 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024198 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.024198 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15320.925553 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 15320.925553 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15320.925553 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 15320.925553 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15320.925553 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 15320.925553 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 86.140818 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.168244 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.168244 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 20746 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 20746 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 20746 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 20746 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 20746 # number of overall hits +system.cpu2.icache.overall_hits::total 20746 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 494 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 494 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 494 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 494 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 494 # number of overall misses +system.cpu2.icache.overall_misses::total 494 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6486500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 6486500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 6486500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 6486500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 6486500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 6486500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 21240 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 21240 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 21240 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 21240 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 21240 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 21240 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.023258 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.023258 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.023258 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.023258 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.023258 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.023258 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13130.566802 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 13130.566802 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13130.566802 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 13130.566802 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13130.566802 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 13130.566802 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1322,106 +1322,106 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 59 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 59 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 59 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 59 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 438 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 438 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 438 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 438 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 438 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 438 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5672000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 5672000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5672000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 5672000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5672000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 5672000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021325 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021325 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021325 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.021325 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021325 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.021325 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12949.771689 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12949.771689 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12949.771689 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 12949.771689 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12949.771689 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 12949.771689 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 58 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 58 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 58 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 58 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 436 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 436 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 436 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 436 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5217500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 5217500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5217500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 5217500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5217500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 5217500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.020527 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.020527 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.020527 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.020527 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.020527 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.020527 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11966.743119 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11966.743119 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11966.743119 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 11966.743119 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11966.743119 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 11966.743119 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 24.875323 # Cycle average of tags in use -system.cpu2.dcache.total_refs 47216 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1686.285714 # Average number of references to valid blocks. +system.cpu2.dcache.tagsinuse 26.073093 # Cycle average of tags in use +system.cpu2.dcache.total_refs 43891 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1513.482759 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 24.875323 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.048585 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.048585 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 50709 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 50709 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 40830 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 40830 # number of WriteReq hits +system.cpu2.dcache.occ_blocks::cpu2.data 26.073093 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.050924 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.050924 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 47692 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 47692 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 37413 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 37413 # number of WriteReq hits system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 91539 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 91539 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 91539 # number of overall hits -system.cpu2.dcache.overall_hits::total 91539 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 389 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 389 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 57 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 528 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 528 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 528 # number of overall misses -system.cpu2.dcache.overall_misses::total 528 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 10172000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 10172000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3390500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 3390500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 1234500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 1234500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 13562500 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 13562500 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 13562500 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 13562500 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 51098 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 51098 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 40969 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 40969 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 92067 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 92067 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 92067 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 92067 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.007613 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.007613 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003393 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.003393 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.826087 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.826087 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005735 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.005735 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005735 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.005735 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 26149.100257 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 26149.100257 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24392.086331 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 24392.086331 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 21657.894737 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 21657.894737 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 25686.553030 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 25686.553030 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 25686.553030 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 25686.553030 # average overall miss latency +system.cpu2.dcache.demand_hits::cpu2.data 85105 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 85105 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 85105 # number of overall hits +system.cpu2.dcache.overall_hits::total 85105 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 405 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 405 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 141 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 141 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 59 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 59 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 546 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 546 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 546 # number of overall misses +system.cpu2.dcache.overall_misses::total 546 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 9305500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 9305500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2828000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2828000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 998500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 998500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 12133500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 12133500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 12133500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 12133500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 48097 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 48097 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 37554 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 37554 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 85651 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 85651 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 85651 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 85651 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.008420 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.008420 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003755 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.003755 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.830986 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.830986 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.006375 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.006375 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006375 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.006375 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 22976.543210 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 22976.543210 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20056.737589 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 20056.737589 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 16923.728814 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 16923.728814 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22222.527473 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 22222.527473 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22222.527473 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 22222.527473 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1430,364 +1430,364 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 234 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 234 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 35 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 269 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 269 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 269 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 269 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 155 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 104 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 259 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 259 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2539505 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2539505 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1736500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1736500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 1057000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 1057000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4276005 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 4276005 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4276005 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 4276005 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003033 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003033 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002539 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002539 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.826087 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002813 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.002813 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002813 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.002813 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16383.903226 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16383.903226 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16697.115385 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16697.115385 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18543.859649 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18543.859649 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16509.671815 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16509.671815 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16509.671815 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16509.671815 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 239 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 239 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 273 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 273 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 273 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 273 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 166 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 107 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 59 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 273 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 273 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 273 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2062000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2062000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1458000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1458000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 880500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 880500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3520000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3520000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3520000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3520000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003451 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003451 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002849 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002849 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.830986 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.830986 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003187 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003187 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003187 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003187 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12421.686747 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 12421.686747 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13626.168224 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13626.168224 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 14923.728814 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 14923.728814 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12893.772894 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12893.772894 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12893.772894 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12893.772894 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 190730 # number of cpu cycles simulated +system.cpu3.numCycles 183564 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.BPredUnit.lookups 50135 # Number of BP lookups -system.cpu3.BPredUnit.condPredicted 46886 # Number of conditional branches predicted -system.cpu3.BPredUnit.condIncorrect 1563 # Number of conditional branches incorrect -system.cpu3.BPredUnit.BTBLookups 43380 # Number of BTB lookups -system.cpu3.BPredUnit.BTBHits 42368 # Number of BTB hits +system.cpu3.BPredUnit.lookups 54292 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 51137 # Number of conditional branches predicted +system.cpu3.BPredUnit.condIncorrect 1552 # Number of conditional branches incorrect +system.cpu3.BPredUnit.BTBLookups 47375 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 46456 # Number of BTB hits system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.usedRAS 844 # Number of times the RAS was used to get a target. +system.cpu3.BPredUnit.usedRAS 865 # Number of times the RAS was used to get a target. system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.fetch.icacheStallCycles 33373 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 273510 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 50135 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 43212 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 99693 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 4441 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 43703 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 29332 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 302436 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 54292 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 47321 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 106466 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 4424 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 35508 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6715 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1058 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 24485 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 321 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 187356 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.459841 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.059659 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 6464 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 1083 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 21183 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 181653 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.664911 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.146175 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 87663 46.79% 46.79% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 51707 27.60% 74.39% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 8154 4.35% 78.74% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3276 1.75% 80.49% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 745 0.40% 80.89% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 30183 16.11% 97.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1182 0.63% 97.63% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 888 0.47% 98.10% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3558 1.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 75187 41.39% 41.39% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 54224 29.85% 71.24% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 6571 3.62% 74.86% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3185 1.75% 76.61% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 729 0.40% 77.01% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 36075 19.86% 96.87% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1175 0.65% 97.52% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 882 0.49% 98.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3625 2.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 187356 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.262858 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.434017 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 40875 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 38262 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 91696 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 6999 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2809 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 269218 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2809 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 41677 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 21676 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 15745 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 84975 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 13759 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 266737 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 40 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 184789 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 501822 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 501822 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 169578 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 15211 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1292 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1426 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 16516 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 73298 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 33720 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 35666 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 28418 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 218299 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 8477 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 222114 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 12726 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 11163 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 773 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 187356 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.185518 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.293170 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 181653 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.295766 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.647578 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 35528 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 31409 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 99893 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 5564 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2795 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 298258 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2795 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 36311 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 17134 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 13439 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 94588 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 10922 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 295479 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 43 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 206753 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 566043 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 566043 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 191392 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 15361 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1256 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1388 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 13950 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 83468 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 39555 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 39943 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 34309 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 244369 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 6827 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 246724 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 12382 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 11033 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 652 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 181653 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.358216 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.312562 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 85320 45.54% 45.54% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 28690 15.31% 60.85% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 33902 18.09% 78.95% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 34456 18.39% 97.34% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3309 1.77% 99.10% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1236 0.66% 99.76% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 327 0.17% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 62 0.03% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 72528 39.93% 39.93% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 24126 13.28% 53.21% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 39707 21.86% 75.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 40305 22.19% 97.25% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3272 1.80% 99.06% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1282 0.71% 99.76% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 320 0.18% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 60 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 187356 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 181653 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 22 7.17% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 75 24.43% 31.60% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 68.40% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 22 7.41% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 65 21.89% 29.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 70.71% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 109540 49.32% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 79567 35.82% 85.14% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 33007 14.86% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 119576 48.47% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 88284 35.78% 84.25% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 38864 15.75% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 222114 # Type of FU issued -system.cpu3.iq.rate 1.164547 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 307 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001382 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 632004 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 239536 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 220090 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 246724 # Type of FU issued +system.cpu3.iq.rate 1.344076 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 297 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001204 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 675462 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 263617 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 244690 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 222421 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 247021 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 28294 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 34138 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2578 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1587 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2601 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1592 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2809 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 1854 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 263586 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 366 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 73298 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 33720 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1219 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 53 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2795 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 1688 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 292203 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 375 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 83468 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 39555 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1173 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 48 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 509 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1217 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1726 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 220807 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 72290 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1307 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 39 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 498 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1226 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1724 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 245374 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 82515 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1350 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 36810 # number of nop insts executed -system.cpu3.iew.exec_refs 105220 # number of memory reference insts executed -system.cpu3.iew.exec_branches 46242 # Number of branches executed -system.cpu3.iew.exec_stores 32930 # Number of stores executed -system.cpu3.iew.exec_rate 1.157694 # Inst execution rate -system.cpu3.iew.wb_sent 220376 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 220090 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 122048 # num instructions producing a value -system.cpu3.iew.wb_consumers 126919 # num instructions consuming a value +system.cpu3.iew.exec_nop 41007 # number of nop insts executed +system.cpu3.iew.exec_refs 121290 # number of memory reference insts executed +system.cpu3.iew.exec_branches 50490 # Number of branches executed +system.cpu3.iew.exec_stores 38775 # Number of stores executed +system.cpu3.iew.exec_rate 1.336722 # Inst execution rate +system.cpu3.iew.wb_sent 244974 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 244690 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 138171 # num instructions producing a value +system.cpu3.iew.wb_consumers 143054 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.153935 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.961621 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.332996 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.965866 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 14631 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7704 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1563 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 177833 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.399791 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.928963 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 14351 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 6175 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1552 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 172395 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.611613 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.012919 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 86250 48.50% 48.50% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 44177 24.84% 73.34% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6214 3.49% 76.84% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8561 4.81% 81.65% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1535 0.86% 82.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 28697 16.14% 98.65% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 590 0.33% 98.98% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 996 0.56% 99.54% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 813 0.46% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 72191 41.88% 41.88% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 48466 28.11% 69.99% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6229 3.61% 73.60% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 7040 4.08% 77.69% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1522 0.88% 78.57% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 34600 20.07% 98.64% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 541 0.31% 98.95% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 992 0.58% 99.53% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 814 0.47% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 177833 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 248929 # Number of instructions committed -system.cpu3.commit.committedOps 248929 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 172395 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 277834 # Number of instructions committed +system.cpu3.commit.committedOps 277834 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 102853 # Number of memory references committed -system.cpu3.commit.loads 70720 # Number of loads committed -system.cpu3.commit.membars 6986 # Number of memory barriers committed -system.cpu3.commit.branches 45078 # Number of branches committed +system.cpu3.commit.refs 118830 # Number of memory references committed +system.cpu3.commit.loads 80867 # Number of loads committed +system.cpu3.commit.membars 5460 # Number of memory barriers committed +system.cpu3.commit.branches 49386 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 170050 # Number of committed integer instructions. +system.cpu3.commit.int_insts 190336 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 813 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 814 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 439993 # The number of ROB reads -system.cpu3.rob.rob_writes 529937 # The number of ROB writes -system.cpu3.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 3374 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 37090 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 206079 # Number of Instructions Simulated -system.cpu3.committedOps 206079 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 206079 # Number of Instructions Simulated -system.cpu3.cpi 0.925519 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.925519 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.080475 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.080475 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 375615 # number of integer regfile reads -system.cpu3.int_regfile_writes 175714 # number of integer regfile writes +system.cpu3.rob.rob_reads 463179 # The number of ROB reads +system.cpu3.rob.rob_writes 587180 # The number of ROB writes +system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1911 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 36223 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 232199 # Number of Instructions Simulated +system.cpu3.committedOps 232199 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 232199 # Number of Instructions Simulated +system.cpu3.cpi 0.790546 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.790546 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.264948 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.264948 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 423588 # number of integer regfile reads +system.cpu3.int_regfile_writes 197545 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 106918 # number of misc regfile reads +system.cpu3.misc_regfile_reads 122942 # number of misc regfile reads system.cpu3.misc_regfile_writes 646 # number of misc regfile writes -system.cpu3.icache.replacements 323 # number of replacements -system.cpu3.icache.tagsinuse 88.249587 # Cycle average of tags in use -system.cpu3.icache.total_refs 23982 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 439 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 54.628702 # Average number of references to valid blocks. +system.cpu3.icache.replacements 321 # number of replacements +system.cpu3.icache.tagsinuse 83.581511 # Cycle average of tags in use +system.cpu3.icache.total_refs 20679 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 436 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 47.428899 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 88.249587 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.172362 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.172362 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 23982 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 23982 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 23982 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 23982 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 23982 # number of overall hits -system.cpu3.icache.overall_hits::total 23982 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 503 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 503 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 503 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 503 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 503 # number of overall misses -system.cpu3.icache.overall_misses::total 503 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7707000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 7707000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 7707000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 7707000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 7707000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 7707000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 24485 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 24485 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 24485 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 24485 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 24485 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 24485 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020543 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.020543 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020543 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.020543 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020543 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.020543 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15322.067594 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 15322.067594 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15322.067594 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 15322.067594 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15322.067594 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 15322.067594 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 83.581511 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.163245 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.163245 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 20679 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 20679 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 20679 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 20679 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 20679 # number of overall hits +system.cpu3.icache.overall_hits::total 20679 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 504 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 504 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 504 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 504 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 504 # number of overall misses +system.cpu3.icache.overall_misses::total 504 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6381500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6381500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6381500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6381500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6381500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6381500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 21183 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 21183 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 21183 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 21183 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 21183 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 21183 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023793 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.023793 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023793 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.023793 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023793 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.023793 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 12661.706349 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 12661.706349 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 12661.706349 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 12661.706349 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 12661.706349 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 12661.706349 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1796,106 +1796,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 64 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 64 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 64 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 64 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 64 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 439 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 439 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 439 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 439 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 439 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 439 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5684000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5684000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5684000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5684000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5684000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5684000 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017929 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017929 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017929 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.017929 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017929 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.017929 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12947.608200 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12947.608200 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12947.608200 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12947.608200 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12947.608200 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12947.608200 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 68 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 68 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 68 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 436 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 436 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 436 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 436 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5023500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5023500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5023500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5023500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5023500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5023500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020583 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020583 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020583 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.020583 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020583 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.020583 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11521.788991 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11521.788991 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11521.788991 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 11521.788991 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11521.788991 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 11521.788991 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 0 # number of replacements -system.cpu3.dcache.tagsinuse 26.048284 # Cycle average of tags in use -system.cpu3.dcache.total_refs 38388 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1323.724138 # Average number of references to valid blocks. +system.cpu3.dcache.tagsinuse 24.842435 # Cycle average of tags in use +system.cpu3.dcache.total_refs 44137 # Total number of references to valid blocks. +system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu3.dcache.avg_refs 1576.321429 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 26.048284 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.050876 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.050876 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 43625 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 43625 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 31927 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 31927 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 16 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 75552 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 75552 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 75552 # number of overall hits -system.cpu3.dcache.overall_hits::total 75552 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 356 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 356 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 134 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 134 # number of WriteReq misses +system.cpu3.dcache.occ_blocks::cpu3.data 24.842435 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.048520 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.048520 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 47956 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 47956 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 37758 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 37758 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 85714 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 85714 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 85714 # number of overall hits +system.cpu3.dcache.overall_hits::total 85714 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 403 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 403 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 136 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 136 # number of WriteReq misses system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 490 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 490 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 490 # number of overall misses -system.cpu3.dcache.overall_misses::total 490 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 9997000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 9997000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3151500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 3151500 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 1323000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 1323000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 13148500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 13148500 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 13148500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 13148500 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 43981 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 43981 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 32061 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 32061 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 76042 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 76042 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 76042 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 76042 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.008094 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.008094 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004180 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.004180 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.777778 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.777778 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006444 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.006444 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006444 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.006444 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 28081.460674 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 28081.460674 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23518.656716 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 23518.656716 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 23625 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 23625 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 26833.673469 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 26833.673469 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 26833.673469 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 26833.673469 # average overall miss latency +system.cpu3.dcache.demand_misses::cpu3.data 539 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 539 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 539 # number of overall misses +system.cpu3.dcache.overall_misses::total 539 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8840000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 8840000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2771500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2771500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 950000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 950000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 11611500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 11611500 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 11611500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 11611500 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 48359 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 48359 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 37894 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 37894 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 69 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 86253 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 86253 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 86253 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 86253 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.008334 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.008334 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003589 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.003589 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.811594 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006249 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.006249 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006249 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.006249 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 21935.483871 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 21935.483871 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20378.676471 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 20378.676471 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 16964.285714 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 16964.285714 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 21542.671614 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 21542.671614 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 21542.671614 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 21542.671614 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1904,288 +1904,288 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 195 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 195 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 32 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 227 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 227 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 227 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 227 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 161 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 102 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 248 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 31 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 279 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 279 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 155 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 263 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 263 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2771504 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2771504 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1583000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1583000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 1148500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 1148500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4354504 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 4354504 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4354504 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 4354504 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003661 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003661 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003181 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003181 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.777778 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.777778 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003459 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003459 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003459 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003459 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17214.310559 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 17214.310559 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15519.607843 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15519.607843 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 20508.928571 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 20508.928571 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16557.049430 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16557.049430 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16557.049430 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16557.049430 # average overall mshr miss latency +system.cpu3.dcache.demand_mshr_misses::cpu3.data 260 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 260 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1965500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1965500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1462000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1462000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 838000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 838000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3427500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3427500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3427500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3427500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003205 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003205 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002771 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002771 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.811594 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003014 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003014 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003014 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003014 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 12680.645161 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 12680.645161 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13923.809524 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13923.809524 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 14964.285714 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 14964.285714 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13182.692308 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13182.692308 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13182.692308 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13182.692308 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 436.337885 # Cycle average of tags in use -system.l2c.total_refs 1474 # Total number of references to valid blocks. -system.l2c.sampled_refs 537 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.744879 # Average number of references to valid blocks. +system.l2c.tagsinuse 435.526886 # Cycle average of tags in use +system.l2c.total_refs 1471 # Total number of references to valid blocks. +system.l2c.sampled_refs 536 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.744403 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 0.838584 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 294.109117 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 59.534191 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 68.191567 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 5.703860 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 2.346215 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.730565 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 4.110047 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.773739 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 0.836552 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 292.896606 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 59.494044 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 70.004577 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 5.700111 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 3.075204 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.772877 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 2.016825 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.730090 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.004488 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.004469 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.000908 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001041 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.001068 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.000087 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000063 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.006658 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 233 # number of ReadReq hits +system.l2c.occ_percent::cpu2.inst 0.000047 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.000012 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000031 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.006646 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 232 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 350 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 348 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 428 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 427 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 431 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 432 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1474 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1471 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 233 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 232 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 350 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 348 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 428 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 427 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 431 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 432 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1474 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 233 # number of overall hits +system.l2c.demand_hits::total 1471 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 232 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 350 # number of overall hits +system.l2c.overall_hits::cpu1.inst 348 # number of overall hits system.l2c.overall_hits::cpu1.data 5 # number of overall hits -system.l2c.overall_hits::cpu2.inst 428 # number of overall hits +system.l2c.overall_hits::cpu2.inst 427 # number of overall hits system.l2c.overall_hits::cpu2.data 11 # number of overall hits -system.l2c.overall_hits::cpu3.inst 431 # number of overall hits +system.l2c.overall_hits::cpu3.inst 432 # number of overall hits system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 1474 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 362 # number of ReadReq misses +system.l2c.overall_hits::total 1471 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 360 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 86 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 90 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 10 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 9 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 8 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 549 # number of ReadReq misses +system.l2c.ReadReq_misses::total 546 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 21 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 21 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 74 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 362 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 360 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 86 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 90 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 10 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 9 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 8 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 680 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 362 # number of overall misses +system.l2c.demand_misses::total 677 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 360 # number of overall misses system.l2c.overall_misses::cpu0.data 168 # number of overall misses -system.l2c.overall_misses::cpu1.inst 86 # number of overall misses +system.l2c.overall_misses::cpu1.inst 90 # number of overall misses system.l2c.overall_misses::cpu1.data 20 # number of overall misses -system.l2c.overall_misses::cpu2.inst 10 # number of overall misses +system.l2c.overall_misses::cpu2.inst 9 # number of overall misses system.l2c.overall_misses::cpu2.data 13 # number of overall misses -system.l2c.overall_misses::cpu3.inst 8 # number of overall misses +system.l2c.overall_misses::cpu3.inst 4 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 680 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 19202500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 4170000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 4498000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 377500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 449000 # number of ReadReq miss cycles +system.l2c.overall_misses::total 677 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 19126500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 4185500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 4718500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 377000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 420000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.data 52500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 386000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 209000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.data 52500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 29188000 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5156500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 751000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 663000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 658499 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7228999 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 19202500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 9326500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 4498000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1128500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 449000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 715500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 386000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 710999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 36416999 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 19202500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 9326500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 4498000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1128500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 449000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 715500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 386000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 710999 # number of overall miss cycles -system.l2c.overall_miss_latency::total 36416999 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 595 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_miss_latency::total 29141500 # number of ReadReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5186500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 748500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 663500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 659500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7258000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 19126500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 9372000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 4718500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1125500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 420000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 716000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 209000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 712000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 36399500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 19126500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 9372000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 4718500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1125500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 420000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 716000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 209000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 712000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 36399500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 592 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 436 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 438 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 438 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 436 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 439 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 436 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2023 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2017 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 23 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 21 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 21 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 80 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 77 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 595 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 592 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 436 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 438 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 438 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 436 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 439 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 436 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2154 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 595 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2148 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 592 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 436 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 438 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 438 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 436 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 439 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 436 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2154 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.608403 # miss rate for ReadReq accesses +system.l2c.overall_accesses::total 2148 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.608108 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.197248 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.205479 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.022831 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.020642 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.018223 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.009174 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.271379 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.270699 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.869565 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.962500 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.961039 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.608403 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.608108 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.197248 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.205479 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.022831 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.020642 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.018223 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.009174 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.315692 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.608403 # miss rate for overall accesses +system.l2c.demand_miss_rate::total 0.315177 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.608108 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.197248 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.205479 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.022831 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.020642 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.018223 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.009174 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.315692 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53045.580110 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 56351.351351 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52302.325581 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 53928.571429 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 44900 # average ReadReq miss latency +system.l2c.overall_miss_rate::total 0.315177 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53129.166667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 56560.810811 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52427.777778 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 53857.142857 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 46666.666667 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.data 52500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 48250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 52250 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.data 52500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 53165.755920 # average ReadReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 54856.382979 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 57769.230769 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 55250 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 54874.916667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 55183.198473 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 53045.580110 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 55514.880952 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52302.325581 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 56425 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 44900 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 55038.461538 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 48250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 54692.230769 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 53554.410294 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 53045.580110 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 55514.880952 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52302.325581 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 56425 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 44900 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 55038.461538 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 48250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 54692.230769 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 53554.410294 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::total 53372.710623 # average ReadReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 55175.531915 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 57576.923077 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 55291.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 54958.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 55404.580153 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 53129.166667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 55785.714286 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52427.777778 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 56275 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 46666.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 55076.923077 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 52250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 54769.230769 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 53765.878877 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 53129.166667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 55785.714286 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52427.777778 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 56275 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 46666.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 55076.923077 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 52250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 54769.230769 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 53765.878877 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2196,164 +2196,161 @@ system.l2c.fast_writes 0 # nu system.l2c.cache_copies 0 # number of cache copies performed system.l2c.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3.inst 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3.inst 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3.inst 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 362 # number of ReadReq MSHR misses +system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.inst 360 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 84 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 88 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 5 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 4 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.inst 6 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.inst 4 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 540 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 539 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 20 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 21 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 21 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 15 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 18 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 18 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 18 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 74 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 362 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 360 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 84 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 88 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 5 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 4 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.inst 6 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 4 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 671 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 362 # number of overall MSHR misses +system.l2c.demand_mshr_misses::total 670 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 360 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 84 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 88 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 5 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 4 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.inst 6 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 4 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 671 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 14801500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3274000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3420500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 291500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 200000 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::total 670 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 14747000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3291000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3580000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 292000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 160000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.data 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 240000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 160000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 22307500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 800000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 840000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 844000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 605000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 3089000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4012500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 593500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 516500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 511500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5634000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 14801500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 7286500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 3420500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 885000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 200000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 556500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 240000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 551500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 27941500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 14801500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 7286500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 3420500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 885000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 200000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 556500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 240000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 551500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 27941500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.608403 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency::total 22310000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 804491 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 722994 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 722495 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 729492 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 2979472 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4039000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 591500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 518000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 513500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5662000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 14747000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 7330000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3580000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 883500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 160000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 558000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 160000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 553500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 27972000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 14747000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 7330000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 3580000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 883500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 160000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 558000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 160000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 553500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 27972000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.608108 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.192661 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.200913 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.011416 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009174 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013667 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.009174 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.266930 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.267229 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.869565 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.962500 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.961039 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.608403 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.608108 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.192661 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.200913 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011416 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009174 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.009174 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.311513 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.608403 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::total 0.311918 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.608108 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.192661 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.200913 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011416 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009174 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.009174 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.311513 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40888.121547 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44243.243243 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40720.238095 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41642.857143 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_rate::total 0.311918 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40963.888889 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44472.972973 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40681.818182 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41714.285714 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 41310.185185 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40190.476190 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40333.333333 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40116.883117 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42686.170213 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 45653.846154 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43041.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42625 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 43007.633588 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40888.121547 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 43372.023810 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40720.238095 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44250 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 41391.465677 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40224.550000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40166.333333 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40138.611111 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40527.333333 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40263.135135 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42968.085106 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 45500 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43166.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42791.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 43221.374046 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40963.888889 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 43630.952381 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40681.818182 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44175 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42807.692308 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42923.076923 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 42423.076923 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 41641.579732 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40888.121547 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 43372.023810 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40720.238095 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 42576.923077 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 41749.253731 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40963.888889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 43630.952381 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40681.818182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44175 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42807.692308 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42923.076923 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 42423.076923 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 41641.579732 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 42576.923077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 41749.253731 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 1523ab302..df50fe29d 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000269 # Number of seconds simulated -sim_ticks 268898000 # Number of ticks simulated -final_tick 268898000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000262 # Number of seconds simulated +sim_ticks 261623500 # Number of ticks simulated +final_tick 261623500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1131883 # Simulator instruction rate (inst/s) -host_op_rate 1131850 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 454173870 # Simulator tick rate (ticks/s) -host_mem_usage 240368 # Number of bytes of host memory used -host_seconds 0.59 # Real time elapsed on the host -sim_insts 670104 # Number of instructions simulated -sim_ops 670104 # Number of ops (including micro ops) simulated +host_inst_rate 776063 # Simulator instruction rate (inst/s) +host_op_rate 776047 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 307506962 # Simulator tick rate (ticks/s) +host_mem_usage 231300 # Number of bytes of host memory used +host_seconds 0.85 # Real time elapsed on the host +sim_insts 660239 # Number of instructions simulated +sim_ops 660239 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 3392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 1408 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 3392 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 53 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 22 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 67832412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 39271397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14042499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5236186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 476017 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 3570127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1904068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3808135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 136140842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 67832412 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14042499 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 476017 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1904068 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 84254996 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 67832412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 39271397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14042499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 5236186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 476017 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 3570127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1904068 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3808135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 136140842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69718508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40363347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 1712384 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3669395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 2201637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 3914021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 12965196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 5381780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139926268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69718508 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 1712384 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 2201637 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 12965196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86597725 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69718508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40363347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 1712384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3669395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 2201637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 3914021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 12965196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 5381780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 139926268 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 537796 # number of cpu cycles simulated +system.cpu0.numCycles 523247 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 160914 # Number of instructions committed -system.cpu0.committedOps 160914 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 110768 # Number of integer alu accesses +system.cpu0.committedInsts 158010 # Number of instructions committed +system.cpu0.committedOps 158010 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 108832 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 26422 # number of instructions that are conditional controls -system.cpu0.num_int_insts 110768 # number of integer instructions +system.cpu0.num_conditional_control_insts 25938 # number of instructions that are conditional controls +system.cpu0.num_int_insts 108832 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 320462 # number of times the integer registers were read -system.cpu0.num_int_register_writes 112374 # number of times the integer registers were written +system.cpu0.num_int_register_reads 314654 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110438 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 75191 # number of memory refs -system.cpu0.num_load_insts 49787 # Number of load instructions -system.cpu0.num_store_insts 25404 # Number of store instructions +system.cpu0.num_mem_refs 73739 # number of memory refs +system.cpu0.num_load_insts 48819 # Number of load instructions +system.cpu0.num_store_insts 24920 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 537796 # Number of busy cycles +system.cpu0.num_busy_cycles 523247 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.icache.replacements 215 # number of replacements -system.cpu0.icache.tagsinuse 212.263647 # Cycle average of tags in use -system.cpu0.icache.total_refs 160510 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 212.464540 # Cycle average of tags in use +system.cpu0.icache.total_refs 157606 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 343.704497 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 337.486081 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 212.263647 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.414577 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.414577 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 160510 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 160510 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 160510 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 160510 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 160510 # number of overall hits -system.cpu0.icache.overall_hits::total 160510 # number of overall hits +system.cpu0.icache.occ_blocks::cpu0.inst 212.464540 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.414970 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.414970 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 157606 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 157606 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 157606 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 157606 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 157606 # number of overall hits +system.cpu0.icache.overall_hits::total 157606 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18554000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18554000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18554000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18554000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18554000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18554000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 160977 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 160977 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 160977 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 160977 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 160977 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 160977 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002901 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002901 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002901 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002901 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002901 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002901 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39730.192719 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 39730.192719 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39730.192719 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 39730.192719 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39730.192719 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 39730.192719 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18144000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18144000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18144000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18144000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18144000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18144000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 158073 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 158073 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 158073 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 158073 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 158073 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 158073 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002954 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002954 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002954 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002954 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002954 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002954 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38852.248394 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38852.248394 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38852.248394 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38852.248394 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -139,44 +139,44 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17153000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17153000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17153000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17153000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17153000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17153000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002901 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002901 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002901 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36730.192719 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 36730.192719 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 36730.192719 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17210000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17210000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17210000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17210000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17210000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17210000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002954 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002954 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002954 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36852.248394 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 36852.248394 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 36852.248394 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 145.520681 # Cycle average of tags in use -system.cpu0.dcache.total_refs 74667 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 145.601248 # Cycle average of tags in use +system.cpu0.dcache.total_refs 73215 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 447.107784 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 438.413174 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 145.520681 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.284220 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.284220 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 49615 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 49615 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 25170 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 25170 # number of WriteReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 145.601248 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.284377 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.284377 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 48647 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48647 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24686 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24686 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 74785 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 74785 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 74785 # number of overall hits -system.cpu0.dcache.overall_hits::total 74785 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 73333 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73333 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73333 # number of overall hits +system.cpu0.dcache.overall_hits::total 73333 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 162 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 162 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses @@ -187,46 +187,46 @@ system.cpu0.dcache.demand_misses::cpu0.data 345 # system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses system.cpu0.dcache.overall_misses::total 345 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5171000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5171000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7310000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7310000 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 522000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 522000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 12481000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 12481000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 12481000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 12481000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 49777 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 49777 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 25353 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 25353 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4649500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4649500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7005000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7005000 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 363500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 363500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11654500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11654500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11654500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11654500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48809 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48809 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24869 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24869 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 75130 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 75130 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 75130 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 75130 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003255 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003255 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007218 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007218 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 73678 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73678 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73678 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73678 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003319 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003319 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007359 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007359 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004592 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004592 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004592 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004592 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31919.753086 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31919.753086 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39945.355191 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39945.355191 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 20076.923077 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 20076.923077 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36176.811594 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36176.811594 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36176.811594 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36176.811594 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004683 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004683 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004683 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004683 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28700.617284 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28700.617284 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38278.688525 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38278.688525 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13980.769231 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 13980.769231 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33781.159420 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33781.159420 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33781.159420 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33781.159420 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -247,104 +247,104 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4684001 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4684001 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6761000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6761000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 444000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 444000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11445001 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11445001 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11445001 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11445001 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003255 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003255 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007218 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007218 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4325500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4325500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6639000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6639000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 311500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 311500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10964500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10964500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10964500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10964500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003319 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003319 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007359 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007359 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004592 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004592 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004592 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004592 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28913.586420 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28913.586420 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36945.355191 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36945.355191 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17076.923077 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17076.923077 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33173.915942 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33173.915942 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33173.915942 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33173.915942 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004683 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004683 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004683 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004683 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26700.617284 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26700.617284 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36278.688525 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36278.688525 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11980.769231 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11980.769231 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31781.159420 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31781.159420 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31781.159420 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31781.159420 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 537796 # number of cpu cycles simulated +system.cpu1.numCycles 523247 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 159902 # Number of instructions committed -system.cpu1.committedOps 159902 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 114536 # Number of integer alu accesses +system.cpu1.committedInsts 173283 # Number of instructions committed +system.cpu1.committedOps 173283 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 108736 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 26689 # number of instructions that are conditional controls -system.cpu1.num_int_insts 114536 # number of integer instructions +system.cpu1.num_conditional_control_insts 36284 # number of instructions that are conditional controls +system.cpu1.num_int_insts 108736 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 313629 # number of times the integer registers were read -system.cpu1.num_int_register_writes 121810 # number of times the integer registers were written +system.cpu1.num_int_register_reads 252002 # number of times the integer registers were read +system.cpu1.num_int_register_writes 93825 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 64016 # number of memory refs -system.cpu1.num_load_insts 42937 # Number of load instructions -system.cpu1.num_store_insts 21079 # Number of store instructions -system.cpu1.num_idle_cycles 71578.001734 # Number of idle cycles -system.cpu1.num_busy_cycles 466217.998266 # Number of busy cycles -system.cpu1.not_idle_fraction 0.866905 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.133095 # Percentage of idle cycles +system.cpu1.num_mem_refs 48621 # number of memory refs +system.cpu1.num_load_insts 40031 # Number of load instructions +system.cpu1.num_store_insts 8590 # Number of store instructions +system.cpu1.num_idle_cycles 68750.001737 # Number of idle cycles +system.cpu1.num_busy_cycles 454496.998263 # Number of busy cycles +system.cpu1.not_idle_fraction 0.868609 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.131391 # Percentage of idle cycles system.cpu1.icache.replacements 280 # number of replacements -system.cpu1.icache.tagsinuse 69.905818 # Cycle average of tags in use -system.cpu1.icache.total_refs 159569 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 65.593035 # Cycle average of tags in use +system.cpu1.icache.total_refs 172950 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 435.980874 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 472.540984 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 69.905818 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.136535 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.136535 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 159569 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 159569 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 159569 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 159569 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 159569 # number of overall hits -system.cpu1.icache.overall_hits::total 159569 # number of overall hits +system.cpu1.icache.occ_blocks::cpu1.inst 65.593035 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.128111 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.128111 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 172950 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 172950 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 172950 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 172950 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 172950 # number of overall hits +system.cpu1.icache.overall_hits::total 172950 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7984500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7984500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7984500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7984500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7984500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7984500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 159935 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 159935 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 159935 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 159935 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 159935 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 159935 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002288 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002288 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002288 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002288 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002288 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002288 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21815.573770 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 21815.573770 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21815.573770 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 21815.573770 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21815.573770 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 21815.573770 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5373500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5373500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5373500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5373500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5373500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5373500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 173316 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 173316 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 173316 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 173316 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 173316 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 173316 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002112 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002112 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002112 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002112 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002112 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002112 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14681.693989 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14681.693989 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14681.693989 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14681.693989 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14681.693989 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14681.693989 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,94 +359,94 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6886000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6886000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6886000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6886000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6886000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6886000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002288 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002288 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002288 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002288 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002288 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002288 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18814.207650 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18814.207650 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18814.207650 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 18814.207650 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18814.207650 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 18814.207650 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4641500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4641500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4641500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4641500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4641500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4641500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002112 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002112 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002112 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002112 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002112 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002112 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12681.693989 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12681.693989 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12681.693989 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12681.693989 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12681.693989 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12681.693989 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 27.731515 # Cycle average of tags in use -system.cpu1.dcache.total_refs 44449 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1532.724138 # Average number of references to valid blocks. +system.cpu1.dcache.tagsinuse 25.918058 # Cycle average of tags in use +system.cpu1.dcache.total_refs 19532 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 651.066667 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 27.731515 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.054163 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.054163 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 42776 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 42776 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 20903 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 20903 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 10 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 10 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 63679 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 63679 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 63679 # number of overall hits -system.cpu1.dcache.overall_hits::total 63679 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 153 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 153 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 259 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 259 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259 # number of overall misses -system.cpu1.dcache.overall_misses::total 259 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3030000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3030000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2410000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2410000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 772000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 772000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5440000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5440000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5440000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5440000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 42929 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 42929 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 21009 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 21009 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 63938 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 63938 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 63938 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 63938 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003564 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.003564 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.005045 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.005045 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.852941 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.852941 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004051 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.004051 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004051 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.004051 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19803.921569 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19803.921569 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22735.849057 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22735.849057 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 13310.344828 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 13310.344828 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21003.861004 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 21003.861004 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21003.861004 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 21003.861004 # average overall miss latency +system.cpu1.dcache.occ_blocks::cpu1.data 25.918058 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.050621 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.050621 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 39847 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 39847 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 8412 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 8412 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 48259 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 48259 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 48259 # number of overall hits +system.cpu1.dcache.overall_hits::total 48259 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 177 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 177 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 282 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 282 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 282 # number of overall misses +system.cpu1.dcache.overall_misses::total 282 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3316000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3316000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1875500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1875500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 659500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 659500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 5191500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5191500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5191500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5191500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 40024 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 40024 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 8517 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 8517 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 48541 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 48541 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 48541 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 48541 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004422 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.004422 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012328 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.012328 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.774648 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.774648 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005810 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005810 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005810 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005810 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18734.463277 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 18734.463277 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17861.904762 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17861.904762 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11990.909091 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 11990.909091 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18409.574468 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18409.574468 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18409.574468 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18409.574468 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -455,114 +455,114 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 153 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 58 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 259 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 259 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2570001 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2570001 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2092000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2092000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 598000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 598000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4662001 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4662001 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4662001 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4662001 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003564 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003564 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.005045 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.005045 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.852941 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.852941 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004051 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.004051 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004051 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.004051 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16797.392157 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16797.392157 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19735.849057 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19735.849057 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10310.344828 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10310.344828 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18000.003861 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18000.003861 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18000.003861 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18000.003861 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 177 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 282 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 282 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 282 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 282 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2962000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2962000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1665500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1665500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 549500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 549500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4627500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4627500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4627500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4627500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004422 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004422 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012328 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.012328 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.774648 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.774648 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005810 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.005810 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005810 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.005810 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16734.463277 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16734.463277 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15861.904762 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15861.904762 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 9990.909091 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 9990.909091 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16409.574468 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16409.574468 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16409.574468 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16409.574468 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 537796 # number of cpu cycles simulated +system.cpu2.numCycles 523246 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 177221 # Number of instructions committed -system.cpu2.committedOps 177221 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 109567 # Number of integer alu accesses +system.cpu2.committedInsts 160665 # Number of instructions committed +system.cpu2.committedOps 160665 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 113639 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 37840 # number of instructions that are conditional controls -system.cpu2.num_int_insts 109567 # number of integer instructions +system.cpu2.num_conditional_control_insts 27518 # number of instructions that are conditional controls +system.cpu2.num_int_insts 113639 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 249142 # number of times the integer registers were read -system.cpu2.num_int_register_writes 92045 # number of times the integer registers were written +system.cpu2.num_int_register_reads 306682 # number of times the integer registers were read +system.cpu2.num_int_register_writes 118721 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 47896 # number of memory refs -system.cpu2.num_load_insts 40447 # Number of load instructions -system.cpu2.num_store_insts 7449 # Number of store instructions -system.cpu2.num_idle_cycles 71854.001733 # Number of idle cycles -system.cpu2.num_busy_cycles 465941.998267 # Number of busy cycles -system.cpu2.not_idle_fraction 0.866392 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.133608 # Percentage of idle cycles +system.cpu2.num_mem_refs 62290 # number of memory refs +system.cpu2.num_load_insts 42488 # Number of load instructions +system.cpu2.num_store_insts 19802 # Number of store instructions +system.cpu2.num_idle_cycles 69015.869837 # Number of idle cycles +system.cpu2.num_busy_cycles 454230.130163 # Number of busy cycles +system.cpu2.not_idle_fraction 0.868101 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.131899 # Percentage of idle cycles system.cpu2.icache.replacements 281 # number of replacements -system.cpu2.icache.tagsinuse 67.534984 # Cycle average of tags in use -system.cpu2.icache.total_refs 176887 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 67.731754 # Cycle average of tags in use +system.cpu2.icache.total_refs 160331 # Total number of references to valid blocks. system.cpu2.icache.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 481.980926 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 436.869210 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 67.534984 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.131904 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.131904 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 176887 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 176887 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 176887 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 176887 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 176887 # number of overall hits -system.cpu2.icache.overall_hits::total 176887 # number of overall hits +system.cpu2.icache.occ_blocks::cpu2.inst 67.731754 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.132289 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.132289 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 160331 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 160331 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 160331 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 160331 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 160331 # number of overall hits +system.cpu2.icache.overall_hits::total 160331 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 367 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 367 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 367 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 367 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 367 # number of overall misses system.cpu2.icache.overall_misses::total 367 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5709500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 5709500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 5709500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 5709500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 5709500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 5709500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 177254 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 177254 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 177254 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 177254 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 177254 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 177254 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002070 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002070 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002070 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002070 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002070 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002070 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15557.220708 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 15557.220708 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15557.220708 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 15557.220708 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15557.220708 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 15557.220708 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5321500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 5321500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 5321500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 5321500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 5321500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 5321500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 160698 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 160698 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 160698 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 160698 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 160698 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 160698 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002284 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002284 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002284 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002284 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002284 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002284 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14500 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 14500 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14500 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 14500 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14500 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 14500 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -577,94 +577,94 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 367 system.cpu2.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 367 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4608500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 4608500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4608500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 4608500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4608500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 4608500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002070 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002070 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002070 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002070 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002070 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002070 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12557.220708 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12557.220708 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12557.220708 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 12557.220708 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12557.220708 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 12557.220708 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4587500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 4587500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4587500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 4587500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4587500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 4587500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002284 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002284 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002284 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12500 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12500 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12500 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12500 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12500 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12500 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 26.638398 # Cycle average of tags in use -system.cpu2.dcache.total_refs 17171 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 26.833050 # Cycle average of tags in use +system.cpu2.dcache.total_refs 41851 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 592.103448 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 1443.137931 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 26.638398 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.052028 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.052028 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 40266 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 40266 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 7273 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 7273 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 18 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 18 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 47539 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 47539 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 47539 # number of overall hits -system.cpu2.dcache.overall_hits::total 47539 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 173 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 173 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 51 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 51 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 278 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 278 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 278 # number of overall misses -system.cpu2.dcache.overall_misses::total 278 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3995000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 3995000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2318000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2318000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 814000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 814000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 6313000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 6313000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 6313000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 6313000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 40439 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 40439 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 7378 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 7378 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 47817 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 47817 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 47817 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 47817 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.004278 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.004278 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.014231 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.014231 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.739130 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.739130 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005814 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.005814 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005814 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.005814 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23092.485549 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 23092.485549 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22076.190476 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 22076.190476 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 15960.784314 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 15960.784314 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22708.633094 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 22708.633094 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22708.633094 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 22708.633094 # average overall miss latency +system.cpu2.dcache.occ_blocks::cpu2.data 26.833050 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.052408 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.052408 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 42328 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42328 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 19626 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 19626 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 61954 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 61954 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 61954 # number of overall hits +system.cpu2.dcache.overall_hits::total 61954 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 152 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 152 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 106 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 106 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 258 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 258 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 258 # number of overall misses +system.cpu2.dcache.overall_misses::total 258 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 1938000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 1938000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2155000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2155000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 612500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 612500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 4093000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4093000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4093000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4093000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 42480 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 42480 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 19732 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 19732 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 62212 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 62212 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 62212 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 62212 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003578 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003578 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.005372 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.005372 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.852941 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.852941 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004147 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004147 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004147 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004147 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12750 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 12750 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20330.188679 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 20330.188679 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10560.344828 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 10560.344828 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15864.341085 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 15864.341085 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15864.341085 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 15864.341085 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -673,114 +673,114 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 173 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 278 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 278 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 278 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 3476000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 3476000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2003000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2003000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 661000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 661000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 5479000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 5479000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 5479000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 5479000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004278 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004278 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014231 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.014231 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.739130 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.739130 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.005814 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.005814 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.005814 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.005814 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 20092.485549 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 20092.485549 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19076.190476 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19076.190476 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 12960.784314 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 12960.784314 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 19708.633094 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 19708.633094 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19708.633094 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 19708.633094 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 152 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 258 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 258 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 258 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 258 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1634000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1634000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1943000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1943000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 496500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 496500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3577000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3577000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3577000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3577000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003578 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003578 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.005372 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.005372 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.852941 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.852941 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004147 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004147 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004147 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004147 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10750 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10750 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 18330.188679 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 18330.188679 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8560.344828 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8560.344828 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13864.341085 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13864.341085 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13864.341085 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13864.341085 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 537796 # number of cpu cycles simulated +system.cpu3.numCycles 523246 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 172067 # Number of instructions committed -system.cpu3.committedOps 172067 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 111206 # Number of integer alu accesses +system.cpu3.committedInsts 168281 # Number of instructions committed +system.cpu3.committedOps 168281 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 108796 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 34437 # number of instructions that are conditional controls -system.cpu3.num_int_insts 111206 # number of integer instructions +system.cpu3.num_conditional_control_insts 33752 # number of instructions that are conditional controls +system.cpu3.num_int_insts 108796 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 269314 # number of times the integer registers were read -system.cpu3.num_int_register_writes 101322 # number of times the integer registers were written +system.cpu3.num_int_register_reads 262371 # number of times the integer registers were read +system.cpu3.num_int_register_writes 98980 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 52937 # number of memory refs -system.cpu3.num_load_insts 41268 # Number of load instructions -system.cpu3.num_store_insts 11669 # Number of store instructions -system.cpu3.num_idle_cycles 72130.001732 # Number of idle cycles -system.cpu3.num_busy_cycles 465665.998268 # Number of busy cycles -system.cpu3.not_idle_fraction 0.865879 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.134121 # Percentage of idle cycles +system.cpu3.num_mem_refs 51213 # number of memory refs +system.cpu3.num_load_insts 40064 # Number of load instructions +system.cpu3.num_store_insts 11149 # Number of store instructions +system.cpu3.num_idle_cycles 69253.869381 # Number of idle cycles +system.cpu3.num_busy_cycles 453992.130619 # Number of busy cycles +system.cpu3.not_idle_fraction 0.867646 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.132354 # Percentage of idle cycles system.cpu3.icache.replacements 280 # number of replacements -system.cpu3.icache.tagsinuse 65.345482 # Cycle average of tags in use -system.cpu3.icache.total_refs 171734 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 70.063196 # Cycle average of tags in use +system.cpu3.icache.total_refs 167948 # Total number of references to valid blocks. system.cpu3.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 469.218579 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 458.874317 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 65.345482 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.127628 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.127628 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 171734 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 171734 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 171734 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 171734 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 171734 # number of overall hits -system.cpu3.icache.overall_hits::total 171734 # number of overall hits +system.cpu3.icache.occ_blocks::cpu3.inst 70.063196 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.136842 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.136842 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 167948 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 167948 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 167948 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 167948 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 167948 # number of overall hits +system.cpu3.icache.overall_hits::total 167948 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 366 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 366 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 366 # number of overall misses system.cpu3.icache.overall_misses::total 366 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5645500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5645500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5645500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5645500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5645500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5645500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 172100 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 172100 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 172100 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 172100 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 172100 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 172100 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002127 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002127 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002127 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002127 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002127 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002127 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15424.863388 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 15424.863388 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15424.863388 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 15424.863388 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15424.863388 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 15424.863388 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7343000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 7343000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 7343000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 7343000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 7343000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 7343000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 168314 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 168314 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 168314 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 168314 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 168314 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 168314 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002175 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002175 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002175 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002175 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002175 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002175 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 20062.841530 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 20062.841530 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 20062.841530 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 20062.841530 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 20062.841530 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 20062.841530 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -795,94 +795,94 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 366 system.cpu3.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 366 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4547000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4547000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4547000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4547000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4547000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4547000 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002127 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002127 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002127 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002127 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002127 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002127 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12423.497268 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12423.497268 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12423.497268 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12423.497268 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12423.497268 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12423.497268 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6611000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 6611000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6611000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 6611000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6611000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 6611000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002175 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002175 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002175 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002175 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002175 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002175 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 18062.841530 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 18062.841530 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 18062.841530 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 18062.841530 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 18062.841530 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 18062.841530 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 0 # number of replacements -system.cpu3.dcache.tagsinuse 25.850163 # Cycle average of tags in use -system.cpu3.dcache.total_refs 25744 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 858.133333 # Average number of references to valid blocks. +system.cpu3.dcache.tagsinuse 27.713697 # Cycle average of tags in use +system.cpu3.dcache.total_refs 24536 # Total number of references to valid blocks. +system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.avg_refs 846.068966 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 25.850163 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.050489 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.050489 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 41084 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41084 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 11491 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 11491 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 52575 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 52575 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 52575 # number of overall hits -system.cpu3.dcache.overall_hits::total 52575 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 176 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 176 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 59 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 59 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 281 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 281 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 281 # number of overall misses -system.cpu3.dcache.overall_misses::total 281 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4401000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 4401000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1861000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 1861000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 928000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 928000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 6262000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 6262000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 6262000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 6262000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41260 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41260 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 11596 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 11596 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 52856 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 52856 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 52856 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 52856 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004266 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.004266 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.009055 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.009055 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830986 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.830986 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005316 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.005316 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005316 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.005316 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 25005.681818 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 25005.681818 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 17723.809524 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 17723.809524 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 15728.813559 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 15728.813559 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 22284.697509 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 22284.697509 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 22284.697509 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 22284.697509 # average overall miss latency +system.cpu3.dcache.occ_blocks::cpu3.data 27.713697 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.054128 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.054128 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 39885 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 39885 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 10974 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 10974 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 50859 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 50859 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 50859 # number of overall hits +system.cpu3.dcache.overall_hits::total 50859 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 172 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 172 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 104 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 104 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 276 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 276 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 276 # number of overall misses +system.cpu3.dcache.overall_misses::total 276 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3405000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 3405000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1971500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 1971500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 653500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 653500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 5376500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 5376500 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 5376500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 5376500 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 40057 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 40057 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 11078 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 11078 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 69 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 51135 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 51135 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 51135 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 51135 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004294 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.004294 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.009388 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.009388 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.797101 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.797101 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005397 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.005397 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005397 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.005397 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 19796.511628 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 19796.511628 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18956.730769 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 18956.730769 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 11881.818182 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 11881.818182 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 19480.072464 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 19480.072464 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 19480.072464 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 19480.072464 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -891,80 +891,80 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 176 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 59 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 281 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 281 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 281 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 3873000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 3873000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1546000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1546000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 751000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 751000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 5419000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 5419000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 5419000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 5419000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004266 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004266 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.009055 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.009055 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830986 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.830986 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005316 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.005316 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005316 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.005316 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 22005.681818 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 22005.681818 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14723.809524 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14723.809524 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 12728.813559 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 12728.813559 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 19284.697509 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 19284.697509 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 19284.697509 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 19284.697509 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 172 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 104 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 55 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 276 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 276 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 276 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 3061000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 3061000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1763500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1763500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 543500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 543500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4824500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 4824500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4824500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 4824500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004294 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004294 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.009388 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.009388 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.797101 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.797101 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005397 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.005397 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005397 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.005397 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17796.511628 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 17796.511628 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16956.730769 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 16956.730769 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 9881.818182 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 9881.818182 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 17480.072464 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 17480.072464 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 17480.072464 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 17480.072464 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 348.825789 # Cycle average of tags in use +system.l2c.tagsinuse 349.154335 # Cycle average of tags in use system.l2c.total_refs 1221 # Total number of references to valid blocks. system.l2c.sampled_refs 429 # Sample count of references to valid blocks. system.l2c.avg_refs 2.846154 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 0.888106 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 231.689332 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 54.189752 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 51.472071 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 6.113701 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1.771073 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.842159 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 1.030424 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.829169 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 0.889459 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 231.842883 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 54.217473 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 6.219466 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 0.812784 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1.917796 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.863537 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 46.262373 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 6.128563 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.003535 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.003538 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.000785 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000012 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy system.l2c.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.005323 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000706 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.data 0.000094 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.005328 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 352 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.inst 355 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 306 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.data 3 # number of ReadReq hits system.l2c.ReadReq_hits::total 1221 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits @@ -972,91 +972,91 @@ system.l2c.UpgradeReq_hits::cpu0.data 2 # nu system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 306 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 3 # number of demand (read+write) hits system.l2c.demand_hits::total 1221 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 182 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 300 # number of overall hits -system.l2c.overall_hits::cpu1.data 3 # number of overall hits +system.l2c.overall_hits::cpu1.inst 352 # number of overall hits +system.l2c.overall_hits::cpu1.data 9 # number of overall hits system.l2c.overall_hits::cpu2.inst 355 # number of overall hits system.l2c.overall_hits::cpu2.data 9 # number of overall hits -system.l2c.overall_hits::cpu3.inst 358 # number of overall hits -system.l2c.overall_hits::cpu3.data 9 # number of overall hits +system.l2c.overall_hits::cpu3.inst 306 # number of overall hits +system.l2c.overall_hits::cpu3.data 3 # number of overall hits system.l2c.overall_hits::total 1221 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 14 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 60 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.data 8 # number of ReadReq misses system.l2c.ReadReq_misses::total 449 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 27 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 11 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 86 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 85 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3.data 15 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 8 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 60 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 23 # number of demand (read+write) misses system.l2c.demand_misses::total 591 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.inst 285 # number of overall misses system.l2c.overall_misses::cpu0.data 165 # number of overall misses -system.l2c.overall_misses::cpu1.inst 66 # number of overall misses -system.l2c.overall_misses::cpu1.data 23 # number of overall misses +system.l2c.overall_misses::cpu1.inst 14 # number of overall misses +system.l2c.overall_misses::cpu1.data 16 # number of overall misses system.l2c.overall_misses::cpu2.inst 12 # number of overall misses system.l2c.overall_misses::cpu2.data 16 # number of overall misses -system.l2c.overall_misses::cpu3.inst 8 # number of overall misses -system.l2c.overall_misses::cpu3.data 16 # number of overall misses +system.l2c.overall_misses::cpu3.inst 60 # number of overall misses +system.l2c.overall_misses::cpu3.data 23 # number of overall misses system.l2c.overall_misses::total 591 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 14828000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 3432000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 3308000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 398000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 529000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 95000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 418000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 104000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 23112000 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5148000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 780000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 728000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 728000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7384000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 14828000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 8580000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 3308000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1178000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 529000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 823000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 418000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 832000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 30496000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 14828000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 8580000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 3308000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1178000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 529000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 823000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 418000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 832000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 30496000 # number of overall miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 14917500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 3451000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 697500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 100000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 601000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 104500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 3071500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.data 410000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 23353000 # number of ReadReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5169500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 736000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 737500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 793500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7436500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 14917500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 8620500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 697500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 836000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 601000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 842000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 3071500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 1203500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 30789500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 14917500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 8620500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 697500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 836000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 601000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 842000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 3071500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 1203500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 30789500 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) @@ -1069,47 +1069,47 @@ system.l2c.ReadReq_accesses::total 1670 # nu system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 27 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 11 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 88 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 87 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 15 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.inst 367 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.inst 366 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 26 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.inst 367 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.inst 366 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 26 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.727273 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.inst 0.032698 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.data 0.181818 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.021858 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.163934 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.727273 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.268862 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.977273 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.977011 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses @@ -1117,54 +1117,54 @@ system.l2c.ReadExReq_miss_rate::cpu3.data 1 # m system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.038251 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.640000 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.inst 0.032698 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.021858 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.163934 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.884615 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.326159 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.038251 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.640000 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.inst 0.032698 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.021858 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.163934 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.884615 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.326159 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52028.070175 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 50121.212121 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 49750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 44083.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 47500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 52250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.data 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 51474.387528 # average ReadReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52000 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52000 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52000 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52028.070175 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 50121.212121 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 51217.391304 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 44083.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 51437.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 52250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 51600.676819 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52028.070175 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 50121.212121 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 51217.391304 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 44083.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 51437.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 52250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 51600.676819 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52342.105263 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52287.878788 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49821.428571 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 50000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 50083.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 52250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51191.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.data 51250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52011.135857 # average ReadReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52217.171717 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52571.428571 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52678.571429 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52900 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52369.718310 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52342.105263 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52245.454545 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 49821.428571 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 50083.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 52625 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 51191.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 52326.086957 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52097.292724 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52342.105263 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52245.454545 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 49821.428571 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 50083.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 52625 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 51191.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 52326.086957 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52097.292724 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1175,107 +1175,110 @@ system.l2c.fast_writes 0 # nu system.l2c.cache_copies 0 # number of cache copies performed system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.inst 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.data 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3.inst 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3.data 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 19 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.data 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.inst 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.inst 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 19 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.inst 285 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.data 66 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 59 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.inst 8 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.data 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 7 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 9 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.inst 53 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.data 7 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 20 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 27 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 11 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 86 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 18 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 20 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 85 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 15 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 14 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu2.data 14 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3.data 15 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 59 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 22 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 15 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.inst 8 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.data 16 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 7 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 15 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 9 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 16 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 53 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.data 22 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 59 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 22 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 15 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.inst 8 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.data 16 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 7 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 15 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 9 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 16 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 53 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.data 22 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11408000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11406500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.data 2640000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2360000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 280000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 80000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 322000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.data 80000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 17210000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 800000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 1080000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 440000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 3440000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 282500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 40000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 360000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 80000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 2120000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.data 280000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 17209000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1124491 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 722495 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 800000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 761996 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 3408982 # number of UpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3960000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 600000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 560000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5680000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 11408000 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 565000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 566500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 609500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5701000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 11406500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.data 6600000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 2360000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 880000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 600000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 322000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 640000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 22890000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 11408000 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 282500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 605000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 360000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 646500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 2120000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 889500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 22910000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 11406500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.data 6600000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 2360000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 880000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 600000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 322000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 640000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 22890000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 282500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 605000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 360000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 646500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 2120000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 889500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 22910000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005450 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.021858 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.024523 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.144809 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.636364 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.977273 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.977011 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses @@ -1283,59 +1286,59 @@ system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005450 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.021858 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024523 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.144809 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.846154 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005450 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.021858 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024523 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.144809 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.846154 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40028.070175 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40023.255814 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.930233 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40160.392857 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40138.611111 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40105.052632 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40105.670588 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40028.070175 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40357.142857 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40464.285714 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40633.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40147.887324 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40333.333333 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40017.482517 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40028.070175 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40406.250000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40431.818182 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40052.447552 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40333.333333 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40017.482517 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40406.250000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40431.818182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40052.447552 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index e04fdea8a..0a4a4cf1a 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,633 +1,633 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000757 # Number of seconds simulated -sim_ticks 757091500 # Number of ticks simulated -final_tick 757091500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000761 # Number of seconds simulated +sim_ticks 761298000 # Number of ticks simulated +final_tick 761298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 129668365 # Simulator tick rate (ticks/s) -host_mem_usage 347944 # Number of bytes of host memory used -host_seconds 5.84 # Real time elapsed on the host -system.physmem.bytes_read::cpu0 90255 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 89097 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 89397 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 87447 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 92253 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 92127 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 87941 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 90122 # Number of bytes read from this memory -system.physmem.bytes_read::total 718639 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 466688 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5395 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5319 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5314 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5343 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5295 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5581 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5197 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5320 # Number of bytes written to this memory -system.physmem.bytes_written::total 509452 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10977 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11088 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11217 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11361 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11298 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11018 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11057 # Number of read requests responded to by this memory -system.physmem.num_reads::total 89080 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 7292 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5395 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5319 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5314 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5343 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5295 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5581 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5197 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5320 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50056 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 119212803 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 117683265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 118079519 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 115503872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 121851850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 121685424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 116156369 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 119037131 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 949210234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 616422189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 7125955 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 7025571 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 7018967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 7057271 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 6993871 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 7371632 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 6864428 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 7026892 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 672906775 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 616422189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 126338758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 124708836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 125098485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 122561144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 128845721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 129057056 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 123020797 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 126064023 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1622117010 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 15543 # number of replacements -system.l2c.tagsinuse 804.498263 # Cycle average of tags in use -system.l2c.total_refs 151705 # Total number of references to valid blocks. -system.l2c.sampled_refs 16364 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.270655 # Average number of references to valid blocks. +host_tick_rate 219241825 # Simulator tick rate (ticks/s) +host_mem_usage 341324 # Number of bytes of host memory used +host_seconds 3.47 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 89717 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 92471 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 92156 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 88405 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 90559 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 92920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 90802 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 90403 # Number of bytes read from this memory +system.physmem.bytes_read::total 727433 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 479872 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5444 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5306 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5518 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5318 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5329 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5364 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5370 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5377 # Number of bytes written to this memory +system.physmem.bytes_written::total 522898 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11345 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11075 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11201 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11041 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11368 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11335 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11107 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11275 # Number of read requests responded to by this memory +system.physmem.num_reads::total 89747 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 7498 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5444 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5306 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5518 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5318 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5329 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5364 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5370 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5377 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50524 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 117847413 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 121464919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 121051152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 116124041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 118953419 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 122054701 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 119272611 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 118748506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 955516762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 630333982 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 7150945 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 6969675 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 7248147 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 6985438 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 6999887 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 7045861 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 7053742 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 7062937 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 686850616 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 630333982 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 124998358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 128434595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 128299299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 123109479 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 125953306 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 129100562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 126326353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 125811443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1642367378 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 15728 # number of replacements +system.l2c.tagsinuse 804.643799 # Cycle average of tags in use +system.l2c.total_refs 152339 # Total number of references to valid blocks. +system.l2c.sampled_refs 16530 # Sample count of references to valid blocks. +system.l2c.avg_refs 9.215910 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 743.034079 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0 7.652510 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1 7.207345 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2 7.804802 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3 7.584993 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu4 7.883519 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu5 7.822009 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu6 7.314161 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu7 8.194845 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.725619 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0 0.007473 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1 0.007038 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2 0.007622 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3 0.007407 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu4 0.007699 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu5 0.007639 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu6 0.007143 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu7 0.008003 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.785643 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0 10656 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10576 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10855 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10944 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10856 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10997 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10762 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10884 # number of ReadReq hits -system.l2c.ReadReq_hits::total 86530 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 77152 # number of Writeback hits -system.l2c.Writeback_hits::total 77152 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 335 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 345 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 353 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 387 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 361 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 367 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 340 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 332 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2820 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 2056 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 2082 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 2008 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 2098 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 2081 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 2029 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 2020 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 2069 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 16443 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12712 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12658 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12863 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 13042 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12937 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 13026 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12782 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12953 # number of demand (read+write) hits -system.l2c.demand_hits::total 102973 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12712 # number of overall hits -system.l2c.overall_hits::cpu1 12658 # number of overall hits -system.l2c.overall_hits::cpu2 12863 # number of overall hits -system.l2c.overall_hits::cpu3 13042 # number of overall hits -system.l2c.overall_hits::cpu4 12937 # number of overall hits -system.l2c.overall_hits::cpu5 13026 # number of overall hits -system.l2c.overall_hits::cpu6 12782 # number of overall hits -system.l2c.overall_hits::cpu7 12953 # number of overall hits -system.l2c.overall_hits::total 102973 # number of overall hits -system.l2c.ReadReq_misses::cpu0 825 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 783 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 805 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 784 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 818 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 847 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 802 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 828 # number of ReadReq misses -system.l2c.ReadReq_misses::total 6492 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1871 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1835 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1867 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1892 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1828 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1835 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1851 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1876 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 14855 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4261 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4189 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4229 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4314 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4275 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4251 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4117 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4314 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 33950 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5086 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 4972 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5034 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5098 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5093 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5098 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 4919 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5142 # number of demand (read+write) misses -system.l2c.demand_misses::total 40442 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5086 # number of overall misses -system.l2c.overall_misses::cpu1 4972 # number of overall misses -system.l2c.overall_misses::cpu2 5034 # number of overall misses -system.l2c.overall_misses::cpu3 5098 # number of overall misses -system.l2c.overall_misses::cpu4 5093 # number of overall misses -system.l2c.overall_misses::cpu5 5098 # number of overall misses -system.l2c.overall_misses::cpu6 4919 # number of overall misses -system.l2c.overall_misses::cpu7 5142 # number of overall misses -system.l2c.overall_misses::total 40442 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 68189898 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 66156919 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 68642411 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 68279416 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 69618906 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 72771903 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 69510913 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 75078411 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 558248777 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 55439380 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 51556398 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 53772873 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 56810367 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 54586881 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 52940893 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 52708899 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 53996365 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 431812056 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 243093964 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 240130019 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 242345503 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 242765011 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 244393485 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 241342993 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 234214460 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 244073518 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1932358953 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 311283862 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 306286938 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 310987914 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 311044427 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 314012391 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 314114896 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 303725373 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 319151929 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2490607730 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 311283862 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 306286938 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 310987914 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 311044427 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 314012391 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 314114896 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 303725373 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 319151929 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2490607730 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0 11481 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1 11359 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2 11660 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3 11728 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu4 11674 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu5 11844 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu6 11564 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu7 11712 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 93022 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 77152 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 77152 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2206 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2180 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2220 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2279 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2189 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2202 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2191 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2208 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 17675 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6317 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6271 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6237 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6412 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6356 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6280 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6137 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6383 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50393 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17798 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17630 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17897 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 18140 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 18030 # number of demand (read+write) accesses +system.l2c.occ_blocks::writebacks 741.658747 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0 7.524103 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1 7.613306 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2 7.692083 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3 7.940636 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu4 7.758878 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu5 8.184629 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu6 8.593994 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu7 7.677424 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.724276 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0 0.007348 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1 0.007435 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2 0.007512 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3 0.007755 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu4 0.007577 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu5 0.007993 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu6 0.008393 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu7 0.007497 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.785785 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0 11015 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10772 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10969 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10679 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10886 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10950 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10937 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10991 # number of ReadReq hits +system.l2c.ReadReq_hits::total 87199 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 77421 # number of Writeback hits +system.l2c.Writeback_hits::total 77421 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 343 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 333 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 352 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 370 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 362 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 336 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 391 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 398 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2885 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 2096 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 2090 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 2017 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 2119 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 2028 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 2062 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 2112 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 2055 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 16579 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 13111 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12862 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12986 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12798 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12914 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 13012 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 13049 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 13046 # number of demand (read+write) hits +system.l2c.demand_hits::total 103778 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 13111 # number of overall hits +system.l2c.overall_hits::cpu1 12862 # number of overall hits +system.l2c.overall_hits::cpu2 12986 # number of overall hits +system.l2c.overall_hits::cpu3 12798 # number of overall hits +system.l2c.overall_hits::cpu4 12914 # number of overall hits +system.l2c.overall_hits::cpu5 13012 # number of overall hits +system.l2c.overall_hits::cpu6 13049 # number of overall hits +system.l2c.overall_hits::cpu7 13046 # number of overall hits +system.l2c.overall_hits::total 103778 # number of overall hits +system.l2c.ReadReq_misses::cpu0 811 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 850 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 841 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 797 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 822 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 866 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 868 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 801 # number of ReadReq misses +system.l2c.ReadReq_misses::total 6656 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1904 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1786 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1883 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1815 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1890 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1852 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1884 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1828 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 14842 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4339 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4322 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4349 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4270 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4225 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4246 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4116 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4276 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 34143 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5150 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5172 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5190 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5067 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5047 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5112 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 4984 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5077 # number of demand (read+write) misses +system.l2c.demand_misses::total 40799 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5150 # number of overall misses +system.l2c.overall_misses::cpu1 5172 # number of overall misses +system.l2c.overall_misses::cpu2 5190 # number of overall misses +system.l2c.overall_misses::cpu3 5067 # number of overall misses +system.l2c.overall_misses::cpu4 5047 # number of overall misses +system.l2c.overall_misses::cpu5 5112 # number of overall misses +system.l2c.overall_misses::cpu6 4984 # number of overall misses +system.l2c.overall_misses::cpu7 5077 # number of overall misses +system.l2c.overall_misses::total 40799 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 67585481 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 72673967 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 72507473 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 67900486 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 70984967 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 72621982 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 74019971 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 71889473 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 570183800 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 54932462 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 51505961 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 54811454 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 53694953 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 54685961 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 53053446 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 55065452 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 53902466 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 431652155 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 247942331 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 244706822 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 247942337 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 243863836 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 241149827 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 241354363 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 234845330 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 242655342 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1944460188 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 315527812 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 317380789 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 320449810 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 311764322 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 312134794 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 313976345 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 308865301 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 314544815 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2514643988 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 315527812 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 317380789 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 320449810 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 311764322 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 312134794 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 313976345 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 308865301 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 314544815 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2514643988 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11826 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11622 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11810 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11476 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11708 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11816 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11805 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11792 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 93855 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 77421 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 77421 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2247 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2119 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2235 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2185 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2252 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2188 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2275 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2226 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 17727 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6435 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6412 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6366 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6389 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6253 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6308 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6228 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6331 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50722 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 18261 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18034 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18176 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17865 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17961 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu5 18124 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17701 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 18095 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 143415 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17798 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17630 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17897 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 18140 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 18030 # number of overall (read+write) accesses +system.l2c.demand_accesses::cpu6 18033 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18123 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 144577 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 18261 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 18034 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18176 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17865 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17961 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu5 18124 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17701 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 18095 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 143415 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.071858 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.068932 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.069039 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.066849 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.070070 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.071513 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.069353 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.070697 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.069790 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.848141 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.841743 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.840991 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.830189 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.835085 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.833333 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.844820 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.849638 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.840453 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.674529 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.667996 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.678050 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.672801 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.672593 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.676911 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.670849 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.675858 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.673705 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.285762 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.282019 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.281276 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.281036 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.282474 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.281284 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.277894 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.284167 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.281993 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.285762 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.282019 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.281276 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.281036 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.282474 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.281284 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.277894 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.284167 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.281993 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 82654.421818 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 84491.595147 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 85270.075776 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 87091.091837 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 85108.687042 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 85917.240850 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 86671.961347 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 90674.409420 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 85990.261399 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 29630.881881 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 28096.129700 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 28801.753080 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 30026.621036 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 29861.532276 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28850.622888 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 28475.904376 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 28782.710554 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29068.465567 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 57050.918564 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 57323.948198 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 57305.628517 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 56273.762401 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 57168.066667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 56773.228182 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 56889.594365 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 56577.078813 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 56917.789485 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 61204.062525 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 61602.360821 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 61777.495828 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 61013.030012 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 61655.682505 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 61615.318949 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 61745.349258 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 62067.664138 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 61584.682508 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 61204.062525 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 61602.360821 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 61777.495828 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 61013.030012 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 61655.682505 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 61615.318949 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 61745.349258 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 62067.664138 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 61584.682508 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 323471 # number of cycles access was blocked +system.l2c.overall_accesses::cpu6 18033 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18123 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 144577 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.068578 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.073137 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.071211 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.069449 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.070208 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.073290 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.073528 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.067927 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.070918 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.847352 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.842850 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.842506 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.830664 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.839254 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.846435 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.828132 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.821204 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.837254 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.674281 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.674049 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.683161 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.668336 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.675676 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.673114 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.660886 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.675407 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.673140 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.282022 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.286792 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.285541 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.283627 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.280998 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.282057 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.276382 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.280141 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.282196 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.282022 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.286792 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.285541 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.283627 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.280998 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.282057 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.276382 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.280141 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.282196 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 83335.981504 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 85498.784706 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 86215.782402 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 85195.089084 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 86356.407543 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 83859.101617 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 85276.464286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 89749.654182 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 85664.633413 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 28851.082983 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 28838.723964 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 29108.578864 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 29583.996143 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28934.370899 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 28646.569114 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 29227.946921 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 29487.125821 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29083.152877 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 57142.735884 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 56618.885238 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 57011.344447 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 57110.968618 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 57076.882130 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 56842.760951 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 57056.688533 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 56748.209074 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 56950.478517 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 61267.536311 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 61365.195089 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 61743.701349 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 61528.384054 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 61845.610065 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 61419.472809 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 61971.368579 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 61954.858184 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 61634.941739 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 61267.536311 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 61365.195089 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 61743.701349 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 61528.384054 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 61845.610065 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 61419.472809 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 61971.368579 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 61954.858184 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 61634.941739 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 618 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 94 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 3441.180851 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 6.574468 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 7293 # number of writebacks -system.l2c.writebacks::total 7293 # number of writebacks +system.l2c.writebacks::writebacks 7498 # number of writebacks +system.l2c.writebacks::total 7498 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 1 # number of UpgradeReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 11 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu0 2 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu0 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 3 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 31 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 34 # number of ReadExReq MSHR hits system.l2c.demand_mshr_hits::cpu0 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 96 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 19 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 98 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 16 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 96 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 818 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 774 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 794 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 778 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 810 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 838 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 793 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 822 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 6427 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1871 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1835 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1867 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1892 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1828 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1835 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1850 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1876 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 14854 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4256 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4182 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4226 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4311 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4274 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4247 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4111 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4312 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 33919 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5074 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 4956 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5020 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5089 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5084 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5085 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 4904 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5134 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40346 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5074 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 4956 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5020 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5089 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5084 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5085 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 4904 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5134 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40346 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 57681466 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 55801476 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 58516973 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 58678465 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 58920974 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 61933964 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 58878980 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 64759967 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 475172265 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 77326932 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 75430964 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 76820936 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 77936944 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 75295947 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 75638458 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 76288450 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 77210443 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 611949074 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 190865870 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 188480880 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 190796375 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 190236368 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 192397382 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 189567870 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 183778356 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 191626863 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1517749964 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 248547336 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 244282356 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 249313348 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 248914833 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 251318356 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 251501834 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 242657336 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 256386830 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1992922229 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 248547336 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 244282356 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 249313348 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 248914833 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 251318356 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 251501834 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 242657336 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 256386830 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1992922229 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 413458717 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 411792191 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 414319722 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 423127681 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 423239170 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 421136201 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 414540172 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 411527705 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3333141559 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 232000375 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 229604409 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 230860874 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 229140383 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 229719408 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 244869353 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 226374384 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 231941380 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1854510566 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 645459092 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 641396600 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 645180596 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 652268064 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 652958578 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 666005554 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 640914556 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 643469085 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5187652125 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.071248 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.068140 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.068096 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.066337 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.069385 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.070753 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.068575 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.070184 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.069091 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.848141 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.841743 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.840991 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.830189 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.835085 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.833333 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.844363 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.849638 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.840396 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.673738 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.666879 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.677569 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.672333 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.672435 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.676274 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.669871 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.675544 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.673090 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.285088 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.281112 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.280494 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.280540 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.281974 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.280567 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.277046 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.283725 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.281323 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.285088 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.281112 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.280494 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.280540 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.281974 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.280567 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.277046 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.283725 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.281323 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 70515.239609 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 72094.930233 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 73698.958438 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 75422.191517 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 72741.943210 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 73906.878282 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 74248.398487 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 78783.414842 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 73933.758363 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41329.199359 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41106.792371 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41146.725228 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41192.887949 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41190.342998 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41219.868120 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41237 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41156.952559 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41197.594857 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 44846.304041 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 45069.555237 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 45148.219356 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44128.129900 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 45015.765559 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44635.712267 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44704.051569 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44440.367115 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 44746.306318 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 48984.496650 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 49290.225182 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 49664.013546 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 48912.327176 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 49433.193548 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 49459.554376 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 49481.512235 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 49939.000779 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 49395.782209 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 48984.496650 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 49290.225182 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 49664.013546 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 48912.327176 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 49433.193548 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 49459.554376 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 49481.512235 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 49939.000779 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 49395.782209 # average overall mshr miss latency +system.l2c.overall_mshr_hits::cpu1 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 19 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 98 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 804 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 843 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 831 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 788 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 815 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 856 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 857 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 798 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 6592 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1902 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1786 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1883 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1815 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1889 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1852 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1884 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1828 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 14839 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4334 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4318 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4340 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4265 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4222 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4242 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4116 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4272 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34109 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5138 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5161 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5171 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5053 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5037 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5098 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 4973 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5070 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40701 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5138 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5161 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5171 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5053 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5037 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5098 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 4973 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5070 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40701 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 57455481 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 61467468 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 61812473 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 57960486 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 60571467 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 61211482 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 62615971 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 61885973 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 484980801 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 78471422 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 73680432 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 77692433 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 74790419 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 77910437 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 76253912 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 77720922 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 75415430 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 611935407 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 195176331 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 192089822 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 194667337 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 191905836 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 189907827 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 189746863 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 184982830 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 190582842 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1529059688 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 252631812 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 253557290 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 256479810 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 249866322 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 250479294 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 250958345 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 247598801 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 252468815 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2014040489 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 252631812 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 253557290 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 256479810 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 249866322 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 250479294 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 250958345 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 247598801 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 252468815 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2014040489 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 426624598 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 414248119 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 417125081 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 415481622 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 425535608 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 422832619 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 413879620 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 421948093 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3357675360 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 234914484 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 229533990 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 238126486 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 230756493 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 230060497 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 233129489 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 235046492 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 235339481 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1866907412 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 661539082 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 643782109 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 655251567 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 646238115 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 655596105 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 655962108 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 648926112 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 657287574 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5224582772 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.067986 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.072535 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.070364 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.068665 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.069611 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.072444 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.072596 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.067673 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.070236 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.846462 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.842850 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.842506 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.830664 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.838810 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.846435 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.828132 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.821204 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.837085 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.673504 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.673425 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.681747 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.667554 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.675196 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.672479 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.660886 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.674775 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.672470 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.281365 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.286182 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.284496 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.282844 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.280441 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.281284 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.275772 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.279755 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.281518 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.281365 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.286182 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.284496 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.282844 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.280441 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.281284 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.275772 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.279755 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.281518 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 71462.041045 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 72915.145907 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 74383.240674 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 73553.916244 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 74320.818405 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 71508.740654 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 73064.143524 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 77551.344612 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 73571.116657 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41257.319664 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41254.441209 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41259.921933 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41206.842424 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41244.275807 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41173.818575 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41253.143312 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41255.705689 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41238.318418 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 45033.763498 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 44485.831867 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44854.225115 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44995.506682 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 44980.536949 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44730.519331 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44942.378523 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44612.088483 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 44828.628456 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 49169.289996 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 49129.488471 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 49599.653839 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 49449.103899 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 49727.872543 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 49226.823264 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 49788.618741 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 49796.610454 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 49483.808481 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 49169.289996 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 49129.488471 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 49599.653839 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 49449.103899 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 49727.872543 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 49226.823264 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 49788.618741 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 49796.610454 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 49483.808481 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -656,114 +656,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.num_reads 98965 # number of read accesses completed -system.cpu0.num_writes 53188 # number of write accesses completed +system.cpu0.num_reads 99935 # number of read accesses completed +system.cpu0.num_writes 53927 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.replacements 22322 # number of replacements -system.cpu0.l1c.tagsinuse 389.061969 # Cycle average of tags in use -system.cpu0.l1c.total_refs 13312 # Total number of references to valid blocks. -system.cpu0.l1c.sampled_refs 22723 # Sample count of references to valid blocks. -system.cpu0.l1c.avg_refs 0.585838 # Average number of references to valid blocks. +system.cpu0.l1c.replacements 22552 # number of replacements +system.cpu0.l1c.tagsinuse 390.299440 # Cycle average of tags in use +system.cpu0.l1c.total_refs 13259 # Total number of references to valid blocks. +system.cpu0.l1c.sampled_refs 22978 # Sample count of references to valid blocks. +system.cpu0.l1c.avg_refs 0.577030 # Average number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::cpu0 389.061969 # Average occupied blocks per requestor -system.cpu0.l1c.occ_percent::cpu0 0.759887 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::total 0.759887 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits::cpu0 8733 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8733 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1107 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1107 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9840 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9840 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9840 # number of overall hits -system.cpu0.l1c.overall_hits::total 9840 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 35619 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 35619 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23007 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23007 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 58626 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 58626 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 58626 # number of overall misses -system.cpu0.l1c.overall_misses::total 58626 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 4549553769 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 4549553769 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 3145624806 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 3145624806 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 7695178575 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 7695178575 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 7695178575 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 7695178575 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44352 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44352 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24114 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24114 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 68466 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 68466 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 68466 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 68466 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.803098 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.803098 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954093 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.954093 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.856279 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.856279 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.856279 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.856279 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 127728.284595 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 127728.284595 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 136724.684053 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 136724.684053 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 131258.802835 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 131258.802835 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 131258.802835 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 131258.802835 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 714656307 # number of cycles access was blocked +system.cpu0.l1c.occ_blocks::cpu0 390.299440 # Average occupied blocks per requestor +system.cpu0.l1c.occ_percent::cpu0 0.762304 # Average percentage of cache occupancy +system.cpu0.l1c.occ_percent::total 0.762304 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 8650 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8650 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1121 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1121 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9771 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9771 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9771 # number of overall hits +system.cpu0.l1c.overall_hits::total 9771 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36111 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36111 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23070 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23070 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 59181 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 59181 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 59181 # number of overall misses +system.cpu0.l1c.overall_misses::total 59181 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 4619304150 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 4619304150 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 3123415012 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 3123415012 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 7742719162 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 7742719162 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 7742719162 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 7742719162 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44761 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44761 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24191 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24191 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 68952 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 68952 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 68952 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 68952 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.806751 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.806751 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953660 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.953660 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.858293 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.858293 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.858293 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.858293 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 127919.585445 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 127919.585445 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 135388.600433 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 135388.600433 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 130831.164766 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 130831.164766 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 130831.164766 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 130831.164766 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1413270 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 63701 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 64534 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11218.918180 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.899619 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9780 # number of writebacks -system.cpu0.l1c.writebacks::total 9780 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35619 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 35619 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23007 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23007 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 58626 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 58626 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 58626 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 58626 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 4478007425 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 4478007425 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 3099554441 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 3099554441 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 7577561866 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 7577561866 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 7577561866 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 7577561866 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1380411824 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1380411824 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 995386324 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 995386324 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2375798148 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2375798148 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.803098 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.803098 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954093 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954093 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.856279 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.856279 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.856279 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.856279 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 125719.627867 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 125719.627867 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 134722.234146 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 134722.234146 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 129252.581892 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 129252.581892 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 129252.581892 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 129252.581892 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9856 # number of writebacks +system.cpu0.l1c.writebacks::total 9856 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36111 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36111 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23070 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23070 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 59181 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 59181 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 59181 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 59181 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 4547088150 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 4547088150 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 3077287012 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 3077287012 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 7624375162 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 7624375162 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 7624375162 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 7624375162 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1436864073 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1436864073 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 955697316 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 955697316 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2392561389 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2392561389 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.806751 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.806751 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953660 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953660 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858293 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.858293 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858293 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.858293 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 125919.751599 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 125919.751599 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 133389.120590 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 133389.120590 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 128831.468917 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 128831.468917 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 128831.468917 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 128831.468917 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -771,114 +771,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 97331 # number of read accesses completed -system.cpu1.num_writes 52743 # number of write accesses completed +system.cpu1.num_reads 97805 # number of read accesses completed +system.cpu1.num_writes 52541 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.replacements 21605 # number of replacements -system.cpu1.l1c.tagsinuse 388.260770 # Cycle average of tags in use -system.cpu1.l1c.total_refs 12987 # Total number of references to valid blocks. -system.cpu1.l1c.sampled_refs 21962 # Sample count of references to valid blocks. -system.cpu1.l1c.avg_refs 0.591340 # Average number of references to valid blocks. +system.cpu1.l1c.replacements 21861 # number of replacements +system.cpu1.l1c.tagsinuse 389.546383 # Cycle average of tags in use +system.cpu1.l1c.total_refs 12913 # Total number of references to valid blocks. +system.cpu1.l1c.sampled_refs 22254 # Sample count of references to valid blocks. +system.cpu1.l1c.avg_refs 0.580255 # Average number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::cpu1 388.260770 # Average occupied blocks per requestor -system.cpu1.l1c.occ_percent::cpu1 0.758322 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::total 0.758322 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits::cpu1 8534 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8534 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1058 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1058 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9592 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9592 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9592 # number of overall hits -system.cpu1.l1c.overall_hits::total 9592 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 35254 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 35254 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 22627 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 22627 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 57881 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 57881 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 57881 # number of overall misses -system.cpu1.l1c.overall_misses::total 57881 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 4617875359 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 4617875359 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 3138675137 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 3138675137 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 7756550496 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 7756550496 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 7756550496 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 7756550496 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 43788 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 43788 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 23685 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 23685 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 67473 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 67473 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 67473 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 67473 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805106 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.805106 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.955330 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.955330 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.857839 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.857839 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.857839 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.857839 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 130988.692319 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 130988.692319 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 138713.710921 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 138713.710921 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 134008.577875 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 134008.577875 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 134008.577875 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 134008.577875 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 723339270 # number of cycles access was blocked +system.cpu1.l1c.occ_blocks::cpu1 389.546383 # Average occupied blocks per requestor +system.cpu1.l1c.occ_percent::cpu1 0.760833 # Average percentage of cache occupancy +system.cpu1.l1c.occ_percent::total 0.760833 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 8526 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8526 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1045 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1045 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9571 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9571 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9571 # number of overall hits +system.cpu1.l1c.overall_hits::total 9571 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 35398 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 35398 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 22650 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 22650 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 58048 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 58048 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 58048 # number of overall misses +system.cpu1.l1c.overall_misses::total 58048 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 4577570179 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 4577570179 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 3175338798 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 3175338798 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 7752908977 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 7752908977 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 7752908977 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 7752908977 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 43924 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 43924 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 23695 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 23695 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 67619 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 67619 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 67619 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 67619 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805892 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.805892 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.955898 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.955898 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.858457 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.858457 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.858457 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.858457 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 129317.198119 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 129317.198119 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 140191.558411 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 140191.558411 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 133560.311759 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 133560.311759 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 133560.311759 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 133560.311759 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1404233 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 62977 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 62944 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11485.768932 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 22.309243 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9483 # number of writebacks -system.cpu1.l1c.writebacks::total 9483 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35254 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 35254 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22627 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 22627 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 57881 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 57881 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 57881 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 57881 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 4547061522 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 4547061522 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 3093362268 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 3093362268 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 7640423790 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 7640423790 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 7640423790 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 7640423790 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1364091847 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1364091847 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 932992416 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 932992416 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2297084263 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2297084263 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805106 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805106 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.955330 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.955330 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857839 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.857839 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857839 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.857839 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 128980.017076 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 128980.017076 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 136711.109206 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 136711.109206 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 132002.276913 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 132002.276913 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 132002.276913 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 132002.276913 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9603 # number of writebacks +system.cpu1.l1c.writebacks::total 9603 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35398 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 35398 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22650 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 22650 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 58048 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 58048 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 58048 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 58048 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 4506790179 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 4506790179 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 3130040798 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 3130040798 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 7636830977 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 7636830977 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 7636830977 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 7636830977 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1394209419 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1394209419 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 928511940 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 928511940 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2322721359 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2322721359 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805892 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805892 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.955898 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.955898 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858457 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.858457 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858457 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.858457 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 127317.650121 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 127317.650121 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 138191.646711 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 138191.646711 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 131560.621847 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 131560.621847 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 131560.621847 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 131560.621847 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -886,114 +886,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 98360 # number of read accesses completed -system.cpu2.num_writes 53068 # number of write accesses completed +system.cpu2.num_reads 100000 # number of read accesses completed +system.cpu2.num_writes 54114 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.replacements 22096 # number of replacements -system.cpu2.l1c.tagsinuse 389.724593 # Cycle average of tags in use -system.cpu2.l1c.total_refs 13250 # Total number of references to valid blocks. -system.cpu2.l1c.sampled_refs 22502 # Sample count of references to valid blocks. -system.cpu2.l1c.avg_refs 0.588837 # Average number of references to valid blocks. +system.cpu2.l1c.replacements 22990 # number of replacements +system.cpu2.l1c.tagsinuse 392.060782 # Cycle average of tags in use +system.cpu2.l1c.total_refs 13456 # Total number of references to valid blocks. +system.cpu2.l1c.sampled_refs 23401 # Sample count of references to valid blocks. +system.cpu2.l1c.avg_refs 0.575018 # Average number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::cpu2 389.724593 # Average occupied blocks per requestor -system.cpu2.l1c.occ_percent::cpu2 0.761181 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::total 0.761181 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits::cpu2 8687 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8687 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1121 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1121 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9808 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9808 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9808 # number of overall hits -system.cpu2.l1c.overall_hits::total 9808 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 35624 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 35624 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 22874 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 22874 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 58498 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 58498 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 58498 # number of overall misses -system.cpu2.l1c.overall_misses::total 58498 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 4545456138 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 4545456138 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 3151736803 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 3151736803 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 7697192941 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 7697192941 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 7697192941 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 7697192941 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 44311 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 44311 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 23995 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 23995 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 68306 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 68306 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 68306 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 68306 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.803954 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.803954 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953282 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.953282 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.856411 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.856411 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.856411 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.856411 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 127595.332865 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 127595.332865 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 137786.867317 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 137786.867317 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 131580.446186 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 131580.446186 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 131580.446186 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 131580.446186 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 716129194 # number of cycles access was blocked +system.cpu2.l1c.occ_blocks::cpu2 392.060782 # Average occupied blocks per requestor +system.cpu2.l1c.occ_percent::cpu2 0.765744 # Average percentage of cache occupancy +system.cpu2.l1c.occ_percent::total 0.765744 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 8750 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8750 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1243 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1243 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9993 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9993 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9993 # number of overall hits +system.cpu2.l1c.overall_hits::total 9993 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36203 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36203 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23173 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23173 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 59376 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 59376 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 59376 # number of overall misses +system.cpu2.l1c.overall_misses::total 59376 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 4641358719 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 4641358719 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 3127191782 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 3127191782 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 7768550501 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 7768550501 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 7768550501 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 7768550501 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44953 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44953 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24416 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24416 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 69369 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 69369 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 69369 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 69369 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805352 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805352 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.949091 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.949091 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.855944 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.855944 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.855944 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.855944 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 128203.704638 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 128203.704638 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 134949.802874 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 134949.802874 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 130836.541717 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 130836.541717 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 130836.541717 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 130836.541717 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1392289 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 63633 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 64514 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11254.053620 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.581192 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9686 # number of writebacks -system.cpu2.l1c.writebacks::total 9686 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35624 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 35624 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22874 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 22874 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 58498 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 58498 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 58498 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 58498 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 4473878832 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 4473878832 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 3105924454 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 3105924454 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 7579803286 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 7579803286 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 7579803286 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 7579803286 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1379555288 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1379555288 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 954692892 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 954692892 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2334248180 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2334248180 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.803954 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.803954 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953282 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953282 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.856411 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.856411 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.856411 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.856411 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 125586.088929 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 125586.088929 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 135784.054123 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 135784.054123 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 129573.716811 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 129573.716811 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 129573.716811 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 129573.716811 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9991 # number of writebacks +system.cpu2.l1c.writebacks::total 9991 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36203 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36203 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23173 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23173 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 59376 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 59376 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 59376 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 59376 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 4568956719 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 4568956719 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 3080855782 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 3080855782 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 7649812501 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 7649812501 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 7649812501 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 7649812501 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1362583834 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1362583834 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 971805765 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 971805765 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2334389599 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2334389599 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805352 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805352 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.949091 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.949091 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.855944 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.855944 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.855944 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.855944 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 126203.815126 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 126203.815126 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 132950.234411 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 132950.234411 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 128836.777503 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 128836.777503 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 128836.777503 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 128836.777503 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1001,114 +1001,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 100000 # number of read accesses completed -system.cpu3.num_writes 53600 # number of write accesses completed +system.cpu3.num_reads 98308 # number of read accesses completed +system.cpu3.num_writes 52892 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.replacements 22673 # number of replacements -system.cpu3.l1c.tagsinuse 391.747074 # Cycle average of tags in use -system.cpu3.l1c.total_refs 13403 # Total number of references to valid blocks. -system.cpu3.l1c.sampled_refs 23070 # Sample count of references to valid blocks. -system.cpu3.l1c.avg_refs 0.580971 # Average number of references to valid blocks. +system.cpu3.l1c.replacements 21879 # number of replacements +system.cpu3.l1c.tagsinuse 388.243829 # Cycle average of tags in use +system.cpu3.l1c.total_refs 13269 # Total number of references to valid blocks. +system.cpu3.l1c.sampled_refs 22290 # Sample count of references to valid blocks. +system.cpu3.l1c.avg_refs 0.595289 # Average number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::cpu3 391.747074 # Average occupied blocks per requestor -system.cpu3.l1c.occ_percent::cpu3 0.765131 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::total 0.765131 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits::cpu3 8720 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8720 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1143 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1143 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9863 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9863 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9863 # number of overall hits -system.cpu3.l1c.overall_hits::total 9863 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36203 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36203 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 22978 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 22978 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 59181 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 59181 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 59181 # number of overall misses -system.cpu3.l1c.overall_misses::total 59181 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 4605371729 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 4605371729 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 3121949330 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 3121949330 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 7727321059 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 7727321059 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 7727321059 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 7727321059 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44923 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44923 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24121 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24121 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 69044 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 69044 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 69044 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 69044 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805890 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.805890 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.952614 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.952614 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.857149 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.857149 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.857149 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.857149 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 127209.671270 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 127209.671270 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 135866.887022 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 135866.887022 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 130570.978169 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 130570.978169 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 130570.978169 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 130570.978169 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 721076565 # number of cycles access was blocked +system.cpu3.l1c.occ_blocks::cpu3 388.243829 # Average occupied blocks per requestor +system.cpu3.l1c.occ_percent::cpu3 0.758289 # Average percentage of cache occupancy +system.cpu3.l1c.occ_percent::total 0.758289 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 8771 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8771 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1066 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1066 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9837 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9837 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9837 # number of overall hits +system.cpu3.l1c.overall_hits::total 9837 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 35672 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 35672 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 22858 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 22858 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 58530 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 58530 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 58530 # number of overall misses +system.cpu3.l1c.overall_misses::total 58530 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 4705192371 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 4705192371 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 3092503889 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 3092503889 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 7797696260 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 7797696260 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 7797696260 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 7797696260 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44443 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44443 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 23924 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 23924 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 68367 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 68367 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 68367 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 68367 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.802646 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.802646 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955442 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.955442 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.856115 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.856115 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.856115 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.856115 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 131901.557832 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 131901.557832 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 135291.971695 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 135291.971695 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 133225.632325 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 133225.632325 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 133225.632325 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 133225.632325 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1411864 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 64491 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 63831 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11181.041773 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 22.118782 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9961 # number of writebacks -system.cpu3.l1c.writebacks::total 9961 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36203 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36203 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22978 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 22978 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 59181 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 59181 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 59181 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 59181 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 4532659362 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 4532659362 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 3075925984 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 3075925984 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 7608585346 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 7608585346 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 7608585346 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 7608585346 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1393944138 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1393944138 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 919834390 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 919834390 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2313778528 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2313778528 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805890 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805890 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.952614 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.952614 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.857149 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.857149 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.857149 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.857149 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 125201.208795 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 125201.208795 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 133863.956132 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 133863.956132 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 128564.663422 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 128564.663422 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 128564.663422 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 128564.663422 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9578 # number of writebacks +system.cpu3.l1c.writebacks::total 9578 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35672 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 35672 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22858 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 22858 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 58530 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 58530 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 58530 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 58530 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 4633860371 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 4633860371 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 3046797889 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 3046797889 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 7680658260 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 7680658260 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 7680658260 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 7680658260 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1383140389 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1383140389 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 919277948 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 919277948 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2302418337 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2302418337 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.802646 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.802646 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955442 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955442 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.856115 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.856115 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.856115 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.856115 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 129901.894231 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 129901.894231 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 133292.409178 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 133292.409178 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 131226.008201 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 131226.008201 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 131226.008201 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 131226.008201 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1116,114 +1116,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99186 # number of read accesses completed -system.cpu4.num_writes 53232 # number of write accesses completed +system.cpu4.num_reads 99646 # number of read accesses completed +system.cpu4.num_writes 53184 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.replacements 22556 # number of replacements -system.cpu4.l1c.tagsinuse 391.523203 # Cycle average of tags in use -system.cpu4.l1c.total_refs 13363 # Total number of references to valid blocks. -system.cpu4.l1c.sampled_refs 22976 # Sample count of references to valid blocks. -system.cpu4.l1c.avg_refs 0.581607 # Average number of references to valid blocks. +system.cpu4.l1c.replacements 22486 # number of replacements +system.cpu4.l1c.tagsinuse 389.564427 # Cycle average of tags in use +system.cpu4.l1c.total_refs 13323 # Total number of references to valid blocks. +system.cpu4.l1c.sampled_refs 22871 # Sample count of references to valid blocks. +system.cpu4.l1c.avg_refs 0.582528 # Average number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::cpu4 391.523203 # Average occupied blocks per requestor -system.cpu4.l1c.occ_percent::cpu4 0.764694 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::total 0.764694 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits::cpu4 8704 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8704 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1177 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1177 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9881 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9881 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9881 # number of overall hits -system.cpu4.l1c.overall_hits::total 9881 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 35925 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 35925 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 22955 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 22955 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 58880 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 58880 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 58880 # number of overall misses -system.cpu4.l1c.overall_misses::total 58880 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 4605243494 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 4605243494 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 3106119837 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 3106119837 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 7711363331 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 7711363331 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 7711363331 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 7711363331 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44629 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44629 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24132 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24132 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 68761 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 68761 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 68761 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 68761 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804970 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.804970 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.951227 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.951227 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.856299 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.856299 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.856299 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.856299 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 128190.493918 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 128190.493918 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 135313.432237 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 135313.432237 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 130967.447877 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 130967.447877 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 130967.447877 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 130967.447877 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 718630789 # number of cycles access was blocked +system.cpu4.l1c.occ_blocks::cpu4 389.564427 # Average occupied blocks per requestor +system.cpu4.l1c.occ_percent::cpu4 0.760868 # Average percentage of cache occupancy +system.cpu4.l1c.occ_percent::total 0.760868 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 8662 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8662 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1144 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1144 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9806 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9806 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9806 # number of overall hits +system.cpu4.l1c.overall_hits::total 9806 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36129 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36129 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 22914 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 22914 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 59043 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 59043 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 59043 # number of overall misses +system.cpu4.l1c.overall_misses::total 59043 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 4597368029 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 4597368029 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 3131496490 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 3131496490 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 7728864519 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 7728864519 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 7728864519 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 7728864519 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44791 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44791 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24058 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24058 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 68849 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 68849 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 68849 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 68849 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.806613 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.806613 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952448 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.952448 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.857572 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.857572 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.857572 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.857572 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 127248.692989 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 127248.692989 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 136663.022170 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 136663.022170 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 130902.300340 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 130902.300340 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 130902.300340 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 130902.300340 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1409065 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 64157 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 64552 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 11201.128310 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 21.828371 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9838 # number of writebacks -system.cpu4.l1c.writebacks::total 9838 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35925 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 35925 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22955 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 22955 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 58880 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 58880 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 58880 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 58880 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 4533093127 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 4533093127 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 3060147977 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 3060147977 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 7593241104 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 7593241104 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 7593241104 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 7593241104 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 1402247556 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 1402247556 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 894394941 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 894394941 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2296642497 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2296642497 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804970 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804970 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.951227 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.951227 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.856299 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.856299 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.856299 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.856299 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 126182.132971 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 126182.132971 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 133310.737399 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 133310.737399 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 128961.295924 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 128961.295924 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 128961.295924 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 128961.295924 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9768 # number of writebacks +system.cpu4.l1c.writebacks::total 9768 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36129 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36129 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22914 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 22914 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 59043 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 59043 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 59043 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 59043 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 4525124029 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 4525124029 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 3085672490 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 3085672490 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 7610796519 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 7610796519 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 7610796519 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 7610796519 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 1426221714 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 1426221714 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 886330386 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 886330386 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2312552100 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2312552100 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.806613 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.806613 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952448 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952448 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857572 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.857572 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857572 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.857572 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 125249.080489 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 125249.080489 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 134663.196736 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 134663.196736 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 128902.605203 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 128902.605203 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 128902.605203 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 128902.605203 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1231,114 +1231,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99811 # number of read accesses completed -system.cpu5.num_writes 54122 # number of write accesses completed +system.cpu5.num_reads 99510 # number of read accesses completed +system.cpu5.num_writes 53712 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.replacements 22776 # number of replacements -system.cpu5.l1c.tagsinuse 391.477551 # Cycle average of tags in use -system.cpu5.l1c.total_refs 13322 # Total number of references to valid blocks. -system.cpu5.l1c.sampled_refs 23147 # Sample count of references to valid blocks. -system.cpu5.l1c.avg_refs 0.575539 # Average number of references to valid blocks. +system.cpu5.l1c.replacements 22704 # number of replacements +system.cpu5.l1c.tagsinuse 391.715809 # Cycle average of tags in use +system.cpu5.l1c.total_refs 13238 # Total number of references to valid blocks. +system.cpu5.l1c.sampled_refs 23109 # Sample count of references to valid blocks. +system.cpu5.l1c.avg_refs 0.572850 # Average number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::cpu5 391.477551 # Average occupied blocks per requestor -system.cpu5.l1c.occ_percent::cpu5 0.764605 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::total 0.764605 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits::cpu5 8701 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8701 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1178 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1178 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9879 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9879 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9879 # number of overall hits -system.cpu5.l1c.overall_hits::total 9879 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36192 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36192 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23103 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23103 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 59295 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 59295 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 59295 # number of overall misses -system.cpu5.l1c.overall_misses::total 59295 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 4578113743 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 4578113743 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 3131851801 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 3131851801 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 7709965544 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 7709965544 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 7709965544 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 7709965544 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44893 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44893 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24281 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24281 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 69174 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 69174 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 69174 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 69174 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806184 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.806184 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.951485 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.951485 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.857186 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.857186 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.857186 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.857186 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 126495.185207 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 126495.185207 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 135560.394797 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 135560.394797 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 130027.245872 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 130027.245872 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 130027.245872 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 130027.245872 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 718707273 # number of cycles access was blocked +system.cpu5.l1c.occ_blocks::cpu5 391.715809 # Average occupied blocks per requestor +system.cpu5.l1c.occ_percent::cpu5 0.765070 # Average percentage of cache occupancy +system.cpu5.l1c.occ_percent::total 0.765070 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 8676 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8676 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1153 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1153 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9829 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9829 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9829 # number of overall hits +system.cpu5.l1c.overall_hits::total 9829 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36073 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36073 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23060 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23060 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 59133 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 59133 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 59133 # number of overall misses +system.cpu5.l1c.overall_misses::total 59133 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 4612203646 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 4612203646 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 3154708419 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 3154708419 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 7766912065 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 7766912065 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 7766912065 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 7766912065 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44749 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44749 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24213 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24213 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 68962 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 68962 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 68962 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 68962 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806119 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.806119 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952381 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.952381 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.857472 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.857472 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.857472 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.857472 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 127857.501344 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 127857.501344 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 136804.354683 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 136804.354683 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 131346.491215 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 131346.491215 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 131346.491215 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 131346.491215 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1402922 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 64475 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 64326 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 11147.068988 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.809564 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 10068 # number of writebacks -system.cpu5.l1c.writebacks::total 10068 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36192 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36192 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23103 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23103 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 59295 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 59295 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 59295 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 59295 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 4505401434 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 4505401434 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 3085574966 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 3085574966 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 7590976400 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 7590976400 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 7590976400 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 7590976400 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 1396623229 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 1396623229 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 970059681 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 970059681 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2366682910 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2366682910 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806184 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806184 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.951485 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.951485 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.857186 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.857186 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.857186 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.857186 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 124486.113893 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 124486.113893 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 133557.328745 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 133557.328745 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 128020.514377 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 128020.514377 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 128020.514377 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 128020.514377 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9873 # number of writebacks +system.cpu5.l1c.writebacks::total 9873 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36073 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36073 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23060 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23060 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 59133 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 59133 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 59133 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 59133 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 4540061646 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 4540061646 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 3108604419 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 3108604419 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 7648666065 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 7648666065 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 7648666065 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 7648666065 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 1397826307 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 1397826307 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 952355893 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 952355893 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2350182200 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2350182200 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806119 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806119 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952381 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952381 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.857472 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.857472 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.857472 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.857472 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 125857.612231 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 125857.612231 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 134805.048526 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 134805.048526 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 129346.829435 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 129346.829435 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 129346.829435 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 129346.829435 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1346,114 +1346,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 96701 # number of read accesses completed -system.cpu6.num_writes 52167 # number of write accesses completed +system.cpu6.num_reads 99341 # number of read accesses completed +system.cpu6.num_writes 53460 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.replacements 21524 # number of replacements -system.cpu6.l1c.tagsinuse 387.796217 # Cycle average of tags in use -system.cpu6.l1c.total_refs 12859 # Total number of references to valid blocks. -system.cpu6.l1c.sampled_refs 21936 # Sample count of references to valid blocks. -system.cpu6.l1c.avg_refs 0.586205 # Average number of references to valid blocks. +system.cpu6.l1c.replacements 22728 # number of replacements +system.cpu6.l1c.tagsinuse 391.033952 # Cycle average of tags in use +system.cpu6.l1c.total_refs 13418 # Total number of references to valid blocks. +system.cpu6.l1c.sampled_refs 23126 # Sample count of references to valid blocks. +system.cpu6.l1c.avg_refs 0.580213 # Average number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::cpu6 387.796217 # Average occupied blocks per requestor -system.cpu6.l1c.occ_percent::cpu6 0.757414 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::total 0.757414 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits::cpu6 8329 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8329 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1106 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1106 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9435 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9435 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9435 # number of overall hits -system.cpu6.l1c.overall_hits::total 9435 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 35191 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 35191 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 22544 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 22544 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 57735 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 57735 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 57735 # number of overall misses -system.cpu6.l1c.overall_misses::total 57735 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 4508353371 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 4508353371 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 3154254558 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 3154254558 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 7662607929 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 7662607929 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 7662607929 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 7662607929 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 43520 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 43520 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 23650 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 23650 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 67170 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 67170 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 67170 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 67170 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808617 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.808617 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953235 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.953235 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859536 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859536 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859536 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859536 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 128110.976414 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 128110.976414 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 139915.478974 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 139915.478974 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 132720.324396 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 132720.324396 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 132720.324396 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 132720.324396 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 719066693 # number of cycles access was blocked +system.cpu6.l1c.occ_blocks::cpu6 391.033952 # Average occupied blocks per requestor +system.cpu6.l1c.occ_percent::cpu6 0.763738 # Average percentage of cache occupancy +system.cpu6.l1c.occ_percent::total 0.763738 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 8762 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8762 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1095 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1095 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9857 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9857 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9857 # number of overall hits +system.cpu6.l1c.overall_hits::total 9857 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 35979 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 35979 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23081 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23081 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 59060 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 59060 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 59060 # number of overall misses +system.cpu6.l1c.overall_misses::total 59060 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 4670056241 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 4670056241 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 3140122564 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 3140122564 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 7810178805 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 7810178805 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 7810178805 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 7810178805 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44741 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44741 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24176 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24176 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 68917 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 68917 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 68917 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 68917 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.804162 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.804162 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954707 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954707 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.856973 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.856973 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.856973 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.856973 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 129799.500848 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 129799.500848 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 136047.942637 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 136047.942637 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 132241.429140 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 132241.429140 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 132241.429140 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 132241.429140 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1402385 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 62816 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 64109 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 11447.190095 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 21.875010 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9499 # number of writebacks -system.cpu6.l1c.writebacks::total 9499 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35191 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 35191 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 22544 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 22544 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 57735 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 57735 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 57735 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 57735 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 4437636067 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 4437636067 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 3109111203 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 3109111203 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 7546747270 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 7546747270 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 7546747270 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 7546747270 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 1416513847 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 1416513847 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 907986926 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 907986926 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2324500773 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2324500773 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808617 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808617 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953235 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953235 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859536 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859536 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859536 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859536 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 126101.448296 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 126101.448296 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 137913.023554 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 137913.023554 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 130713.557980 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 130713.557980 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 130713.557980 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 130713.557980 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9866 # number of writebacks +system.cpu6.l1c.writebacks::total 9866 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35979 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 35979 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23081 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23081 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 59060 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 59060 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 59060 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 59060 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 4598108241 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 4598108241 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 3093974564 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 3093974564 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 7692082805 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 7692082805 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 7692082805 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 7692082805 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 1335573448 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 1335573448 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 977750934 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 977750934 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2313324382 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2313324382 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.804162 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.804162 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954707 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954707 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.856973 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.856973 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.856973 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.856973 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 127799.778788 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 127799.778788 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 134048.549196 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 134048.549196 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 130241.835506 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 130241.835506 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 130241.835506 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 130241.835506 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1461,114 +1461,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 98233 # number of read accesses completed -system.cpu7.num_writes 53134 # number of write accesses completed +system.cpu7.num_reads 99191 # number of read accesses completed +system.cpu7.num_writes 53936 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.replacements 22239 # number of replacements -system.cpu7.l1c.tagsinuse 390.077286 # Cycle average of tags in use -system.cpu7.l1c.total_refs 13228 # Total number of references to valid blocks. -system.cpu7.l1c.sampled_refs 22658 # Sample count of references to valid blocks. -system.cpu7.l1c.avg_refs 0.583811 # Average number of references to valid blocks. +system.cpu7.l1c.replacements 22510 # number of replacements +system.cpu7.l1c.tagsinuse 390.052988 # Cycle average of tags in use +system.cpu7.l1c.total_refs 13451 # Total number of references to valid blocks. +system.cpu7.l1c.sampled_refs 22924 # Sample count of references to valid blocks. +system.cpu7.l1c.avg_refs 0.586765 # Average number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::cpu7 390.077286 # Average occupied blocks per requestor -system.cpu7.l1c.occ_percent::cpu7 0.761870 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::total 0.761870 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits::cpu7 8637 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8637 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1096 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1096 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9733 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9733 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9733 # number of overall hits -system.cpu7.l1c.overall_hits::total 9733 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 35699 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 35699 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 22823 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 22823 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 58522 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 58522 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 58522 # number of overall misses -system.cpu7.l1c.overall_misses::total 58522 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 4580220165 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 4580220165 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 3149286383 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 3149286383 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 7729506548 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 7729506548 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 7729506548 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 7729506548 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44336 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44336 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 23919 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 23919 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 68255 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 68255 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 68255 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 68255 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805192 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.805192 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954179 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.954179 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.857402 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.857402 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.857402 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.857402 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 128301.077481 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 128301.077481 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 137987.397932 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 137987.397932 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 132078.646458 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 132078.646458 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 132078.646458 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 132078.646458 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 716139762 # number of cycles access was blocked +system.cpu7.l1c.occ_blocks::cpu7 390.052988 # Average occupied blocks per requestor +system.cpu7.l1c.occ_percent::cpu7 0.761822 # Average percentage of cache occupancy +system.cpu7.l1c.occ_percent::total 0.761822 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 8796 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8796 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1169 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1169 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9965 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9965 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9965 # number of overall hits +system.cpu7.l1c.overall_hits::total 9965 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 35920 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 35920 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23167 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23167 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 59087 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 59087 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 59087 # number of overall misses +system.cpu7.l1c.overall_misses::total 59087 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 4583534857 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 4583534857 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 3157115869 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 3157115869 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 7740650726 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 7740650726 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 7740650726 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 7740650726 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 44716 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 44716 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24336 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24336 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 69052 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 69052 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 69052 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 69052 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.803292 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.803292 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.951964 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.951964 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.855688 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.855688 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.855688 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.855688 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 127603.977088 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 127603.977088 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 136276.422023 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 136276.422023 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 131004.294109 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 131004.294109 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 131004.294109 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 131004.294109 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1403287 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 63505 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 64246 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 11276.903582 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.842403 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9791 # number of writebacks -system.cpu7.l1c.writebacks::total 9791 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35699 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 35699 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22823 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 22823 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 58522 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 58522 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 58522 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 58522 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 4508506825 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 4508506825 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 3103586023 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 3103586023 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 7612092848 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 7612092848 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 7612092848 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 7612092848 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 1364395277 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 1364395277 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 924938405 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 924938405 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2289333682 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2289333682 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805192 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805192 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954179 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954179 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857402 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.857402 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857402 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.857402 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 126292.244181 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 126292.244181 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 135985.016124 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 135985.016124 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 130072.329175 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 130072.329175 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 130072.329175 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 130072.329175 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9883 # number of writebacks +system.cpu7.l1c.writebacks::total 9883 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35920 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 35920 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23167 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23167 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 59087 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 59087 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 59087 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 59087 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 4511708857 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 4511708857 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 3110789869 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 3110789869 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 7622498726 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 7622498726 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 7622498726 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 7622498726 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 1423430289 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 1423430289 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 942416285 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 942416285 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2365846574 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2365846574 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.803292 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.803292 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.951964 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.951964 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.855688 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.855688 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.855688 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.855688 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 125604.366843 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 125604.366843 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 134276.767341 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 134276.767341 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 129004.666441 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 129004.666441 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 129004.666441 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 129004.666441 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency |