133 files changed, 562 insertions, 15 deletions
diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
index fa5ac1725..fa5ac1725 100644
--- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out
index 8744b6907..8744b6907 100644
--- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out
diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt
index 8303336ed..8303336ed 100644
--- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt
diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr
index eb1796ead..eb1796ead 100644
--- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr
diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout
index 9aaca3eeb..9aaca3eeb 100644
--- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
index 841e8766f..841e8766f 100644
--- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out
index b5a24e5fb..b5a24e5fb 100644
--- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt
index b8593d3a3..b8593d3a3 100644
--- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr
index 87866a2a5..87866a2a5 100644
--- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout
index 9aaca3eeb..9aaca3eeb 100644
--- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
index 48a760b08..48a760b08 100644
--- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out
index eddb9ff53..eddb9ff53 100644
--- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt
index 5e7441c54..5e7441c54 100644
--- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr
index 87866a2a5..87866a2a5 100644
--- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout
index 9aaca3eeb..9aaca3eeb 100644
--- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout
diff --git a/tests/long/00.gzip/test.py b/tests/long/00.gzip/test.py
index 06ccb656b..f69914046 100644
--- a/tests/long/00.gzip/test.py
+++ b/tests/long/00.gzip/test.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -29,5 +29,5 @@
 m5.AddToPath('../configs/common')
 from cpu2000 import gzip_log
 
-workload = gzip_log('alpha', 'tru64', 'smred')
+workload = gzip_log(isa, opsys, 'smred')
 root.system.cpu.workload = workload.makeLiveProcess()
diff --git a/tests/long/10.mcf/test.py b/tests/long/10.mcf/test.py
index f545aad3d..ffe2758f1 100644
--- a/tests/long/10.mcf/test.py
+++ b/tests/long/10.mcf/test.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -29,5 +29,5 @@
 m5.AddToPath('../configs/common')
 from cpu2000 import mcf
 
-workload = mcf('alpha', 'tru64', 'lgred')
+workload = mcf(isa, opsys, 'lgred')
 root.system.cpu.workload = workload.makeLiveProcess()
diff --git a/tests/long/20.parser/ref/alpha/linux/NOTE b/tests/long/20.parser/ref/alpha/tru64/NOTE
index 5e7d8c358..5e7d8c358 100644
--- a/tests/long/20.parser/ref/alpha/linux/NOTE
+++ b/tests/long/20.parser/ref/alpha/tru64/NOTE
diff --git a/tests/long/20.parser/test.py b/tests/long/20.parser/test.py
index 8703ae634..82ab71c90 100644
--- a/tests/long/20.parser/test.py
+++ b/tests/long/20.parser/test.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -29,5 +29,5 @@
 m5.AddToPath('../configs/common')
 from cpu2000 import parser
 
-workload = parser('alpha', 'tru64', 'lgred')
+workload = parser(isa, opsys, 'lgred')
 root.system.cpu.workload = workload.makeLiveProcess()
diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
index 915a6967f..915a6967f 100644
--- a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.out b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out
index 80e067401..80e067401 100644
--- a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.out
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out
diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt
index 9d00cb146..9d00cb146 100644
--- a/tests/long/30.eon/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt
diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr
index d414f5cfe..d414f5cfe 100644
--- a/tests/long/30.eon/ref/alpha/linux/o3-timing/stderr
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr
diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout
index 039e2d4ce..039e2d4ce 100644
--- a/tests/long/30.eon/ref/alpha/linux/o3-timing/stdout
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout
diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
index 088cd1a9f..088cd1a9f 100644
--- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out
index bec900d0f..bec900d0f 100644
--- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out
diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt
index a308f5e36..a308f5e36 100644
--- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt
diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr
index 1d6957eca..1d6957eca 100644
--- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr
diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout
index 039e2d4ce..039e2d4ce 100644
--- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout
diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
index 452538e49..452538e49 100644
--- a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out
index 602da9705..602da9705 100644
--- a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out
diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt
index 328856ce7..328856ce7 100644
--- a/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt
diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr
index 8534c55aa..8534c55aa 100644
--- a/tests/long/30.eon/ref/alpha/linux/simple-timing/stderr
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr
diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout
index 039e2d4ce..039e2d4ce 100644
--- a/tests/long/30.eon/ref/alpha/linux/simple-timing/stdout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout
diff --git a/tests/long/30.eon/test.py b/tests/long/30.eon/test.py
index 828b6390c..318da1049 100644
--- a/tests/long/30.eon/test.py
+++ b/tests/long/30.eon/test.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -29,5 +29,5 @@
 m5.AddToPath('../configs/common')
 from cpu2000 import eon_cook
 
-workload = eon_cook('alpha', 'tru64', 'mdred')
+workload = eon_cook(isa, opsys, 'mdred')
 root.system.cpu.workload = workload.makeLiveProcess()
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
index 59c6e25e2..59c6e25e2 100644
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out
index c6e4aa136..c6e4aa136 100644
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt
index 9db3f64bc..9db3f64bc 100644
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr
index bc72461c8..bc72461c8 100644
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout
index d4a078b85..d4a078b85 100644
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index 5f64dcebd..5f64dcebd 100644
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out
index 6998f4828..6998f4828 100644
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
index 45f793ab7..45f793ab7 100644
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr
index bc72461c8..bc72461c8 100644
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout
index d4a078b85..d4a078b85 100644
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout
diff --git a/tests/long/40.perlbmk/test.py b/tests/long/40.perlbmk/test.py
index 2f9dd0ff0..e32416265 100644
--- a/tests/long/40.perlbmk/test.py
+++ b/tests/long/40.perlbmk/test.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -29,5 +29,5 @@
 m5.AddToPath('../configs/common')
 from cpu2000 import perlbmk_makerand
 
-workload = perlbmk_makerand('alpha', 'tru64', 'lgred')
+workload = perlbmk_makerand(isa, opsys, 'lgred')
 root.system.cpu.workload = workload.makeLiveProcess()
diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index cf4e15676..cf4e15676 100644
--- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out
index 52c225902..52c225902 100644
--- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out
diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt
index 3069385f0..3069385f0 100644
--- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt
diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.msg b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg
index 327142d7c..327142d7c 100644
--- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.msg
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg
diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.out b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.out
index 726b45c60..726b45c60 100644
--- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.out
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.out
diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr
index eb1796ead..eb1796ead 100644
--- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr
diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout
index e69de29bb..e69de29bb 100644
--- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index 179e8ea77..179e8ea77 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out
index 725aaed50..725aaed50 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt
index 9c60e1316..9c60e1316 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.msg b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg
index 327142d7c..327142d7c 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.msg
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.out b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.out
index 726b45c60..726b45c60 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.out
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.out
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr
index eb1796ead..eb1796ead 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout
index e69de29bb..e69de29bb 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index 0e1a3c9f1..0e1a3c9f1 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out
index 0dc85858d..0dc85858d 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt
index 9a9778162..9a9778162 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.msg b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg
index 327142d7c..327142d7c 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.msg
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.out b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.out
index 726b45c60..726b45c60 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.out
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.out
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr
index eb1796ead..eb1796ead 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout
index e69de29bb..e69de29bb 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout
diff --git a/tests/long/50.vortex/test.py b/tests/long/50.vortex/test.py
index bd57ef6e6..fbf0dc081 100644
--- a/tests/long/50.vortex/test.py
+++ b/tests/long/50.vortex/test.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -29,5 +29,5 @@
 m5.AddToPath('../configs/common')
 from cpu2000 import vortex
 
-workload = vortex('alpha', 'tru64', 'smred')
+workload = vortex(isa, opsys, 'smred')
 root.system.cpu.workload = workload.makeLiveProcess()
diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index 9ae62655d..9ae62655d 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out
index 690cc5723..690cc5723 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out
diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt
index bc6866525..bc6866525 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt
diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr
index cdd59eda7..cdd59eda7 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr
diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout
index 0c5c00118..0c5c00118 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
index ad57a5293..ad57a5293 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out
index 891519c26..891519c26 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt
index 7422e3ae7..7422e3ae7 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr
index 87866a2a5..87866a2a5 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout
index 0c5c00118..0c5c00118 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index 0a123d4a4..0a123d4a4 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out
index 4692c5d40..4692c5d40 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
index 45b7beb7c..45b7beb7c 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr
index 87866a2a5..87866a2a5 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout
index 0c5c00118..0c5c00118 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout
diff --git a/tests/long/60.bzip2/test.py b/tests/long/60.bzip2/test.py
index 362ca524e..7fa3d1a07 100644
--- a/tests/long/60.bzip2/test.py
+++ b/tests/long/60.bzip2/test.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -29,5 +29,5 @@
 m5.AddToPath('../configs/common')
 from cpu2000 import bzip2_source
 
-workload = bzip2_source('alpha', 'tru64', 'lgred')
+workload = bzip2_source(isa, opsys, 'lgred')
 root.system.cpu.workload = workload.makeLiveProcess()
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 5604f880f..5604f880f 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out
index a78c52d7f..a78c52d7f 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
index c77face31..c77face31 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.out b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out
index 00387ae5c..00387ae5c 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.out
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pin b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pin
index 62b922e4e..62b922e4e 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pin
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pin
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl1 b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1
index bdc569e39..bdc569e39 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl1
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl2 b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2
index 6e2601e82..6e2601e82 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl2
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sav b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sav
index 04c8e9935..04c8e9935 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sav
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sav
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sv2 b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2
index 9dd68ecdb..9dd68ecdb 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sv2
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.twf b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.twf
index a4c2eac35..a4c2eac35 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.twf
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.twf
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr
index eb1796ead..eb1796ead 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
index f32f0a972..f32f0a972 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index 789f77815..789f77815 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out
index b4087eb1c..b4087eb1c 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt
index 2cd5a06bf..2cd5a06bf 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.out b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out
index 00387ae5c..00387ae5c 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.out
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pin b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin
index 62b922e4e..62b922e4e 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pin
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl1 b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1
index bdc569e39..bdc569e39 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl1
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl2 b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2
index 6e2601e82..6e2601e82 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl2
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sav b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav
index 04c8e9935..04c8e9935 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sav
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sv2 b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2
index 9dd68ecdb..9dd68ecdb 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sv2
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.twf b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf
index a4c2eac35..a4c2eac35 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.twf
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr
index eb1796ead..eb1796ead 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout
index f32f0a972..f32f0a972 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index e2265235e..e2265235e 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out
index fcf06c7db..fcf06c7db 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
index 5cdae9c4a..5cdae9c4a 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.out b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out
index 00387ae5c..00387ae5c 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.out
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pin b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pin
index 62b922e4e..62b922e4e 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pin
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pin
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl1 b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1
index bdc569e39..bdc569e39 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl1
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl2 b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2
index 6e2601e82..6e2601e82 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl2
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sav b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sav
index 04c8e9935..04c8e9935 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sav
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sav
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sv2 b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2
index 9dd68ecdb..9dd68ecdb 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sv2
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.twf b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.twf
index a4c2eac35..a4c2eac35 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.twf
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.twf
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr
index eb1796ead..eb1796ead 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
index f32f0a972..f32f0a972 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..2a1613fa1
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -0,0 +1,64 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+simulate_stalls=false
+system=system
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out
new file mode 100644
index 000000000..d24c09793
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out
@@ -0,0 +1,57 @@
+[root]
+type=Root
+dummy=0
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+input=cin
+output=cout
+env=
+cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=AtomicSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+width=1
+function_trace=false
+function_trace_start=0
+simulate_stalls=false
+
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt
new file mode 100644
index 000000000..45fd6b479
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt
@@ -0,0 +1,18 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate                                 676464                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 149916                       # Number of bytes of host memory used
+host_seconds                                   285.95                       # Real time elapsed on the host
+host_tick_rate                                 676463                       # Simulator tick rate (ticks/s)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                   193435973                       # Number of instructions simulated
+sim_seconds                                  0.000193                       # Number of seconds simulated
+sim_ticks                                   193435972                       # Number of ticks simulated
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.numCycles                        193435973                       # number of cpu cycles simulated
+system.cpu.num_insts                        193435973                       # Number of instructions executed
+system.cpu.num_refs                          76732959                       # Number of memory references
+system.cpu.workload.PROG:num_syscalls             396                       # Number of system calls
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.out b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.out
new file mode 100644
index 000000000..00387ae5c
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.out
@@ -0,0 +1,276 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+          Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84  block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0   MISSING_ROWS:-46
+
+bdxlen:86  bdylen:78
+l:0  t:78  r:86  b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+  tempfile[0][0] = 0.982500    tempfile[0][1] = 90.000000
+  tempfile[1][0] = 0.915000    tempfile[1][1] = 20.000000
+  tempfile[2][0] = 0.700000    tempfile[2][1] = 10.000000
+  tempfile[3][0] = 0.100000    tempfile[3][1] = 0.000000
+
+  I   T  fds     Wire Penalty P_lim Epct binC rowC  acc  s/p early  FDs    MRs
+  1 500    0      929     592   160 30.0  1.0  3.0 84.2 34.7  0.0     0     40
+  2 491    0      876     106   726  0.0  0.8  2.5 80.0 18.5  0.0     0     46
+  3 482    0      822     273   372  0.0  0.5  1.5 80.8 21.2  0.0     0     46
+  4 474    0      826      53   247  0.0  0.5  0.9 65.0 21.9  0.0     0     48
+  5 465    8      987      73   190  0.0  0.5  0.5 50.0 38.3  0.0     0     46
+  6 457    8      851      67   226  0.0  0.5  0.5 53.8 42.9  0.0     0     52
+  7 449    8     1067     108   190  0.0  0.5  0.5 46.2 53.8  0.0     0     50
+  8 441    8      918     106   171  0.0  0.5  0.5 47.1 40.4  0.0     0     48
+  9 434    8      812     101   197  0.0  0.5  0.5 53.6 21.0  0.0     0     48
+ 10 426    8     1038     121   181  0.0  0.5  0.5 43.6 27.1  0.0     0     48
+ 11 419    8      898      93   187  0.0  0.5  0.5 45.3 47.8  0.0     0     50
+ 12 411    4      857      94   240  0.0  0.5  0.5 62.7 51.6  0.0     0     44
+ 13 404    8     1043      88   185  0.0  0.5  0.5 54.0 52.8  0.0     0     50
+ 14 397    8      767      94   154  0.0  0.5  0.5 33.8 35.0  0.0     0     50
+ 15 390    8      862      89   183  0.0  0.5  0.5 55.6 29.0  0.0     0     46
+ 16 383    4      798      79   173  0.0  0.5  0.5 57.5 35.3  0.0     0     52
+ 17 376    8      827     100   152  0.0  0.5  0.5 35.3 81.8  0.0     0     50
+ 18 370    8      878     101   208  0.0  0.5  0.5 44.7 46.2  0.0     0     48
+ 19 363    4      921      67   167  0.0  0.5  0.5 57.1 34.7  0.0     0     48
+ 20 357    8      933      93   154  0.0  0.5  0.5 46.5 43.6  0.0     0     52
+ 21 351    8      930      89   147  0.0  0.5  0.5 39.4 36.5  0.0     0     52
+ 22 345    8      951      79   142  0.0  0.5  0.5 32.8 51.3  0.0     0     50
+ 23 339    8     1046      87   207  0.0  0.5  0.5 52.8 61.0  0.0     0     48
+ 24 333    4      989      96   185  0.0  0.5  0.5 45.3 43.3  0.0     0     42
+ 25 327    4      577      86   157  0.0  0.5  0.5 31.1 55.3  0.0     0     52
+ 26 321    8      776      97   174  0.0  0.5  0.5 47.9 62.5  0.0     0     52
+ 27 315    8      850      81   188  0.0  0.5  0.5 45.0 55.2  0.0     0     50
+ 28 310    8      898      97   148  0.0  0.5  0.5 43.0 45.8  0.0     0     48
+ 29 304    8      889      65   173  0.0  0.5  0.5 32.5 41.3  0.0     0     50
+ 30 299    8      858      81   153  0.0  0.5  0.5 44.3 29.2  0.0     0     46
+ 31 294    8      871      82   187  0.0  0.5  0.5 45.7 47.7  0.0     0     48
+ 32 289    8      782     109   173  0.0  0.5  0.5 35.2 57.4  0.0     0     48
+ 33 284    8      743      98   189  0.0  0.6  0.5 41.8 64.3  0.0     0     52
+ 34 279    8      943      90   147  0.0  0.5  0.5 38.6 32.8  0.0     0     48
+ 35 274    8      907      57   166  0.0  0.5  0.5 33.6 51.0  0.0     0     48
+ 36 269    8      900      70   148  0.0  0.5  0.5 45.0 41.4  0.0     0     50
+ 37 264    4      875     106   133  0.0  0.5  0.5 31.7 55.3  0.0     0     52
+ 38 260    8     1023     145   149  0.0  0.6  0.5 28.7 65.0  0.0     0     52
+ 39 255    8      801     151   173  0.0  0.9  0.5 41.7 41.2  0.0     0     48
+ 40 251    8      741     104   159  0.0  0.8  0.5 36.2 47.5  0.0     0     48
+ 41 246    8      828     108   149  0.0  0.5  0.5 34.6 50.9  0.0     0     50
+ 42 242    8      947     128   132  0.0  0.7  0.5 34.2 39.0  0.0     0     50
+ 43 238    8      917     101   142  0.0  0.8  0.5 34.4 50.9  0.0     0     48
+ 44 234    8      761      86   129  0.0  0.5  0.5 42.0 36.4  0.0     0     52
+ 45 229    8      979     106   137  0.0  0.5  0.5 29.2 55.3  0.0     0     50
+ 46 225    8      806      74   130  0.0  0.7  0.5 33.1 65.4  0.0     0     52
+ 47 221    8      971     125   114  0.0  0.5  0.5 31.9 45.6  0.0     0     52
+ 48 218    8      869     125   104  0.0  0.9  0.5 30.0 56.0  0.0     0     48
+ 49 214    8      999     153   140  0.0  0.8  0.5 30.4 46.4  0.0     0     52
+ 50 210    8      798     192   139  0.0  1.0  0.5 28.9 50.0  0.0     0     52
+ 51 206    8      860     125   157  0.0  1.2  0.5 31.5 26.9  0.0     0     52
+ 52 203    8      893     186   127  5.9  0.9  0.5 26.4 42.3  0.0     0     46
+ 53 199    8      863     126   141  0.0  1.2  0.5 32.5 44.4  0.0     0     44
+ 54 196    8      788      97   133  0.0  0.9  0.5 37.5 40.0  0.0     0     50
+ 55 192    8      926     119   116  0.0  0.6  0.5 26.1 55.3  0.0     0     52
+ 56 189    8      789     162   107  0.0  0.8  0.5 25.2 40.4  0.0     0     48
+ 57 186    8      878     107   128  0.0  1.1  0.5 23.1 34.0  0.0     0     52
+ 58 182    8      775     105   122  0.0  0.8  0.5 25.5 57.4  0.0     0     50
+ 59 179    8      747      94   129  0.0  0.7  0.5 34.3 37.3  0.0     0     50
+ 60 176    8      845      96   138  0.0  0.6  0.5 28.3 41.7  0.0     0     52
+ 61 173    8      961     121   110  0.0  0.6  0.5 29.0 52.6  0.0     0     48
+ 62 170    4      911     110   109  0.0  0.9  0.5 33.5 33.3  0.0     0     48
+ 63 167    8      656     109   109  0.0  0.8  0.5 21.9 44.7  0.0     0     52
+ 64 164    8      934     117   105  0.0  0.8  0.5 15.5 50.0  0.0     0     52
+ 65 161    8      972     125    95  0.0  0.8  0.5 24.4 50.0  0.0     0     50
+ 66 158    8      894     125   101  0.0  0.9  0.5 27.2 35.9  0.0     0     52
+ 67 155    8      798     146   129  0.0  1.0  0.5 22.8 58.7  0.0     0     52
+ 68 153    8      901     183    92  0.0  1.1  0.5 23.6 34.5  0.0     0     52
+ 69 150    8      977     197   103  0.0  1.4  0.5 23.6 36.8  0.0     0     52
+ 70 147    8      905     262    93  0.0  1.5  0.5 20.3 63.4  0.0     0     52
+ 71 145    8      995     148   122  0.0  1.9  0.5 20.9 35.3  0.0     0     52
+ 72 142    8      934     230    99  0.0  1.6  0.5 20.0 65.9  0.0     0     52
+ 73 140    8      862     173   100  0.0  1.8  0.5 26.8 46.8  0.0     0     52
+ 74 137    8      924     139    90  0.0  1.7  0.5 16.8 42.5  0.0     0     52
+ 75 135    8      888     168   113  0.0  1.6  0.5 22.9 40.4  0.0     0     52
+ 76 133    8      712     212    84  0.0  1.6  0.5 13.4 46.9  0.0     0     52
+ 77 130    8      868     210    91  0.0  1.7  0.5 17.7 51.2  0.0     0     52
+ 78 128    8      952     307    92  0.0  1.9  0.5 19.7 44.9  0.0     0     50
+ 79 126    8      801     157   107  0.0  2.2  0.5 15.8 39.0  0.0     0     52
+ 80 123    8      849     147    93  0.0  2.1  0.5 15.6 51.4  0.0     0     52
+ 81 121    8      799     154    86  0.0  1.9  0.5 12.2 50.0  0.0     0     52
+ 82 119    8      941     213    82  0.0  1.8  0.5 19.5 41.2  0.0     0     50
+ 83 117    8      751     268    94  0.0  2.0  0.5 20.8 42.6  0.0     0     50
+ 84 115    8      828     198   102  0.0  2.2  0.5 15.5 59.5  0.0     0     52
+ 85 113    8      898     266   123  0.0  2.2  0.5 13.2 85.2  0.0     0     52
+ 86 111    8      943     190    93  0.0  2.4  0.5 19.5 45.1  0.0     0     52
+ 87 109    8      864     183    65  0.0  2.4  0.5 14.9 31.8  0.0     0     52
+ 88 107    8      793     203    93  0.0  2.4  0.5 11.8 35.3  0.0     0     52
+ 89 105    8      752     162    74  1.2  2.4  0.5 13.1 21.4  0.0     0     52
+ 90 103    8      801     149    77  0.0  2.3  0.5  9.7 58.3  0.0     0     52
+ 91 102    8      901     230    99  0.0  2.2  0.5 16.0 25.5  0.0     0     52
+ 92 100    8      826     201    87  0.0  2.4  0.5 12.8 45.7  0.0     0     52
+ 93  98    8      810     196    83  0.0  2.5  0.5 14.0 24.4  0.0     0     52
+ 94  96    8      857     209    68  1.0  2.5  0.5 11.5 27.0  5.1     0     52
+ 95  95    8      771     174    91  0.0  2.6  0.5 10.5 26.5  0.0     0     52
+ 96  93    8      955     210    59  0.0  2.6  0.5 10.0 36.7  0.7     0     52
+ 97  91    8      833     206    53  0.0  2.7  0.5 10.2 19.4  1.4     0     52
+ 98  90    8      888     229    86  0.0  2.8  0.5  8.1 36.0  0.0     0     52
+ 99  88    8      794     186    91  1.0  2.9  0.5  8.3 25.0  0.5     0     52
+100  81    8      756     170    72  1.0  2.9  0.5  6.0 23.8  7.0     0     52
+101  74    8      791     176    67  0.0  2.9  0.5  4.4 58.3  4.0     0     52
+102  67    8      813     213    43  0.0  3.0  0.5  7.0 150.0  4.2     0     52
+103  62    8      779     245    39  0.0  3.1  0.5  3.2 16.7 13.0     0     52
+104  56    8      767     303    63  0.0  3.2  0.5  4.1 20.0  0.7     0     52
+105  52    8      757     270    57  0.0  3.5  0.5  6.4  3.7  0.5     0     52
+106  47    8      763     283    41  0.0  3.7  0.5  4.5  0.0  0.0     0     52
+107  43    8      768     283    36  0.0  3.7  0.5  2.9 18.2  3.6     0     52
+108  39    8      804     283    25  0.0  3.7  0.5  3.1  0.0  6.2     0     52
+109  36    8      781     283    24  0.0  3.7  0.5  3.6  6.7  6.7     0     52
+110  33    8      738     298    42  0.0  3.7  0.5  3.3 15.4  3.5     0     52
+111  30    8      761     298    36  0.0  3.7  0.5  2.2  0.0  4.3     0     52
+112  27    8      769     298    37  0.0  3.7  0.5  0.9  0.0  2.2     0     52
+113  25    8      745     298    31  0.0  3.7  0.5  1.5  0.0  6.6     0     52
+114  23    8      753     298    16  0.0  3.7  0.5  1.3  0.0  2.8     0     52
+115  21    8      745     298    11  0.0  3.7  0.5  1.5  0.0 14.0     0     52
+116  19    8      747     298    21  0.0  3.7  0.5  2.1  0.0  5.8     0     52
+117  13    8      737     298    12  0.0  3.7  0.5  1.0  0.0 10.0     0     52
+118   9    8      736     298     4  0.0  3.7  0.5  1.5  0.0 18.5     0     52
+119   0    8      739     298     0  0.0  3.7  0.5  1.8  0.0 18.0     0     52
+120   0    8      732     298     0  0.0  3.7  0.5  1.2  0.0 21.8     0     52
+121   0    8      732      19    -1 0.0  0.0  0.5  0.0 100.0 54.8
+
+Initial Wiring Cost: 645   Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645   Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216   Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429   Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 82                   -20
+  2                 86                   -16
+
+LONGEST Block is:2   Its length is:86
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 86                   -16
+  2                 86                   -16
+
+LONGEST Block is:1   Its length is:86
+Added: 1  feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl:   1.650
+finalRowControl:   0.300
+iter      T      Wire accept
+ 122  0.001       976   16%
+ 123  0.001       971    0%
+ 124  0.001       971    0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL:  1  is:   0
+MAX OF CHANNEL:  2  is:   4
+MAX OF CHANNEL:  3  is:   1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0    FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T:      55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0 
+Number of Nets: 15 
+Number of Pins: 46 
+Usage statistics not available
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pin b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pin
new file mode 100644
index 000000000..62b922e4e
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pin
@@ -0,0 +1,17 @@
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1 b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1
new file mode 100644
index 000000000..bdc569e39
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1
@@ -0,0 +1,11 @@
+$COUNT_1/$AND2_4/$IV_1 0 0  4 26  0 1
+$COUNT_1/$AND2_3/$IV_1 4 0  8 26  2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0  14 26  0 1
+ACOUNT_1 14 0  18 26  2 1
+twfeed1 18 0  22 26  0 1
+$COUNT_1/$FJK3_1 22 0  86 26  0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52  6 78  0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52  12 78  2 2
+$COUNT_1/$AND2_2/$IV_1 12 52  16 78  2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52  22 78  2 2
+$COUNT_1/$FJK3_2 22 52  86 78  0 2
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2 b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2
new file mode 100644
index 000000000..6e2601e82
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2
@@ -0,0 +1,2 @@
+1 0 0  86 26  0 0
+2 0 52  86 78  0 0
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sav b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sav
new file mode 100644
index 000000000..04c8e9935
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sav
@@ -0,0 +1,18 @@
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2 b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2
new file mode 100644
index 000000000..9dd68ecdb
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2
@@ -0,0 +1,19 @@
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.twf b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.twf
new file mode 100644
index 000000000..a4c2eac35
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.twf
@@ -0,0 +1,29 @@
+net 1
+segment channel 2
+ pin1 1  pin2 7 0 0
+net 2
+segment channel 3
+pin1 41  pin2 42 0 0
+segment channel 2
+pin1 12  pin2 3 0 0
+net 3
+segment channel 2
+pin1 35  pin2 36 0 0
+segment channel 2
+pin1 19  pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5  pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14  pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23  pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25  pin2 31 0 0
+net 14
+net 15
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr
new file mode 100644
index 000000000..94662b6e8
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr
@@ -0,0 +1,8 @@
+warn: More than two loadable segments in ELF object.
+warn: Ignoring segment @ 0x11e394 length 0x10.
+warn: More than two loadable segments in ELF object.
+warn: Ignoring segment @ 0x0 length 0x0.
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0.  Starting simulation...
+warn: Ignoring request to flush register windows.
+warn: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout
new file mode 100644
index 000000000..7c0e5ba5f
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout
@@ -0,0 +1,28 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+         Yale University
+  1   2   3   4   5   6   7   8   9  10  11  12  13  14  15 
+ 16  17  18  19  20  21  22  23  24  25  26  27  28  29  30 
+ 31  32  33  34  35  36  37  38  39  40  41  42  43  44  45 
+ 46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 
+ 61  62  63  64  65  66  67  68  69  70  71  72  73  74  75 
+ 76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
+ 91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
+122 123 124 M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Mar 12 2007 16:53:49
+M5 started Mon Mar 12 17:37:07 2007
+M5 executing on zizzer.eecs.umich.edu
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic
+Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav
+Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+Exiting @ tick 193435972 because target called exit()
diff --git a/tests/long/70.twolf/test.py b/tests/long/70.twolf/test.py
index 65973c1ee..b2a2dc0b6 100644
--- a/tests/long/70.twolf/test.py
+++ b/tests/long/70.twolf/test.py
@@ -30,7 +30,7 @@ m5.AddToPath('../configs/common')
 from cpu2000 import twolf
 import os
 
-workload = twolf('alpha', 'tru64', 'smred')
+workload = twolf(isa, opsys, 'smred')
 root.system.cpu.workload = workload.makeLiveProcess()
 cwd = root.system.cpu.workload.cwd