diff options
Diffstat (limited to 'tests')
201 files changed, 13042 insertions, 1228 deletions
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py index a66cd436e..5600d9f22 100644 --- a/tests/configs/o3-timing.py +++ b/tests/configs/o3-timing.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -37,7 +37,7 @@ class MyCache(BaseCache): mshrs = 10 tgts_per_mshr = 5 -cpu = DerivO3CPU() +cpu = DerivO3CPU(cpu_id=0) cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), MyCache(size = '2MB')) diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index fa5ac1725..fa5ac1725 100644 --- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out index 8744b6907..8744b6907 100644 --- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt index 8303336ed..8303336ed 100644 --- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr index eb1796ead..eb1796ead 100644 --- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout index 9aaca3eeb..9aaca3eeb 100644 --- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index 841e8766f..841e8766f 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out index b5a24e5fb..b5a24e5fb 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt index b8593d3a3..b8593d3a3 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr index 87866a2a5..87866a2a5 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout index 9aaca3eeb..9aaca3eeb 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 48a760b08..48a760b08 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out index eddb9ff53..eddb9ff53 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt index 5e7441c54..5e7441c54 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr index 87866a2a5..87866a2a5 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout index 9aaca3eeb..9aaca3eeb 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini new file mode 100644 index 000000000..1cf7e8a9b --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -0,0 +1,64 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=workload +clock=1 +cpu_id=0 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +simulate_stalls=false +system=system +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out new file mode 100644 index 000000000..f6ace951d --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out @@ -0,0 +1,57 @@ +[root] +type=Root +dummy=0 + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 +zero=false + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip +input=cin +output=cout +env= +cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt new file mode 100644 index 000000000..6cf88af9d --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 713136 # Simulator instruction rate (inst/s) +host_mem_usage 148308 # Number of bytes of host memory used +host_seconds 2088.68 # Real time elapsed on the host +host_tick_rate 713136 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1489514860 # Number of instructions simulated +sim_seconds 0.001490 # Number of seconds simulated +sim_ticks 1489514859 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1489514860 # number of cpu cycles simulated +system.cpu.num_insts 1489514860 # Number of instructions executed +system.cpu.num_refs 569359656 # Number of memory references +system.cpu.workload.PROG:num_syscalls 19 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr new file mode 100644 index 000000000..e74a68c71 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr @@ -0,0 +1,7 @@ +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0xb4000 length 0x10. +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x0 length 0x0. +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... +warn: Ignoring request to flush register windows. diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout new file mode 100644 index 000000000..3f5dab90b --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout @@ -0,0 +1,44 @@ +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 21 2007 00:46:54 +M5 started Wed Mar 21 00:47:20 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1489514859 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini new file mode 100644 index 000000000..75db6656a --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -0,0 +1,187 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache icache l2cache toL2Bus workload +clock=1 +cpu_id=0 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +system=system +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out new file mode 100644 index 000000000..11cb72660 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out @@ -0,0 +1,178 @@ +[root] +type=Root +dummy=0 + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 +zero=false + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip +input=cin +output=cout +env= +cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..f83fd185e --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt @@ -0,0 +1,230 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 531377 # Simulator instruction rate (inst/s) +host_mem_usage 154376 # Number of bytes of host memory used +host_seconds 2803.12 # Real time elapsed on the host +host_tick_rate 1212716 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1489514860 # Number of instructions simulated +sim_seconds 0.003399 # Number of seconds simulated +sim_ticks 3399390003 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 2848.782706 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1848.782706 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 402318208 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 551182478 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 193480 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 357702478 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 193480 # number of ReadReq MSHR misses +system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_avg_miss_latency 3103.285714 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2103.285714 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 21723 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 14723 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses +system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3023.717816 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2023.717816 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 166586897 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 785395584 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001557 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 259745 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 525650584 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 259745 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 1255.221220 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2949.038694 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 1949.038694 # average overall mshr miss latency +system.cpu.dcache.demand_hits 568905105 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1336578062 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000796 # miss rate for demand accesses +system.cpu.dcache.demand_misses 453225 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 883353062 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 453225 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2949.038694 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 1949.038694 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 568905105 # number of overall hits +system.cpu.dcache.overall_miss_latency 1336578062 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000796 # miss rate for overall accesses +system.cpu.dcache.overall_misses 453225 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 883353062 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 453225 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 449136 # number of replacements +system.cpu.dcache.sampled_refs 453232 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4068.114109 # Cycle average of tags in use +system.cpu.dcache.total_refs 568906424 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 33495000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 316447 # number of writebacks +system.cpu.icache.ReadReq_accesses 1489514861 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3979.992714 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2979.992714 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1489513763 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 4370032 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 3272032 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1356569.911658 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1489514861 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3979.992714 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2979.992714 # average overall mshr miss latency +system.cpu.icache.demand_hits 1489513763 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 4370032 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 3272032 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 1098 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1489514861 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3979.992714 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2979.992714 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1489513763 # number of overall hits +system.cpu.icache.overall_miss_latency 4370032 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_misses 1098 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 3272032 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 1098 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 115 # number of replacements +system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 865.251814 # Cycle average of tags in use +system.cpu.icache.total_refs 1489513763 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadReq_accesses 454330 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3215.864263 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1941.261615 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 427145 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 87423270 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.059835 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 27185 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 52773197 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.059835 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 27185 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 316447 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 316438 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.000028 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 9 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.000028 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 9 # number of Writeback MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 27.352695 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 454330 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3215.864263 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1941.261615 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 427145 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 87423270 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.059835 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 27185 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 52773197 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.059835 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 27185 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 770777 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3214.799956 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1941.261615 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 743583 # number of overall hits +system.cpu.l2cache.overall_miss_latency 87423270 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.035281 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 27194 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 52773197 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.035270 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 27185 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 2632 # number of replacements +system.cpu.l2cache.sampled_refs 27185 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 23773.580402 # Cycle average of tags in use +system.cpu.l2cache.total_refs 743583 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 2531 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 3399390003 # number of cpu cycles simulated +system.cpu.num_insts 1489514860 # Number of instructions executed +system.cpu.num_refs 569359656 # Number of memory references +system.cpu.workload.PROG:num_syscalls 19 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr new file mode 100644 index 000000000..e74a68c71 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr @@ -0,0 +1,7 @@ +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0xb4000 length 0x10. +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x0 length 0x0. +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... +warn: Ignoring request to flush register windows. diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout new file mode 100644 index 000000000..8d54e9042 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout @@ -0,0 +1,44 @@ +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 29 2007 03:54:03 +M5 started Thu Mar 29 03:54:23 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 3399390003 because target called exit() diff --git a/tests/long/00.gzip/test.py b/tests/long/00.gzip/test.py index 06ccb656b..f69914046 100644 --- a/tests/long/00.gzip/test.py +++ b/tests/long/00.gzip/test.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -29,5 +29,5 @@ m5.AddToPath('../configs/common') from cpu2000 import gzip_log -workload = gzip_log('alpha', 'tru64', 'smred') +workload = gzip_log(isa, opsys, 'smred') root.system.cpu.workload = workload.makeLiveProcess() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini new file mode 100644 index 000000000..73a28200e --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -0,0 +1,64 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=workload +clock=1 +cpu_id=0 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +simulate_stalls=false +system=system +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.workload] +type=LiveProcess +cmd=mcf mcf.in +cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf +gid=100 +input=/dist/m5/cpu2000/data/mcf/lgred/input/mcf.in +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out new file mode 100644 index 000000000..2b86e6bfb --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out @@ -0,0 +1,57 @@ +[root] +type=Root +dummy=0 + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 +zero=false + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.workload] +type=LiveProcess +cmd=mcf mcf.in +executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf +input=/dist/m5/cpu2000/data/mcf/lgred/input/mcf.in +output=cout +env= +cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt new file mode 100644 index 000000000..41e6bfc52 --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 624449 # Simulator instruction rate (inst/s) +host_mem_usage 148644 # Number of bytes of host memory used +host_seconds 2753.78 # Real time elapsed on the host +host_tick_rate 624449 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1719594534 # Number of instructions simulated +sim_seconds 0.001720 # Number of seconds simulated +sim_ticks 1719594533 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1719594534 # number of cpu cycles simulated +system.cpu.num_insts 1719594534 # Number of instructions executed +system.cpu.num_refs 774793634 # Number of memory references +system.cpu.workload.PROG:num_syscalls 632 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out new file mode 100644 index 000000000..6bbb02cf0 --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out @@ -0,0 +1,3092 @@ +() +1642 +*** +1759 +() +1641 +*** +1691 +() +1640 +() +1639 +() +1638 +() +1637 +() +1636 +() +1635 +() +1634 +() +1633 +() +1632 +() +1631 +() +1630 +() +1629 +() +1628 +() +1627 +() +1626 +() +1625 +*** +1784 +() +1624 +() +1623 +() +1622 +*** +1688 +() +1621 +() +1618 +() +1617 +*** +1796 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a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr new file mode 100644 index 000000000..9c09fd847 --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr @@ -0,0 +1,7 @@ +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0xa2000 length 0x10. +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x0 length 0x0. +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... +warn: Ignoring request to flush register windows. diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout new file mode 100644 index 000000000..6711761e8 --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout @@ -0,0 +1,33 @@ + +MCF SPEC version 1.6.I +by Andreas Loebel +Copyright (c) 1998,1999 ZIB Berlin +All Rights Reserved. + +nodes : 1800 +active arcs : 8190 +simplex iterations : 6837 +flow value : 12860044181 +new implicit arcs : 300000 +active arcs : 308190 +simplex iterations : 11843 +flow value : 9360043604 +new implicit arcs : 22787 +active arcs : 330977 +simplex iterations : 11931 +flow value : 9360043512 +checksum : 798014 +optimal +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 23 2007 22:37:06 +M5 started Fri Mar 23 22:37:22 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1719594533 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini new file mode 100644 index 000000000..dfb81664a --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -0,0 +1,187 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache icache l2cache toL2Bus workload +clock=1 +cpu_id=0 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +system=system +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=mcf mcf.in +cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf +gid=100 +input=/dist/m5/cpu2000/data/mcf/lgred/input/mcf.in +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out new file mode 100644 index 000000000..e5ed0b288 --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out @@ -0,0 +1,178 @@ +[root] +type=Root +dummy=0 + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 +zero=false + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.workload] +type=LiveProcess +cmd=mcf mcf.in +executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf +input=/dist/m5/cpu2000/data/mcf/lgred/input/mcf.in +output=cout +env= +cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..b11288b2d --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt @@ -0,0 +1,230 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 446147 # Simulator instruction rate (inst/s) +host_mem_usage 154148 # Number of bytes of host memory used +host_seconds 3854.32 # Real time elapsed on the host +host_tick_rate 13681801 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1719594534 # Number of instructions simulated +sim_seconds 0.052734 # Number of seconds simulated +sim_ticks 52734070003 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 607807189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3420.154300 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2420.154300 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 594739458 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 44693656366 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.021500 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 13067731 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 31625925366 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.021500 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 13067731 # number of ReadReq MSHR misses +system.cpu.dcache.SwapReq_accesses 15448 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_avg_miss_latency 3631.818182 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2631.818182 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 15437 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 39950 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.000712 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 11 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 28950 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.000712 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 11 # number of SwapReq MSHR misses +system.cpu.dcache.WriteReq_accesses 166970997 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3255.499606 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2255.499606 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 165264000 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5557128061 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.010223 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1706997 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 3850131061 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.010223 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1706997 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 51.440428 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 774778186 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3401.130933 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2401.130933 # average overall mshr miss latency +system.cpu.dcache.demand_hits 760003458 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 50250784427 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.019070 # miss rate for demand accesses +system.cpu.dcache.demand_misses 14774728 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 35476056427 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.019070 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 14774728 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 774778186 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3401.130933 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2401.130933 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 760003458 # number of overall hits +system.cpu.dcache.overall_miss_latency 50250784427 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.019070 # miss rate for overall accesses +system.cpu.dcache.overall_misses 14774728 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 35476056427 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.019070 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 14774728 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 14770643 # number of replacements +system.cpu.dcache.sampled_refs 14774739 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4094.978951 # Cycle average of tags in use +system.cpu.dcache.total_refs 760018895 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 35437000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 4191356 # number of writebacks +system.cpu.icache.ReadReq_accesses 1719594535 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4032.295228 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3032.295228 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1719593634 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 3633098 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 901 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 2732098 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 901 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1908538.994451 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1719594535 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 4032.295228 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3032.295228 # average overall mshr miss latency +system.cpu.icache.demand_hits 1719593634 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 3633098 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_misses 901 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 2732098 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 901 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1719594535 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 4032.295228 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3032.295228 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1719593634 # number of overall hits +system.cpu.icache.overall_miss_latency 3633098 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_misses 901 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 2732098 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 901 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 31 # number of replacements +system.cpu.icache.sampled_refs 901 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 750.163929 # Cycle average of tags in use +system.cpu.icache.total_refs 1719593634 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadReq_accesses 14775639 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3097.556051 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1926.730191 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 8592784 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 19151739918 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.418449 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 6182855 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11912693395 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.418449 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 6182855 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 4191356 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 4164131 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.006496 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 27225 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.006496 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 27225 # number of Writeback MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 2.063273 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 14775639 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3097.556051 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1926.730191 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 8592784 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 19151739918 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.418449 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 6182855 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 11912693395 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.418449 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 6182855 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 18966995 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3083.976361 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1926.730191 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 12756915 # number of overall hits +system.cpu.l2cache.overall_miss_latency 19151739918 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.327415 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 6210080 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 11912693395 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.325980 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 6182855 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 6150087 # number of replacements +system.cpu.l2cache.sampled_refs 6182855 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 27594.660688 # Cycle average of tags in use +system.cpu.l2cache.total_refs 12756915 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 12316534000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1069081 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 52734070003 # number of cpu cycles simulated +system.cpu.num_insts 1719594534 # Number of instructions executed +system.cpu.num_refs 774793634 # Number of memory references +system.cpu.workload.PROG:num_syscalls 632 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out b/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out new file mode 100644 index 000000000..6bbb02cf0 --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out @@ -0,0 +1,3092 @@ +() +1642 +*** +1759 +() +1641 +*** +1691 +() +1640 +() +1639 +() +1638 +() +1637 +() +1636 +() +1635 +() +1634 +() +1633 +() +1632 +() +1631 +() +1630 +() +1629 +() +1628 +() +1627 +() +1626 +() +1625 +*** +1784 +() +1624 +() +1623 +() +1622 +*** +1688 +() +1621 +() +1618 +() +1617 +*** +1796 +() +1616 +() +1615 +*** +1668 +() +1614 +() +1613 +() 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+463 +507 +542 +567 +593 +614 +631 +() +19 +33 +*** +1185 +*** +1694 +() +18 +44 +94 +146 +184 +226 +263 +314 +361 +415 +460 +509 +546 +573 +597 +618 +634 +644 +() +17 +31 +65 +102 +*** +807 +() +16 +34 +84 +133 +177 +213 +256 +298 +352 +400 +453 +496 +() +14 +37 +81 +135 +173 +217 +253 +300 +347 +403 +448 +499 +537 +563 +587 +611 +628 +641 +() +13 +22 +42 +*** +691 +() +12 +47 +93 +147 +183 +227 +264 +313 +362 +417 +462 +510 +544 +581 +612 +636 +() +11 +29 +*** +760 +() +10 +30 +63 +*** +1121 +() +9 +35 +83 +132 +176 +214 +257 +297 +353 +399 +451 +497 +*** +1304 +() +8 +25 +64 +*** +828 +() +7 +23 +51 +89 +*** +1174 +*** +1300 +() +6 +28 +71 +120 +167 +203 +247 +284 +340 +387 +440 +486 +528 +565 +600 +626 +() +5 +*** +668 +() +4 +32 +77 +*** +1032 +() +3 +15 +38 +76 +*** +1314 +() +2 +27 +*** +1053 +() +1 +21 +58 +107 +156 +194 +237 +274 +322 +*** +1151 +*** +1777 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr new file mode 100644 index 000000000..9c09fd847 --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr @@ -0,0 +1,7 @@ +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0xa2000 length 0x10. +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x0 length 0x0. +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... +warn: Ignoring request to flush register windows. diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout new file mode 100644 index 000000000..7d97093d4 --- /dev/null +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout @@ -0,0 +1,33 @@ + +MCF SPEC version 1.6.I +by Andreas Loebel +Copyright (c) 1998,1999 ZIB Berlin +All Rights Reserved. + +nodes : 1800 +active arcs : 8190 +simplex iterations : 6837 +flow value : 12860044181 +new implicit arcs : 300000 +active arcs : 308190 +simplex iterations : 11843 +flow value : 9360043604 +new implicit arcs : 22787 +active arcs : 330977 +simplex iterations : 11931 +flow value : 9360043512 +checksum : 798014 +optimal +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 29 2007 15:41:48 +M5 started Thu Mar 29 15:42:11 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 52734070003 because target called exit() diff --git a/tests/long/10.mcf/test.py b/tests/long/10.mcf/test.py index f545aad3d..ffe2758f1 100644 --- a/tests/long/10.mcf/test.py +++ b/tests/long/10.mcf/test.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -29,5 +29,5 @@ m5.AddToPath('../configs/common') from cpu2000 import mcf -workload = mcf('alpha', 'tru64', 'lgred') +workload = mcf(isa, opsys, 'lgred') root.system.cpu.workload = workload.makeLiveProcess() diff --git a/tests/long/20.parser/ref/alpha/linux/NOTE b/tests/long/20.parser/ref/alpha/tru64/NOTE index 5e7d8c358..5e7d8c358 100644 --- a/tests/long/20.parser/ref/alpha/linux/NOTE +++ b/tests/long/20.parser/ref/alpha/tru64/NOTE diff --git a/tests/long/20.parser/test.py b/tests/long/20.parser/test.py index 8703ae634..82ab71c90 100644 --- a/tests/long/20.parser/test.py +++ b/tests/long/20.parser/test.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -29,5 +29,5 @@ m5.AddToPath('../configs/common') from cpu2000 import parser -workload = parser('alpha', 'tru64', 'lgred') +workload = parser(isa, opsys, 'lgred') root.system.cpu.workload = workload.makeLiveProcess() diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 915a6967f..915a6967f 100644 --- a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.out b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out index 80e067401..80e067401 100644 --- a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt index 9d00cb146..9d00cb146 100644 --- a/tests/long/30.eon/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr index d414f5cfe..d414f5cfe 100644 --- a/tests/long/30.eon/ref/alpha/linux/o3-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout index 039e2d4ce..039e2d4ce 100644 --- a/tests/long/30.eon/ref/alpha/linux/o3-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini index 088cd1a9f..088cd1a9f 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out index bec900d0f..bec900d0f 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt index a308f5e36..a308f5e36 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr index 1d6957eca..1d6957eca 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout index 039e2d4ce..039e2d4ce 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini index 452538e49..452538e49 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out index 602da9705..602da9705 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt index 328856ce7..328856ce7 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr index 8534c55aa..8534c55aa 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout index 039e2d4ce..039e2d4ce 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout diff --git a/tests/long/30.eon/test.py b/tests/long/30.eon/test.py index 828b6390c..318da1049 100644 --- a/tests/long/30.eon/test.py +++ b/tests/long/30.eon/test.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -29,5 +29,5 @@ m5.AddToPath('../configs/common') from cpu2000 import eon_cook -workload = eon_cook('alpha', 'tru64', 'mdred') +workload = eon_cook(isa, opsys, 'mdred') root.system.cpu.workload = workload.makeLiveProcess() diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini index 59c6e25e2..59c6e25e2 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out index c6e4aa136..c6e4aa136 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt index 9db3f64bc..9db3f64bc 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr index bc72461c8..bc72461c8 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout index d4a078b85..d4a078b85 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index 5f64dcebd..5f64dcebd 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out index 6998f4828..6998f4828 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt index 45f793ab7..45f793ab7 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr index bc72461c8..bc72461c8 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout index d4a078b85..d4a078b85 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout diff --git a/tests/long/40.perlbmk/test.py b/tests/long/40.perlbmk/test.py index 2f9dd0ff0..e32416265 100644 --- a/tests/long/40.perlbmk/test.py +++ b/tests/long/40.perlbmk/test.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -29,5 +29,5 @@ m5.AddToPath('../configs/common') from cpu2000 import perlbmk_makerand -workload = perlbmk_makerand('alpha', 'tru64', 'lgred') +workload = perlbmk_makerand(isa, opsys, 'lgred') root.system.cpu.workload = workload.makeLiveProcess() diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index cf4e15676..cf4e15676 100644 --- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out index 52c225902..52c225902 100644 --- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt index 3069385f0..3069385f0 100644 --- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.msg b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg index 327142d7c..327142d7c 100644 --- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.msg +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.out b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.out index 726b45c60..726b45c60 100644 --- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.out +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.out diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr index eb1796ead..eb1796ead 100644 --- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout index e69de29bb..e69de29bb 100644 --- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini index 179e8ea77..179e8ea77 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out index 725aaed50..725aaed50 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt index 9c60e1316..9c60e1316 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.msg b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg index 327142d7c..327142d7c 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.msg +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.out b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.out index 726b45c60..726b45c60 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.out +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.out diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr index eb1796ead..eb1796ead 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout index e69de29bb..e69de29bb 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 0e1a3c9f1..0e1a3c9f1 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out index 0dc85858d..0dc85858d 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt index 9a9778162..9a9778162 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.msg b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg index 327142d7c..327142d7c 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.msg +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.out b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.out index 726b45c60..726b45c60 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.out +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.out diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr index eb1796ead..eb1796ead 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout index e69de29bb..e69de29bb 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini new file mode 100644 index 000000000..7dbc37b58 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -0,0 +1,64 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=workload +clock=1 +cpu_id=0 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +simulate_stalls=false +system=system +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.workload] +type=LiveProcess +cmd=vortex bendian.raw +cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out new file mode 100644 index 000000000..ee1fc877f --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out @@ -0,0 +1,57 @@ +[root] +type=Root +dummy=0 + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 +zero=false + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.workload] +type=LiveProcess +cmd=vortex bendian.raw +executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex +input=cin +output=cout +env= +cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt new file mode 100644 index 000000000..323b8a93c --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 638506 # Simulator instruction rate (inst/s) +host_mem_usage 150340 # Number of bytes of host memory used +host_seconds 213.38 # Real time elapsed on the host +host_tick_rate 638505 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 136246936 # Number of instructions simulated +sim_seconds 0.000136 # Number of seconds simulated +sim_ticks 136246935 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 136246936 # number of cpu cycles simulated +system.cpu.num_insts 136246936 # Number of instructions executed +system.cpu.num_refs 58111522 # Number of memory references +system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.msg b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.msg new file mode 100644 index 000000000..0ac2d9980 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.msg @@ -0,0 +1,158 @@ + + SYSTEM TYPE... + __ZTC__ := False + __UNIX__ := True + __RISC__ := True + SPEC_CPU2000_LP64 := False + __MAC__ := False + __BCC__ := False + __BORLANDC__ := False + __GUI__ := False + __WTC__ := False + __HP__ := False + + CODE OPTIONS... + __MACROIZE_HM__ := True + __MACROIZE_MEM__ := True + ENV01 := True + USE_HPP_STYPE_HDRS := False + USE_H_STYPE_HDRS := False + + CODE INCLUSION PARAMETERS... + INCLUDE_ALL_CODE := False + INCLUDE_DELETE_CODE := True + __SWAP_GRP_POS__ := True + __INCLUDE_MTRX__ := False + __BAD_CODE__ := False + API_INCLUDE := False + BE_CAREFUL := False + OLDWAY := False + NOTUSED := False + + SYSTEM PARAMETERS... + EXT_ENUM := 999999999L + CHUNK_CONSTANT := 55555555 + CORE_CONSTANT := 55555555 + CORE_LIMIT := 20971520 + CorePage_Size := 384000 + ALIGN_BYTES := True + CORE_BLOCK_ALIGN := 8 + FAR_MEM := False + + MEMORY MANAGEMENT PARAMETERS... + SYSTEM_ALLOC := True + SYSTEM_FREESTORE := True + __NO_DISKCACHE__ := False + __FREEZE_VCHUNKS__ := True + __FREEZE_GRP_PACKETS__ := True + __MINIMIZE_TREE_CACHE__:= True + + SYSTEM STD PARAMETERS... + __STDOUT__ := False + NULL := 0 + LPTR := False + False_Status := 1 + True_Status := 0 + LARGE := True + TWOBYTE_BOOL := False + __NOSTR__ := False + + MEMORY VALIDATION PARAMETERS... + CORE_CRC_CHECK := False + VALIDATE_MEM_CHUNKS := False + + SYSTEM DEBUG OPTIONS... + DEBUG := False + MCSTAT := False + TRACKBACK := False + FLUSH_FILES := False + DEBUG_CORE0 := False + DEBUG_RISC := False + __TREE_BUG__ := False + __TRACK_FILE_READS__ := False + PAGE_SPACE := False + LEAVE_NO_TRACE := True + NULL_TRACE_STRS := False + + TIME PARAMETERS... + CLOCK_IS_LONG := False + __DISPLAY_TIME__ := False + __TREE_TIME__ := False + __DISPLAY_ERRORS__ := False + + API MACROS... + __BMT01__ := True + OPTIMIZE := True + + END OF DEFINES. + + + + ... IMPLODE MEMORY ... + + SWAP to DiskCache := False + + FREEZE_GRP_PACKETS:= True + + QueBug := 1000 + + sizeof(boolean) = 4 + sizeof(sizetype) = 4 + sizeof(chunkstruc) = 32 + + sizeof(shorttype ) = 2 + sizeof(idtype ) = 2 + sizeof(sizetype ) = 4 + sizeof(indextype ) = 4 + sizeof(numtype ) = 4 + sizeof(handletype) = 4 + sizeof(tokentype ) = 8 + + sizeof(short ) = 2 + sizeof(int ) = 4 + + sizeof(lt64 ) = 4 + sizeof(farlongtype) = 4 + sizeof(long ) = 4 + sizeof(longaddr ) = 4 + + sizeof(float ) = 4 + sizeof(double ) = 8 + + sizeof(addrtype ) = 4 + sizeof(char * ) = 4 + ALLOC CORE_1 :: 8 + BHOOLE NATH + + OPEN File ./input/bendian.rnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 2030c0 + DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] + DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] + DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] + DB Handle Chunk's StackPtr = 20797 + + DB[ 1] LOADED; Handles= 20797 + KERNEL in CORE[ 1] Restored @ 1b4750 + + OPEN File ./input/bendian.wnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 21c40 + DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] + DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] + DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] + DB Handle Chunk's StackPtr = 17 + + DB[ 2] LOADED; Handles= 17 + VORTEx_Status == -8 || fffffff8 + + BE HERE NOW !!! + + + + ... VORTEx ON LINE ... + + + ... END OF SESSION ... diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.out b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.out new file mode 100644 index 000000000..726b45c60 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.out @@ -0,0 +1,258 @@ + CREATE Db Header and Db Primal ... + NEW DB [ 3] Created. + +VORTEX INPUT PARAMETERS:: + MESSAGE FileName: smred.msg + OUTPUT FileName: smred.out + DISK CACHE FileName: NULL + PART DB FileName: parts.db + DRAW DB FileName: draw.db + PERSON DB FileName: emp.db + PERSONS Data FileName: ./input/persons.250 + PARTS Count : 100 + OUTER Loops : 1 + INNER Loops : 1 + LOOKUP Parts : 25 + DELETE Parts : 10 + STUFF Parts : 10 + DEPTH Traverse: 5 + % DECREASE Parts : 0 + % INCREASE LookUps : 0 + % INCREASE Deletes : 0 + % INCREASE Stuffs : 0 + FREEZE_PACKETS : 1 + ALLOC_CHUNKS : 10000 + EXTEND_CHUNKS : 5000 + DELETE Draw objects : True + DELETE Part objects : False + QUE_BUG : 1000 + VOID_BOUNDARY : 67108864 + VOID_RESERVE : 1048576 + + COMMIT_DBS : False + + + + BMT TEST :: files... + EdbName := PartLib + EdbFileName := parts.db + DrwName := DrawLib + DrwFileName := draw.db + EmpName := PersonLib + EmpFileName := emp.db + + Swap to DiskCache := False + Freeze the cache := True + + + BMT TEST :: parms... + DeBug modulo := 1000 + Create Parts count:= 100 + Outer Loops := 1 + Inner Loops := 1 + Look Ups := 25 + Delete Parts := 10 + Stuff Parts := 10 + Traverse Limit := 5 + Delete Draws := True + Delete Parts := False + Delete ALL Parts := after every <mod 0>Outer Loop + + INITIALIZE LIBRARY :: + + INITIALIZE SCHEMA :: + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 4] Created. + PartLibCreate:: Db[ 4]; VpartsDir= 1 + + Part Count= 1 + + Initialize the Class maps + LIST HEADS loaded ... DbListHead_Class = 207 + DbListNode_Class = 206 + +...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. + + +...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. + + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 5] Created. + DrawLibCreate:: Db[ 5]; VpartsDir= 1 + + Initialize the Class maps of this schema. + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 6] Created. + + ***NOTE*** Persons Library Extended! + + Create <131072> Persons. + ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; + + LAST Person Read:: + ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; + + BUILD <Query0> for <Part2> class:: + + if (link[1].length >= 5) :: + + Build Query2 for <Address> class:: + + if (State == CA || State == T*) + + Build Query1 for <Person> class:: + + if (LastName >= H* && LastName <= P* && Query0(Residence)) :: + + BUILD <Query3> for <DrawObj> class:: + + if (Id >= 3000 + && (Id >= 3000 && Id <= 3001) + && Id >= 3002) + + BUILD <Query4> for <NamedDrawObj> class:: + + if (Nam == Pre* + || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post + || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) + && Id <= 7) + SEED := 1008; Swap = False; RgnEntries = 135 + + OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. + + Create 100 New Parts + Create Part 1. Token[ 4: 2]. + + < 100> Parts Created. CurrentId= 100 + + Connect each instantiated Part TO 3 unique Parts + Connect Part 1. Token[ 4: 2] + Connect Part 25. Token[ 4: 26] FromList= 26. + Connect Part 12. Token[ 4: 13] FromList= 13. + Connect Part 59. Token[ 4: 60] FromList= 60. + + SET <DrawObjs> entries:: + 1. [ 5: 5] := <1 >; @[: 6] + Iteration count = 100 + + SET <NamedDrawObjs> entries:: + 1. [ 5: 39] := <14 >; + Iteration count = 12 + + SET <LibRectangles> entries:: + 1. [ 5: 23] := <8 >; @[: 24] + Iteration count = 12 + + LIST <DbRectangles> entries:: + 1. [ 5: 23] + Iteration count = 12 + + SET <PersonNames > entries:: + Iteration count = 250 + + COMMIT All Image copies:: Release=<True>; Max Parts= 100 + < 100> Part images' Committed. + < 0> are Named. + < 50> Point images' Committed. + < 81> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. TestObj Committed. + < 0> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. CartesianPoint Committed. + < 0> CartesianPoint images' Committed. + + BEGIN Inner Loop Sequence::. + + INNER LOOP [ 1: 1] : + + LOOK UP 25 Random Parts and Export each Part. + + LookUp for 26 parts; Asserts = 8 + <Part2 > Asserts = 2; NULL Asserts = 3. + <DrawObj > Asserts = 0; NULL Asserts = 5. + <NamedObj > Asserts = 0; NULL Asserts = 0. + <Person > Asserts = 0; NULL Asserts = 5. + <TestObj > Asserts = 60; NULL Asserts = 0. + + DELETE 10 Random Parts. + + PartDelete :: Token[ 4: 91]. + PartDisconnect:: Token[ 4: 91] id:= 90 for each link. + DisConnect link [ 0]:= 50; PartToken[ 51: 51]. + DisConnect link [ 1]:= 17; PartToken[ 18: 18]. + DisConnect link [ 2]:= 72; PartToken[ 73: 73]. + DeleteFromList:: Vchunk[ 4: 91]. (* 1) + DisConnect FromList[ 0]:= 56; Token[ 57: 57]. + Vlists[ 89] := 100; + + Delete for 11 parts; + + Traverse Count= 0 + + TRAVERSE PartId[ 6] and all Connections to 5 Levels + SEED In Traverse Part [ 4: 65] @ Level = 4. + + Traverse Count= 357 + Traverse Asserts = 5. True Tests = 1 + < 5> DrawObj objects DELETED. + < 2> are Named. + < 2> Point objects DELETED. + + CREATE 10 Additional Parts + + Create 10 New Parts + Create Part 101. Token[ 4: 102]. + + < 10> Parts Created. CurrentId= 110 + + Connect each instantiated Part TO 3 unique Parts + + COMMIT All Image copies:: Release=<True>; Max Parts= 110 + < 81> Part images' Committed. + < 0> are Named. + < 38> Point images' Committed. + < 31> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Committed. + < 15> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Committed. + < 16> CartesianPoint images' Committed. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Deleted. + < 15> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. + < 16> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + + END INNER LOOP [ 1: 1]. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + < 0> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + < 0> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + STATUS= -201 +V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr new file mode 100644 index 000000000..c0f1c1fbb --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr @@ -0,0 +1,569 @@ +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x1838c0 length 0x10. +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x0 length 0x0. +0: system.remote_gdb.listener: listening for remote gdb on port 7001 +warn: Entering event queue @ 0. Starting simulation... +warn: Ignoring request to flush register windows. +warn: ignoring syscall time(4026527856, 4026528256, ...) +warn: ignoring syscall time(4026527408, 1375098, ...) +warn: ignoring syscall time(4026527320, 1, ...) +warn: ignoring syscall time(4026527056, 413, ...) +warn: ignoring syscall time(4026527056, 414, ...) +warn: ignoring syscall time(4026527296, 4026527696, ...) +warn: ignoring syscall time(4026526848, 1375098, ...) +warn: Increasing stack size by one page. +warn: ignoring syscall time(4026527056, 409, ...) +warn: ignoring syscall time(4026527056, 409, ...) +warn: ignoring syscall time(4026526968, 409, ...) +warn: ignoring syscall time(4026527048, 409, ...) +warn: ignoring syscall time(4026527008, 409, ...) +warn: ignoring syscall time(4026526992, 409, ...) +warn: ignoring syscall time(4026526992, 409, ...) +warn: ignoring syscall time(4026526880, 409, ...) +warn: ignoring syscall time(4026526320, 19045, ...) +warn: ignoring syscall time(4026526840, 409, ...) +warn: ignoring syscall time(4026526880, 409, ...) +warn: ignoring syscall time(4026526880, 409, ...) +warn: ignoring syscall time(4026526856, 409, ...) +warn: ignoring syscall time(4026526848, 409, ...) +warn: ignoring syscall time(4026526880, 409, ...) +warn: ignoring syscall time(4026526864, 409, ...) +warn: ignoring syscall time(4026526856, 409, ...) +warn: ignoring syscall time(4026526944, 409, ...) +warn: ignoring syscall time(4026527016, 4026527416, ...) +warn: ignoring syscall time(4026526568, 1375098, ...) +warn: ignoring syscall time(4026527192, 18732, ...) +warn: ignoring syscall time(4026526640, 409, ...) +warn: ignoring syscall time(4026526744, 0, ...) +warn: ignoring syscall time(4026527328, 0, ...) +warn: ignoring syscall time(4026527752, 225, ...) +warn: ignoring syscall time(4026527056, 409, ...) +warn: ignoring syscall time(4026526864, 409, ...) +warn: ignoring syscall time(4026526880, 409, ...) +warn: ignoring syscall time(4026527104, 4026527504, ...) +warn: ignoring syscall time(4026526656, 1375098, ...) +warn: ignoring syscall time(4026526832, 0, ...) +warn: ignoring syscall time(4026527328, 0, ...) +warn: ignoring syscall time(4026527192, 1879089152, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall time(4026527480, 1595768, ...) +warn: ignoring syscall time(4026526920, 17300, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026526920, 19045, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026526920, 19045, ...) +warn: ignoring syscall time(4026526920, 17300, ...) +warn: ignoring syscall time(4026525976, 20500, ...) +warn: ignoring syscall time(4026525976, 4026526444, ...) +warn: ignoring syscall time(4026526064, 7004192, ...) +warn: ignoring syscall time(4026527520, 4, ...) +warn: ignoring syscall time(4026525768, 0, ...) diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout new file mode 100644 index 000000000..8e5f7bf90 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout @@ -0,0 +1,13 @@ +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 21 2007 00:48:18 +M5 started Wed Mar 21 00:48:40 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic tests/run.py long/50.vortex/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 136246935 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini new file mode 100644 index 000000000..770dac1b9 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -0,0 +1,187 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache icache l2cache toL2Bus workload +clock=1 +cpu_id=0 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +system=system +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=vortex bendian.raw +cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out new file mode 100644 index 000000000..30db17922 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out @@ -0,0 +1,178 @@ +[root] +type=Root +dummy=0 + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 +zero=false + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.workload] +type=LiveProcess +cmd=vortex bendian.raw +executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex +input=cin +output=cout +env= +cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..78f34213e --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt @@ -0,0 +1,230 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 473146 # Simulator instruction rate (inst/s) +host_mem_usage 156372 # Number of bytes of host memory used +host_seconds 287.96 # Real time elapsed on the host +host_tick_rate 4801122 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 136246936 # Number of instructions simulated +sim_seconds 0.001383 # Number of seconds simulated +sim_ticks 1382530003 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3575.086285 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2575.086285 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 37185812 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 162627100 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 45489 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 117138100 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 45489 # number of ReadReq MSHR misses +system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_avg_miss_latency 3413.933333 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2413.933333 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 15901 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 51209 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.000942 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 15 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 36209 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.000942 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 15 # number of SwapReq MSHR misses +system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 4579.703729 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3579.703729 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 20759130 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 481665760 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.005041 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 105174 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 376491760 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005041 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 105174 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4276.384116 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3276.384116 # average overall mshr miss latency +system.cpu.dcache.demand_hits 57944942 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 644292860 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002593 # miss rate for demand accesses +system.cpu.dcache.demand_misses 150663 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 493629860 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002593 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 150663 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4276.384116 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3276.384116 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 57944942 # number of overall hits +system.cpu.dcache.overall_miss_latency 644292860 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002593 # miss rate for overall accesses +system.cpu.dcache.overall_misses 150663 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 493629860 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002593 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 150663 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 146582 # number of replacements +system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4060.510189 # Cycle average of tags in use +system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 33018000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 107279 # number of writebacks +system.cpu.icache.ReadReq_accesses 136246937 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2909.600795 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1909.600795 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 136059913 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 544165179 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.001373 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 357141179 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.001373 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 727.499749 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 136246937 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2909.600795 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1909.600795 # average overall mshr miss latency +system.cpu.icache.demand_hits 136059913 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 544165179 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.001373 # miss rate for demand accesses +system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 357141179 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.001373 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 136246937 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2909.600795 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1909.600795 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 136059913 # number of overall hits +system.cpu.icache.overall_miss_latency 544165179 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.001373 # miss rate for overall accesses +system.cpu.icache.overall_misses 187024 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 357141179 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.001373 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 184976 # number of replacements +system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1952.728312 # Cycle average of tags in use +system.cpu.icache.total_refs 136059913 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 1000315000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadReq_accesses 337636 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3564.034868 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1961.482636 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 202957 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 480000652 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.398888 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 134679 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 264170520 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.398888 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 134679 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 106771 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.004735 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 508 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.004735 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 508 # number of Writeback MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 2.299750 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 337636 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3564.034868 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1961.482636 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 202957 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 480000652 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.398888 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 134679 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 264170520 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.398888 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 134679 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 444915 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3550.642088 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1961.482636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 309728 # number of overall hits +system.cpu.l2cache.overall_miss_latency 480000652 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.303849 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 135187 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 264170520 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.302707 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 134679 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 101911 # number of replacements +system.cpu.l2cache.sampled_refs 134679 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 30685.350019 # Cycle average of tags in use +system.cpu.l2cache.total_refs 309728 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 319451000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 82918 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1382530003 # number of cpu cycles simulated +system.cpu.num_insts 136246936 # Number of instructions executed +system.cpu.num_refs 58111522 # Number of memory references +system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.msg b/tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.msg new file mode 100644 index 000000000..0ac2d9980 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.msg @@ -0,0 +1,158 @@ + + SYSTEM TYPE... + __ZTC__ := False + __UNIX__ := True + __RISC__ := True + SPEC_CPU2000_LP64 := False + __MAC__ := False + __BCC__ := False + __BORLANDC__ := False + __GUI__ := False + __WTC__ := False + __HP__ := False + + CODE OPTIONS... + __MACROIZE_HM__ := True + __MACROIZE_MEM__ := True + ENV01 := True + USE_HPP_STYPE_HDRS := False + USE_H_STYPE_HDRS := False + + CODE INCLUSION PARAMETERS... + INCLUDE_ALL_CODE := False + INCLUDE_DELETE_CODE := True + __SWAP_GRP_POS__ := True + __INCLUDE_MTRX__ := False + __BAD_CODE__ := False + API_INCLUDE := False + BE_CAREFUL := False + OLDWAY := False + NOTUSED := False + + SYSTEM PARAMETERS... + EXT_ENUM := 999999999L + CHUNK_CONSTANT := 55555555 + CORE_CONSTANT := 55555555 + CORE_LIMIT := 20971520 + CorePage_Size := 384000 + ALIGN_BYTES := True + CORE_BLOCK_ALIGN := 8 + FAR_MEM := False + + MEMORY MANAGEMENT PARAMETERS... + SYSTEM_ALLOC := True + SYSTEM_FREESTORE := True + __NO_DISKCACHE__ := False + __FREEZE_VCHUNKS__ := True + __FREEZE_GRP_PACKETS__ := True + __MINIMIZE_TREE_CACHE__:= True + + SYSTEM STD PARAMETERS... + __STDOUT__ := False + NULL := 0 + LPTR := False + False_Status := 1 + True_Status := 0 + LARGE := True + TWOBYTE_BOOL := False + __NOSTR__ := False + + MEMORY VALIDATION PARAMETERS... + CORE_CRC_CHECK := False + VALIDATE_MEM_CHUNKS := False + + SYSTEM DEBUG OPTIONS... + DEBUG := False + MCSTAT := False + TRACKBACK := False + FLUSH_FILES := False + DEBUG_CORE0 := False + DEBUG_RISC := False + __TREE_BUG__ := False + __TRACK_FILE_READS__ := False + PAGE_SPACE := False + LEAVE_NO_TRACE := True + NULL_TRACE_STRS := False + + TIME PARAMETERS... + CLOCK_IS_LONG := False + __DISPLAY_TIME__ := False + __TREE_TIME__ := False + __DISPLAY_ERRORS__ := False + + API MACROS... + __BMT01__ := True + OPTIMIZE := True + + END OF DEFINES. + + + + ... IMPLODE MEMORY ... + + SWAP to DiskCache := False + + FREEZE_GRP_PACKETS:= True + + QueBug := 1000 + + sizeof(boolean) = 4 + sizeof(sizetype) = 4 + sizeof(chunkstruc) = 32 + + sizeof(shorttype ) = 2 + sizeof(idtype ) = 2 + sizeof(sizetype ) = 4 + sizeof(indextype ) = 4 + sizeof(numtype ) = 4 + sizeof(handletype) = 4 + sizeof(tokentype ) = 8 + + sizeof(short ) = 2 + sizeof(int ) = 4 + + sizeof(lt64 ) = 4 + sizeof(farlongtype) = 4 + sizeof(long ) = 4 + sizeof(longaddr ) = 4 + + sizeof(float ) = 4 + sizeof(double ) = 8 + + sizeof(addrtype ) = 4 + sizeof(char * ) = 4 + ALLOC CORE_1 :: 8 + BHOOLE NATH + + OPEN File ./input/bendian.rnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 2030c0 + DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] + DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] + DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] + DB Handle Chunk's StackPtr = 20797 + + DB[ 1] LOADED; Handles= 20797 + KERNEL in CORE[ 1] Restored @ 1b4750 + + OPEN File ./input/bendian.wnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 21c40 + DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] + DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] + DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] + DB Handle Chunk's StackPtr = 17 + + DB[ 2] LOADED; Handles= 17 + VORTEx_Status == -8 || fffffff8 + + BE HERE NOW !!! + + + + ... VORTEx ON LINE ... + + + ... END OF SESSION ... diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.out b/tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.out new file mode 100644 index 000000000..726b45c60 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.out @@ -0,0 +1,258 @@ + CREATE Db Header and Db Primal ... + NEW DB [ 3] Created. + +VORTEX INPUT PARAMETERS:: + MESSAGE FileName: smred.msg + OUTPUT FileName: smred.out + DISK CACHE FileName: NULL + PART DB FileName: parts.db + DRAW DB FileName: draw.db + PERSON DB FileName: emp.db + PERSONS Data FileName: ./input/persons.250 + PARTS Count : 100 + OUTER Loops : 1 + INNER Loops : 1 + LOOKUP Parts : 25 + DELETE Parts : 10 + STUFF Parts : 10 + DEPTH Traverse: 5 + % DECREASE Parts : 0 + % INCREASE LookUps : 0 + % INCREASE Deletes : 0 + % INCREASE Stuffs : 0 + FREEZE_PACKETS : 1 + ALLOC_CHUNKS : 10000 + EXTEND_CHUNKS : 5000 + DELETE Draw objects : True + DELETE Part objects : False + QUE_BUG : 1000 + VOID_BOUNDARY : 67108864 + VOID_RESERVE : 1048576 + + COMMIT_DBS : False + + + + BMT TEST :: files... + EdbName := PartLib + EdbFileName := parts.db + DrwName := DrawLib + DrwFileName := draw.db + EmpName := PersonLib + EmpFileName := emp.db + + Swap to DiskCache := False + Freeze the cache := True + + + BMT TEST :: parms... + DeBug modulo := 1000 + Create Parts count:= 100 + Outer Loops := 1 + Inner Loops := 1 + Look Ups := 25 + Delete Parts := 10 + Stuff Parts := 10 + Traverse Limit := 5 + Delete Draws := True + Delete Parts := False + Delete ALL Parts := after every <mod 0>Outer Loop + + INITIALIZE LIBRARY :: + + INITIALIZE SCHEMA :: + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 4] Created. + PartLibCreate:: Db[ 4]; VpartsDir= 1 + + Part Count= 1 + + Initialize the Class maps + LIST HEADS loaded ... DbListHead_Class = 207 + DbListNode_Class = 206 + +...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. + + +...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. + + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 5] Created. + DrawLibCreate:: Db[ 5]; VpartsDir= 1 + + Initialize the Class maps of this schema. + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 6] Created. + + ***NOTE*** Persons Library Extended! + + Create <131072> Persons. + ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; + + LAST Person Read:: + ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; + + BUILD <Query0> for <Part2> class:: + + if (link[1].length >= 5) :: + + Build Query2 for <Address> class:: + + if (State == CA || State == T*) + + Build Query1 for <Person> class:: + + if (LastName >= H* && LastName <= P* && Query0(Residence)) :: + + BUILD <Query3> for <DrawObj> class:: + + if (Id >= 3000 + && (Id >= 3000 && Id <= 3001) + && Id >= 3002) + + BUILD <Query4> for <NamedDrawObj> class:: + + if (Nam == Pre* + || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post + || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) + && Id <= 7) + SEED := 1008; Swap = False; RgnEntries = 135 + + OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. + + Create 100 New Parts + Create Part 1. Token[ 4: 2]. + + < 100> Parts Created. CurrentId= 100 + + Connect each instantiated Part TO 3 unique Parts + Connect Part 1. Token[ 4: 2] + Connect Part 25. Token[ 4: 26] FromList= 26. + Connect Part 12. Token[ 4: 13] FromList= 13. + Connect Part 59. Token[ 4: 60] FromList= 60. + + SET <DrawObjs> entries:: + 1. [ 5: 5] := <1 >; @[: 6] + Iteration count = 100 + + SET <NamedDrawObjs> entries:: + 1. [ 5: 39] := <14 >; + Iteration count = 12 + + SET <LibRectangles> entries:: + 1. [ 5: 23] := <8 >; @[: 24] + Iteration count = 12 + + LIST <DbRectangles> entries:: + 1. [ 5: 23] + Iteration count = 12 + + SET <PersonNames > entries:: + Iteration count = 250 + + COMMIT All Image copies:: Release=<True>; Max Parts= 100 + < 100> Part images' Committed. + < 0> are Named. + < 50> Point images' Committed. + < 81> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. TestObj Committed. + < 0> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. CartesianPoint Committed. + < 0> CartesianPoint images' Committed. + + BEGIN Inner Loop Sequence::. + + INNER LOOP [ 1: 1] : + + LOOK UP 25 Random Parts and Export each Part. + + LookUp for 26 parts; Asserts = 8 + <Part2 > Asserts = 2; NULL Asserts = 3. + <DrawObj > Asserts = 0; NULL Asserts = 5. + <NamedObj > Asserts = 0; NULL Asserts = 0. + <Person > Asserts = 0; NULL Asserts = 5. + <TestObj > Asserts = 60; NULL Asserts = 0. + + DELETE 10 Random Parts. + + PartDelete :: Token[ 4: 91]. + PartDisconnect:: Token[ 4: 91] id:= 90 for each link. + DisConnect link [ 0]:= 50; PartToken[ 51: 51]. + DisConnect link [ 1]:= 17; PartToken[ 18: 18]. + DisConnect link [ 2]:= 72; PartToken[ 73: 73]. + DeleteFromList:: Vchunk[ 4: 91]. (* 1) + DisConnect FromList[ 0]:= 56; Token[ 57: 57]. + Vlists[ 89] := 100; + + Delete for 11 parts; + + Traverse Count= 0 + + TRAVERSE PartId[ 6] and all Connections to 5 Levels + SEED In Traverse Part [ 4: 65] @ Level = 4. + + Traverse Count= 357 + Traverse Asserts = 5. True Tests = 1 + < 5> DrawObj objects DELETED. + < 2> are Named. + < 2> Point objects DELETED. + + CREATE 10 Additional Parts + + Create 10 New Parts + Create Part 101. Token[ 4: 102]. + + < 10> Parts Created. CurrentId= 110 + + Connect each instantiated Part TO 3 unique Parts + + COMMIT All Image copies:: Release=<True>; Max Parts= 110 + < 81> Part images' Committed. + < 0> are Named. + < 38> Point images' Committed. + < 31> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Committed. + < 15> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Committed. + < 16> CartesianPoint images' Committed. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Deleted. + < 15> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. + < 16> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + + END INNER LOOP [ 1: 1]. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + < 0> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + < 0> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + STATUS= -201 +V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr new file mode 100644 index 000000000..c0f1c1fbb --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr @@ -0,0 +1,569 @@ +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x1838c0 length 0x10. +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x0 length 0x0. +0: system.remote_gdb.listener: listening for remote gdb on port 7001 +warn: Entering event queue @ 0. Starting simulation... +warn: Ignoring request to flush register windows. +warn: ignoring syscall time(4026527856, 4026528256, ...) +warn: ignoring syscall time(4026527408, 1375098, ...) +warn: ignoring syscall time(4026527320, 1, ...) +warn: ignoring syscall time(4026527056, 413, ...) +warn: ignoring syscall time(4026527056, 414, ...) +warn: ignoring syscall time(4026527296, 4026527696, ...) +warn: ignoring syscall time(4026526848, 1375098, ...) +warn: Increasing stack size by one page. +warn: ignoring syscall time(4026527056, 409, ...) +warn: ignoring syscall time(4026527056, 409, ...) +warn: ignoring syscall time(4026526968, 409, ...) +warn: ignoring syscall time(4026527048, 409, ...) +warn: ignoring syscall time(4026527008, 409, ...) +warn: ignoring syscall time(4026526992, 409, ...) +warn: ignoring syscall time(4026526992, 409, ...) +warn: ignoring syscall time(4026526880, 409, ...) +warn: ignoring syscall time(4026526320, 19045, ...) +warn: ignoring syscall time(4026526840, 409, ...) +warn: ignoring syscall time(4026526880, 409, ...) +warn: ignoring syscall time(4026526880, 409, ...) +warn: ignoring syscall time(4026526856, 409, ...) +warn: ignoring syscall time(4026526848, 409, ...) +warn: ignoring syscall time(4026526880, 409, ...) +warn: ignoring syscall time(4026526864, 409, ...) +warn: ignoring syscall time(4026526856, 409, ...) +warn: ignoring syscall time(4026526944, 409, ...) +warn: ignoring syscall time(4026527016, 4026527416, ...) +warn: ignoring syscall time(4026526568, 1375098, ...) +warn: ignoring syscall time(4026527192, 18732, ...) +warn: ignoring syscall time(4026526640, 409, ...) +warn: ignoring syscall time(4026526744, 0, ...) +warn: ignoring syscall time(4026527328, 0, ...) +warn: ignoring syscall time(4026527752, 225, ...) +warn: ignoring syscall time(4026527056, 409, ...) +warn: ignoring syscall time(4026526864, 409, ...) +warn: ignoring syscall time(4026526880, 409, ...) +warn: ignoring syscall time(4026527104, 4026527504, ...) +warn: ignoring syscall time(4026526656, 1375098, ...) +warn: ignoring syscall time(4026526832, 0, ...) +warn: ignoring syscall time(4026527328, 0, ...) +warn: ignoring syscall time(4026527192, 1879089152, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall time(4026527480, 1595768, ...) +warn: ignoring syscall time(4026526920, 17300, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026526920, 19045, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026526920, 19045, ...) +warn: ignoring syscall time(4026526920, 17300, ...) +warn: ignoring syscall time(4026525976, 20500, ...) +warn: ignoring syscall time(4026525976, 4026526444, ...) +warn: ignoring syscall time(4026526064, 7004192, ...) +warn: ignoring syscall time(4026527520, 4, ...) +warn: ignoring syscall time(4026525768, 0, ...) diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout new file mode 100644 index 000000000..dc2b61804 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout @@ -0,0 +1,13 @@ +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 29 2007 03:55:17 +M5 started Thu Mar 29 03:55:38 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1382530003 because target called exit() diff --git a/tests/long/50.vortex/test.py b/tests/long/50.vortex/test.py index bd57ef6e6..fbf0dc081 100644 --- a/tests/long/50.vortex/test.py +++ b/tests/long/50.vortex/test.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -29,5 +29,5 @@ m5.AddToPath('../configs/common') from cpu2000 import vortex -workload = vortex('alpha', 'tru64', 'smred') +workload = vortex(isa, opsys, 'smred') root.system.cpu.workload = workload.makeLiveProcess() diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 9ae62655d..9ae62655d 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out index 690cc5723..690cc5723 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt index bc6866525..bc6866525 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr index cdd59eda7..cdd59eda7 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout index 0c5c00118..0c5c00118 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini index ad57a5293..ad57a5293 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out index 891519c26..891519c26 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt index 7422e3ae7..7422e3ae7 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr index 87866a2a5..87866a2a5 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout index 0c5c00118..0c5c00118 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 0a123d4a4..0a123d4a4 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out index 4692c5d40..4692c5d40 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt index 45b7beb7c..45b7beb7c 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr index 87866a2a5..87866a2a5 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout index 0c5c00118..0c5c00118 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout diff --git a/tests/long/60.bzip2/test.py b/tests/long/60.bzip2/test.py index 362ca524e..7fa3d1a07 100644 --- a/tests/long/60.bzip2/test.py +++ b/tests/long/60.bzip2/test.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -29,5 +29,5 @@ m5.AddToPath('../configs/common') from cpu2000 import bzip2_source -workload = bzip2_source('alpha', 'tru64', 'lgred') +workload = bzip2_source(isa, opsys, 'lgred') root.system.cpu.workload = workload.makeLiveProcess() diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 5604f880f..5604f880f 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out index a78c52d7f..a78c52d7f 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt index c77face31..c77face31 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.out b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out index 00387ae5c..00387ae5c 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.out +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pin b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pin index 62b922e4e..62b922e4e 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pin +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pin diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl1 b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 index bdc569e39..bdc569e39 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl1 +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl2 b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 index 6e2601e82..6e2601e82 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl2 +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sav b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sav index 04c8e9935..04c8e9935 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sav +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sav diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sv2 b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 index 9dd68ecdb..9dd68ecdb 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sv2 +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.twf b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.twf index a4c2eac35..a4c2eac35 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.twf +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.twf diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr index eb1796ead..eb1796ead 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout index f32f0a972..f32f0a972 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index 789f77815..789f77815 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out index b4087eb1c..b4087eb1c 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt index 2cd5a06bf..2cd5a06bf 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.out b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out index 00387ae5c..00387ae5c 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pin b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin index 62b922e4e..62b922e4e 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pin +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl1 b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 index bdc569e39..bdc569e39 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl1 +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl2 b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 index 6e2601e82..6e2601e82 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl2 +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sav b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav index 04c8e9935..04c8e9935 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sav +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sv2 b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 index 9dd68ecdb..9dd68ecdb 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sv2 +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.twf b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf index a4c2eac35..a4c2eac35 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.twf +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr index eb1796ead..eb1796ead 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout index f32f0a972..f32f0a972 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index e2265235e..e2265235e 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out index fcf06c7db..fcf06c7db 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt index 5cdae9c4a..5cdae9c4a 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.out b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out index 00387ae5c..00387ae5c 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pin b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pin index 62b922e4e..62b922e4e 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pin +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pin diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl1 b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 index bdc569e39..bdc569e39 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl1 +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl2 b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 index 6e2601e82..6e2601e82 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl2 +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sav b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sav index 04c8e9935..04c8e9935 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sav +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sav diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sv2 b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 index 9dd68ecdb..9dd68ecdb 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sv2 +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.twf b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.twf index a4c2eac35..a4c2eac35 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.twf +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.twf diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr index eb1796ead..eb1796ead 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout index f32f0a972..f32f0a972 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini new file mode 100644 index 000000000..2a1613fa1 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -0,0 +1,64 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=workload +clock=1 +cpu_id=0 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +simulate_stalls=false +system=system +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out new file mode 100644 index 000000000..d24c09793 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out @@ -0,0 +1,57 @@ +[root] +type=Root +dummy=0 + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 +zero=false + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf +input=cin +output=cout +env= +cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt new file mode 100644 index 000000000..45fd6b479 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 676464 # Simulator instruction rate (inst/s) +host_mem_usage 149916 # Number of bytes of host memory used +host_seconds 285.95 # Real time elapsed on the host +host_tick_rate 676463 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 193435973 # Number of instructions simulated +sim_seconds 0.000193 # Number of seconds simulated +sim_ticks 193435972 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 193435973 # number of cpu cycles simulated +system.cpu.num_insts 193435973 # Number of instructions executed +system.cpu.num_refs 76732959 # Number of memory references +system.cpu.workload.PROG:num_syscalls 396 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.out b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.out new file mode 100644 index 000000000..00387ae5c --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.out @@ -0,0 +1,276 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + + +NOTE: Restart file .rs2 not used + +TimberWolf will perform a global route step +rowSep: 1.000000 +feedThruWidth: 4 + +****************** +BLOCK DATA +block:1 desire:85 +block:2 desire:85 +Total Desired Length: 170 +total cell length: 168 +total block length: 168 +block x-span:84 block y-span:78 +implicit feed thru range: -84 +Using default value of bin.penalty.control:1.000000 +numBins automatically set to:5 +binWidth = average_cell_width + 0 sigma= 17 +average_cell_width is:16 +standard deviation of cell length is:23.6305 +TimberWolfSC starting from the beginning + + + +THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 +The number of nets with 1 pin is 4 +The number of nets with 2 pin is 9 +The number of nets with 3 pin is 0 +The number of nets with 4 pin is 2 +The number of nets with 5 pin is 0 +The number of nets with 6 pin is 0 +The number of nets with 7 pin is 0 +The number of nets with 8 pin is 0 +The number of nets with 9 pin is 0 +The number of nets with 10 pin or more is 0 + +New Cost Function: Initial Horizontal Cost:242 +New Cost Function: FEEDS:0 MISSING_ROWS:-46 + +bdxlen:86 bdylen:78 +l:0 t:78 r:86 b:0 + + + +THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 + + + +THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 + +The rand generator seed was at utemp() : 1 + + + tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 + tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 + tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 + tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 + + I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs + 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 + 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 + 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 + 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 + 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 + 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 + 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 + 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 + 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 + 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 + 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 + 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 + 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 + 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 + 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 + 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 + 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 + 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 + 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 + 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 + 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 + 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 + 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 + 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 + 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 + 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 + 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 + 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 + 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 + 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 + 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 + 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 + 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 + 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 + 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 + 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 + 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 + 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 + 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 + 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 + 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 + 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 + 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 + 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 + 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 + 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 + 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 + 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 + 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 + 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 + 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 + 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 + 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 + 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 + 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 + 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 + 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 + 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 + 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 + 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 + 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 + 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 + 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 + 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 + 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 + 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 + 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 + 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 + 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 + 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 + 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 + 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 + 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 + 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 + 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 + 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 + 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 + 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 + 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 + 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 + 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 + 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 + 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 + 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 + 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 + 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 + 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 + 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 + 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 + 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 + 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 + 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 + 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 + 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 + 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 +100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 +101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 +102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 +103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 +104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 +105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 +106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 +107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 +108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 +109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 +110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 +111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 +112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 +113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 +114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 +115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 +116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 +117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 +118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 +119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 +120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 +121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 + +Initial Wiring Cost: 645 Final Wiring Cost: 732 +############## Percent Wire Cost Reduction: -13 + + +Initial Wire Length: 645 Final Wire Length: 732 +************** Percent Wire Length Reduction: -13 + + +Initial Horiz. Wire: 216 Final Horiz. Wire: 147 +$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 + + +Initial Vert. Wire: 429 Final Vert. Wire: 585 +@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 + +Before Feeds are Added: +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 82 -20 + 2 86 -16 + +LONGEST Block is:2 Its length is:86 +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 86 -16 + 2 86 -16 + +LONGEST Block is:1 Its length is:86 +Added: 1 feed-through cells + +Removed the cell overlaps --- Will do neighbor interchanges only now + +TOTAL INTERCONNECT LENGTH: 994 +OVERLAP PENALTY: 0 + +initialRowControl: 1.650 +finalRowControl: 0.300 +iter T Wire accept + 122 0.001 976 16% + 123 0.001 971 0% + 124 0.001 971 0% +Total Feed-Alignment Movement (Pass 1): 0 +Total Feed-Alignment Movement (Pass 2): 0 +Total Feed-Alignment Movement (Pass 3): 0 +Total Feed-Alignment Movement (Pass 4): 0 +Total Feed-Alignment Movement (Pass 5): 0 +Total Feed-Alignment Movement (Pass 6): 0 +Total Feed-Alignment Movement (Pass 7): 0 +Total Feed-Alignment Movement (Pass 8): 0 + +The rand generator seed was at globroute() : 987654321 + + +Total Number of Net Segments: 9 +Number of Switchable Net Segments: 0 + +Number of channels: 3 + + + +THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 + + +no. of accepted flips: 0 +no. of attempted flips: 0 +THIS IS THE NUMBER OF TRACKS: 5 + + + +FINAL NUMBER OF ROUTING TRACKS: 5 + +MAX OF CHANNEL: 1 is: 0 +MAX OF CHANNEL: 2 is: 4 +MAX OF CHANNEL: 3 is: 1 +FINAL TOTAL INTERCONNECT LENGTH: 978 +FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 +MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 + + +cost_scale_factor:3.90616 + +Number of Feed Thrus: 0 +Number of Implicit Feed Thrus: 0 + +Statistics: +Number of Standard Cells: 10 +Number of Pads: 0 +Number of Nets: 15 +Number of Pins: 46 +Usage statistics not available diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pin b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pin new file mode 100644 index 000000000..62b922e4e --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pin @@ -0,0 +1,17 @@ +$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 +$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 +B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 +B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 +B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1 b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1 new file mode 100644 index 000000000..bdc569e39 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1 @@ -0,0 +1,11 @@ +$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 +$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 +$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 +ACOUNT_1 14 0 18 26 2 1 +twfeed1 18 0 22 26 0 1 +$COUNT_1/$FJK3_1 22 0 86 26 0 1 +$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 +$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 +$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 +$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 +$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2 b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2 new file mode 100644 index 000000000..6e2601e82 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2 @@ -0,0 +1,2 @@ +1 0 0 86 26 0 0 +2 0 52 86 78 0 0 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sav b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sav new file mode 100644 index 000000000..04c8e9935 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sav @@ -0,0 +1,18 @@ +0.009592 +121 +0 +1 +0.000000 +0.500000 +3.906156 +1 +1 1 2 37 13 +2 2 0 34 65 +3 2 2 63 65 +4 1 0 59 13 +5 1 2 32 13 +6 2 0 23 65 +7 1 2 12 13 +8 2 0 6 65 +9 1 0 70 13 +10 2 0 70 65 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2 b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2 new file mode 100644 index 000000000..9dd68ecdb --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2 @@ -0,0 +1,19 @@ +0.001000 +123 +0 +2 +0.000000 +0.500000 +3.906156 +1 +1 1 2 16 13 +2 2 2 19 65 +3 2 2 14 65 +4 1 0 11 13 +5 1 2 6 13 +6 2 0 3 65 +7 1 0 2 13 +8 2 2 9 65 +9 1 0 50 13 +10 2 0 54 65 +11 1 0 84 13 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.twf b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.twf new file mode 100644 index 000000000..a4c2eac35 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.twf @@ -0,0 +1,29 @@ +net 1 +segment channel 2 + pin1 1 pin2 7 0 0 +net 2 +segment channel 3 +pin1 41 pin2 42 0 0 +segment channel 2 +pin1 12 pin2 3 0 0 +net 3 +segment channel 2 +pin1 35 pin2 36 0 0 +segment channel 2 +pin1 19 pin2 35 0 0 +net 4 +segment channel 2 + pin1 5 pin2 38 0 0 +net 5 +net 7 +segment channel 2 + pin1 14 pin2 43 0 0 +net 8 +segment channel 2 + pin1 23 pin2 17 0 0 +net 9 +net 11 +segment channel 2 + pin1 25 pin2 31 0 0 +net 14 +net 15 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr new file mode 100644 index 000000000..94662b6e8 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr @@ -0,0 +1,8 @@ +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x11e394 length 0x10. +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x0 length 0x0. +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... +warn: Ignoring request to flush register windows. +warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout new file mode 100644 index 000000000..7c0e5ba5f --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout @@ -0,0 +1,28 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 12 2007 16:53:49 +M5 started Mon Mar 12 17:37:07 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 193435972 because target called exit() diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini new file mode 100644 index 000000000..0e057cbbe --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -0,0 +1,187 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache icache l2cache toL2Bus workload +clock=1 +cpu_id=0 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +system=system +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out new file mode 100644 index 000000000..5f60c76d0 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out @@ -0,0 +1,178 @@ +[root] +type=Root +dummy=0 + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 +zero=false + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf +input=cin +output=cout +env= +cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..2fbdef851 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt @@ -0,0 +1,226 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 471554 # Simulator instruction rate (inst/s) +host_mem_usage 155352 # Number of bytes of host memory used +host_seconds 410.21 # Real time elapsed on the host +host_tick_rate 766692 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 193435973 # Number of instructions simulated +sim_seconds 0.000315 # Number of seconds simulated +sim_ticks 314505003 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 57734138 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3705.925703 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2705.925703 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 57733640 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1845551 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 1347551 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses +system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_avg_miss_latency 3995 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2995 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 22405 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 3995 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.000045 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 1 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 2995 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.000045 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses +system.cpu.dcache.WriteReq_accesses 18976414 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3678.678637 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2678.678637 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 18975328 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3995045 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000057 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1086 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 2909045 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000057 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1086 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 48410.960883 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 76710552 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3687.244949 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2687.244949 # average overall mshr miss latency +system.cpu.dcache.demand_hits 76708968 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 5840596 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1584 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4256596 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1584 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 76710552 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3687.244949 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2687.244949 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 76708968 # number of overall hits +system.cpu.dcache.overall_miss_latency 5840596 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1584 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4256596 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1584 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 26 # number of replacements +system.cpu.dcache.sampled_refs 1585 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 1216.403972 # Cycle average of tags in use +system.cpu.dcache.total_refs 76731373 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 23 # number of writebacks +system.cpu.icache.ReadReq_accesses 193435974 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3138.680633 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2138.680633 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 193423706 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 38505334 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 12268 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 26237334 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000063 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 12268 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 15766.523150 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 193435974 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3138.680633 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2138.680633 # average overall mshr miss latency +system.cpu.icache.demand_hits 193423706 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 38505334 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses +system.cpu.icache.demand_misses 12268 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 26237334 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000063 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 12268 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 193435974 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3138.680633 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2138.680633 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 193423706 # number of overall hits +system.cpu.icache.overall_miss_latency 38505334 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses +system.cpu.icache.overall_misses 12268 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 26237334 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000063 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 12268 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 10342 # number of replacements +system.cpu.icache.sampled_refs 12268 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1567.271345 # Cycle average of tags in use +system.cpu.icache.total_refs 193423706 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadReq_accesses 13852 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2847.598413 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1846.400619 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 8685 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 14713541 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.373015 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 5167 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 9540352 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.373015 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 5167 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 23 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 1.685311 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 13852 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2847.598413 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1846.400619 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 8685 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 14713541 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.373015 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5167 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 9540352 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.373015 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5167 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 13875 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2847.598413 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1846.400619 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 8708 # number of overall hits +system.cpu.l2cache.overall_miss_latency 14713541 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.372396 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5167 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 9540352 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.372396 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5167 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 5167 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 3448.701925 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8708 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 314505003 # number of cpu cycles simulated +system.cpu.num_insts 193435973 # Number of instructions executed +system.cpu.num_refs 76732959 # Number of memory references +system.cpu.workload.PROG:num_syscalls 396 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.out b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.out new file mode 100644 index 000000000..00387ae5c --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.out @@ -0,0 +1,276 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + + +NOTE: Restart file .rs2 not used + +TimberWolf will perform a global route step +rowSep: 1.000000 +feedThruWidth: 4 + +****************** +BLOCK DATA +block:1 desire:85 +block:2 desire:85 +Total Desired Length: 170 +total cell length: 168 +total block length: 168 +block x-span:84 block y-span:78 +implicit feed thru range: -84 +Using default value of bin.penalty.control:1.000000 +numBins automatically set to:5 +binWidth = average_cell_width + 0 sigma= 17 +average_cell_width is:16 +standard deviation of cell length is:23.6305 +TimberWolfSC starting from the beginning + + + +THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 +The number of nets with 1 pin is 4 +The number of nets with 2 pin is 9 +The number of nets with 3 pin is 0 +The number of nets with 4 pin is 2 +The number of nets with 5 pin is 0 +The number of nets with 6 pin is 0 +The number of nets with 7 pin is 0 +The number of nets with 8 pin is 0 +The number of nets with 9 pin is 0 +The number of nets with 10 pin or more is 0 + +New Cost Function: Initial Horizontal Cost:242 +New Cost Function: FEEDS:0 MISSING_ROWS:-46 + +bdxlen:86 bdylen:78 +l:0 t:78 r:86 b:0 + + + +THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 + + + +THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 + +The rand generator seed was at utemp() : 1 + + + tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 + tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 + tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 + tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 + + I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs + 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 + 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 + 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 + 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 + 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 + 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 + 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 + 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 + 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 + 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 + 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 + 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 + 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 + 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 + 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 + 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 + 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 + 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 + 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 + 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 + 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 + 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 + 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 + 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 + 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 + 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 + 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 + 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 + 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 + 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 + 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 + 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 + 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 + 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 + 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 + 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 + 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 + 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 + 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 + 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 + 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 + 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 + 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 + 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 + 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 + 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 + 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 + 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 + 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 + 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 + 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 + 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 + 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 + 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 + 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 + 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 + 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 + 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 + 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 + 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 + 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 + 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 + 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 + 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 + 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 + 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 + 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 + 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 + 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 + 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 + 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 + 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 + 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 + 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 + 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 + 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 + 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 + 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 + 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 + 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 + 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 + 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 + 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 + 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 + 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 + 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 + 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 + 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 + 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 + 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 + 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 + 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 + 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 + 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 + 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 +100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 +101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 +102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 +103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 +104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 +105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 +106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 +107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 +108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 +109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 +110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 +111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 +112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 +113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 +114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 +115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 +116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 +117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 +118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 +119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 +120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 +121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 + +Initial Wiring Cost: 645 Final Wiring Cost: 732 +############## Percent Wire Cost Reduction: -13 + + +Initial Wire Length: 645 Final Wire Length: 732 +************** Percent Wire Length Reduction: -13 + + +Initial Horiz. Wire: 216 Final Horiz. Wire: 147 +$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 + + +Initial Vert. Wire: 429 Final Vert. Wire: 585 +@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 + +Before Feeds are Added: +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 82 -20 + 2 86 -16 + +LONGEST Block is:2 Its length is:86 +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 86 -16 + 2 86 -16 + +LONGEST Block is:1 Its length is:86 +Added: 1 feed-through cells + +Removed the cell overlaps --- Will do neighbor interchanges only now + +TOTAL INTERCONNECT LENGTH: 994 +OVERLAP PENALTY: 0 + +initialRowControl: 1.650 +finalRowControl: 0.300 +iter T Wire accept + 122 0.001 976 16% + 123 0.001 971 0% + 124 0.001 971 0% +Total Feed-Alignment Movement (Pass 1): 0 +Total Feed-Alignment Movement (Pass 2): 0 +Total Feed-Alignment Movement (Pass 3): 0 +Total Feed-Alignment Movement (Pass 4): 0 +Total Feed-Alignment Movement (Pass 5): 0 +Total Feed-Alignment Movement (Pass 6): 0 +Total Feed-Alignment Movement (Pass 7): 0 +Total Feed-Alignment Movement (Pass 8): 0 + +The rand generator seed was at globroute() : 987654321 + + +Total Number of Net Segments: 9 +Number of Switchable Net Segments: 0 + +Number of channels: 3 + + + +THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 + + +no. of accepted flips: 0 +no. of attempted flips: 0 +THIS IS THE NUMBER OF TRACKS: 5 + + + +FINAL NUMBER OF ROUTING TRACKS: 5 + +MAX OF CHANNEL: 1 is: 0 +MAX OF CHANNEL: 2 is: 4 +MAX OF CHANNEL: 3 is: 1 +FINAL TOTAL INTERCONNECT LENGTH: 978 +FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 +MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 + + +cost_scale_factor:3.90616 + +Number of Feed Thrus: 0 +Number of Implicit Feed Thrus: 0 + +Statistics: +Number of Standard Cells: 10 +Number of Pads: 0 +Number of Nets: 15 +Number of Pins: 46 +Usage statistics not available diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pin b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pin new file mode 100644 index 000000000..62b922e4e --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pin @@ -0,0 +1,17 @@ +$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 +$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 +B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 +B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 +B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 new file mode 100644 index 000000000..bdc569e39 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 @@ -0,0 +1,11 @@ +$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 +$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 +$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 +ACOUNT_1 14 0 18 26 2 1 +twfeed1 18 0 22 26 0 1 +$COUNT_1/$FJK3_1 22 0 86 26 0 1 +$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 +$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 +$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 +$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 +$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl2 b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl2 new file mode 100644 index 000000000..6e2601e82 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl2 @@ -0,0 +1,2 @@ +1 0 0 86 26 0 0 +2 0 52 86 78 0 0 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sav b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sav new file mode 100644 index 000000000..04c8e9935 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sav @@ -0,0 +1,18 @@ +0.009592 +121 +0 +1 +0.000000 +0.500000 +3.906156 +1 +1 1 2 37 13 +2 2 0 34 65 +3 2 2 63 65 +4 1 0 59 13 +5 1 2 32 13 +6 2 0 23 65 +7 1 2 12 13 +8 2 0 6 65 +9 1 0 70 13 +10 2 0 70 65 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sv2 b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sv2 new file mode 100644 index 000000000..9dd68ecdb --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sv2 @@ -0,0 +1,19 @@ +0.001000 +123 +0 +2 +0.000000 +0.500000 +3.906156 +1 +1 1 2 16 13 +2 2 2 19 65 +3 2 2 14 65 +4 1 0 11 13 +5 1 2 6 13 +6 2 0 3 65 +7 1 0 2 13 +8 2 2 9 65 +9 1 0 50 13 +10 2 0 54 65 +11 1 0 84 13 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.twf b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.twf new file mode 100644 index 000000000..a4c2eac35 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.twf @@ -0,0 +1,29 @@ +net 1 +segment channel 2 + pin1 1 pin2 7 0 0 +net 2 +segment channel 3 +pin1 41 pin2 42 0 0 +segment channel 2 +pin1 12 pin2 3 0 0 +net 3 +segment channel 2 +pin1 35 pin2 36 0 0 +segment channel 2 +pin1 19 pin2 35 0 0 +net 4 +segment channel 2 + pin1 5 pin2 38 0 0 +net 5 +net 7 +segment channel 2 + pin1 14 pin2 43 0 0 +net 8 +segment channel 2 + pin1 23 pin2 17 0 0 +net 9 +net 11 +segment channel 2 + pin1 25 pin2 31 0 0 +net 14 +net 15 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr new file mode 100644 index 000000000..6e24f6d54 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr @@ -0,0 +1,8 @@ +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x11e394 length 0x10. +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x0 length 0x0. +0: system.remote_gdb.listener: listening for remote gdb on port 7002 +warn: Entering event queue @ 0. Starting simulation... +warn: Ignoring request to flush register windows. +warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout new file mode 100644 index 000000000..d50dfc3c4 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout @@ -0,0 +1,28 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 29 2007 16:12:35 +M5 started Thu Mar 29 16:13:01 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 314505003 because target called exit() diff --git a/tests/long/70.twolf/test.py b/tests/long/70.twolf/test.py index 65973c1ee..b2a2dc0b6 100644 --- a/tests/long/70.twolf/test.py +++ b/tests/long/70.twolf/test.py @@ -30,7 +30,7 @@ m5.AddToPath('../configs/common') from cpu2000 import twolf import os -workload = twolf('alpha', 'tru64', 'smred') +workload = twolf(isa, opsys, 'smred') root.system.cpu.workload = workload.makeLiveProcess() cwd = root.system.cpu.workload.cwd diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 2296e2545..4d44e14fe 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -70,6 +29,7 @@ commitToFetchDelay=1 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=8 +cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 @@ -155,7 +115,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -331,7 +291,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -417,12 +377,3 @@ range=0:134217727 zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out index 1b1b58f1b..686c3b2f6 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -173,6 +170,7 @@ type=DerivO3CPU clock=1 phase=0 numThreads=1 +cpu_id=0 activity=0 workload=system.cpu.workload checker=null @@ -253,7 +251,7 @@ assoc=2 block_size=64 latency=1 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -291,7 +289,7 @@ assoc=2 block_size=64 latency=1 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -367,51 +365,3 @@ clock=1000 width=64 responder_set=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index 4e3fdbcd2..988584966 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 675 # Number of BTB hits -global.BPredUnit.BTBLookups 2343 # Number of BTB lookups -global.BPredUnit.RASInCorrect 76 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 437 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1563 # Number of conditional branches predicted -global.BPredUnit.lookups 5229 # Number of BP lookups -global.BPredUnit.usedRAS 2821 # Number of times the RAS was used to get a target. -host_inst_rate 11609 # Simulator instruction rate (inst/s) -host_mem_usage 177052 # Number of bytes of host memory used -host_seconds 0.48 # Real time elapsed on the host -host_tick_rate 2887871 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 23 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 117 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 3775 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 3734 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 615 # Number of BTB hits +global.BPredUnit.BTBLookups 1663 # Number of BTB lookups +global.BPredUnit.RASInCorrect 78 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 439 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1180 # Number of conditional branches predicted +global.BPredUnit.lookups 2032 # Number of BP lookups +global.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target. +host_inst_rate 15105 # Simulator instruction rate (inst/s) +host_mem_usage 154056 # Number of bytes of host memory used +host_seconds 0.37 # Real time elapsed on the host +host_tick_rate 3572881 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 24 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 13 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2144 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5623 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 1400135 # Number of ticks simulated +sim_ticks 1331134 # Number of ticks simulated system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 97 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 51243 +system.cpu.commit.COM:committed_per_cycle.samples 30311 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 48519 9468.42% - 1 1590 310.29% - 2 483 94.26% - 3 227 44.30% - 4 131 25.56% - 5 104 20.30% - 6 61 11.90% - 7 31 6.05% - 8 97 18.93% + 0 27595 9103.96% + 1 1579 520.93% + 2 482 159.02% + 3 232 76.54% + 4 131 43.22% + 5 104 34.31% + 6 60 19.79% + 7 27 8.91% + 8 101 33.32% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 979 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 1791 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 368 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 370 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 13830 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4834 # The number of squashed insts skipped by commit system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 249.001423 # CPI: Cycles Per Instruction -system.cpu.cpi_total 249.001423 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1600 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 6986.684848 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6882.626263 # average ReadReq mshr miss latency +system.cpu.cpi 236.730215 # CPI: Cycles Per Instruction +system.cpu.cpi_total 236.730215 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1606 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 7256.076023 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7095.200000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1435 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1152803 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.103125 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 165 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 66 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 681380 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.061875 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 99 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_miss_latency 1240789 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.106476 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 171 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 71 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 709520 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.062267 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 5293.047244 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5141.082192 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 558 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 1344434 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.312808 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 254 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 181 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 375299 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 8026.070225 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7200.452055 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 456 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2857281 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.438424 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 525633 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 3366.651163 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.587209 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 10.930636 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 43 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 144766 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2412 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 5959.992840 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 6143.482558 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1993 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 2497237 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.173715 # miss rate for demand accesses -system.cpu.dcache.demand_misses 419 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 247 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1056679 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.071310 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 172 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 2418 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 7776.223909 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 7139.612717 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1891 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 4098070 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.217949 # miss rate for demand accesses +system.cpu.dcache.demand_misses 527 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 354 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 1235153 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.071547 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2412 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 5959.992840 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 6143.482558 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2418 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 7776.223909 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 7139.612717 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1993 # number of overall hits -system.cpu.dcache.overall_miss_latency 2497237 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.173715 # miss rate for overall accesses -system.cpu.dcache.overall_misses 419 # number of overall misses -system.cpu.dcache.overall_mshr_hits 247 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1056679 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.071310 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 172 # number of overall MSHR misses +system.cpu.dcache.overall_hits 1891 # number of overall hits +system.cpu.dcache.overall_miss_latency 4098070 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.217949 # miss rate for overall accesses +system.cpu.dcache.overall_misses 527 # number of overall misses +system.cpu.dcache.overall_mshr_hits 354 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 1235153 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.071547 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -119,90 +119,90 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 172 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 101.349720 # Cycle average of tags in use -system.cpu.dcache.total_refs 1993 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 102.478227 # Cycle average of tags in use +system.cpu.dcache.total_refs 1891 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 17501 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 17469 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 70 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 168 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 29666 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 28130 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 5553 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 2529 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BranchResolved 169 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 11765 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 10684 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2098 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 907 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 200 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 60 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 5229 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 6371 # Number of cache lines fetched -system.cpu.fetch.Cycles 13322 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 296 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 35572 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2057 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.097242 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 6371 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 3496 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.661522 # Number of inst fetches per cycle +system.cpu.decode.DECODE:UnblockCycles 61 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2032 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1710 # Number of cache lines fetched +system.cpu.fetch.Cycles 3962 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 12603 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 472 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.065089 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1710 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 919 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.403696 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 53773 +system.cpu.fetch.rateDist.samples 31219 system.cpu.fetch.rateDist.min_value 0 - 0 46825 8707.90% - 1 199 37.01% - 2 504 93.73% - 3 1429 265.75% - 4 1462 271.88% - 5 245 45.56% - 6 322 59.88% - 7 1223 227.44% - 8 1564 290.85% + 0 28979 9282.49% + 1 197 63.10% + 2 198 63.42% + 3 167 53.49% + 4 197 63.10% + 5 187 59.90% + 6 222 71.11% + 7 122 39.08% + 8 950 304.30% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 6370 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5088.614350 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4278.032258 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5924 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 2269522 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.070016 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 446 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 136 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1326190 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.048666 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 1710 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5139.251163 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4349.151613 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1280 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 2209878 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.251462 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 430 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 120 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1348237 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.181287 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 310 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 3444.375000 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 19.109677 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 4.129032 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 8 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 27555 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 6370 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5088.614350 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4278.032258 # average overall mshr miss latency -system.cpu.icache.demand_hits 5924 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 2269522 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.070016 # miss rate for demand accesses -system.cpu.icache.demand_misses 446 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 136 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1326190 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.048666 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 1710 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5139.251163 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4349.151613 # average overall mshr miss latency +system.cpu.icache.demand_hits 1280 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 2209878 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.251462 # miss rate for demand accesses +system.cpu.icache.demand_misses 430 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 120 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1348237 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.181287 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 310 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 6370 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5088.614350 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4278.032258 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1710 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5139.251163 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4349.151613 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5924 # number of overall hits -system.cpu.icache.overall_miss_latency 2269522 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.070016 # miss rate for overall accesses -system.cpu.icache.overall_misses 446 # number of overall misses -system.cpu.icache.overall_mshr_hits 136 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1326190 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.048666 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 1280 # number of overall hits +system.cpu.icache.overall_miss_latency 2209878 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.251462 # miss rate for overall accesses +system.cpu.icache.overall_misses 430 # number of overall misses +system.cpu.icache.overall_mshr_hits 120 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1348237 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.181287 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 310 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -218,77 +218,77 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 310 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 147.070827 # Cycle average of tags in use -system.cpu.icache.total_refs 5924 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 148.421347 # Cycle average of tags in use +system.cpu.icache.total_refs 1280 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1346363 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 2364 # Number of branches executed +system.cpu.idleCycles 1299916 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1267 # Number of branches executed system.cpu.iew.EXEC:nop 48 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.251650 # Inst execution rate -system.cpu.iew.EXEC:refs 5460 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 2123 # Number of stores executed +system.cpu.iew.EXEC:rate 0.270476 # Inst execution rate +system.cpu.iew.EXEC:refs 2748 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1031 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 6466 # num instructions consuming a value -system.cpu.iew.WB:count 11620 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.798639 # average fanout of values written-back +system.cpu.iew.WB:consumers 5354 # num instructions consuming a value +system.cpu.iew.WB:count 8160 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.757378 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 5164 # num instructions producing a value -system.cpu.iew.WB:rate 0.216094 # insts written-back per cycle -system.cpu.iew.WB:sent 11692 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 401 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 4055 # num instructions producing a value +system.cpu.iew.WB:rate 0.261379 # insts written-back per cycle +system.cpu.iew.WB:sent 8228 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 404 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 7230 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3775 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2144 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2557 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 3734 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 19465 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3337 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 308 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 13532 # Number of executed instructions +system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 10469 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1717 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 299 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8444 # Number of executed instructions system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 2529 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 907 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 1656 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 81 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 40 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 60 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2796 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 2922 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu.iew.lsq.thread.0.squashedLoads 1165 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 60 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 279 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 122 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.004016 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.004016 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 13840 # Type of FU issued +system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.004224 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.004224 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8743 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.01% # Type of FU issued - IntAlu 8249 59.60% # Type of FU issued + (null) 2 0.02% # Type of FU issued + IntAlu 5868 67.12% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.01% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3432 24.80% # Type of FU issued - MemWrite 2154 15.56% # Type of FU issued + MemRead 1809 20.69% # Type of FU issued + MemWrite 1061 12.14% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 86 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.006214 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 87 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009951 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 1.16% # attempts to use FU when none available + IntAlu 1 1.15% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,43 +297,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 53 61.63% # attempts to use FU when none available - MemWrite 32 37.21% # attempts to use FU when none available + MemRead 54 62.07% # attempts to use FU when none available + MemWrite 32 36.78% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 53773 +system.cpu.iq.ISSUE:issued_per_cycle.samples 31219 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 46903 8722.41% - 1 3262 606.62% - 2 1316 244.73% - 3 1665 309.63% - 4 333 61.93% - 5 188 34.96% - 6 73 13.58% - 7 23 4.28% - 8 10 1.86% + 0 27042 8662.03% + 1 1845 590.99% + 2 1151 368.69% + 3 572 183.22% + 4 318 101.86% + 5 182 58.30% + 6 76 24.34% + 7 22 7.05% + 8 11 3.52% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.257378 # Inst issue rate -system.cpu.iq.iqInstsAdded 19393 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 13840 # Number of instructions issued +system.cpu.iq.ISSUE:rate 0.280054 # Inst issue rate +system.cpu.iq.iqInstsAdded 10397 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8743 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 13381 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 72 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4378 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 68 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 9575 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 480 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4520.691667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2303.372917 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 2169932 # number of ReadReq miss cycles +system.cpu.iq.iqSquashedOperandsExamined 2580 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 481 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4807.594595 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2390.114345 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 2312453 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 480 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1105619 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 481 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1149645 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 480 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 481 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -342,32 +342,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 480 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4520.691667 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2303.372917 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4807.594595 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2390.114345 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2169932 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 2312453 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 481 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1105619 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1149645 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 481 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 480 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4520.691667 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2303.372917 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4807.594595 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2390.114345 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2169932 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 2312453 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 480 # number of overall misses +system.cpu.l2cache.overall_misses 481 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1105619 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1149645 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 481 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -380,31 +380,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 480 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 481 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 248.469634 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 250.999286 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 53773 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 7860 # Number of cycles rename is blocking +system.cpu.numCycles 31219 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 7810 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 28280 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 453 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 8 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 36016 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 29203 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 20142 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 5460 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 2529 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 483 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 16091 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 9161 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IdleCycles 10837 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 465 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 6 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 14384 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11306 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8499 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2010 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 907 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 491 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4448 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 9164 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 828 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 825 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.timesIdled 369 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 365 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr index eb1796ead..8053728f7 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr @@ -1,2 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index 511bc594d..ef47b0265 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,8 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 22 2007 23:06:52 -M5 started Mon Jan 22 23:06:54 2007 -M5 executing on ewok +M5 compiled Mar 30 2007 13:12:55 +M5 started Fri Mar 30 13:13:02 2007 +M5 executing on zamp.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 1400135 because target called exit() +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1331134 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index db88e7673..bd6b9bcdc 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -70,6 +29,7 @@ commitToFetchDelay=1 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=8 +cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 @@ -155,7 +115,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -331,7 +291,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -417,12 +377,3 @@ range=0:134217727 zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out index 9ee1931ca..58df46dcb 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -173,6 +170,7 @@ type=DerivO3CPU clock=1 phase=0 numThreads=1 +cpu_id=0 activity=0 workload=system.cpu.workload checker=null @@ -253,7 +251,7 @@ assoc=2 block_size=64 latency=1 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -291,7 +289,7 @@ assoc=2 block_size=64 latency=1 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -367,51 +365,3 @@ clock=1000 width=64 responder_set=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index 3aae57d12..1919ca3fe 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 200 # Number of BTB hits -global.BPredUnit.BTBLookups 718 # Number of BTB lookups -global.BPredUnit.RASInCorrect 42 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 218 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 459 # Number of conditional branches predicted -global.BPredUnit.lookups 898 # Number of BP lookups -global.BPredUnit.usedRAS 171 # Number of times the RAS was used to get a target. -host_inst_rate 22132 # Simulator instruction rate (inst/s) -host_mem_usage 176684 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -host_tick_rate 6945216 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads. +global.BPredUnit.BTBHits 187 # Number of BTB hits +global.BPredUnit.BTBLookups 653 # Number of BTB lookups +global.BPredUnit.RASInCorrect 41 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 217 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 426 # Number of conditional branches predicted +global.BPredUnit.lookups 832 # Number of BP lookups +global.BPredUnit.usedRAS 170 # Number of times the RAS was used to get a target. +host_inst_rate 19984 # Simulator instruction rate (inst/s) +host_mem_usage 153584 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 6228839 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads. memdepunit.memDep.conflictingStores 8 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 783 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 381 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 701 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 382 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 752028 # Number of ticks simulated +sim_ticks 746028 # Number of ticks simulated system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 51 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 52 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 28200 +system.cpu.commit.COM:committed_per_cycle.samples 29809 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 27270 9670.21% - 1 239 84.75% - 2 332 117.73% - 3 127 45.04% - 4 83 29.43% - 5 54 19.15% - 6 26 9.22% - 7 18 6.38% - 8 51 18.09% + 0 28885 9690.03% + 1 239 80.18% + 2 325 109.03% + 3 129 43.28% + 4 78 26.17% + 5 53 17.78% + 6 29 9.73% + 7 19 6.37% + 8 52 17.44% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 415 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 141 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 140 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1703 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1536 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 315.051529 # CPI: Cycles Per Instruction -system.cpu.cpi_total 315.051529 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 560 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 7231.967391 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7288.377049 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 468 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 665341 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.164286 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 31 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 444591 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.108929 # mshr miss rate for ReadReq accesses +system.cpu.cpi 312.537914 # CPI: Cycles Per Instruction +system.cpu.cpi_total 312.537914 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 565 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 7055.843750 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7158.016393 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 469 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 677361 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.169912 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 96 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 436639 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.107965 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 6647.685714 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6571.666667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 224 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 465338 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.238095 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 70 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 46 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 157720 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 7089.086420 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6946.208333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 213 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 574216 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 81 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 57 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 166709 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 2980 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.141176 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 8.023529 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 8 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 23840 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 854 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 6979.500000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7086.011765 # average overall mshr miss latency -system.cpu.dcache.demand_hits 692 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1130679 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.189696 # miss rate for demand accesses -system.cpu.dcache.demand_misses 162 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 77 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 602311 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.099532 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 859 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 7071.056497 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 7098.211765 # average overall mshr miss latency +system.cpu.dcache.demand_hits 682 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1251577 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.206054 # miss rate for demand accesses +system.cpu.dcache.demand_misses 177 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 92 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 603348 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.098952 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 854 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 6979.500000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7086.011765 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 859 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 7071.056497 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 7098.211765 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 692 # number of overall hits -system.cpu.dcache.overall_miss_latency 1130679 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.189696 # miss rate for overall accesses -system.cpu.dcache.overall_misses 162 # number of overall misses -system.cpu.dcache.overall_mshr_hits 77 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 602311 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.099532 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 682 # number of overall hits +system.cpu.dcache.overall_miss_latency 1251577 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.206054 # miss rate for overall accesses +system.cpu.dcache.overall_misses 177 # number of overall misses +system.cpu.dcache.overall_mshr_hits 92 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 603348 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.098952 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -121,88 +121,88 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 46.684988 # Cycle average of tags in use -system.cpu.dcache.total_refs 692 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 46.650284 # Cycle average of tags in use +system.cpu.dcache.total_refs 682 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 21865 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 23701 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 150 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 4900 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 5406 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 928 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 336 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BranchResolved 129 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 4617 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 5228 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 877 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 297 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 2 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 898 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 813 # Number of cache lines fetched -system.cpu.fetch.Cycles 1774 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 146 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5593 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 258 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.031468 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 813 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 371 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.195991 # Number of inst fetches per cycle +system.cpu.decode.DECODE:UnblockCycles 4 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 832 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 760 # Number of cache lines fetched +system.cpu.fetch.Cycles 1674 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 131 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 5310 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 230 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.027635 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 760 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 357 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.176371 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 28537 +system.cpu.fetch.rateDist.samples 30107 system.cpu.fetch.rateDist.min_value 0 - 0 27576 9663.24% - 1 50 17.52% - 2 92 32.24% - 3 74 25.93% - 4 117 41.00% - 5 71 24.88% - 6 43 15.07% - 7 56 19.62% - 8 458 160.49% + 0 29196 9697.41% + 1 37 12.29% + 2 87 28.90% + 3 73 24.25% + 4 125 41.52% + 5 66 21.92% + 6 42 13.95% + 7 50 16.61% + 8 431 143.16% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 813 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4955.450199 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4151.809783 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 562 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1243818 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.308733 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 251 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 67 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 763933 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.226322 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 760 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4979.783333 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4157.255435 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 520 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1195148 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.315789 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 240 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 764935 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.242105 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 184 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 3445 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.054348 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 2.826087 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 4 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 13780 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 813 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4955.450199 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4151.809783 # average overall mshr miss latency -system.cpu.icache.demand_hits 562 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1243818 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.308733 # miss rate for demand accesses -system.cpu.icache.demand_misses 251 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 67 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 763933 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.226322 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 760 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 4979.783333 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4157.255435 # average overall mshr miss latency +system.cpu.icache.demand_hits 520 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1195148 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.315789 # miss rate for demand accesses +system.cpu.icache.demand_misses 240 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 764935 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.242105 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 184 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 813 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4955.450199 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4151.809783 # average overall mshr miss latency +system.cpu.icache.overall_accesses 760 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 4979.783333 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4157.255435 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 562 # number of overall hits -system.cpu.icache.overall_miss_latency 1243818 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.308733 # miss rate for overall accesses -system.cpu.icache.overall_misses 251 # number of overall misses -system.cpu.icache.overall_mshr_hits 67 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 763933 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.226322 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 520 # number of overall hits +system.cpu.icache.overall_miss_latency 1195148 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.315789 # miss rate for overall accesses +system.cpu.icache.overall_misses 240 # number of overall misses +system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 764935 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.242105 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 184 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -218,59 +218,59 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 184 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 91.596649 # Cycle average of tags in use -system.cpu.icache.total_refs 562 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 91.559894 # Cycle average of tags in use +system.cpu.icache.total_refs 520 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 723492 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 566 # Number of branches executed -system.cpu.iew.EXEC:nop 267 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.118022 # Inst execution rate -system.cpu.iew.EXEC:refs 1013 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 341 # Number of stores executed +system.cpu.idleCycles 715922 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 547 # Number of branches executed +system.cpu.iew.EXEC:nop 269 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.108081 # Inst execution rate +system.cpu.iew.EXEC:refs 940 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 340 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1860 # num instructions consuming a value -system.cpu.iew.WB:count 3219 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.785484 # average fanout of values written-back +system.cpu.iew.WB:consumers 1841 # num instructions consuming a value +system.cpu.iew.WB:count 3178 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.788702 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1461 # num instructions producing a value -system.cpu.iew.WB:rate 0.112801 # insts written-back per cycle -system.cpu.iew.WB:sent 3234 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 152 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 14742 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 783 # Number of dispatched load instructions +system.cpu.iew.WB:producers 1452 # num instructions producing a value +system.cpu.iew.WB:rate 0.105557 # insts written-back per cycle +system.cpu.iew.WB:sent 3194 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 151 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 16588 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 701 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 79 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 381 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4280 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 672 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 123 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3368 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 62 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 382 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 4113 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 600 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 110 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3254 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 336 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 297 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 82 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 29 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 12 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 15 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 368 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 87 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 95 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 57 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.003174 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.003174 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 3491 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 286 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 88 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 15 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 96 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 55 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.003200 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.003200 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 3364 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 2447 70.09% # Type of FU issued + IntAlu 2398 71.28% # Type of FU issued IntMult 1 0.03% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -279,13 +279,13 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 694 19.88% # Type of FU issued - MemWrite 349 10.00% # Type of FU issued + MemRead 618 18.37% # Type of FU issued + MemWrite 347 10.32% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:fu_busy_cnt 34 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009739 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.010107 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available IntAlu 1 2.94% # attempts to use FU when none available @@ -303,35 +303,35 @@ system.cpu.iq.ISSUE:fu_full.start_dist InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 28537 +system.cpu.iq.ISSUE:issued_per_cycle.samples 30107 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 27012 9465.61% - 1 616 215.86% - 2 356 124.75% - 3 247 86.55% - 4 177 62.02% - 5 81 28.38% - 6 32 11.21% - 7 11 3.85% - 8 5 1.75% + 0 28628 9508.75% + 1 616 204.60% + 2 335 111.27% + 3 225 74.73% + 4 177 58.79% + 5 80 26.57% + 6 31 10.30% + 7 11 3.65% + 8 4 1.33% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.122332 # Inst issue rate -system.cpu.iq.iqInstsAdded 4007 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3491 # Number of instructions issued +system.cpu.iq.ISSUE:rate 0.111735 # Inst issue rate +system.cpu.iq.iqInstsAdded 3838 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3364 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1470 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1301 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 35 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 801 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 682 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadReq_accesses 269 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4621.724907 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2296.401487 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1243244 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 4610.717472 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2315.289963 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 1240283 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 269 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 617732 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 622813 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 269 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -343,29 +343,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 269 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4621.724907 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2296.401487 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 4610.717472 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2315.289963 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1243244 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1240283 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 269 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 617732 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 622813 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 269 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 269 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4621.724907 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2296.401487 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 4610.717472 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2315.289963 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1243244 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1240283 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 269 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 617732 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 622813 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 269 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -382,29 +382,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 269 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 138.802893 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 138.742329 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 28537 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14783 # Number of cycles rename is blocking +system.cpu.numCycles 30107 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 16613 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 18 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 5489 # Number of cycles rename is idle +system.cpu.rename.RENAME:IQFullEvents 14 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 5311 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 5285 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4708 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3399 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 852 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 336 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 25 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1631 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 7052 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:RenameLookups 5020 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 4436 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 3192 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 802 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 297 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 23 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1424 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 7061 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 88 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 78 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 207 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr index fb2137f1e..e582c15a8 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr @@ -1,3 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index 6436baf8f..25e5ec43b 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -6,8 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 22 2007 23:06:52 -M5 started Mon Jan 22 23:07:09 2007 -M5 executing on ewok +M5 compiled Mar 30 2007 13:12:55 +M5 started Fri Mar 30 13:13:05 2007 +M5 executing on zamp.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing -Exiting @ tick 752028 because target called exit() +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 746028 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 6eef745b4..e11ca74dd 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -70,6 +29,7 @@ commitToFetchDelay=1 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=8 +cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 @@ -155,7 +115,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -331,7 +291,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -433,12 +393,3 @@ range=0:134217727 zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out index f36f666af..0d9c5215b 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -189,6 +186,7 @@ type=DerivO3CPU clock=1 phase=0 numThreads=1 +cpu_id=0 activity=0 workload=system.cpu.workload0 system.cpu.workload1 checker=null @@ -269,7 +267,7 @@ assoc=2 block_size=64 latency=1 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -307,7 +305,7 @@ assoc=2 block_size=64 latency=1 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -383,51 +381,3 @@ clock=1000 width=64 responder_set=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index bb9e9360c..684314d31 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 1334 # Number of BTB hits -global.BPredUnit.BTBLookups 6012 # Number of BTB lookups -global.BPredUnit.RASInCorrect 173 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1201 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 4031 # Number of conditional branches predicted -global.BPredUnit.lookups 12370 # Number of BP lookups -global.BPredUnit.usedRAS 6337 # Number of times the RAS was used to get a target. -host_inst_rate 11366 # Simulator instruction rate (inst/s) -host_mem_usage 178064 # Number of bytes of host memory used -host_seconds 0.99 # Real time elapsed on the host -host_tick_rate 2259917 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 27 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 20 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 97 # Number of conflicting stores. -memdepunit.memDep.conflictingStores 3 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 5749 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 2822 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 4490 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1747 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 827 # Number of BTB hits +global.BPredUnit.BTBLookups 3697 # Number of BTB lookups +global.BPredUnit.RASInCorrect 179 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1207 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 2534 # Number of conditional branches predicted +global.BPredUnit.lookups 4455 # Number of BP lookups +global.BPredUnit.usedRAS 640 # Number of times the RAS was used to get a target. +host_inst_rate 15344 # Simulator instruction rate (inst/s) +host_mem_usage 154676 # Number of bytes of host memory used +host_seconds 0.73 # Real time elapsed on the host +host_tick_rate 2857242 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 24 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 26 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 4 # Number of conflicting stores. +memdepunit.memDep.conflictingStores 5 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2132 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 2142 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1150 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1138 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11247 # Number of instructions simulated sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 2237162 # Number of ticks simulated +sim_ticks 2095164 # Number of ticks simulated system.cpu.commit.COM:branches 1724 # Number of branches committed system.cpu.commit.COM:branches_0 862 # Number of branches committed system.cpu.commit.COM:branches_1 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 128 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 123 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 188940 +system.cpu.commit.COM:committed_per_cycle.samples 165684 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 183303 9701.65% - 1 3121 165.18% - 2 1239 65.58% - 3 531 28.10% - 4 275 14.55% - 5 154 8.15% - 6 128 6.77% - 7 61 3.23% - 8 128 6.77% + 0 159919 9652.05% + 1 3333 201.17% + 2 1165 70.31% + 3 515 31.08% + 4 270 16.30% + 5 201 12.13% + 6 102 6.16% + 7 56 3.38% + 8 123 7.42% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist system.cpu.commit.COM:count 11281 # Number of instructions committed -system.cpu.commit.COM:count_0 5641 # Number of instructions committed -system.cpu.commit.COM:count_1 5640 # Number of instructions committed +system.cpu.commit.COM:count_0 5640 # Number of instructions committed +system.cpu.commit.COM:count_1 5641 # Number of instructions committed system.cpu.commit.COM:loads 1958 # Number of loads committed system.cpu.commit.COM:loads_0 979 # Number of loads committed system.cpu.commit.COM:loads_1 979 # Number of loads committed @@ -61,141 +61,141 @@ system.cpu.commit.COM:refs_1 1791 # Nu system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 943 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 947 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 28509 # The number of squashed insts skipped by commit -system.cpu.committedInsts_0 5624 # Number of Instructions Simulated -system.cpu.committedInsts_1 5623 # Number of Instructions Simulated +system.cpu.commit.commitSquashedInsts 9432 # The number of squashed insts skipped by commit +system.cpu.committedInsts_0 5623 # Number of Instructions Simulated +system.cpu.committedInsts_1 5624 # Number of Instructions Simulated system.cpu.committedInsts_total 11247 # Number of Instructions Simulated -system.cpu.cpi_0 397.788407 # CPI: Cycles Per Instruction -system.cpu.cpi_1 397.859150 # CPI: Cycles Per Instruction -system.cpu.cpi_total 198.911888 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3186 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 3186 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 9969.378125 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency_0 9969.378125 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10500.608040 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 10500.608040 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2866 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 2866 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3190201 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 3190201 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.100439 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate_0 0.100439 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 320 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 320 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 121 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 121 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2089621 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 2089621 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.062461 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.062461 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 199 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 199 # number of ReadReq MSHR misses +system.cpu.cpi_0 372.606082 # CPI: Cycles Per Instruction +system.cpu.cpi_1 372.539829 # CPI: Cycles Per Instruction +system.cpu.cpi_total 186.286476 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 3234 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 3234 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 10308.511696 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency_0 10308.511696 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10789.975000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 10789.975000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2892 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 2892 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3525511 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 3525511 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.105751 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate_0 0.105751 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 342 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 342 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 142 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 142 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2157995 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 2157995 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.061843 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.061843 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 200 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 200 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1624 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses_0 1624 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 6540.875740 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency_0 6540.875740 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7803.746575 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 7803.746575 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1117 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_0 1117 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3316224 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 3316224 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.312192 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate_0 0.312192 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 507 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses_0 507 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 361 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits_0 361 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1139347 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 1139347 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 8945.050491 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency_0 8945.050491 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9931.897260 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 9931.897260 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 911 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 911 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 6377821 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 6377821 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.439039 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate_0 0.439039 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 713 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses_0 713 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 567 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits_0 567 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1450057 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 1450057 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses_0 146 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 3973 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 3625.380952 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.544928 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles_no_mshrs 994 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 10.991329 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 1 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 84 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 3973 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 304532 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 994 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4810 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 4810 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 4858 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 4858 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7867.503023 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 7867.503023 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 9387.044550 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 9387.044550 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9359.327536 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 9359.327536 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 10427.895954 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 10427.895954 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_hits 3983 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 3983 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 3803 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 3803 # number of demand (read+write) hits system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 6506425 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 6506425 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 9903332 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 9903332 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.171933 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.171933 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.217168 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.217168 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_misses 827 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 827 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 1055 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 1055 # number of demand (read+write) misses system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 482 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 482 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits 709 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 709 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3228968 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 3228968 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3608052 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 3608052 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.071726 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.071726 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.071223 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.071223 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 345 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 345 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 346 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 346 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4810 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 4810 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 4858 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 4858 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7867.503023 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 7867.503023 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 9387.044550 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 9387.044550 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9359.327536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 9359.327536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 10427.895954 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 10427.895954 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3983 # number of overall hits -system.cpu.dcache.overall_hits_0 3983 # number of overall hits +system.cpu.dcache.overall_hits 3803 # number of overall hits +system.cpu.dcache.overall_hits_0 3803 # number of overall hits system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 6506425 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 6506425 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 9903332 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 9903332 # number of overall miss cycles system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.171933 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.171933 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.217168 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.217168 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_misses 827 # number of overall misses -system.cpu.dcache.overall_misses_0 827 # number of overall misses +system.cpu.dcache.overall_misses 1055 # number of overall misses +system.cpu.dcache.overall_misses_0 1055 # number of overall misses system.cpu.dcache.overall_misses_1 0 # number of overall misses -system.cpu.dcache.overall_mshr_hits 482 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 482 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits 709 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 709 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3228968 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 3228968 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3608052 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 3608052 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.071726 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.071726 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.071223 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.071223 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 345 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 345 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 346 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 346 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -215,153 +215,153 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements_0 0 # number of replacements system.cpu.dcache.replacements_1 0 # number of replacements -system.cpu.dcache.sampled_refs 345 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 346 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 198.670475 # Cycle average of tags in use -system.cpu.dcache.total_refs 3983 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 200.098842 # Cycle average of tags in use +system.cpu.dcache.total_refs 3803 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks_0 0 # number of writebacks system.cpu.dcache.writebacks_1 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 97618 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 267 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 390 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 67048 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 262280 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 12122 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 5552 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 680 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 155 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 12370 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 13012 # Number of cache lines fetched -system.cpu.fetch.Cycles 27804 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 800 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 79582 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 4833 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.065467 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 52787 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 7671 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.421180 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 112235 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 273 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 396 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 24032 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 212833 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 4096 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1856 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 672 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 181 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 4455 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 3542 # Number of cache lines fetched +system.cpu.fetch.Cycles 8000 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 608 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 26459 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1268 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.026888 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 3542 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1467 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.159692 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 188950 +system.cpu.fetch.rateDist.samples 165688 system.cpu.fetch.rateDist.min_value 0 - 0 174142 9216.30% - 1 378 20.01% - 2 298 15.77% - 3 3656 193.49% - 4 2200 116.43% - 5 1017 53.82% - 6 974 51.55% - 7 2369 125.38% - 8 3916 207.25% + 0 161234 9731.18% + 1 342 20.64% + 2 283 17.08% + 3 285 17.20% + 4 390 23.54% + 5 369 22.27% + 6 367 22.15% + 7 255 15.39% + 8 2163 130.55% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 13010 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 13010 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 7746.912281 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency_0 7746.912281 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 7155.055556 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 7155.055556 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 12098 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 12098 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 7065184 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 7065184 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.070100 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate_0 0.070100 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 912 # number of ReadReq misses -system.cpu.icache.ReadReq_misses_0 912 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 282 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 282 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4507685 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 4507685 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.048424 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.048424 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 630 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 630 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 3542 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 3542 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 7880.839306 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency_0 7880.839306 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 7272.060897 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 7272.060897 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2677 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 2677 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 6816926 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 6816926 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.244212 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate_0 0.244212 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 865 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_0 865 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 241 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 241 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4537766 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 4537766 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.176172 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.176172 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 624 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 624 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 5648.647059 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 19.203175 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 4.290064 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 17 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 96027 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 13010 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 13010 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 3542 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 3542 # number of demand (read+write) accesses system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 7746.912281 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 7746.912281 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency 7880.839306 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 7880.839306 # average overall miss latency system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 7155.055556 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 7155.055556 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 7272.060897 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 7272.060897 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_hits 12098 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 12098 # number of demand (read+write) hits +system.cpu.icache.demand_hits 2677 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 2677 # number of demand (read+write) hits system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 7065184 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 7065184 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 6816926 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 6816926 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.070100 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.070100 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.244212 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.244212 # miss rate for demand accesses system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.icache.demand_misses 912 # number of demand (read+write) misses -system.cpu.icache.demand_misses_0 912 # number of demand (read+write) misses +system.cpu.icache.demand_misses 865 # number of demand (read+write) misses +system.cpu.icache.demand_misses_0 865 # number of demand (read+write) misses system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 282 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 282 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits 241 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 241 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4507685 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 4507685 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 4537766 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 4537766 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.048424 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.048424 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.176172 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.176172 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 630 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 630 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 624 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 624 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 13010 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 13010 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 3542 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 3542 # number of overall (read+write) accesses system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 7746.912281 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 7746.912281 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 7880.839306 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 7880.839306 # average overall miss latency system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 7155.055556 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 7155.055556 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 7272.060897 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 7272.060897 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 12098 # number of overall hits -system.cpu.icache.overall_hits_0 12098 # number of overall hits +system.cpu.icache.overall_hits 2677 # number of overall hits +system.cpu.icache.overall_hits_0 2677 # number of overall hits system.cpu.icache.overall_hits_1 0 # number of overall hits -system.cpu.icache.overall_miss_latency 7065184 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 7065184 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 6816926 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 6816926 # number of overall miss cycles system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.070100 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.070100 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.244212 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.244212 # miss rate for overall accesses system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.icache.overall_misses 912 # number of overall misses -system.cpu.icache.overall_misses_0 912 # number of overall misses +system.cpu.icache.overall_misses 865 # number of overall misses +system.cpu.icache.overall_misses_0 865 # number of overall misses system.cpu.icache.overall_misses_1 0 # number of overall misses -system.cpu.icache.overall_mshr_hits 282 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 282 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits 241 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 241 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4507685 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 4507685 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 4537766 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 4537766 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.048424 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.048424 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.176172 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.176172 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 630 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 630 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 624 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 624 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -381,121 +381,121 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 6 # number of replacements system.cpu.icache.replacements_0 6 # number of replacements system.cpu.icache.replacements_1 0 # number of replacements -system.cpu.icache.sampled_refs 630 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 624 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 289.377534 # Cycle average of tags in use -system.cpu.icache.total_refs 12098 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 289.929418 # Cycle average of tags in use +system.cpu.icache.total_refs 2677 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks_0 0 # number of writebacks system.cpu.icache.writebacks_1 0 # number of writebacks -system.cpu.idleCycles 2048213 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 4035 # Number of branches executed -system.cpu.iew.EXEC:branches_0 2458 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1577 # Number of branches executed +system.cpu.idleCycles 1929477 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 2535 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1269 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1266 # Number of branches executed system.cpu.iew.EXEC:nop 84 # number of nop insts executed system.cpu.iew.EXEC:nop_0 42 # number of nop insts executed system.cpu.iew.EXEC:nop_1 42 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.142196 # Inst execution rate -system.cpu.iew.EXEC:refs 10960 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 7253 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 3707 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 3812 # Number of stores executed -system.cpu.iew.EXEC:stores_0 2509 # Number of stores executed -system.cpu.iew.EXEC:stores_1 1303 # Number of stores executed +system.cpu.iew.EXEC:rate 0.100864 # Inst execution rate +system.cpu.iew.EXEC:refs 5422 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 2727 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 2695 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1997 # Number of stores executed +system.cpu.iew.EXEC:stores_0 1003 # Number of stores executed +system.cpu.iew.EXEC:stores_1 994 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 12377 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 6652 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 5725 # num instructions consuming a value -system.cpu.iew.WB:count 22520 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 12790 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 9730 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.808516 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.819753 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.795459 # average fanout of values written-back +system.cpu.iew.WB:consumers 10258 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5162 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 5096 # num instructions consuming a value +system.cpu.iew.WB:count 16101 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 8089 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 8012 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.770326 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.768888 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.771782 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 10007 # num instructions producing a value -system.cpu.iew.WB:producers_0 5453 # num instructions producing a value -system.cpu.iew.WB:producers_1 4554 # num instructions producing a value -system.cpu.iew.WB:rate 0.119185 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.067690 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.051495 # insts written-back per cycle -system.cpu.iew.WB:sent 22674 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 12874 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 9800 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 1030 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 62040 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 8571 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 5358 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 6237 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 39780 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 7148 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 4744 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 2404 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 903 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 26868 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 7902 # num instructions producing a value +system.cpu.iew.WB:producers_0 3969 # num instructions producing a value +system.cpu.iew.WB:producers_1 3933 # num instructions producing a value +system.cpu.iew.WB:rate 0.097177 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.048821 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.048356 # insts written-back per cycle +system.cpu.iew.WB:sent 16249 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 8166 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 8083 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 1031 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 84087 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 4274 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 468 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2288 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 20693 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3425 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 1724 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 1701 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 741 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 16712 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 57 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 5552 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 117 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 3088 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 64 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1856 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 131 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 70 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 34 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 60 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 4770 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 3678 # Number of stores squashed -system.cpu.iew.lsq.thread.1.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.1.cacheBlocked 756 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 64 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1153 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 338 # Number of stores squashed +system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.1.forwLoads 65 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 29 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 59 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 1843 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 935 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 63 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 798 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 232 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.002514 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.002513 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.005027 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 16536 # Type of FU issued +system.cpu.iew.lsq.thread.1.squashedLoads 1163 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 326 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 119 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 791 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 240 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.002684 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.002684 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.005368 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8768 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.01% # Type of FU issued - IntAlu 9136 55.25% # Type of FU issued + (null) 2 0.02% # Type of FU issued + IntAlu 5895 67.23% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.01% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 4850 29.33% # Type of FU issued - MemWrite 2545 15.39% # Type of FU issued + MemRead 1838 20.96% # Type of FU issued + MemWrite 1030 11.75% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 11235 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1 8685 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 7383 65.71% # Type of FU issued + IntAlu 5859 67.46% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -504,34 +504,34 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 2518 22.41% # Type of FU issued - MemWrite 1329 11.83% # Type of FU issued + MemRead 1800 20.73% # Type of FU issued + MemWrite 1021 11.76% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 27771 # Type of FU issued +system.cpu.iq.ISSUE:FU_type 17453 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist - (null) 4 0.01% # Type of FU issued - IntAlu 16519 59.48% # Type of FU issued + (null) 4 0.02% # Type of FU issued + IntAlu 11754 67.35% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 4 0.01% # Type of FU issued + FloatAdd 4 0.02% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 7368 26.53% # Type of FU issued - MemWrite 3874 13.95% # Type of FU issued + MemRead 3638 20.84% # Type of FU issued + MemWrite 2051 11.75% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 146 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 73 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 73 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.005257 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.002629 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.002629 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 133 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 69 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 64 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007620 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.003953 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.003667 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available IntAlu 0 0.00% # attempts to use FU when none available @@ -543,52 +543,52 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 83 56.85% # attempts to use FU when none available - MemWrite 63 43.15% # attempts to use FU when none available + MemRead 79 59.40% # attempts to use FU when none available + MemWrite 54 40.60% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 188950 +system.cpu.iq.ISSUE:issued_per_cycle.samples 165688 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 174613 9241.23% - 1 6958 368.25% - 2 3428 181.42% - 3 2696 142.68% - 4 636 33.66% - 5 439 23.23% - 6 143 7.57% - 7 24 1.27% - 8 13 0.69% + 0 156701 9457.59% + 1 4387 264.77% + 2 2473 149.26% + 3 1076 64.94% + 4 569 34.34% + 5 325 19.62% + 6 120 7.24% + 7 25 1.51% + 8 12 0.72% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.146975 # Inst issue rate -system.cpu.iq.iqInstsAdded 39654 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 27771 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 27426 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 185 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 20011 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 973 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 973 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 6750.932169 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency_0 6750.932169 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 3603.773895 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 3603.773895 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 6568657 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 6568657 # number of ReadReq miss cycles +system.cpu.iq.ISSUE:rate 0.105337 # Inst issue rate +system.cpu.iq.iqInstsAdded 20568 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 17453 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 41 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8303 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 214 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4870 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 968 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 968 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 7151.675620 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency_0 7151.675620 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 3855.918388 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 3855.918388 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 6922822 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 6922822 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate_0 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 973 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses_0 973 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 3506472 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 3506472 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 968 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_0 968 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 3732529 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 3732529 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate_0 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 973 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses_0 973 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 968 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_0 968 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -597,52 +597,52 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 973 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 973 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 968 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 968 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 6750.932169 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 6750.932169 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 7151.675620 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 7151.675620 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 3603.773895 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_0 3603.773895 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 3855.918388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 3855.918388 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_0 0 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6568657 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 6568657 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 6922822 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 6922822 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_0 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.l2cache.demand_misses 973 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_0 973 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 968 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_0 968 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 3506472 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 3506472 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 3732529 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 3732529 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_0 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 973 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_0 973 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 968 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_0 968 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 973 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 973 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 968 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 968 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 6750.932169 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 6750.932169 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 7151.675620 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 7151.675620 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 3603.773895 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_0 3603.773895 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 3855.918388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 3855.918388 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency @@ -650,26 +650,26 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> system.cpu.l2cache.overall_hits 0 # number of overall hits system.cpu.l2cache.overall_hits_0 0 # number of overall hits system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6568657 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 6568657 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 6922822 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 6922822 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate_0 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.l2cache.overall_misses 973 # number of overall misses -system.cpu.l2cache.overall_misses_0 973 # number of overall misses +system.cpu.l2cache.overall_misses 968 # number of overall misses +system.cpu.l2cache.overall_misses_0 968 # number of overall misses system.cpu.l2cache.overall_misses_1 0 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3506472 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 3506472 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 3732529 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 3732529 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate_0 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 973 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_0 973 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 968 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_0 968 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -689,35 +689,35 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements_0 0 # number of replacements system.cpu.l2cache.replacements_1 0 # number of replacements -system.cpu.l2cache.sampled_refs 973 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 968 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 489.113488 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 491.189820 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 188950 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 74870 # Number of cycles rename is blocking +system.cpu.numCycles 165688 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 87802 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 21 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 263382 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2455 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 31 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 72755 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 60875 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 44048 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 11047 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 5552 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 2536 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 35946 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 20340 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IQFullEvents 24 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 213369 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2127 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 18 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 28570 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 22635 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 17117 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3694 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1856 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 2143 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 9015 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 22337 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 51 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4990 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.timesIdled 690 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:skidInsts 4330 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.timesIdled 688 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr index c36de0b79..54505c240 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr @@ -1,3 +1,5 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index f07a960f8..b4ae56cae 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -7,8 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 22 2007 23:06:52 -M5 started Mon Jan 22 23:07:23 2007 -M5 executing on ewok +M5 compiled Mar 30 2007 13:12:55 +M5 started Fri Mar 30 13:13:07 2007 +M5 executing on zamp.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing -Exiting @ tick 2237162 because target called exit() +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 2095164 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini index ccb504cd3..06059c3eb 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -1,11 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 +dummy=0 [system] type=System diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out index 392fec336..7f9a83d25 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt index 4fe3d3732..1ed7d50eb 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 104057 # Simulator instruction rate (inst/s) -host_mem_usage 179368 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 103746 # Simulator tick rate (ticks/s) +host_inst_rate 65718 # Simulator instruction rate (inst/s) +host_mem_usage 179556 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host +host_tick_rate 65601 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 10367 # Number of instructions simulated +sim_insts 11001 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 10366 # Number of ticks simulated +sim_ticks 11000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 10367 # number of cpu cycles simulated -system.cpu.num_insts 10367 # Number of instructions executed -system.cpu.num_refs 2607 # Number of memory references +system.cpu.numCycles 11001 # number of cpu cycles simulated +system.cpu.num_insts 11001 # Number of instructions executed +system.cpu.num_refs 2760 # Number of memory references system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout index 567033922..c89235e64 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout @@ -7,6 +7,7 @@ CASX FAIL: Passed CASX WORK: Passed LDTX: Passed LDTW: Passed +STTW: Passed Done M5 Simulator System @@ -15,8 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 6 2007 15:43:35 -M5 started Tue Mar 6 15:52:39 2007 +M5 compiled Mar 29 2007 15:29:35 +M5 started Thu Mar 29 15:39:35 2007 M5 executing on zeep command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic -Exiting @ tick 10366 because target called exit() +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 11000 because target called exit() |