diff options
Diffstat (limited to 'tests')
11 files changed, 2820 insertions, 2831 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 461a61aa2..16e62cf5e 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 28 2013 09:59:18 -gem5 started Mar 28 2013 09:59:39 +gem5 compiled Apr 18 2013 13:37:41 +gem5 started Apr 18 2013 13:56:06 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5132969930500 because m5_exit instruction encountered +Exiting @ tick 5132953103000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 317043d0e..77940f18e 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,131 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.132970 # Number of seconds simulated -sim_ticks 5132969930500 # Number of ticks simulated -final_tick 5132969930500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.132953 # Number of seconds simulated +sim_ticks 5132953103000 # Number of ticks simulated +final_tick 5132953103000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124251 # Simulator instruction rate (inst/s) -host_op_rate 245606 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1563205434 # Simulator tick rate (ticks/s) -host_mem_usage 769808 # Number of bytes of host memory used -host_seconds 3283.62 # Real time elapsed on the host -sim_insts 407992820 # Number of instructions simulated -sim_ops 806477449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2455424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1078336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10828544 # Number of bytes read from this memory -system.physmem.bytes_read::total 14365568 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1078336 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1078336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9561728 # Number of bytes written to this memory -system.physmem.bytes_written::total 9561728 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38366 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16849 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 169196 # Number of read requests responded to by this memory -system.physmem.num_reads::total 224462 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149402 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149402 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 478363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 561 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 210080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2109606 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2798685 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 210080 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 210080 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1862806 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1862806 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1862806 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 478363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 561 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 210080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2109606 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4661492 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 224462 # Total number of read requests seen -system.physmem.writeReqs 149402 # Total number of write requests seen -system.physmem.cpureqs 377855 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 14365568 # Total number of bytes read from memory -system.physmem.bytesWritten 9561728 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14365568 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9561728 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 117 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3983 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 14085 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 13102 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 13279 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 16301 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13529 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 13167 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13352 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 16230 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13914 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 13149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 13590 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 15875 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13170 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12525 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 13306 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 15771 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 9020 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 8543 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8624 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 11619 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8726 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 8620 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8763 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 11646 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 9037 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8560 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 8885 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 11311 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8333 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8041 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8600 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 11074 # Track writes on a per bank basis +host_inst_rate 118788 # Simulator instruction rate (inst/s) +host_op_rate 234812 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1494512187 # Simulator tick rate (ticks/s) +host_mem_usage 768808 # Number of bytes of host memory used +host_seconds 3434.53 # Real time elapsed on the host +sim_insts 407981680 # Number of instructions simulated +sim_ops 806469686 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2427072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1080064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10859584 # Number of bytes read from this memory +system.physmem.bytes_read::total 14370176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1080064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1080064 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9570112 # Number of bytes written to this memory +system.physmem.bytes_written::total 9570112 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 37923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 49 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16876 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 169681 # Number of read requests responded to by this memory +system.physmem.num_reads::total 224534 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149533 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149533 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 472841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 611 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 210418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2115660 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2799592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 210418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 210418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1864446 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1864446 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1864446 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 472841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 611 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 210418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2115660 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4664038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 224534 # Total number of read requests seen +system.physmem.writeReqs 149533 # Total number of write requests seen +system.physmem.cpureqs 378540 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14370176 # Total number of bytes read from memory +system.physmem.bytesWritten 9570112 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14370176 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9570112 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 118 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4466 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 14182 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 13235 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 13224 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 16247 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13672 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 13108 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13087 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 16327 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13931 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 13220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 13507 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 15686 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 13366 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 12693 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 13279 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 15652 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 9160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 8678 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 8635 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 11642 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 8788 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 8537 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8431 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 11660 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 9003 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 8633 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 8850 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 11092 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8524 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8172 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8641 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 11087 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry -system.physmem.totGap 5132969877000 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry +system.physmem.totGap 5132953050000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 224462 # Categorize read packet sizes +system.physmem.readPktSize::6 224534 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 149402 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 173725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 19496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3016 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1787 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1703 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1643 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1099 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 996 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 849 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 765 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 852 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 836 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 149533 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 174096 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 19313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3462 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2988 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1869 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1047 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 799 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 880 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 827 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -136,46 +136,46 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 11 # What write queue length does an incoming req see -system.physmem.totQLat 4645349999 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9161289999 # Sum of mem lat for all requests -system.physmem.totBusLat 1121725000 # Total cycles spent in databus access -system.physmem.totBankLat 3394215000 # Total cycles spent in bank access -system.physmem.avgQLat 20706.28 # Average queueing delay per request -system.physmem.avgBankLat 15129.44 # Average bank access latency per request +system.physmem.wrQLenPdf::0 5394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6441 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see +system.physmem.totQLat 4726159249 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9244557999 # Sum of mem lat for all requests +system.physmem.totBusLat 1122080000 # Total cycles spent in databus access +system.physmem.totBankLat 3396318750 # Total cycles spent in bank access +system.physmem.avgQLat 21059.81 # Average queueing delay per request +system.physmem.avgBankLat 15134.03 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 40835.72 # Average memory access latency +system.physmem.avgMemAccLat 41193.85 # Average memory access latency system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s @@ -183,45 +183,45 @@ system.physmem.avgConsumedWrBW 1.86 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 14.56 # Average write queue length over time -system.physmem.readRowHits 193479 # Number of row buffer hits during reads -system.physmem.writeRowHits 105949 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.24 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.92 # Row buffer hit rate for writes -system.physmem.avgGap 13729510.94 # Average gap between requests -system.iocache.replacements 47582 # number of replacements -system.iocache.tagsinuse 0.103934 # Cycle average of tags in use +system.physmem.avgWrQLen 11.69 # Average write queue length over time +system.physmem.readRowHits 193610 # Number of row buffer hits during reads +system.physmem.writeRowHits 105925 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.27 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.84 # Row buffer hit rate for writes +system.physmem.avgGap 13722015.17 # Average gap between requests +system.iocache.replacements 47570 # number of replacements +system.iocache.tagsinuse 0.103974 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47598 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47586 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4992018141000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.103934 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.006496 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.006496 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 917 # number of ReadReq misses -system.iocache.ReadReq_misses::total 917 # number of ReadReq misses +system.iocache.warmup_cycle 4991995541000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.103974 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.006498 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.006498 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses +system.iocache.ReadReq_misses::total 905 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47637 # number of demand (read+write) misses -system.iocache.demand_misses::total 47637 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47637 # number of overall misses -system.iocache.overall_misses::total 47637 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144155397 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 144155397 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9929896111 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9929896111 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10074051508 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10074051508 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10074051508 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10074051508 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 917 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 917 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses +system.iocache.demand_misses::total 47625 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses +system.iocache.overall_misses::total 47625 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 145555660 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 145555660 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10008674105 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10008674105 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10154229765 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10154229765 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10154229765 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10154229765 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47637 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47637 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47637 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47637 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -230,40 +230,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 157203.268266 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 157203.268266 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212540.584568 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 212540.584568 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211475.355459 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 211475.355459 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211475.355459 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 211475.355459 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 131232 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160834.983425 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 160834.983425 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214226.757384 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 214226.757384 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 213212.173543 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 213212.173543 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 213212.173543 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 213212.173543 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 133059 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11911 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 12235 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.017715 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.875276 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 917 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 917 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 905 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 905 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47637 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47637 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47637 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47637 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96449927 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 96449927 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7499098563 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7499098563 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7595548490 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7595548490 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7595548490 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7595548490 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47625 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47625 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47625 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47625 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 98473941 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 98473941 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7577901783 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7577901783 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7676375724 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7676375724 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7676375724 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7676375724 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -272,18 +272,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105179.854962 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 105179.854962 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160511.527461 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 160511.527461 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159446.406995 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 159446.406995 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159446.406995 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 159446.406995 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108810.984530 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 108810.984530 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162198.240218 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 162198.240218 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 161183.742236 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 161183.742236 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 161183.742236 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 161183.742236 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -293,142 +293,142 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 86228247 # Number of BP lookups -system.cpu.branchPred.condPredicted 86228247 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1109691 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 81322722 # Number of BTB lookups -system.cpu.branchPred.BTBHits 79235054 # Number of BTB hits +system.cpu.branchPred.lookups 86237029 # Number of BP lookups +system.cpu.branchPred.condPredicted 86237029 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1109949 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 81299216 # Number of BTB lookups +system.cpu.branchPred.BTBHits 79239397 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.432860 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 97.466373 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.numCycles 448477988 # number of cpu cycles simulated +system.cpu.numCycles 448469531 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27463696 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 426083477 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86228247 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79235054 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 163617772 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4719624 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 125826 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 63227537 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 35895 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 53383 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 393 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9034836 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 484573 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2662 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 258095876 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.259036 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.417947 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27529474 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 426122909 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86237029 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79239397 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 163627324 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4728707 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 117219 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 63156445 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36498 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 53889 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 420 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9038392 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 487130 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2791 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 258101520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.259173 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.417982 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 94906138 36.77% 36.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1565225 0.61% 37.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71916844 27.86% 65.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 940016 0.36% 65.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1600383 0.62% 66.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2424857 0.94% 67.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1078498 0.42% 67.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1383259 0.54% 68.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82280656 31.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 94901402 36.77% 36.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1566001 0.61% 37.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71924847 27.87% 65.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 935145 0.36% 65.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1600289 0.62% 66.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2428838 0.94% 67.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1075499 0.42% 67.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1377865 0.53% 68.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82291634 31.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 258095876 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192269 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.950066 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31171664 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60678279 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159406116 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3268443 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3571374 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 838032918 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 987 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3571374 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33913667 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37519467 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 11021070 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159605851 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12464447 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 834371126 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19504 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5869459 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4764277 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 8601 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 995955832 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1811371309 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1811370333 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 976 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964482413 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31473412 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 459237 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 467213 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 28827657 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17084902 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10144761 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1200685 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 943086 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 828239567 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1251844 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 823277169 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 150176 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 22096824 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33604785 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 197691 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 258095876 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.189811 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.384487 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 258101520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192292 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.950171 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31223769 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60616281 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159439032 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3242187 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3580251 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 838065302 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 921 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3580251 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33968457 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37481730 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 11034324 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159610574 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12426184 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 834407058 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 18980 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5821881 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4760224 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 8257 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 995986207 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1811362671 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1811361735 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 936 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964469787 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 31516413 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 458013 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 465231 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 28772388 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17093245 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10135018 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1252851 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1005934 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 828306143 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1250828 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 823325440 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 150511 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 22168488 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33636711 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 196648 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 258101520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.189929 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.384557 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 71559419 27.73% 27.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15540861 6.02% 33.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10303423 3.99% 37.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7474044 2.90% 40.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75918752 29.41% 70.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3850758 1.49% 71.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72514611 28.10% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 781198 0.30% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 152810 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 71580535 27.73% 27.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15499802 6.01% 33.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10327986 4.00% 37.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7455254 2.89% 40.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75927506 29.42% 70.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3856019 1.49% 71.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72517162 28.10% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 787235 0.31% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 150021 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 258095876 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 258101520 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 369026 34.39% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 552435 51.48% 85.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 151573 14.13% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 366750 34.22% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 553108 51.61% 85.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 151931 14.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 311214 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 795705202 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 309801 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 795758940 96.65% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued @@ -457,246 +457,246 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17863780 2.17% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9396973 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17866354 2.17% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9390345 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 823277169 # Type of FU issued -system.cpu.iq.rate 1.835714 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1073034 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001303 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1906003583 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 851598062 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 818801577 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 376 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 823325440 # Type of FU issued +system.cpu.iq.rate 1.835856 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1071789 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001302 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1906104602 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 851735215 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 818848735 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 378 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 450 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 94 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 824038818 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 824087257 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 171 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1644527 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 1645357 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3094800 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 23435 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11502 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1720038 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3104742 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 23669 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11440 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1716567 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932547 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 11959 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932461 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11842 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3571374 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26260647 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2115726 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 829491411 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 321621 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17084902 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10144761 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 719315 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1617594 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12405 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11502 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 654420 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 592576 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1246996 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 821399469 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17452724 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1877699 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3580251 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26245227 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2113533 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 829556971 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 304073 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17093245 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10135018 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 718533 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1617499 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11192 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11440 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 653820 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 594083 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1247903 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 821445654 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17451760 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1879785 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26617414 # number of memory reference insts executed -system.cpu.iew.exec_branches 83217280 # Number of branches executed -system.cpu.iew.exec_stores 9164690 # Number of stores executed -system.cpu.iew.exec_rate 1.831527 # Inst execution rate -system.cpu.iew.wb_sent 820937084 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 818801671 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639944880 # num instructions producing a value -system.cpu.iew.wb_consumers 1045797819 # num instructions consuming a value +system.cpu.iew.exec_refs 26608752 # number of memory reference insts executed +system.cpu.iew.exec_branches 83225006 # Number of branches executed +system.cpu.iew.exec_stores 9156992 # Number of stores executed +system.cpu.iew.exec_rate 1.831664 # Inst execution rate +system.cpu.iew.wb_sent 820984205 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 818848829 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639993786 # num instructions producing a value +system.cpu.iew.wb_consumers 1045886534 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.825734 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611920 # average fanout of values written-back +system.cpu.iew.wb_rate 1.825874 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611915 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 22903910 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1054151 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1114557 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 254524502 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.168565 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.854370 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 22977930 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1054178 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1115022 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 254521269 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.168575 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.855004 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82731188 32.50% 32.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11811542 4.64% 37.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3909670 1.54% 38.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74949600 29.45% 68.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2435927 0.96% 69.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1480813 0.58% 69.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 938860 0.37% 70.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70918382 27.86% 97.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5348520 2.10% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82765060 32.52% 32.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11818595 4.64% 37.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3860584 1.52% 38.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74956276 29.45% 68.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2441275 0.96% 69.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1480165 0.58% 69.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 888603 0.35% 70.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70922136 27.86% 97.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5388575 2.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 254524502 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407992820 # Number of instructions committed -system.cpu.commit.committedOps 806477449 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 254521269 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407981680 # Number of instructions committed +system.cpu.commit.committedOps 806469686 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22414822 # Number of memory references committed -system.cpu.commit.loads 13990099 # Number of loads committed -system.cpu.commit.membars 474403 # Number of memory barriers committed -system.cpu.commit.branches 82204209 # Number of branches committed +system.cpu.commit.refs 22406951 # Number of memory references committed +system.cpu.commit.loads 13988500 # Number of loads committed +system.cpu.commit.membars 474453 # Number of memory barriers committed +system.cpu.commit.branches 82201236 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735419466 # Number of committed integer instructions. +system.cpu.commit.int_insts 735408262 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5348520 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5388575 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1078479140 # The number of ROB reads -system.cpu.rob.rob_writes 1662352652 # The number of ROB writes -system.cpu.timesIdled 1219186 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 190382112 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9817459293 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407992820 # Number of Instructions Simulated -system.cpu.committedOps 806477449 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407992820 # Number of Instructions Simulated -system.cpu.cpi 1.099230 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.099230 # CPI: Total CPI of All Threads -system.cpu.ipc 0.909728 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.909728 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1507089895 # number of integer regfile reads -system.cpu.int_regfile_writes 977019847 # number of integer regfile writes +system.cpu.rob.rob_reads 1078502153 # The number of ROB reads +system.cpu.rob.rob_writes 1662494402 # The number of ROB writes +system.cpu.timesIdled 1221401 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 190368011 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9817434094 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407981680 # Number of Instructions Simulated +system.cpu.committedOps 806469686 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407981680 # Number of Instructions Simulated +system.cpu.cpi 1.099239 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.099239 # CPI: Total CPI of All Threads +system.cpu.ipc 0.909720 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.909720 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1507130605 # number of integer regfile reads +system.cpu.int_regfile_writes 977067823 # number of integer regfile writes system.cpu.fp_regfile_reads 94 # number of floating regfile reads -system.cpu.misc_regfile_reads 264717116 # number of misc regfile reads -system.cpu.misc_regfile_writes 402314 # number of misc regfile writes -system.cpu.icache.replacements 1047040 # number of replacements -system.cpu.icache.tagsinuse 510.337680 # Cycle average of tags in use -system.cpu.icache.total_refs 7922656 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1047552 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.563019 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 56182186000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.337680 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996753 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996753 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7922656 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7922656 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7922656 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7922656 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7922656 # number of overall hits -system.cpu.icache.overall_hits::total 7922656 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1112177 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1112177 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1112177 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1112177 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1112177 # number of overall misses -system.cpu.icache.overall_misses::total 1112177 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15267217991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15267217991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15267217991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15267217991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15267217991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15267217991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9034833 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9034833 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9034833 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9034833 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9034833 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9034833 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123099 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123099 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123099 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123099 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123099 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123099 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13727.327567 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13727.327567 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13727.327567 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13727.327567 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13727.327567 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13727.327567 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 9786 # number of cycles access was blocked +system.cpu.misc_regfile_reads 264732336 # number of misc regfile reads +system.cpu.misc_regfile_writes 402254 # number of misc regfile writes +system.cpu.icache.replacements 1049385 # number of replacements +system.cpu.icache.tagsinuse 509.447090 # Cycle average of tags in use +system.cpu.icache.total_refs 7923264 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1049897 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.546706 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 56158934000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 509.447090 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.995014 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.995014 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7923264 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7923264 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7923264 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7923264 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7923264 # number of overall hits +system.cpu.icache.overall_hits::total 7923264 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1115125 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1115125 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1115125 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1115125 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1115125 # number of overall misses +system.cpu.icache.overall_misses::total 1115125 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15322207492 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15322207492 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15322207492 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15322207492 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15322207492 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15322207492 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9038389 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9038389 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9038389 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9038389 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9038389 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9038389 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123377 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123377 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123377 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123377 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123377 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123377 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13740.349729 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13740.349729 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13740.349729 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13740.349729 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13740.349729 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13740.349729 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 10877 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 290 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 301 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 33.744828 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 36.136213 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62286 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 62286 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 62286 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 62286 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 62286 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 62286 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1049891 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1049891 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1049891 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1049891 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1049891 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1049891 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12557489993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12557489993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12557489993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12557489993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12557489993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12557489993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116205 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116205 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116205 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116205 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116205 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116205 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11960.755919 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11960.755919 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11960.755919 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11960.755919 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11960.755919 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11960.755919 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62547 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 62547 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 62547 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 62547 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 62547 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 62547 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1052578 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1052578 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1052578 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1052578 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1052578 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1052578 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12612158993 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12612158993 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12612158993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12612158993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12612158993 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12612158993 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116456 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116456 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116456 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116456 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116456 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116456 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11982.160935 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11982.160935 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11982.160935 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11982.160935 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11982.160935 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11982.160935 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 9201 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.008096 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 25985 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 9214 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.820165 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5102794236000 # Cycle when the warmup percentage was hit. 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was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.007408 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375463 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.375463 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 27369 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 27369 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25991 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 25991 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25991 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 25991 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10086 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 10086 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10086 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 10086 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10086 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 10086 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 117807500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 117807500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 117807500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 117807500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 117807500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 117807500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36075 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 36075 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 27371 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 27371 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 27371 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 27371 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9373 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 9373 # number of ReadReq misses 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overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36742 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 36742 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36077 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 36077 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36077 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 36077 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.279584 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.279584 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.279569 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.279569 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.279569 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.279569 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11680.299425 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11680.299425 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11680.299425 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11680.299425 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11680.299425 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11680.299425 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36744 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 36744 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36744 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 36744 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.255103 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.255103 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.255089 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.255089 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.255089 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.255089 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11198.815747 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11198.815747 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11198.815747 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11198.815747 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11198.815747 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11198.815747 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -705,78 +705,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1386 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1386 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10086 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10086 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10086 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10086 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10086 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 10086 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 97635500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 97635500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 97635500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 97635500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 97635500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 97635500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.279584 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.279584 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.279569 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.279569 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.279569 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.279569 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9680.299425 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9680.299425 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9680.299425 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9680.299425 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9680.299425 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9680.299425 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1896 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1896 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9373 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9373 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9373 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 9373 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9373 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 9373 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 86220500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 86220500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 86220500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 86220500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 86220500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 86220500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.255103 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.255103 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.255089 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.255089 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.255089 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.255089 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9198.815747 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9198.815747 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9198.815747 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9198.815747 # average overall mshr miss latency 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-system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.772185 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.772185 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 134808 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 134808 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 134808 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 134808 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 134808 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 134808 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 109105 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 109105 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 109105 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 109105 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 109105 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 109105 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1388403500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1388403500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1388403500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1388403500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1388403500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1388403500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 243913 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 243913 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 243913 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 243913 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 243913 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 243913 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.447311 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.447311 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.447311 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.447311 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.447311 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.447311 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12725.388387 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12725.388387 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12725.388387 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12725.388387 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12725.388387 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12725.388387 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 107843 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 12.947477 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 134583 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 107858 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.247779 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5099863447000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.947477 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809217 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.809217 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 134601 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 134601 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 134601 # number of demand (read+write) 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1371802000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1371802000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1371802000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1371802000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1371802000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 243413 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 243413 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 243413 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 243413 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 243413 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 243413 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.447026 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.447026 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.447026 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.447026 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.447026 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.447026 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12607.083778 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12607.083778 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12607.083778 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12607.083778 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12607.083778 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12607.083778 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -785,146 +785,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 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-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1170193500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1170193500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1170193500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1170193500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1170193500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.447311 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.447311 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.447311 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.447311 # mshr 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cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1154178000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1154178000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1154178000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1154178000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.447026 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.447026 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.447026 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.447026 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.447026 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.447026 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10607.083778 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10607.083778 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10607.083778 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10607.083778 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10607.083778 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10607.083778 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1660424 # number of replacements -system.cpu.dcache.tagsinuse 511.994188 # Cycle average of tags in use -system.cpu.dcache.total_refs 19105277 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1660936 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.502717 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 27985000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.994188 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11003963 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11003963 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8096336 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8096336 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19100299 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19100299 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19100299 # number of overall hits -system.cpu.dcache.overall_hits::total 19100299 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2241441 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2241441 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318912 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318912 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2560353 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2560353 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2560353 # number of overall misses -system.cpu.dcache.overall_misses::total 2560353 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32061348000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32061348000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9677558995 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9677558995 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41738906995 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41738906995 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41738906995 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41738906995 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13245404 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13245404 # number of ReadReq accesses(hits+misses) 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demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118203 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118203 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118203 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14303.900036 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14303.900036 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30345.546718 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30345.546718 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16302.012650 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16302.012650 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16302.012650 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16302.012650 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 390714 # number of cycles access was blocked +system.cpu.dcache.replacements 1657617 # number of replacements +system.cpu.dcache.tagsinuse 511.997737 # Cycle average of tags in use +system.cpu.dcache.total_refs 19103102 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1658129 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.520878 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 27986000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.997737 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 11006955 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11006955 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8090467 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8090467 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19097422 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19097422 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19097422 # number of overall hits +system.cpu.dcache.overall_hits::total 19097422 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2237002 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2237002 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318492 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318492 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2555494 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2555494 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2555494 # number of overall misses +system.cpu.dcache.overall_misses::total 2555494 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32016735000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32016735000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9683080495 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9683080495 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41699815495 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41699815495 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41699815495 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41699815495 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13243957 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13243957 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8408959 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8408959 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21652916 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21652916 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21652916 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21652916 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168907 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.168907 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037875 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037875 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118021 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118021 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118021 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118021 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14312.340803 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14312.340803 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30402.900214 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30402.900214 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16317.712151 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16317.712151 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16317.712151 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16317.712151 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 383482 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42563 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42249 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.179663 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.076712 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 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-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8836657995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26284342995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26284342995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26284342995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26284342995 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97349027500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97349027500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2523629000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2523629000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99872656500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99872656500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103662 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103662 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034750 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034750 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076890 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076890 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076890 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076890 # mshr miss rate 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miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30268.664186 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30268.664186 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15789.233505 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15789.233505 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15789.233505 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15789.233505 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -932,141 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-system.cpu.l2cache.occ_blocks::cpu.dtb.walker 7.214267 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.131819 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3279.773941 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 11476.405015 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.764182 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000110 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 113549 # number of replacements +system.cpu.l2cache.tagsinuse 64828.327724 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3928640 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 177472 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.136675 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 50064.846561 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 9.159250 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.124586 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3285.119507 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 11469.077820 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.763929 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000140 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.050045 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.175116 # Average percentage of cache occupancy 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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128125.833333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55745.876551 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55571.771535 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55658.049036 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10272.484775 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10272.484775 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39403.921676 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39403.921676 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 83578.733333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128125.833333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55745.876551 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42896.616660 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44066.654783 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 83578.733333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128125.833333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55745.876551 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42896.616660 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44066.654783 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 49 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16876 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36893 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 53823 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4124 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 4124 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133799 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133799 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 49 # number of demand (read+write) MSHR misses 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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 257504 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 968789302 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7292325574 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8265302425 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3930045 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 257504 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 968789302 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7292325574 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8265302425 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89237875000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89237875000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2360777500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2360777500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91598652500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91598652500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000686 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016076 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026931 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021280 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.930086 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.930086 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.465043 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.465043 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000686 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016076 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102973 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.066604 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000686 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016076 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102973 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.066604 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 80205 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 51500.800000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57406.334558 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55134.309137 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55869.180796 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10289.063288 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10289.063288 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39299.662232 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39299.662232 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 80205 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 51500.800000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57406.334558 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42722.128594 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44052.949148 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 80205 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 51500.800000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57406.334558 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42722.128594 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44052.949148 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats index 098094868..6d0e83626 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -1,26 +1,26 @@ -Real time: Mar/28/2013 10:19:36 +Real time: Apr/22/2013 16:53:22 Profiler Stats -------------- -Elapsed_time_in_seconds: 824 -Elapsed_time_in_minutes: 13.7333 -Elapsed_time_in_hours: 0.228889 -Elapsed_time_in_days: 0.00953704 +Elapsed_time_in_seconds: 481 +Elapsed_time_in_minutes: 8.01667 +Elapsed_time_in_hours: 0.133611 +Elapsed_time_in_days: 0.00556713 -Virtual_time_in_seconds: 785.96 -Virtual_time_in_minutes: 13.0993 -Virtual_time_in_hours: 0.218322 -Virtual_time_in_days: 0.00909676 +Virtual_time_in_seconds: 480.45 +Virtual_time_in_minutes: 8.0075 +Virtual_time_in_hours: 0.133458 +Virtual_time_in_days: 0.00556076 -Ruby_current_time: 10416271238 +Ruby_current_time: 10410297758 Ruby_start_time: 0 -Ruby_cycles: 10416271238 +Ruby_cycles: 10410297758 -mbytes_resident: 597.965 -mbytes_total: 848.508 -resident_ratio: 0.704734 +mbytes_resident: 604.641 +mbytes_total: 843.926 +resident_ratio: 0.716471 -ruby_cycles_executed: [ 10416271239 10416271239 ] +ruby_cycles_executed: [ 10410297759 10410297759 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 @@ -30,18 +30,18 @@ DMA-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 151895075 average: 1.00011 | standard deviation: 0.0104983 | 0 151878333 16742 ] +sequencer_requests_outstanding: [binsize: 1 max: 2 count: 151886718 average: 1.00011 | standard deviation: 0.0104983 | 0 151869977 16741 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 2 max: 270 count: 151895074 average: 3.45632 | standard deviation: 5.15571 | 0 149239942 0 0 0 0 0 0 0 967471 601 1437653 515 54191 578 16215 159 100 5 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3728 6095 8851 10338 50892 181 524 114 95 129 11 19 5 10 11 7 17 11 13 20 10 22 6 8 20 12 460 4446 10447 18595 13927 42308 850 876 2239 314 825 19 13 50 26 40 9 27 54 19 22 11 23 46 13 18 16 21 30 78 155 130 157 221 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 2 max: 218 count: 14874061 average: 5.10543 | standard deviation: 8.68005 | 0 13485161 0 0 0 0 0 0 0 129669 71 1200389 321 19342 354 4658 120 69 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 946 797 3688 3455 2377 59 103 45 35 24 6 0 1 3 5 3 8 4 3 2 5 4 5 2 7 3 3 1340 2962 4560 6434 5662 323 275 230 120 126 7 4 3 16 9 3 17 8 8 3 7 7 6 3 3 5 5 12 23 21 44 49 12 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 2 max: 270 count: 9471875 average: 5.1858 | standard deviation: 15.4023 | 0 9121731 0 0 0 0 0 0 0 27134 22 181251 122 14247 125 1633 27 16 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 780 3347 3709 6401 48396 97 398 53 53 99 4 17 4 4 4 3 7 5 7 15 3 18 1 5 10 6 457 1055 3050 9771 7123 36234 361 508 1904 182 686 8 8 45 4 27 3 7 43 7 17 3 13 40 5 12 5 11 15 22 105 69 105 209 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 2 max: 213 count: 126380154 average: 3.11846 | standard deviation: 2.02437 | 0 125567964 0 0 0 0 0 0 0 794781 477 434 39 45 17 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1899 1850 989 40 49 13 20 10 1 5 1 2 0 2 1 1 2 1 1 3 0 0 0 1 2 2 0 2035 4358 4208 198 205 161 86 103 7 4 4 1 2 6 4 3 3 3 4 1 1 2 0 5 2 6 5 2 33 28 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_RMW_Read: [binsize: 2 max: 214 count: 490994 average: 6.03795 | standard deviation: 9.42736 | 0 425859 0 0 0 0 0 0 0 10420 25 32755 15 11997 35 8470 5 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83 81 392 393 46 9 3 4 5 1 0 0 0 1 0 0 0 1 2 0 2 0 0 0 1 1 0 8 55 15 120 161 1 4 2 4 9 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_Locked_RMW_Read: [binsize: 2 max: 212 count: 338995 average: 5.4473 | standard deviation: 7.76902 | 0 300232 0 0 0 0 0 0 0 5467 6 22824 18 8560 47 1454 7 6 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 20 73 49 24 3 0 2 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 8 22 41 52 46 4 3 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 338995 average: 3 | standard deviation: 0 | 0 0 0 338995 ] -miss_latency_NULL: [binsize: 2 max: 270 count: 151895074 average: 3.45632 | standard deviation: 5.15571 | 0 149239942 0 0 0 0 0 0 0 967471 601 1437653 515 54191 578 16215 159 100 5 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3728 6095 8851 10338 50892 181 524 114 95 129 11 19 5 10 11 7 17 11 13 20 10 22 6 8 20 12 460 4446 10447 18595 13927 42308 850 876 2239 314 825 19 13 50 26 40 9 27 54 19 22 11 23 46 13 18 16 21 30 78 155 130 157 221 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 2 max: 270 count: 151886717 average: 3.45795 | standard deviation: 5.18215 | 0 149232339 0 0 0 0 0 0 0 967168 602 1434707 493 54299 574 16370 170 112 2 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3741 6150 8984 10304 51755 196 509 88 111 143 4 23 9 11 17 5 17 5 8 27 4 15 2 9 6 9 472 4506 10321 18243 13984 43613 883 877 2441 340 822 17 25 50 17 23 15 17 60 7 30 13 21 47 21 27 9 21 24 90 134 133 147 269 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 216 count: 14872957 average: 5.10751 | standard deviation: 8.69983 | 0 13484012 0 0 0 0 0 0 0 129492 97 1200237 320 19353 366 4823 123 70 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 919 791 3671 3477 2370 72 98 38 42 34 2 3 2 5 2 3 1 0 2 0 1 4 1 3 1 5 6 1421 2829 4534 6423 5889 348 264 260 122 133 10 9 4 7 1 7 4 5 1 6 6 4 4 8 6 4 10 4 25 22 57 48 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 270 count: 9468113 average: 5.20871 | standard deviation: 15.524 | 0 9118662 0 0 0 0 0 0 0 27223 26 178592 96 14286 118 1530 29 18 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 770 3337 3846 6346 49267 90 393 32 59 105 1 20 4 2 15 2 13 3 2 21 2 9 0 4 4 3 465 1055 3041 9490 7168 37336 375 495 2067 204 683 2 13 45 6 20 6 10 50 5 24 6 14 40 6 18 3 9 17 31 81 62 93 235 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 214 count: 126376928 average: 3.11849 | standard deviation: 2.02507 | 0 125564891 0 0 0 0 0 0 0 794588 449 385 48 51 21 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1937 1912 1006 41 48 20 17 14 2 3 1 0 2 3 0 0 3 2 2 6 1 2 1 1 0 1 1 2014 4386 4163 214 182 154 101 111 7 3 5 3 1 4 2 2 3 5 1 0 1 3 3 7 3 1 2 3 33 29 13 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_RMW_Read: [binsize: 2 max: 215 count: 490895 average: 6.04017 | standard deviation: 9.43848 | 0 425774 0 0 0 0 0 0 0 10405 25 32646 14 12062 22 8519 5 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 86 87 389 392 44 14 0 4 7 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 9 45 16 122 165 3 12 1 6 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Locked_RMW_Read: [binsize: 2 max: 216 count: 338912 average: 5.45579 | standard deviation: 7.80876 | 0 300088 0 0 0 0 0 0 0 5460 5 22847 15 8547 47 1498 13 7 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 23 72 48 26 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 7 20 40 57 41 3 5 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 338912 average: 3 | standard deviation: 0 | 0 0 0 338912 ] +miss_latency_NULL: [binsize: 2 max: 270 count: 151886717 average: 3.45795 | standard deviation: 5.18215 | 0 149232339 0 0 0 0 0 0 0 967168 602 1434707 493 54299 574 16370 170 112 2 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3741 6150 8984 10304 51755 196 509 88 111 143 4 23 9 11 17 5 17 5 8 27 4 15 2 9 6 9 472 4506 10321 18243 13984 43613 883 877 2441 340 822 17 25 50 17 23 15 17 60 7 30 13 21 47 21 27 9 21 24 90 134 133 147 269 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -52,12 +52,12 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] imcomplete_dir_Times: 0 -miss_latency_LD_NULL: [binsize: 2 max: 218 count: 14874061 average: 5.10543 | standard deviation: 8.68005 | 0 13485161 0 0 0 0 0 0 0 129669 71 1200389 321 19342 354 4658 120 69 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 946 797 3688 3455 2377 59 103 45 35 24 6 0 1 3 5 3 8 4 3 2 5 4 5 2 7 3 3 1340 2962 4560 6434 5662 323 275 230 120 126 7 4 3 16 9 3 17 8 8 3 7 7 6 3 3 5 5 12 23 21 44 49 12 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_NULL: [binsize: 2 max: 270 count: 9471875 average: 5.1858 | standard deviation: 15.4023 | 0 9121731 0 0 0 0 0 0 0 27134 22 181251 122 14247 125 1633 27 16 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 780 3347 3709 6401 48396 97 398 53 53 99 4 17 4 4 4 3 7 5 7 15 3 18 1 5 10 6 457 1055 3050 9771 7123 36234 361 508 1904 182 686 8 8 45 4 27 3 7 43 7 17 3 13 40 5 12 5 11 15 22 105 69 105 209 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH_NULL: [binsize: 2 max: 213 count: 126380154 average: 3.11846 | standard deviation: 2.02437 | 0 125567964 0 0 0 0 0 0 0 794781 477 434 39 45 17 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1899 1850 989 40 49 13 20 10 1 5 1 2 0 2 1 1 2 1 1 3 0 0 0 1 2 2 0 2035 4358 4208 198 205 161 86 103 7 4 4 1 2 6 4 3 3 3 4 1 1 2 0 5 2 6 5 2 33 28 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_RMW_Read_NULL: [binsize: 2 max: 214 count: 490994 average: 6.03795 | standard deviation: 9.42736 | 0 425859 0 0 0 0 0 0 0 10420 25 32755 15 11997 35 8470 5 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83 81 392 393 46 9 3 4 5 1 0 0 0 1 0 0 0 1 2 0 2 0 0 0 1 1 0 8 55 15 120 161 1 4 2 4 9 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_Locked_RMW_Read_NULL: [binsize: 2 max: 212 count: 338995 average: 5.4473 | standard deviation: 7.76902 | 0 300232 0 0 0 0 0 0 0 5467 6 22824 18 8560 47 1454 7 6 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 20 73 49 24 3 0 2 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 8 22 41 52 46 4 3 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 338995 average: 3 | standard deviation: 0 | 0 0 0 338995 ] +miss_latency_LD_NULL: [binsize: 2 max: 216 count: 14872957 average: 5.10751 | standard deviation: 8.69983 | 0 13484012 0 0 0 0 0 0 0 129492 97 1200237 320 19353 366 4823 123 70 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 919 791 3671 3477 2370 72 98 38 42 34 2 3 2 5 2 3 1 0 2 0 1 4 1 3 1 5 6 1421 2829 4534 6423 5889 348 264 260 122 133 10 9 4 7 1 7 4 5 1 6 6 4 4 8 6 4 10 4 25 22 57 48 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 2 max: 270 count: 9468113 average: 5.20871 | standard deviation: 15.524 | 0 9118662 0 0 0 0 0 0 0 27223 26 178592 96 14286 118 1530 29 18 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 770 3337 3846 6346 49267 90 393 32 59 105 1 20 4 2 15 2 13 3 2 21 2 9 0 4 4 3 465 1055 3041 9490 7168 37336 375 495 2067 204 683 2 13 45 6 20 6 10 50 5 24 6 14 40 6 18 3 9 17 31 81 62 93 235 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_NULL: [binsize: 2 max: 214 count: 126376928 average: 3.11849 | standard deviation: 2.02507 | 0 125564891 0 0 0 0 0 0 0 794588 449 385 48 51 21 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1937 1912 1006 41 48 20 17 14 2 3 1 0 2 3 0 0 3 2 2 6 1 2 1 1 0 1 1 2014 4386 4163 214 182 154 101 111 7 3 5 3 1 4 2 2 3 5 1 0 1 3 3 7 3 1 2 3 33 29 13 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_RMW_Read_NULL: [binsize: 2 max: 215 count: 490895 average: 6.04017 | standard deviation: 9.43848 | 0 425774 0 0 0 0 0 0 0 10405 25 32646 14 12062 22 8519 5 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 86 87 389 392 44 14 0 4 7 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 9 45 16 122 165 3 12 1 6 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Locked_RMW_Read_NULL: [binsize: 2 max: 216 count: 338912 average: 5.45579 | standard deviation: 7.80876 | 0 300088 0 0 0 0 0 0 0 5460 5 22847 15 8547 47 1498 13 7 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 23 72 48 26 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 7 20 40 57 41 3 5 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 338912 average: 3 | standard deviation: 0 | 0 0 0 338912 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -71,10 +71,10 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 1 max: 19 count: 10868463 average: 0.59509 | standard deviation: 1.42425 | 9251200 1053 635 975 1612868 1042 121 110 109 275 4 9 9 51 0 0 1 0 0 1 ] - virtual_network_0_delay_cycles: [binsize: 1 max: 19 count: 6100210 average: 1.0435 | standard deviation: 1.75778 | 4509207 549 222 262 1588385 908 120 110 101 271 4 9 9 51 0 0 1 0 0 1 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4687708 average: 0.0215679 | standard deviation: 0.291665 | 4661845 408 333 614 24389 107 1 0 8 3 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 80545 average: 0.0133217 | standard deviation: 0.21003 | 80148 96 80 99 94 27 0 0 0 1 ] +Total_delay_cycles: [binsize: 1 max: 13 count: 10870925 average: 0.594928 | standard deviation: 1.42414 | 9253812 1012 651 887 1612847 1000 118 100 122 292 7 8 8 61 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 13 count: 6098339 average: 1.04364 | standard deviation: 1.75794 | 4507669 499 240 245 1588105 876 117 99 116 289 7 8 8 61 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4691441 average: 0.0216927 | standard deviation: 0.292466 | 4665403 421 342 554 24629 83 1 0 6 2 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 81145 average: 0.0143817 | standard deviation: 0.224975 | 80740 92 69 88 113 41 0 1 0 1 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -86,82 +86,82 @@ Total_delay_cycles: [binsize: 1 max: 19 count: 10868463 average: 0.59509 | stand Resource Usage -------------- page_size: 4096 -user_time: 784 -system_time: 1 -page_reclaims: 148403 -page_faults: 35 +user_time: 479 +system_time: 0 +page_reclaims: 146294 +page_faults: 18 swaps: 0 -block_inputs: 20600 -block_outputs: 736 +block_inputs: 16016 +block_outputs: 528 Network Stats ------------- -total_msg_count_Control: 8498316 67986528 -total_msg_count_Request_Control: 239871 1918968 -total_msg_count_Response_Data: 8796423 633342456 -total_msg_count_Response_Control: 10879743 87037944 -total_msg_count_Writeback_Data: 4769004 343368288 -total_msg_count_Writeback_Control: 289518 2316144 -total_msgs: 33472875 total_bytes: 1135970328 +total_msg_count_Control: 8502765 68022120 +total_msg_count_Request_Control: 241699 1933592 +total_msg_count_Response_Data: 8804706 633938832 +total_msg_count_Response_Control: 10887918 87103344 +total_msg_count_Writeback_Data: 4768101 343303272 +total_msg_count_Writeback_Control: 288537 2308296 +total_msgs: 33493726 total_bytes: 1136609456 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.0315382 - links_utilized_percent_switch_0_link_0: 0.037253 bw: 16000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.0258234 bw: 16000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Request_Control: 41862 334896 [ 41862 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 805815 58018680 [ 0 805815 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 466550 3732400 [ 0 466550 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 817583 6540664 [ 817583 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 39381 2835432 [ 0 39381 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 495523 3964184 [ 0 15983 479540 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 408673 29424456 [ 408575 98 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 34072 272576 [ 34072 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 0.0345328 + links_utilized_percent_switch_0_link_0: 0.0411595 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.0279062 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Request_Control: 42248 337984 [ 42248 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 890958 64148976 [ 0 890958 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 508775 4070200 [ 0 508775 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 902852 7222816 [ 902852 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 39576 2849472 [ 0 39576 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 538021 4304168 [ 0 16306 521715 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 441060 31756320 [ 440947 113 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 43642 349136 [ 43642 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.0764968 - links_utilized_percent_switch_1_link_0: 0.0852244 bw: 16000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.0677692 bw: 16000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Request_Control: 38683 309464 [ 38683 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 1828030 131618160 [ 0 1828030 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 1263466 10107728 [ 0 1263466 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Control: 1837549 14700392 [ 1837549 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 32554 2343888 [ 0 32554 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 1296124 10368992 [ 0 16536 1279588 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Data: 1180995 85031640 [ 1180869 126 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 62434 499472 [ 62434 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 0.0735425 + links_utilized_percent_switch_1_link_0: 0.0813498 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.0657351 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 38897 311176 [ 38897 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 1741967 125421624 [ 0 1741967 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 1220914 9767312 [ 0 1220914 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 1751526 14012208 [ 1751526 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 32667 2352024 [ 0 32667 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 1253613 10028904 [ 0 16665 1236948 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 1148307 82678104 [ 1148172 135 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 52537 420296 [ 52537 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.112511 - links_utilized_percent_switch_2_link_0: 0.0996306 bw: 16000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.125392 bw: 16000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Control: 2655132 21241056 [ 2655132 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 201773 14527656 [ 0 201773 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 1880978 15047824 [ 0 121850 1759128 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Data: 1589668 114456096 [ 1589444 224 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 96506 772048 [ 96506 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 177640 1421120 [ 177640 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 78781 630248 [ 78781 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 2682566 193144752 [ 0 2682566 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 1722824 13782592 [ 0 1722824 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_2: 0.112637 + links_utilized_percent_switch_2_link_0: 0.0997841 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.125489 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Control: 2654378 21235024 [ 2654378 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 204194 14701968 [ 0 204194 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 1883048 15064384 [ 0 124385 1758663 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Data: 1589367 114434424 [ 1589119 248 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 96179 769432 [ 96179 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 179877 1439016 [ 179877 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 79409 635272 [ 79409 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 2682782 193160304 [ 0 2682782 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 1723320 13786560 [ 0 1723320 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.00665498 - links_utilized_percent_switch_3_link_0: 0.00509748 bw: 16000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.00821249 bw: 16000 base_latency: 1 +links_utilized_percent_switch_3: 0.0067475 + links_utilized_percent_switch_3_link_0: 0.00517033 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.00832467 bw: 16000 base_latency: 1 - outgoing_messages_switch_3_link_0_Control: 177640 1421120 [ 177640 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 96523 6949656 [ 0 96523 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 15587 124696 [ 0 15587 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 177640 12790080 [ 0 177640 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 112110 896880 [ 0 112110 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Control: 179877 1439016 [ 179877 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 97783 7040376 [ 0 97783 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 16569 132552 [ 0 16569 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 179877 12951144 [ 0 179877 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 114352 914816 [ 0 114352 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 @@ -172,117 +172,117 @@ links_utilized_percent_switch_4: 0 switch_5_inlinks: 5 switch_5_outlinks: 5 -links_utilized_percent_switch_5: 0.0454411 - links_utilized_percent_switch_5_link_0: 0.037253 bw: 16000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.0852244 bw: 16000 base_latency: 1 - links_utilized_percent_switch_5_link_2: 0.0996306 bw: 16000 base_latency: 1 - links_utilized_percent_switch_5_link_3: 0.00509748 bw: 16000 base_latency: 1 +links_utilized_percent_switch_5: 0.0454927 + links_utilized_percent_switch_5_link_0: 0.0411595 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.0813498 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_2: 0.0997841 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_3: 0.00517033 bw: 16000 base_latency: 1 links_utilized_percent_switch_5_link_4: 0 bw: 16000 base_latency: 1 - outgoing_messages_switch_5_link_0_Request_Control: 41862 334896 [ 41862 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 805815 58018680 [ 0 805815 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 466550 3732400 [ 0 466550 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Request_Control: 38683 309464 [ 38683 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 1828030 131618160 [ 0 1828030 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 1263466 10107728 [ 0 1263466 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_2_Control: 2655132 21241056 [ 2655132 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_2_Response_Data: 201773 14527656 [ 0 201773 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_2_Response_Control: 1880978 15047824 [ 0 121850 1759128 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_2_Writeback_Data: 1589668 114456096 [ 1589444 224 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_2_Writeback_Control: 96506 772048 [ 96506 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_3_Control: 177640 1421120 [ 177640 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_3_Response_Data: 96523 6949656 [ 0 96523 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_3_Response_Control: 15587 124696 [ 0 15587 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Request_Control: 42248 337984 [ 42248 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 890958 64148976 [ 0 890958 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 508775 4070200 [ 0 508775 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Request_Control: 38897 311176 [ 38897 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 1741967 125421624 [ 0 1741967 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 1220914 9767312 [ 0 1220914 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Control: 2654378 21235024 [ 2654378 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Response_Data: 204194 14701968 [ 0 204194 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Response_Control: 1883048 15064384 [ 0 124385 1758663 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Writeback_Data: 1589367 114434424 [ 1589119 248 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Writeback_Control: 96179 769432 [ 96179 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_3_Control: 179877 1439016 [ 179877 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_3_Response_Data: 97783 7040376 [ 0 97783 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_3_Response_Control: 16569 132552 [ 0 16569 0 0 0 0 0 0 0 0 ] base_latency: 1 Cache Stats: system.ruby.l1_cntrl0.L1IcacheMemory - system.ruby.l1_cntrl0.L1IcacheMemory_total_misses: 313126 - system.ruby.l1_cntrl0.L1IcacheMemory_total_demand_misses: 313126 + system.ruby.l1_cntrl0.L1IcacheMemory_total_misses: 352190 + system.ruby.l1_cntrl0.L1IcacheMemory_total_demand_misses: 352190 system.ruby.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 system.ruby.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 system.ruby.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 system.ruby.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% - system.ruby.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 313126 100% + system.ruby.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 352190 100% Cache Stats: system.ruby.l1_cntrl0.L1DcacheMemory - system.ruby.l1_cntrl0.L1DcacheMemory_total_misses: 504457 - system.ruby.l1_cntrl0.L1DcacheMemory_total_demand_misses: 504457 + system.ruby.l1_cntrl0.L1DcacheMemory_total_misses: 550662 + system.ruby.l1_cntrl0.L1DcacheMemory_total_demand_misses: 550662 system.ruby.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 system.ruby.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 system.ruby.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.l1_cntrl0.L1DcacheMemory_request_type_LD: 54.7331% - system.ruby.l1_cntrl0.L1DcacheMemory_request_type_ST: 45.2669% + system.ruby.l1_cntrl0.L1DcacheMemory_request_type_LD: 55.6706% + system.ruby.l1_cntrl0.L1DcacheMemory_request_type_ST: 44.3294% - system.ruby.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 504457 100% + system.ruby.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 550662 100% --- L1Cache --- - Event Counts - -Load [6004899 8869162 ] 14874061 -Ifetch [67402410 58977750 ] 126380160 -Store [5078812 5562047 ] 10640859 -Inv [16081 16662 ] 32743 -L1_Replacement [790678 1810849 ] 2601527 -Fwd_GETX [12181 11488 ] 23669 -Fwd_GETS [13596 10533 ] 24129 +Load [6569518 8303439 ] 14872957 +Ifetch [70368031 56008906 ] 126376937 +Store [5484765 5152067 ] 10636832 +Inv [16419 16800 ] 33219 +L1_Replacement [875917 1724584 ] 2600501 +Fwd_GETX [12082 11527 ] 23609 +Fwd_GETS [13743 10570 ] 24313 Fwd_GET_INSTR [4 0 ] 4 -Data [367 1125 ] 1492 -Data_Exclusive [240655 1040298 ] 1280953 -DataS_fromL1 [10533 13600 ] 24133 -Data_all_Acks [554260 773007 ] 1327267 -Ack [11768 9519 ] 21287 -Ack_all [12135 10644 ] 22779 -WB_Ack [442647 1243303 ] 1685950 +Data [398 1087 ] 1485 +Data_Exclusive [267040 1013910 ] 1280950 +DataS_fromL1 [10570 13747 ] 24317 +Data_all_Acks [612950 713223 ] 1326173 +Ack [11894 9559 ] 21453 +Ack_all [12292 10646 ] 22938 +WB_Ack [484589 1200709 ] 1685298 PF_Load [0 0 ] 0 PF_Ifetch [0 0 ] 0 PF_Store [0 0 ] 0 - Transitions - -NP Load [267792 1102795 ] 1370587 -NP Ifetch [313000 498627 ] 811627 -NP Store [210910 210451 ] 421361 -NP Inv [5429 3933 ] 9362 +NP Load [298305 1072264 ] 1370569 +NP Ifetch [352056 459391 ] 811447 +NP Store [226579 193953 ] 420532 +NP Inv [5722 3873 ] 9595 NP L1_Replacement [0 0 ] 0 NP PF_Load [0 0 ] 0 NP PF_Ifetch [0 0 ] 0 NP PF_Store [0 0 ] 0 -I Load [8313 10000 ] 18313 -I Ifetch [126 437 ] 563 -I Store [5674 5720 ] 11394 +I Load [8252 10124 ] 18376 +I Ifetch [134 456 ] 590 +I Store [5632 5779 ] 11411 I Inv [0 0 ] 0 -I L1_Replacement [8682 8060 ] 16742 +I L1_Replacement [8759 7985 ] 16744 I PF_Load [0 0 ] 0 I PF_Ifetch [0 0 ] 0 I PF_Store [0 0 ] 0 -S Load [551889 484566 ] 1036455 -S Ifetch [67089280 58478684 ] 125567964 -S Store [11768 9519 ] 21287 -S Inv [10451 12551 ] 23002 -S L1_Replacement [339349 559486 ] 898835 +S Load [574695 455064 ] 1029759 +S Ifetch [70015833 55549058 ] 125564891 +S Store [11894 9559 ] 21453 +S Inv [10461 12745 ] 23206 +S L1_Replacement [382569 515890 ] 898459 S PF_Load [0 0 ] 0 S PF_Store [0 0 ] 0 -E Load [1058703 2799902 ] 3858605 +E Load [1245572 2614603 ] 3860175 E Ifetch [0 0 ] 0 -E Store [78784 87850 ] 166634 -E Inv [103 52 ] 155 -E L1_Replacement [160570 950900 ] 1111470 -E Fwd_GETX [228 182 ] 410 -E Fwd_GETS [848 1108 ] 1956 +E Store [84229 82251 ] 166480 +E Inv [123 47 ] 170 +E L1_Replacement [181344 930396 ] 1111740 +E Fwd_GETX [229 170 ] 399 +E Fwd_GETS [930 990 ] 1920 E Fwd_GET_INSTR [0 0 ] 0 E PF_Load [0 0 ] 0 E PF_Store [0 0 ] 0 -M Load [4118202 4471899 ] 8590101 +M Load [4442694 4151384 ] 8594078 M Ifetch [0 0 ] 0 -M Store [4771676 5248507 ] 10020183 -M Inv [98 126 ] 224 -M L1_Replacement [282077 292403 ] 574480 -M Fwd_GETX [11953 11306 ] 23259 -M Fwd_GETS [12747 9423 ] 22170 +M Store [5156431 4860525 ] 10016956 +M Inv [113 135 ] 248 +M L1_Replacement [303245 270313 ] 573558 +M Fwd_GETX [11853 11357 ] 23210 +M Fwd_GETS [12813 9580 ] 22393 M Fwd_GET_INSTR [4 0 ] 4 M PF_Load [0 0 ] 0 M PF_Store [0 0 ] 0 @@ -292,9 +292,9 @@ IS Ifetch [0 0 ] 0 IS Store [0 0 ] 0 IS Inv [0 0 ] 0 IS L1_Replacement [0 0 ] 0 -IS Data_Exclusive [240655 1040298 ] 1280953 -IS DataS_fromL1 [10533 13600 ] 24133 -IS Data_all_Acks [338043 557961 ] 896004 +IS Data_Exclusive [267040 1013910 ] 1280950 +IS DataS_fromL1 [10570 13747 ] 24317 +IS Data_all_Acks [381137 514578 ] 895715 IS PF_Load [0 0 ] 0 IS PF_Store [0 0 ] 0 @@ -303,8 +303,8 @@ IM Ifetch [0 0 ] 0 IM Store [0 0 ] 0 IM Inv [0 0 ] 0 IM L1_Replacement [0 0 ] 0 -IM Data [367 1125 ] 1492 -IM Data_all_Acks [216217 215046 ] 431263 +IM Data [398 1087 ] 1485 +IM Data_all_Acks [231813 198645 ] 430458 IM Ack [0 0 ] 0 IM PF_Load [0 0 ] 0 IM PF_Store [0 0 ] 0 @@ -314,8 +314,8 @@ SM Ifetch [0 0 ] 0 SM Store [0 0 ] 0 SM Inv [0 0 ] 0 SM L1_Replacement [0 0 ] 0 -SM Ack [11768 9519 ] 21287 -SM Ack_all [12135 10644 ] 22779 +SM Ack [11894 9559 ] 21453 +SM Ack_all [12292 10646 ] 22938 SM PF_Load [0 0 ] 0 SM PF_Store [0 0 ] 0 @@ -331,14 +331,14 @@ IS_I PF_Load [0 0 ] 0 IS_I PF_Store [0 0 ] 0 M_I Load [0 0 ] 0 -M_I Ifetch [4 2 ] 6 +M_I Ifetch [8 1 ] 9 M_I Store [0 0 ] 0 M_I Inv [0 0 ] 0 M_I L1_Replacement [0 0 ] 0 M_I Fwd_GETX [0 0 ] 0 -M_I Fwd_GETS [1 2 ] 3 +M_I Fwd_GETS [0 0 ] 0 M_I Fwd_GET_INSTR [0 0 ] 0 -M_I WB_Ack [442646 1243301 ] 1685947 +M_I WB_Ack [484589 1200709 ] 1685298 M_I PF_Load [0 0 ] 0 M_I PF_Store [0 0 ] 0 @@ -347,7 +347,7 @@ SINK_WB_ACK Ifetch [0 0 ] 0 SINK_WB_ACK Store [0 0 ] 0 SINK_WB_ACK Inv [0 0 ] 0 SINK_WB_ACK L1_Replacement [0 0 ] 0 -SINK_WB_ACK WB_Ack [1 2 ] 3 +SINK_WB_ACK WB_Ack [0 0 ] 0 SINK_WB_ACK PF_Load [0 0 ] 0 SINK_WB_ACK PF_Store [0 0 ] 0 @@ -390,98 +390,98 @@ PF_IS_I DataS_fromL1 [0 0 ] 0 PF_IS_I Data_all_Acks [0 0 ] 0 Cache Stats: system.ruby.l1_cntrl1.L1IcacheMemory - system.ruby.l1_cntrl1.L1IcacheMemory_total_misses: 499064 - system.ruby.l1_cntrl1.L1IcacheMemory_total_demand_misses: 499064 + system.ruby.l1_cntrl1.L1IcacheMemory_total_misses: 459847 + system.ruby.l1_cntrl1.L1IcacheMemory_total_demand_misses: 459847 system.ruby.l1_cntrl1.L1IcacheMemory_total_prefetches: 0 system.ruby.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0 system.ruby.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0 system.ruby.l1_cntrl1.L1IcacheMemory_request_type_IFETCH: 100% - system.ruby.l1_cntrl1.L1IcacheMemory_access_mode_type_Supervisor: 499064 100% + system.ruby.l1_cntrl1.L1IcacheMemory_access_mode_type_Supervisor: 459847 100% Cache Stats: system.ruby.l1_cntrl1.L1DcacheMemory - system.ruby.l1_cntrl1.L1DcacheMemory_total_misses: 1338485 - system.ruby.l1_cntrl1.L1DcacheMemory_total_demand_misses: 1338485 + system.ruby.l1_cntrl1.L1DcacheMemory_total_misses: 1291679 + system.ruby.l1_cntrl1.L1DcacheMemory_total_demand_misses: 1291679 system.ruby.l1_cntrl1.L1DcacheMemory_total_prefetches: 0 system.ruby.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0 system.ruby.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.l1_cntrl1.L1DcacheMemory_request_type_LD: 83.1384% - system.ruby.l1_cntrl1.L1DcacheMemory_request_type_ST: 16.8616% + system.ruby.l1_cntrl1.L1DcacheMemory_request_type_LD: 83.797% + system.ruby.l1_cntrl1.L1DcacheMemory_request_type_ST: 16.203% - system.ruby.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 1338485 100% + system.ruby.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 1291679 100% Cache Stats: system.ruby.l2_cntrl0.L2cacheMemory - system.ruby.l2_cntrl0.L2cacheMemory_total_misses: 225442 - system.ruby.l2_cntrl0.L2cacheMemory_total_demand_misses: 225442 + system.ruby.l2_cntrl0.L2cacheMemory_total_misses: 227803 + system.ruby.l2_cntrl0.L2cacheMemory_total_demand_misses: 227803 system.ruby.l2_cntrl0.L2cacheMemory_total_prefetches: 0 system.ruby.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 system.ruby.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETS: 25.7405% - system.ruby.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 7.27238% - system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETX: 66.9871% + system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETS: 25.6248% + system.ruby.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 7.23871% + system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETX: 67.1365% - system.ruby.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 225442 100% + system.ruby.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 227803 100% --- L2Cache --- - Event Counts - -L1_GET_INSTR [812190 ] 812190 -L1_GETS [1389132 ] 1389132 -L1_GETX [432758 ] 432758 -L1_UPGRADE [21287 ] 21287 -L1_PUTX [1685953 ] 1685953 +L1_GET_INSTR [812037 ] 812037 +L1_GETS [1389190 ] 1389190 +L1_GETX [431946 ] 431946 +L1_UPGRADE [21453 ] 21453 +L1_PUTX [1685298 ] 1685298 L1_PUTX_old [0 ] 0 Fwd_L1_GETX [0 ] 0 Fwd_L1_GETS [0 ] 0 Fwd_L1_GET_INSTR [0 ] 0 -L2_Replacement [96407 ] 96407 -L2_Replacement_clean [15703 ] 15703 -Mem_Data [177640 ] 177640 -Mem_Ack [112110 ] 112110 -WB_Data [23855 ] 23855 -WB_Data_clean [502 ] 502 -Ack [1764 ] 1764 -Ack_all [7976 ] 7976 -Unblock [24133 ] 24133 +L2_Replacement [97649 ] 97649 +L2_Replacement_clean [16703 ] 16703 +Mem_Data [179877 ] 179877 +Mem_Ack [114352 ] 114352 +WB_Data [24047 ] 24047 +WB_Data_clean [518 ] 518 +Ack [1736 ] 1736 +Ack_all [8297 ] 8297 +Unblock [24317 ] 24317 Unblock_Cancel [0 ] 0 -Exclusive_Unblock [1734995 ] 1734995 +Exclusive_Unblock [1734346 ] 1734346 MEM_Inv [0 ] 0 - Transitions - -NP L1_GET_INSTR [16391 ] 16391 -NP L1_GETS [33901 ] 33901 -NP L1_GETX [127348 ] 127348 +NP L1_GET_INSTR [16486 ] 16486 +NP L1_GETS [34061 ] 34061 +NP L1_GETX [129330 ] 129330 NP L1_PUTX [0 ] 0 NP L1_PUTX_old [0 ] 0 -SS L1_GET_INSTR [795630 ] 795630 -SS L1_GETS [83818 ] 83818 -SS L1_GETX [1691 ] 1691 -SS L1_UPGRADE [21287 ] 21287 -SS L1_PUTX [3 ] 3 +SS L1_GET_INSTR [795239 ] 795239 +SS L1_GETS [83682 ] 83682 +SS L1_GETX [1684 ] 1684 +SS L1_UPGRADE [21453 ] 21453 +SS L1_PUTX [0 ] 0 SS L1_PUTX_old [0 ] 0 -SS L2_Replacement [258 ] 258 -SS L2_Replacement_clean [7563 ] 7563 +SS L2_Replacement [262 ] 262 +SS L2_Replacement_clean [7865 ] 7865 SS MEM_Inv [0 ] 0 -M L1_GET_INSTR [165 ] 165 -M L1_GETS [1247052 ] 1247052 -M L1_GETX [280047 ] 280047 +M L1_GET_INSTR [308 ] 308 +M L1_GETS [1246889 ] 1246889 +M L1_GETX [277320 ] 277320 M L1_PUTX [0 ] 0 M L1_PUTX_old [0 ] 0 -M L2_Replacement [95992 ] 95992 -M L2_Replacement_clean [7918 ] 7918 +M L2_Replacement [97222 ] 97222 +M L2_Replacement_clean [8585 ] 8585 M MEM_Inv [0 ] 0 MT L1_GET_INSTR [4 ] 4 -MT L1_GETS [24129 ] 24129 -MT L1_GETX [23669 ] 23669 -MT L1_PUTX [1685947 ] 1685947 +MT L1_GETS [24313 ] 24313 +MT L1_GETX [23609 ] 23609 +MT L1_PUTX [1685298 ] 1685298 MT L1_PUTX_old [0 ] 0 -MT L2_Replacement [157 ] 157 -MT L2_Replacement_clean [222 ] 222 +MT L2_Replacement [165 ] 165 +MT L2_Replacement_clean [253 ] 253 MT MEM_Inv [0 ] 0 M_I L1_GET_INSTR [0 ] 0 @@ -490,7 +490,7 @@ M_I L1_GETX [0 ] 0 M_I L1_UPGRADE [0 ] 0 M_I L1_PUTX [0 ] 0 M_I L1_PUTX_old [0 ] 0 -M_I Mem_Ack [112110 ] 112110 +M_I Mem_Ack [114352 ] 114352 M_I MEM_Inv [0 ] 0 MT_I L1_GET_INSTR [0 ] 0 @@ -499,9 +499,9 @@ MT_I L1_GETX [0 ] 0 MT_I L1_UPGRADE [0 ] 0 MT_I L1_PUTX [0 ] 0 MT_I L1_PUTX_old [0 ] 0 -MT_I WB_Data [108 ] 108 +MT_I WB_Data [114 ] 114 MT_I WB_Data_clean [0 ] 0 -MT_I Ack_all [49 ] 49 +MT_I Ack_all [51 ] 51 MT_I MEM_Inv [0 ] 0 MCT_I L1_GET_INSTR [0 ] 0 @@ -510,9 +510,9 @@ MCT_I L1_GETX [0 ] 0 MCT_I L1_UPGRADE [0 ] 0 MCT_I L1_PUTX [0 ] 0 MCT_I L1_PUTX_old [0 ] 0 -MCT_I WB_Data [116 ] 116 +MCT_I WB_Data [134 ] 134 MCT_I WB_Data_clean [0 ] 0 -MCT_I Ack_all [106 ] 106 +MCT_I Ack_all [119 ] 119 I_I L1_GET_INSTR [0 ] 0 I_I L1_GETS [0 ] 0 @@ -520,8 +520,8 @@ I_I L1_GETX [0 ] 0 I_I L1_UPGRADE [0 ] 0 I_I L1_PUTX [0 ] 0 I_I L1_PUTX_old [0 ] 0 -I_I Ack [1506 ] 1506 -I_I Ack_all [7563 ] 7563 +I_I Ack [1475 ] 1475 +I_I Ack_all [7865 ] 7865 S_I L1_GET_INSTR [0 ] 0 S_I L1_GETS [0 ] 0 @@ -529,8 +529,8 @@ S_I L1_GETX [0 ] 0 S_I L1_UPGRADE [0 ] 0 S_I L1_PUTX [0 ] 0 S_I L1_PUTX_old [0 ] 0 -S_I Ack [258 ] 258 -S_I Ack_all [258 ] 258 +S_I Ack [261 ] 261 +S_I Ack_all [262 ] 262 S_I MEM_Inv [0 ] 0 ISS L1_GET_INSTR [0 ] 0 @@ -540,7 +540,7 @@ ISS L1_PUTX [0 ] 0 ISS L1_PUTX_old [0 ] 0 ISS L2_Replacement [0 ] 0 ISS L2_Replacement_clean [0 ] 0 -ISS Mem_Data [33901 ] 33901 +ISS Mem_Data [34061 ] 34061 ISS MEM_Inv [0 ] 0 IS L1_GET_INSTR [0 ] 0 @@ -550,7 +550,7 @@ IS L1_PUTX [0 ] 0 IS L1_PUTX_old [0 ] 0 IS L2_Replacement [0 ] 0 IS L2_Replacement_clean [0 ] 0 -IS Mem_Data [16391 ] 16391 +IS Mem_Data [16486 ] 16486 IS MEM_Inv [0 ] 0 IM L1_GET_INSTR [0 ] 0 @@ -560,11 +560,11 @@ IM L1_PUTX [0 ] 0 IM L1_PUTX_old [0 ] 0 IM L2_Replacement [0 ] 0 IM L2_Replacement_clean [0 ] 0 -IM Mem_Data [127348 ] 127348 +IM Mem_Data [129330 ] 129330 IM MEM_Inv [0 ] 0 SS_MB L1_GET_INSTR [0 ] 0 -SS_MB L1_GETS [186 ] 186 +SS_MB L1_GETS [183 ] 183 SS_MB L1_GETX [1 ] 1 SS_MB L1_UPGRADE [0 ] 0 SS_MB L1_PUTX [0 ] 0 @@ -572,11 +572,11 @@ SS_MB L1_PUTX_old [0 ] 0 SS_MB L2_Replacement [0 ] 0 SS_MB L2_Replacement_clean [0 ] 0 SS_MB Unblock_Cancel [0 ] 0 -SS_MB Exclusive_Unblock [22978 ] 22978 +SS_MB Exclusive_Unblock [23137 ] 23137 SS_MB MEM_Inv [0 ] 0 MT_MB L1_GET_INSTR [0 ] 0 -MT_MB L1_GETS [46 ] 46 +MT_MB L1_GETS [62 ] 62 MT_MB L1_GETX [2 ] 2 MT_MB L1_UPGRADE [0 ] 0 MT_MB L1_PUTX [0 ] 0 @@ -584,31 +584,20 @@ MT_MB L1_PUTX_old [0 ] 0 MT_MB L2_Replacement [0 ] 0 MT_MB L2_Replacement_clean [0 ] 0 MT_MB Unblock_Cancel [0 ] 0 -MT_MB Exclusive_Unblock [1712017 ] 1712017 +MT_MB Exclusive_Unblock [1711209 ] 1711209 MT_MB MEM_Inv [0 ] 0 -M_MB L1_GET_INSTR [0 ] 0 -M_MB L1_GETS [0 ] 0 -M_MB L1_GETX [0 ] 0 -M_MB L1_UPGRADE [0 ] 0 -M_MB L1_PUTX [0 ] 0 -M_MB L1_PUTX_old [0 ] 0 -M_MB L2_Replacement [0 ] 0 -M_MB L2_Replacement_clean [0 ] 0 -M_MB Exclusive_Unblock [0 ] 0 -M_MB MEM_Inv [0 ] 0 - MT_IIB L1_GET_INSTR [0 ] 0 MT_IIB L1_GETS [0 ] 0 MT_IIB L1_GETX [0 ] 0 MT_IIB L1_UPGRADE [0 ] 0 -MT_IIB L1_PUTX [3 ] 3 +MT_IIB L1_PUTX [0 ] 0 MT_IIB L1_PUTX_old [0 ] 0 MT_IIB L2_Replacement [0 ] 0 MT_IIB L2_Replacement_clean [0 ] 0 -MT_IIB WB_Data [23620 ] 23620 -MT_IIB WB_Data_clean [502 ] 502 -MT_IIB Unblock [11 ] 11 +MT_IIB WB_Data [23791 ] 23791 +MT_IIB WB_Data_clean [518 ] 518 +MT_IIB Unblock [8 ] 8 MT_IIB MEM_Inv [0 ] 0 MT_IB L1_GET_INSTR [0 ] 0 @@ -619,7 +608,7 @@ MT_IB L1_PUTX [0 ] 0 MT_IB L1_PUTX_old [0 ] 0 MT_IB L2_Replacement [0 ] 0 MT_IB L2_Replacement_clean [0 ] 0 -MT_IB WB_Data [11 ] 11 +MT_IB WB_Data [8 ] 8 MT_IB WB_Data_clean [0 ] 0 MT_IB Unblock_Cancel [0 ] 0 MT_IB MEM_Inv [0 ] 0 @@ -632,41 +621,41 @@ MT_SB L1_PUTX [0 ] 0 MT_SB L1_PUTX_old [0 ] 0 MT_SB L2_Replacement [0 ] 0 MT_SB L2_Replacement_clean [0 ] 0 -MT_SB Unblock [24122 ] 24122 +MT_SB Unblock [24309 ] 24309 MT_SB MEM_Inv [0 ] 0 Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 274163 - memory_reads: 177640 - memory_writes: 96523 - memory_refreshes: 588410 - memory_total_request_delays: 1038324 - memory_delays_per_request: 3.78725 - memory_delays_in_input_queue: 39505 - memory_delays_behind_head_of_bank_queue: 7889 - memory_delays_stalled_at_head_of_bank_queue: 990930 - memory_stalls_for_bank_busy: 981321 + memory_total_requests: 277660 + memory_reads: 179877 + memory_writes: 97783 + memory_refreshes: 595612 + memory_total_request_delays: 1053031 + memory_delays_per_request: 3.79252 + memory_delays_in_input_queue: 41105 + memory_delays_behind_head_of_bank_queue: 8032 + memory_delays_stalled_at_head_of_bank_queue: 1003894 + memory_stalls_for_bank_busy: 993997 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 2239 - memory_stalls_for_bus: 7329 + memory_stalls_for_arbitration: 2275 + memory_stalls_for_bus: 7591 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 29 - memory_stalls_for_read_read_turnaround: 12 - accesses_per_bank: 9082 9112 8244 8400 9230 8573 8966 8230 8398 8230 8230 8246 8347 8114 8111 7298 8351 8467 8382 8429 8595 8485 8298 8250 8587 8384 8675 9378 9287 9169 10231 8384 + memory_stalls_for_read_write_turnaround: 24 + memory_stalls_for_read_read_turnaround: 7 + accesses_per_bank: 9197 9271 8435 8566 9408 8743 9113 8368 8530 8379 8370 8376 8453 8237 8220 7443 8424 8515 8423 8429 8600 8511 8363 8339 8693 8492 8814 9468 9371 9231 10342 8536 --- Directory --- - Event Counts - -Fetch [177640 ] 177640 -Data [96523 ] 96523 -Memory_Data [177640 ] 177640 -Memory_Ack [96523 ] 96523 +Fetch [179877 ] 179877 +Data [97783 ] 97783 +Memory_Data [179877 ] 179877 +Memory_Ack [97783 ] 97783 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 -CleanReplacement [15587 ] 15587 +CleanReplacement [16569 ] 16569 - Transitions - -I Fetch [177640 ] 177640 +I Fetch [179877 ] 179877 I DMA_READ [0 ] 0 I DMA_WRITE [0 ] 0 @@ -682,20 +671,20 @@ ID_W Memory_Ack [0 ] 0 ID_W DMA_READ [0 ] 0 ID_W DMA_WRITE [0 ] 0 -M Data [96523 ] 96523 +M Data [97783 ] 97783 M DMA_READ [0 ] 0 M DMA_WRITE [0 ] 0 -M CleanReplacement [15587 ] 15587 +M CleanReplacement [16569 ] 16569 IM Fetch [0 ] 0 IM Data [0 ] 0 -IM Memory_Data [177640 ] 177640 +IM Memory_Data [179877 ] 179877 IM DMA_READ [0 ] 0 IM DMA_WRITE [0 ] 0 MI Fetch [0 ] 0 MI Data [0 ] 0 -MI Memory_Ack [96523 ] 96523 +MI Memory_Ack [97783 ] 97783 MI DMA_READ [0 ] 0 MI DMA_WRITE [0 ] 0 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout index ddc70162e..0fb07bdf2 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-bo gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 28 2013 10:05:24 -gem5 started Mar 28 2013 10:05:51 +gem5 compiled Apr 18 2013 13:38:36 +gem5 started Apr 18 2013 13:38:48 gem5 executing on ribera.cs.wisc.edu command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000000 ticks per second info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5208135619000 because m5_exit instruction encountered +Exiting @ tick 5205148879000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index d9c7ac7b1..79f3ff0c1 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,125 +1,125 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.208136 # Number of seconds simulated -sim_ticks 5208135619000 # Number of ticks simulated -final_tick 5208135619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.205149 # Number of seconds simulated +sim_ticks 5205148879000 # Number of ticks simulated +final_tick 5205148879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 129465 # Simulator instruction rate (inst/s) -host_op_rate 248187 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6321029655 # Simulator tick rate (ticks/s) -host_mem_usage 868876 # Number of bytes of host memory used -host_seconds 823.94 # Real time elapsed on the host -sim_insts 106670761 # Number of instructions simulated -sim_ops 204490715 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 35248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 110464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 48224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 539219248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 38302123 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 112752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 59160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 471821984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 55029081 # Number of bytes read from this memory -system.physmem.bytes_read::total 1104738284 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 539219248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 471821984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1011041232 # Number of instructions bytes read from this memory +host_inst_rate 128983 # Simulator instruction rate (inst/s) +host_op_rate 247272 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6293860084 # Simulator tick rate (ticks/s) +host_mem_usage 868904 # Number of bytes of host memory used +host_seconds 827.02 # Real time elapsed on the host +sim_insts 106671342 # Number of instructions simulated +sim_ops 204498755 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 35240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 160344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 75328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 562944184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 41978278 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 62896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 30152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 448071240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 51341424 # Number of bytes read from this memory +system.physmem.bytes_read::total 1104699086 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 562944184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 448071240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1011015424 # Number of instructions bytes read from this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 30881325 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 36960563 # Number of bytes written to this memory -system.physmem.bytes_written::total 70833008 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 822 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 13808 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 6028 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 67402406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 6418181 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 14094 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 7395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 58977748 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9244544 # Number of read requests responded to by this memory -system.physmem.num_reads::total 142085026 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu0.data 33612947 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 34199698 # Number of bytes written to this memory +system.physmem.bytes_written::total 70803765 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 821 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 20043 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 9416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 70368023 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 6999506 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 7862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3769 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56008905 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8662168 # Number of read requests responded to by this memory +system.physmem.num_reads::total 142080513 # Number of read requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4645692 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 5165176 # Number of write requests responded to by this memory -system.physmem.num_writes::total 9857606 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 6768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 21210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 9259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 103534026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 7354287 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 21649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 11359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 90593260 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 10565985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 212117803 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 103534026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 90593260 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 194127286 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 574314 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::cpu0.data 5025316 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 4781707 # Number of write requests responded to by this memory +system.physmem.num_writes::total 9853761 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 6770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 30805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 14472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 108151409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 8064760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 12083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 5793 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 86082310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 9863584 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 212231986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 108151409 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 86082310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 194233719 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 574643 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 5929439 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 7096697 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13600454 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 581082 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 21210 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 9262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 103534026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13283726 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 21649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 11359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 90593260 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 17662682 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 225718257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 822 # Total number of read requests seen +system.physmem.bw_write::cpu0.data 6457634 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 6570359 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13602640 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 581414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 30805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 14475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 108151409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 14522394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 12083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 5793 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 86082310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 16433943 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 225834626 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 821 # Total number of read requests seen system.physmem.writeReqs 46736 # Total number of write requests seen -system.physmem.cpureqs 47278 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 52608 # Total number of bytes read from memory +system.physmem.cpureqs 47279 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 52544 # Total number of bytes read from memory system.physmem.bytesWritten 2991104 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 35248 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 35240 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 2991104 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 64 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 326 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 309 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 32 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 16 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 32 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 16 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 2992 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2928 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2960 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 2784 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2944 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2848 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2856 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2912 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 2952 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2912 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 2848 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2832 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 3024 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2992 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2976 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2832 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 3024 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2944 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2992 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 2960 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2968 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2992 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 2856 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 2896 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2800 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 2864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 2864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2960 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 2928 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 30 # Number of times wr buffer was full causing retry -system.physmem.totGap 67214585000 # Total gap between requests +system.physmem.numWrRetry 31 # Number of times wr buffer was full causing retry +system.physmem.totGap 64277169000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 310 # Categorize read packet sizes +system.physmem.readPktSize::3 309 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 512 # Categorize read packet sizes @@ -130,7 +130,7 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 46736 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 339 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 30 # What read queue length does an incoming req see @@ -162,15 +162,15 @@ system.physmem.rdQLenPdf::28 2 # Wh system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 2 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 1965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1974 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1999 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 2032 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 2032 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 2032 # What write queue length does an incoming req see @@ -185,23 +185,23 @@ system.physmem.wrQLenPdf::19 2032 # Wh system.physmem.wrQLenPdf::20 2032 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 2032 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 58 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32 # What write queue length does an incoming req see -system.physmem.totQLat 44820022 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 56685022 # Sum of mem lat for all requests -system.physmem.totBusLat 4110000 # Total cycles spent in databus access -system.physmem.totBankLat 7755000 # Total cycles spent in bank access -system.physmem.avgQLat 54525.57 # Average queueing delay per request -system.physmem.avgBankLat 9434.31 # Average bank access latency per request +system.physmem.wrQLenPdf::26 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 33 # What write queue length does an incoming req see +system.physmem.totQLat 41690522 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 53523022 # Sum of mem lat for all requests +system.physmem.totBusLat 4105000 # Total cycles spent in databus access +system.physmem.totBankLat 7727500 # Total cycles spent in bank access +system.physmem.avgQLat 50780.17 # Average queueing delay per request +system.physmem.avgBankLat 9412.30 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 68959.88 # Average memory access latency +system.physmem.avgMemAccLat 65192.48 # Average memory access latency system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s @@ -210,11 +210,11 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.15 # Average write queue length over time -system.physmem.readRowHits 707 # Number of row buffer hits during reads +system.physmem.readRowHits 704 # Number of row buffer hits during reads system.physmem.writeRowHits 45223 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.01 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.75 # Row buffer hit rate for reads system.physmem.writeRowHitRate 96.76 # Row buffer hit rate for writes -system.physmem.avgGap 1413318.16 # Average gap between requests +system.physmem.avgGap 1351581.66 # Average gap between requests system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). @@ -275,52 +275,52 @@ system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array system.ruby.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.cpu0.numCycles 10415384713 # number of cpu cycles simulated +system.cpu0.numCycles 10410297758 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 58007070 # Number of instructions committed -system.cpu0.committedOps 111693294 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 104699305 # Number of integer alu accesses +system.cpu0.committedInsts 60288276 # Number of instructions committed +system.cpu0.committedOps 115773081 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 108731496 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 0 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9926831 # number of instructions that are conditional controls -system.cpu0.num_int_insts 104699305 # number of integer instructions +system.cpu0.num_conditional_control_insts 10277696 # number of instructions that are conditional controls +system.cpu0.num_int_insts 108731496 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 256785271 # number of times the integer registers were read -system.cpu0.num_int_register_writes 132412981 # number of times the integer registers were written +system.cpu0.num_int_register_reads 267473663 # number of times the integer registers were read +system.cpu0.num_int_register_writes 137108635 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 11918647 # number of memory refs -system.cpu0.num_load_insts 7262283 # Number of load instructions -system.cpu0.num_store_insts 4656364 # Number of store instructions -system.cpu0.num_idle_cycles 9902585340.160280 # Number of idle cycles -system.cpu0.num_busy_cycles 512799372.839719 # Number of busy cycles -system.cpu0.not_idle_fraction 0.049235 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.950765 # Percentage of idle cycles +system.cpu0.num_mem_refs 12880520 # number of memory refs +system.cpu0.num_load_insts 7843945 # Number of load instructions +system.cpu0.num_store_insts 5036575 # Number of store instructions +system.cpu0.num_idle_cycles 9879714305.974102 # Number of idle cycles +system.cpu0.num_busy_cycles 530583452.025898 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050967 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949033 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.numCycles 10416271238 # number of cpu cycles simulated +system.cpu1.numCycles 10407399002 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48663691 # Number of instructions committed -system.cpu1.committedOps 92797421 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 89245391 # Number of integer alu accesses +system.cpu1.committedInsts 46383066 # Number of instructions committed +system.cpu1.committedOps 88725674 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 85218419 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 0 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 8303775 # number of instructions that are conditional controls -system.cpu1.num_int_insts 89245391 # number of integer instructions +system.cpu1.num_conditional_control_insts 7955161 # number of instructions that are conditional controls +system.cpu1.num_int_insts 85218419 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 224679883 # number of times the integer registers were read -system.cpu1.num_int_register_writes 106822538 # number of times the integer registers were written +system.cpu1.num_int_register_reads 213998429 # number of times the integer registers were read +system.cpu1.num_int_register_writes 102139748 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 14447171 # number of memory refs -system.cpu1.num_load_insts 9256256 # Number of load instructions -system.cpu1.num_store_insts 5190915 # Number of store instructions -system.cpu1.num_idle_cycles 10072379281.574066 # Number of idle cycles -system.cpu1.num_busy_cycles 343891956.425934 # Number of busy cycles -system.cpu1.not_idle_fraction 0.033015 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.966985 # Percentage of idle cycles +system.cpu1.num_mem_refs 13480502 # number of memory refs +system.cpu1.num_load_insts 8673583 # Number of load instructions +system.cpu1.num_store_insts 4806919 # Number of store instructions +system.cpu1.num_idle_cycles 10081113907.619320 # Number of idle cycles +system.cpu1.num_busy_cycles 326285094.380681 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031351 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968649 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 329a0721d..665c3f4ff 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 26 2013 15:13:59 -gem5 started Mar 27 2013 00:05:57 +gem5 compiled Apr 18 2013 13:37:41 +gem5 started Apr 18 2013 14:16:02 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -81,4 +81,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 434516346000 because target called exit() +Exiting @ tick 434543595000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index c0fc89981..97c2e1466 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,103 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.434516 # Number of seconds simulated -sim_ticks 434516346000 # Number of ticks simulated -final_tick 434516346000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.434544 # Number of seconds simulated +sim_ticks 434543595000 # Number of ticks simulated +final_tick 434543595000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41156 # Simulator instruction rate (inst/s) -host_op_rate 76102 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21627180 # Simulator tick rate (ticks/s) -host_mem_usage 403680 # Number of bytes of host memory used -host_seconds 20091.22 # Real time elapsed on the host +host_inst_rate 65471 # Simulator instruction rate (inst/s) +host_op_rate 121063 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34406418 # Simulator tick rate (ticks/s) +host_mem_usage 403752 # Number of bytes of host memory used +host_seconds 12629.72 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 207552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24467712 # Number of bytes read from this memory -system.physmem.bytes_read::total 24675264 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 207552 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 207552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18791168 # Number of bytes written to this memory -system.physmem.bytes_written::total 18791168 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3243 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382308 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385551 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293612 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293612 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 477662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 56310222 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 56787884 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 477662 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 477662 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43246171 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43246171 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43246171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 477662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 56310222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 100034055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385553 # Total number of read requests seen -system.physmem.writeReqs 293612 # Total number of write requests seen -system.physmem.cpureqs 889187 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 24675264 # Total number of bytes read from memory -system.physmem.bytesWritten 18791168 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24675264 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18791168 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 146 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 209992 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 23303 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 24507 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 23750 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 22586 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 23590 # Track reads on a per bank basis +system.physmem.bytes_read::cpu.inst 207168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24469184 # Number of bytes read from this memory +system.physmem.bytes_read::total 24676352 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 207168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 207168 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18791424 # Number of bytes written to this memory +system.physmem.bytes_written::total 18791424 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3237 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382331 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385568 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293616 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293616 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 476748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 56310079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 56786827 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 476748 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 476748 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43244048 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43244048 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43244048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 476748 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 56310079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 100030875 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385570 # Total number of read requests seen +system.physmem.writeReqs 293616 # Total number of write requests seen +system.physmem.cpureqs 889416 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 24676352 # Total number of bytes read from memory +system.physmem.bytesWritten 18791424 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24676352 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18791424 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 147 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 210200 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 23300 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 24510 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 23756 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 22591 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 23592 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 24765 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 24370 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 24533 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 24384 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24225 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 24541 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 24693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 24138 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 24300 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 24598 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 23473 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 24673 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 23908 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 17801 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 18813 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18266 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 17554 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 18027 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18651 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18325 # Track writes on a per bank basis +system.physmem.perBankRdReqs::10 24144 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 24284 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 24592 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 23476 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 24665 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 23905 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 17803 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 18814 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18269 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 17556 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 18028 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18647 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18328 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 18330 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 18772 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 18767 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 18400 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 18544 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 18575 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 18773 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 18765 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 18401 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 18543 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 18573 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 17879 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 18803 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 18105 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 18800 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 18107 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 30 # Number of times wr buffer was full causing retry -system.physmem.totGap 434516329000 # Total gap between requests +system.physmem.totGap 434543578000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385553 # Categorize read packet sizes +system.physmem.readPktSize::6 385570 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 293612 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 380638 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4317 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293616 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 380658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4312 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 385 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -124,7 +124,7 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 12706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 12705 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 12716 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 12716 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 12716 # What write queue length does an incoming req see @@ -141,13 +141,13 @@ system.physmem.wrQLenPdf::13 12766 # Wh system.physmem.wrQLenPdf::14 12766 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 12766 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12766 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 12765 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 50 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 50 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see @@ -156,162 +156,162 @@ system.physmem.wrQLenPdf::28 41 # Wh system.physmem.wrQLenPdf::29 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 33 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 31 # What write queue length does an incoming req see -system.physmem.totQLat 3419098500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12003058500 # Sum of mem lat for all requests -system.physmem.totBusLat 1927035000 # Total cycles spent in databus access -system.physmem.totBankLat 6656925000 # Total cycles spent in bank access -system.physmem.avgQLat 8871.40 # Average queueing delay per request -system.physmem.avgBankLat 17272.45 # Average bank access latency per request +system.physmem.totQLat 3416691250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12001501250 # Sum of mem lat for all requests +system.physmem.totBusLat 1927115000 # Total cycles spent in databus access +system.physmem.totBankLat 6657695000 # Total cycles spent in bank access +system.physmem.avgQLat 8864.78 # Average queueing delay per request +system.physmem.avgBankLat 17273.74 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31143.85 # Average memory access latency +system.physmem.avgMemAccLat 31138.52 # Average memory access latency system.physmem.avgRdBW 56.79 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 43.25 # Average achieved write bandwidth in MB/s +system.physmem.avgWrBW 43.24 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 56.79 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 43.25 # Average consumed write bandwidth in MB/s +system.physmem.avgConsumedWrBW 43.24 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.78 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 9.12 # Average write queue length over time -system.physmem.readRowHits 331790 # Number of row buffer hits during reads -system.physmem.writeRowHits 191871 # Number of row buffer hits during writes +system.physmem.avgWrQLen 9.11 # Average write queue length over time +system.physmem.readRowHits 331804 # Number of row buffer hits during reads +system.physmem.writeRowHits 191849 # Number of row buffer hits during writes system.physmem.readRowHitRate 86.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.35 # Row buffer hit rate for writes -system.physmem.avgGap 639780.21 # Average gap between requests -system.cpu.branchPred.lookups 214953506 # Number of BP lookups -system.cpu.branchPred.condPredicted 214953506 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13134677 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 150549169 # Number of BTB lookups -system.cpu.branchPred.BTBHits 147861057 # Number of BTB hits +system.physmem.writeRowHitRate 65.34 # Row buffer hit rate for writes +system.physmem.avgGap 639800.55 # Average gap between requests +system.cpu.branchPred.lookups 214941297 # Number of BP lookups +system.cpu.branchPred.condPredicted 214941297 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13134170 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 150507127 # Number of BTB lookups +system.cpu.branchPred.BTBHits 147849168 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.214462 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 98.233998 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 869032693 # number of cpu cycles simulated +system.cpu.numCycles 869087191 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 180543347 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1193643366 # Number of instructions fetch has processed -system.cpu.fetch.Branches 214953506 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 147861057 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 371295648 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 83421023 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 231519953 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32147 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 318682 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 69 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 173452328 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3838970 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 853739491 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.595744 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.389493 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180529479 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1193576474 # Number of instructions fetch has processed +system.cpu.fetch.Branches 214941297 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 147849168 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 371266839 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83403229 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 231605654 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 31859 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 315081 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 80 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 173437780 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3837204 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 853761597 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.595537 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.389460 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 486849125 57.03% 57.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24709977 2.89% 59.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 27353576 3.20% 63.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28812018 3.37% 66.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 18473026 2.16% 68.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 24594053 2.88% 71.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30667708 3.59% 75.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28872353 3.38% 78.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183407655 21.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 486899007 57.03% 57.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24703220 2.89% 59.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 27351293 3.20% 63.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28808692 3.37% 66.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18472602 2.16% 68.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 24587756 2.88% 71.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30665646 3.59% 75.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28871909 3.38% 78.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183401472 21.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 853739491 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.247348 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.373531 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 237039901 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 188071412 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 313434986 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 45163547 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 70029645 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2166977882 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 70029645 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 270401805 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 53948111 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16882 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 322744473 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 136598575 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2120230208 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 31449 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 21240578 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 101108934 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 75 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2216675851 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5356592687 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5356461793 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 130894 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 853761597 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.247318 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.373368 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 236998203 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 188180276 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 313422880 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 45147633 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 70012605 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2166855434 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 70012605 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 270389606 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 53986414 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16429 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 322684460 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 136672083 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2120106693 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 31519 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 21337249 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 101081597 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 78 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2216557030 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5356293513 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5356152135 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 141378 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 602634997 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1385 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1357 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 330209766 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 512741559 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 204921816 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 196294424 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 55462952 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2034039963 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22861 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1808186247 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 841927 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 499552997 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 818679497 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 22309 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 853739491 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.117960 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.887291 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 602516176 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1382 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1352 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 330488922 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 512705517 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 204907925 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 196340700 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 55518293 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2033906543 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22903 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1808080301 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 844129 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 499423460 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 818593930 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 22351 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 853761597 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.117781 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.887022 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 233388219 27.34% 27.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 145263278 17.01% 44.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 138308175 16.20% 60.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 133084460 15.59% 76.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 96060946 11.25% 87.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 58814461 6.89% 94.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34920030 4.09% 98.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11982406 1.40% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1917516 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 233333722 27.33% 27.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 145354336 17.03% 44.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 138354387 16.21% 60.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 133038603 15.58% 76.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 96103978 11.26% 87.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 58771252 6.88% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34916322 4.09% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11980698 1.40% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1908299 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 853739491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 853761597 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4979468 32.47% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7769551 50.66% 83.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2586637 16.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4978338 32.41% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7792932 50.73% 83.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2590948 16.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2717049 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1190849468 65.86% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2717915 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1190782663 65.86% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.01% # Type of FU issued @@ -340,84 +340,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 438947652 24.28% 90.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 175672078 9.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 438926011 24.28% 90.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 175653712 9.71% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1808186247 # Type of FU issued -system.cpu.iq.rate 2.080688 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15335656 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008481 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4486267345 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2533832707 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1768692964 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22223 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 41984 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 4908 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1820794592 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 10262 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 170635682 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1808080301 # Type of FU issued +system.cpu.iq.rate 2.080436 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15362218 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008496 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4486103997 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2533565590 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1768588128 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 24549 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 46362 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 5401 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1820713311 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 11293 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 170590285 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 128639402 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 477025 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 270655 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 55762006 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 128603360 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 477781 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 270908 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 55748152 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12171 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 618 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12303 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 614 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 70029645 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16354856 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2869041 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2034062824 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2371349 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 512741559 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 204922192 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5971 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1818134 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 76688 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 270655 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 9112390 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4491959 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 13604349 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1780493134 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 431419821 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 27693113 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 70012605 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16361207 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2863228 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2033929446 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2371289 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 512705517 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 204908338 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6072 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1817776 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 76759 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 270908 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 9111612 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4490464 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 13602076 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1780387317 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 431399251 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 27692984 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 602103819 # number of memory reference insts executed -system.cpu.iew.exec_branches 169268529 # Number of branches executed -system.cpu.iew.exec_stores 170683998 # Number of stores executed -system.cpu.iew.exec_rate 2.048822 # Inst execution rate -system.cpu.iew.wb_sent 1775386741 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1768697872 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1341621194 # num instructions producing a value -system.cpu.iew.wb_consumers 1964432295 # num instructions consuming a value +system.cpu.iew.exec_refs 602062000 # number of memory reference insts executed +system.cpu.iew.exec_branches 169264678 # Number of branches executed +system.cpu.iew.exec_stores 170662749 # Number of stores executed +system.cpu.iew.exec_rate 2.048572 # Inst execution rate +system.cpu.iew.wb_sent 1775274937 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1768593529 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1341496349 # num instructions producing a value +system.cpu.iew.wb_consumers 1964252976 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.035249 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.682956 # average fanout of values written-back +system.cpu.iew.wb_rate 2.035001 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.682955 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 505108426 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 504973387 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 13166732 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 783709846 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.950963 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.458599 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 13165974 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 783748992 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.950865 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.458310 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 290449300 37.06% 37.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 195531985 24.95% 62.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 62027309 7.91% 69.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92272320 11.77% 81.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25028455 3.19% 84.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28378984 3.62% 88.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9417725 1.20% 89.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10760096 1.37% 91.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69843672 8.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 290412107 37.05% 37.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 195557118 24.95% 62.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 62107499 7.92% 69.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92255388 11.77% 81.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25035287 3.19% 84.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28388589 3.62% 88.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9410992 1.20% 89.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10755720 1.37% 91.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69826292 8.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 783709846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 783748992 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -428,204 +428,204 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69843672 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69826292 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2747963301 # The number of ROB reads -system.cpu.rob.rob_writes 4138406089 # The number of ROB writes -system.cpu.timesIdled 337869 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 15293202 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2747884788 # The number of ROB reads +system.cpu.rob.rob_writes 4138119354 # The number of ROB writes +system.cpu.timesIdled 343577 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 15325594 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.050982 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.050982 # CPI: Total CPI of All Threads -system.cpu.ipc 0.951491 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.951491 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3357369347 # number of integer regfile reads -system.cpu.int_regfile_writes 1848457687 # number of integer regfile writes -system.cpu.fp_regfile_reads 4903 # number of floating regfile reads +system.cpu.cpi 1.051048 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.051048 # CPI: Total CPI of All Threads +system.cpu.ipc 0.951432 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.951432 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3357192668 # number of integer regfile reads +system.cpu.int_regfile_writes 1848351672 # number of integer regfile writes +system.cpu.fp_regfile_reads 5396 # number of floating regfile reads system.cpu.fp_regfile_writes 7 # number of floating regfile writes -system.cpu.misc_regfile_reads 980231667 # number of misc regfile reads +system.cpu.misc_regfile_reads 980175338 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 5495 # number of replacements -system.cpu.icache.tagsinuse 1031.765588 # Cycle average of tags in use -system.cpu.icache.total_refs 173216071 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7085 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24448.281016 # Average number of references to valid blocks. +system.cpu.icache.replacements 5459 # number of replacements +system.cpu.icache.tagsinuse 1031.272902 # Cycle average of tags in use +system.cpu.icache.total_refs 173201219 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7046 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 24581.495742 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1031.765588 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.503792 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.503792 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 173231264 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 173231264 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 173231264 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 173231264 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 173231264 # number of overall hits -system.cpu.icache.overall_hits::total 173231264 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 221064 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 221064 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 221064 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 221064 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 221064 # number of overall misses -system.cpu.icache.overall_misses::total 221064 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1408552499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1408552499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1408552499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1408552499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1408552499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1408552499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 173452328 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 173452328 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 173452328 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 173452328 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 173452328 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 173452328 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001274 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001274 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001274 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001274 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001274 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001274 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6371.695523 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6371.695523 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6371.695523 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6371.695523 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6371.695523 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6371.695523 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 444 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1031.272902 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.503551 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.503551 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 173216530 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 173216530 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 173216530 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 173216530 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 173216530 # number of overall hits +system.cpu.icache.overall_hits::total 173216530 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 221250 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 221250 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 221250 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 221250 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 221250 # number of overall misses +system.cpu.icache.overall_misses::total 221250 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1405122498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1405122498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1405122498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1405122498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1405122498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1405122498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 173437780 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 173437780 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 173437780 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 173437780 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 173437780 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 173437780 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001276 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001276 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001276 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001276 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001276 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001276 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6350.836149 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6350.836149 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6350.836149 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6350.836149 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6350.836149 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6350.836149 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 511 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 31.714286 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 34.066667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2465 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2465 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2465 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2465 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2465 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2465 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 218599 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 218599 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 218599 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 218599 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 218599 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 218599 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 888293499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 888293499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 888293499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 888293499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 888293499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 888293499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001260 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001260 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001260 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001260 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001260 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001260 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4063.575309 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4063.575309 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4063.575309 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4063.575309 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4063.575309 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4063.575309 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2445 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2445 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2445 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2445 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2445 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2445 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 218805 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 218805 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 218805 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 218805 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 218805 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 218805 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 886299999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 886299999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 886299999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 886299999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 886299999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 886299999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001262 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001262 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001262 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001262 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001262 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001262 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4050.638692 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4050.638692 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4050.638692 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4050.638692 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4050.638692 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4050.638692 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 352874 # number of replacements -system.cpu.l2cache.tagsinuse 29622.750601 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3697631 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 385235 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 9.598378 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 352890 # number of replacements +system.cpu.l2cache.tagsinuse 29622.917064 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3697451 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 385249 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 9.597562 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 202056635000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21052.992991 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 232.749062 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8337.008547 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.642486 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.007103 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.254425 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.904015 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3789 # 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number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 210169 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206764 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206764 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3238 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 382364 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 385602 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3238 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 382364 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 385602 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 158016497 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7941834689 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8099851186 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2107112859 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2107112859 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7783948782 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7783948782 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 158016497 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15725783471 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15883799968 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 158016497 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15725783471 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15883799968 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461188 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099648 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101082 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992782 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992782 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268059 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268059 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461188 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150920 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151778 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461188 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150920 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151778 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48800.647622 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45226.849026 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45291.555408 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10025.802373 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10025.802373 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37646.537995 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37646.537995 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48800.647622 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41127.782613 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41192.213650 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48800.647622 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41127.782613 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41192.213650 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2529574 # number of replacements -system.cpu.dcache.tagsinuse 4087.791317 # Cycle average of tags in use -system.cpu.dcache.total_refs 405282445 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2533670 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 159.958655 # Average number of references to valid blocks. +system.cpu.dcache.replacements 2529450 # number of replacements +system.cpu.dcache.tagsinuse 4087.791832 # Cycle average of tags in use +system.cpu.dcache.total_refs 405306727 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2533546 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 159.976068 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 1794502000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.791317 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4087.791832 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.997996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.997996 # 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number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3889577 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3889577 # number of overall misses -system.cpu.dcache.overall_misses::total 3889577 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 51333969000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 51333969000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23756626000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23756626000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 75090595000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 75090595000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 75090595000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 75090595000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 259442208 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 259442208 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 256575503 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 256575503 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148160629 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148160629 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 404736132 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 404736132 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 404736132 # number of overall hits +system.cpu.dcache.overall_hits::total 404736132 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2890458 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2890458 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 999573 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 999573 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3890031 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3890031 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3890031 # number of overall misses +system.cpu.dcache.overall_misses::total 3890031 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 51324442500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 51324442500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23758155000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23758155000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75082597500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75082597500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75082597500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75082597500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 259465961 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 259465961 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 408602410 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 408602410 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 408602410 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 408602410 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 408626163 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 408626163 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 408626163 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 408626163 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011140 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.011140 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006700 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006700 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009519 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009519 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009519 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009519 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17761.641834 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17761.641834 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23770.460408 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23770.460408 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19305.594156 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19305.594156 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19305.594156 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19305.594156 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6831 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006701 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006701 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009520 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009520 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009520 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009520 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17756.508657 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17756.508657 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23768.304066 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23768.304066 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19301.285131 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19301.285131 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19301.285131 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19301.285131 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6798 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 659 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 655 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.365706 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.378626 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2331206 # number of writebacks -system.cpu.dcache.writebacks::total 2331206 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1127586 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1127586 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16841 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16841 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1144427 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1144427 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1144427 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1144427 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762573 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762573 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 982577 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 982577 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2745150 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2745150 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2745150 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2745150 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27778194500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27778194500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21591081000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 21591081000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49369275500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 49369275500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49369275500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 49369275500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006794 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006794 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006587 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006587 # mshr miss rate for WriteReq accesses +system.cpu.dcache.writebacks::writebacks 2331126 # number of writebacks +system.cpu.dcache.writebacks::total 2331126 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1127945 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1127945 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16844 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16844 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1144789 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1144789 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1144789 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1144789 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762513 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762513 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 982729 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 982729 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2745242 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2745242 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2745242 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2745242 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27781259000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27781259000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21592303500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 21592303500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49373562500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 49373562500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49373562500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 49373562500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006793 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006793 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006588 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006588 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006718 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006718 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006718 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006718 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15760.024975 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15760.024975 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21973.932832 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21973.932832 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17984.181374 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17984.181374 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17984.181374 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17984.181374 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15762.300193 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15762.300193 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21971.778079 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21971.778079 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17985.140290 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17985.140290 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17985.140290 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17985.140290 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index f095afad7..451dd9824 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 28 2013 09:59:18 -gem5 started Mar 28 2013 09:59:40 +gem5 compiled Apr 18 2013 13:37:41 +gem5 started Apr 18 2013 14:20:21 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5112099860500 because m5_exit instruction encountered +Exiting @ tick 5112099861500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 55530e4a5..c125666af 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 5.112100 # Number of seconds simulated -sim_ticks 5112099860500 # Number of ticks simulated -final_tick 5112099860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 5112099861500 # Number of ticks simulated +final_tick 5112099861500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1028107 # Simulator instruction rate (inst/s) -host_op_rate 2105009 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26291327617 # Simulator tick rate (ticks/s) -host_mem_usage 628192 # Number of bytes of host memory used -host_seconds 194.44 # Real time elapsed on the host +host_inst_rate 1058684 # Simulator instruction rate (inst/s) +host_op_rate 2167614 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27073251373 # Simulator tick rate (ticks/s) +host_mem_usage 628224 # Number of bytes of host memory used +host_seconds 188.82 # Real time elapsed on the host sim_insts 199905607 # Number of instructions simulated -sim_ops 409299132 # Number of ops (including micro ops) simulated +sim_ops 409299164 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2420928 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory @@ -194,7 +194,7 @@ system.iocache.tagsinuse 0.042441 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 47584 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994822603059 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 4994822604059 # Cycle when the warmup percentage was hit. system.iocache.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor system.iocache.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy system.iocache.occ_percent::total 0.002653 # Average percentage of cache occupancy @@ -245,57 +245,57 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10224199744 # number of cpu cycles simulated +system.cpu.numCycles 10224199746 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 199905607 # Number of instructions committed -system.cpu.committedOps 409299132 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374462045 # Number of integer alu accesses +system.cpu.committedOps 409299164 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374462077 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39972114 # number of instructions that are conditional controls -system.cpu.num_int_insts 374462045 # number of integer instructions +system.cpu.num_conditional_control_insts 39972120 # number of instructions that are conditional controls +system.cpu.num_int_insts 374462077 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 915890298 # number of times the integer registers were read -system.cpu.num_int_register_writes 480542887 # number of times the integer registers were written +system.cpu.num_int_register_reads 915890450 # number of times the integer registers were read +system.cpu.num_int_register_writes 480542967 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 35654170 # number of memory refs system.cpu.num_load_insts 27234345 # Number of load instructions system.cpu.num_store_insts 8419825 # Number of store instructions -system.cpu.num_idle_cycles 9770518400.401503 # Number of idle cycles -system.cpu.num_busy_cycles 453681343.598497 # Number of busy cycles +system.cpu.num_idle_cycles 9770518373.401503 # Number of idle cycles +system.cpu.num_busy_cycles 453681372.598497 # Number of busy cycles system.cpu.not_idle_fraction 0.044373 # Percentage of non-idle cycles system.cpu.idle_fraction 0.955627 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.icache.replacements 790584 # number of replacements system.cpu.icache.tagsinuse 510.666660 # Cycle average of tags in use -system.cpu.icache.total_refs 243492014 # Total number of references to valid blocks. +system.cpu.icache.total_refs 243492011 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 791096 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 307.790728 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit. +system.cpu.icache.avg_refs 307.790725 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 148824779500 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.997396 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 243492014 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243492014 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243492014 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243492014 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243492014 # number of overall hits -system.cpu.icache.overall_hits::total 243492014 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 243492011 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243492011 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243492011 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243492011 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243492011 # number of overall hits +system.cpu.icache.overall_hits::total 243492011 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 791103 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 791103 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 791103 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 791103 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 791103 # number of overall misses system.cpu.icache.overall_misses::total 791103 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244283117 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244283117 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244283117 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244283117 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244283117 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244283117 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 244283114 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244283114 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244283114 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244283114 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244283114 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244283114 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses @@ -316,7 +316,7 @@ system.cpu.itb_walker_cache.tagsinuse 3.026333 # Cy system.cpu.itb_walker_cache.total_refs 7886 # Total number of references to valid blocks. system.cpu.itb_walker_cache.sampled_refs 3489 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.avg_refs 2.260246 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5102064745500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.warmup_cycle 5102064746500 # Cycle when the warmup percentage was hit. system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026333 # Average occupied blocks per requestor system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189146 # Average percentage of cache occupancy system.cpu.itb_walker_cache.occ_percent::total 0.189146 # Average percentage of cache occupancy @@ -364,7 +364,7 @@ system.cpu.dtb_walker_cache.tagsinuse 5.014191 # Cy system.cpu.dtb_walker_cache.total_refs 12947 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.sampled_refs 7641 # Sample count of references to valid blocks. system.cpu.dtb_walker_cache.avg_refs 1.694412 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5100425401500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.warmup_cycle 5100425402500 # Cycle when the warmup percentage was hit. system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.014191 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313387 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.occ_percent::total 0.313387 # Average percentage of cache occupancy @@ -403,31 +403,31 @@ system.cpu.dtb_walker_cache.cache_copies 0 # nu system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1621965 # number of replacements +system.cpu.dcache.replacements 1621960 # number of replacements system.cpu.dcache.tagsinuse 511.999425 # Cycle average of tags in use -system.cpu.dcache.total_refs 20168700 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1622477 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.430808 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.total_refs 20168705 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1622472 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.430849 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 7550500 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 12073043 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12073043 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8093389 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8093389 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20166432 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20166432 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20166432 # number of overall hits -system.cpu.dcache.overall_hits::total 20166432 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308511 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308511 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316250 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316250 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1624761 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1624761 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1624761 # number of overall misses -system.cpu.dcache.overall_misses::total 1624761 # number of overall misses +system.cpu.dcache.ReadReq_hits::cpu.data 12073184 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12073184 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8093253 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8093253 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20166437 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20166437 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20166437 # number of overall hits +system.cpu.dcache.overall_hits::total 20166437 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308370 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308370 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316386 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316386 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1624756 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1624756 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1624756 # number of overall misses +system.cpu.dcache.overall_misses::total 1624756 # number of overall misses system.cpu.dcache.ReadReq_accesses::cpu.data 13381554 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13381554 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 8409639 # number of WriteReq accesses(hits+misses) @@ -436,10 +436,10 @@ system.cpu.dcache.demand_accesses::cpu.data 21791193 # system.cpu.dcache.demand_accesses::total 21791193 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 21791193 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 21791193 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097785 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097785 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037606 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037606 # miss rate for WriteReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097774 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097774 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037622 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037622 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.074560 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.074560 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074560 # miss rate for overall accesses @@ -452,56 +452,56 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1535695 # number of writebacks -system.cpu.dcache.writebacks::total 1535695 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1535700 # number of writebacks +system.cpu.dcache.writebacks::total 1535700 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 105930 # number of replacements -system.cpu.l2cache.tagsinuse 64821.868749 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3456653 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 64819.953894 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3456507 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 170058 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 20.326318 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 20.325460 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 51906.789291 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 51906.788142 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132241 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2490.593013 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 10424.349245 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2490.593014 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 10422.435538 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.159063 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989103 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.159034 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.989074 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6501 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 777765 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1275631 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2062699 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1538634 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1538634 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1275492 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2062560 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1538639 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1538639 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 179586 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 179586 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 179720 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 179720 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 6501 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 777765 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1455217 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2242285 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1455212 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2242280 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 6501 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 777765 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1455217 # number of overall hits -system.cpu.l2cache.overall_hits::total 2242285 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1455212 # number of overall hits +system.cpu.l2cache.overall_hits::total 2242280 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 32248 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 45580 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 32246 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 45578 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 1803 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 1803 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 134391 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 134391 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 134393 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 134393 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses @@ -515,33 +515,33 @@ system.cpu.l2cache.overall_misses::total 179971 # nu system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6503 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 791090 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1307879 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2108279 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1538634 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1538634 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1307738 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2108138 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1538639 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1538639 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 313977 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 313977 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 314113 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 314113 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6503 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 791090 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1621856 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2422256 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1621851 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2422251 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6503 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 791090 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1621856 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2422256 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1621851 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2422251 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000308 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016844 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024658 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.021620 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989029 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989029 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428028 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.428028 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427849 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.427849 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000308 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016844 # miss rate for demand accesses diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index 3bb47e888..c33799826 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 28 2013 09:59:18 -gem5 started Mar 28 2013 09:59:40 +gem5 compiled Apr 18 2013 13:37:41 +gem5 started Apr 18 2013 13:43:22 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5191816279000 because m5_exit instruction encountered +Exiting @ tick 5187335906000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 00dd0b701..fe64538c7 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,126 +1,126 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.191816 # Number of seconds simulated -sim_ticks 5191816279000 # Number of ticks simulated -final_tick 5191816279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.187336 # Number of seconds simulated +sim_ticks 5187335906000 # Number of ticks simulated +final_tick 5187335906000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 631596 # Simulator instruction rate (inst/s) -host_op_rate 1217489 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25553396248 # Simulator tick rate (ticks/s) -host_mem_usage 629228 # Number of bytes of host memory used -host_seconds 203.18 # Real time elapsed on the host -sim_insts 128324646 # Number of instructions simulated -sim_ops 247363464 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2859648 # Number of bytes read from this memory +host_inst_rate 632480 # Simulator instruction rate (inst/s) +host_op_rate 1219228 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25568906299 # Simulator tick rate (ticks/s) +host_mem_usage 629256 # Number of bytes of host memory used +host_seconds 202.88 # Real time elapsed on the host +sim_insts 128315489 # Number of instructions simulated +sim_ops 247353050 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2850304 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 823360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9009408 # Number of bytes read from this memory -system.physmem.bytes_read::total 12692736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 823360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 823360 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8106432 # Number of bytes written to this memory -system.physmem.bytes_written::total 8106432 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 44682 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 824512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9026304 # Number of bytes read from this memory +system.physmem.bytes_read::total 12701440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 824512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 824512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8120576 # Number of bytes written to this memory +system.physmem.bytes_written::total 8120576 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 44536 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12865 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140772 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198324 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126663 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126663 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 550799 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12883 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141036 # Number of read requests responded to by this memory +system.physmem.num_reads::total 198460 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126884 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126884 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 549474 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 158588 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1735309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2444758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 158588 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 158588 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1561387 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1561387 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1561387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 550799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158947 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1740065 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2448548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158947 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158947 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1565462 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1565462 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1565462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 549474 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 158588 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1735309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4006145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198324 # Total number of read requests seen -system.physmem.writeReqs 126663 # Total number of write requests seen -system.physmem.cpureqs 326610 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 12692736 # Total number of bytes read from memory -system.physmem.bytesWritten 8106432 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 12692736 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 8106432 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 80 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 1618 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 12615 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 12250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 12267 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 12575 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 12362 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 12187 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12619 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 12562 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 12247 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 11965 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 12423 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12610 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 12268 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12172 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 12546 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 12576 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8002 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7779 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7802 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 8120 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7982 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7804 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8130 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 8156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7749 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7475 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7958 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 8068 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7819 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7741 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7995 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 8083 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 158947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1740065 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4014010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198460 # Total number of read requests seen +system.physmem.writeReqs 126884 # Total number of write requests seen +system.physmem.cpureqs 326965 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 12701440 # Total number of bytes read from memory +system.physmem.bytesWritten 8120576 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 12701440 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 8120576 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 110 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 1615 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 12387 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 12046 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 12118 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 12449 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 12193 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 12119 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12473 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 12536 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 12592 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 12290 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 12456 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 12641 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 12408 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 12254 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 12740 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 12648 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7793 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7533 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7699 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7988 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7862 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7739 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7964 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 8103 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 8131 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7898 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7933 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 8107 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7973 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7879 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 8130 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 5 # Number of times wr buffer was full causing retry -system.physmem.totGap 5191816215500 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times wr buffer was full causing retry +system.physmem.totGap 5187335842500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 198324 # Categorize read packet sizes +system.physmem.readPktSize::6 198460 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 126663 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 155046 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8732 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3394 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2216 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2094 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1034 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 975 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1097 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 32 # What read queue length does an incoming req see +system.physmem.writePktSize::6 126884 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 155340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8720 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3417 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2141 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2004 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 958 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 968 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 518 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 325 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -132,92 +132,92 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see -system.physmem.totQLat 4084993999 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7884046499 # Sum of mem lat for all requests -system.physmem.totBusLat 991220000 # Total cycles spent in databus access -system.physmem.totBankLat 2807832500 # Total cycles spent in bank access -system.physmem.avgQLat 20605.89 # Average queueing delay per request -system.physmem.avgBankLat 14163.52 # Average bank access latency per request +system.physmem.wrQLenPdf::0 4200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see +system.physmem.totQLat 4133329999 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7970683749 # Sum of mem lat for all requests +system.physmem.totBusLat 991750000 # Total cycles spent in databus access +system.physmem.totBankLat 2845603750 # Total cycles spent in bank access +system.physmem.avgQLat 20838.57 # Average queueing delay per request +system.physmem.avgBankLat 14346.38 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 39769.41 # Average memory access latency -system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 40184.94 # Average memory access latency +system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.57 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 8.79 # Average write queue length over time -system.physmem.readRowHits 175346 # Number of row buffer hits during reads -system.physmem.writeRowHits 94626 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.45 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.71 # Row buffer hit rate for writes -system.physmem.avgGap 15975458.14 # Average gap between requests -system.iocache.replacements 47501 # number of replacements -system.iocache.tagsinuse 0.114811 # Cycle average of tags in use +system.physmem.avgWrQLen 12.90 # Average write queue length over time +system.physmem.readRowHits 174211 # Number of row buffer hits during reads +system.physmem.writeRowHits 94671 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.61 # Row buffer hit rate for writes +system.physmem.avgGap 15944157.08 # Average gap between requests +system.iocache.replacements 47504 # number of replacements +system.iocache.tagsinuse 0.157150 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47517 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47520 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5044702860000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.114811 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.007176 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.007176 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 836 # number of ReadReq misses -system.iocache.ReadReq_misses::total 836 # number of ReadReq misses +system.iocache.warmup_cycle 5044705088000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.157150 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.009822 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.009822 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 837 # number of ReadReq misses +system.iocache.ReadReq_misses::total 837 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47556 # number of demand (read+write) misses -system.iocache.demand_misses::total 47556 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47556 # number of overall misses -system.iocache.overall_misses::total 47556 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 136123397 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 136123397 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10718582907 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10718582907 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10854706304 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10854706304 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10854706304 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10854706304 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 836 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 836 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47557 # number of demand (read+write) misses +system.iocache.demand_misses::total 47557 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47557 # number of overall misses +system.iocache.overall_misses::total 47557 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 139731143 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 139731143 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10765565415 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10765565415 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10905296558 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10905296558 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10905296558 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10905296558 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 837 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 837 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47556 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47556 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47556 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47556 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47557 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47557 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47557 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47557 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -226,40 +226,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162827.029904 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 162827.029904 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229421.723181 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 229421.723181 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228251.036757 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 228251.036757 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228251.036757 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 228251.036757 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 175533 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166942.823178 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 166942.823178 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 230427.341931 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 230427.341931 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 229310.018672 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 229310.018672 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 229310.018672 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 229310.018672 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 177808 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16256 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16153 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.798044 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.007739 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46667 # number of writebacks -system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 836 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 836 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 46669 # number of writebacks +system.iocache.writebacks::total 46669 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 837 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 837 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47556 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47556 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47556 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47556 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92629177 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 92629177 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8287786786 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8287786786 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8380415963 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8380415963 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8380415963 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8380415963 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47557 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47557 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47557 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47557 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96185423 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 96185423 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8334760316 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8334760316 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8430945739 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8430945739 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8430945739 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8430945739 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -268,14 +268,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110800.450957 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 110800.450957 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177392.696618 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 177392.696618 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176222.053221 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176222.053221 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176222.053221 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176222.053221 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114916.873357 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 114916.873357 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 178398.123202 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 178398.123202 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 177280.857476 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 177280.857476 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 177280.857476 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 177280.857476 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -289,75 +289,75 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10383632558 # number of cpu cycles simulated +system.cpu.numCycles 10374671812 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128324646 # Number of instructions committed -system.cpu.committedOps 247363464 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232097683 # Number of integer alu accesses +system.cpu.committedInsts 128315489 # Number of instructions committed +system.cpu.committedOps 247353050 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232087369 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23165556 # number of instructions that are conditional controls -system.cpu.num_int_insts 232097683 # number of integer instructions +system.cpu.num_conditional_control_insts 23166071 # number of instructions that are conditional controls +system.cpu.num_int_insts 232087369 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 567280399 # number of times the integer registers were read -system.cpu.num_int_register_writes 293347970 # number of times the integer registers were written +system.cpu.num_int_register_reads 567244076 # number of times the integer registers were read +system.cpu.num_int_register_writes 293343891 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 22249385 # number of memory refs -system.cpu.num_load_insts 13880834 # Number of load instructions -system.cpu.num_store_insts 8368551 # Number of store instructions -system.cpu.num_idle_cycles 9782435662.998116 # Number of idle cycles -system.cpu.num_busy_cycles 601196895.001884 # Number of busy cycles -system.cpu.not_idle_fraction 0.057899 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942101 # Percentage of idle cycles +system.cpu.num_mem_refs 22240299 # number of memory refs +system.cpu.num_load_insts 13876403 # Number of load instructions +system.cpu.num_store_insts 8363896 # Number of store instructions +system.cpu.num_idle_cycles 9773542516.998116 # Number of idle cycles +system.cpu.num_busy_cycles 601129295.001884 # Number of busy cycles +system.cpu.not_idle_fraction 0.057942 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942058 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 795387 # number of replacements -system.cpu.icache.tagsinuse 510.410338 # Cycle average of tags in use -system.cpu.icache.total_refs 144562130 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 795899 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 181.633763 # Average number of references to valid blocks. +system.cpu.icache.replacements 790572 # number of replacements +system.cpu.icache.tagsinuse 510.408986 # Cycle average of tags in use +system.cpu.icache.total_refs 144555062 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 791084 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 182.730357 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 160005789000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.410338 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996895 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996895 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144562130 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144562130 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144562130 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144562130 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144562130 # number of overall hits -system.cpu.icache.overall_hits::total 144562130 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 795906 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 795906 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 795906 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 795906 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 795906 # number of overall misses -system.cpu.icache.overall_misses::total 795906 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11017856500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11017856500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11017856500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11017856500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11017856500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11017856500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145358036 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145358036 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145358036 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145358036 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145358036 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145358036 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005475 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005475 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005475 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005475 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005475 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005475 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13843.163012 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13843.163012 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13843.163012 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13843.163012 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13843.163012 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13843.163012 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 510.408986 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996893 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996893 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 144555062 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144555062 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144555062 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144555062 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144555062 # number of overall hits +system.cpu.icache.overall_hits::total 144555062 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791091 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791091 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791091 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791091 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791091 # number of overall misses +system.cpu.icache.overall_misses::total 791091 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 10944017000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 10944017000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 10944017000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 10944017000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 10944017000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 10944017000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145346153 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145346153 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145346153 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145346153 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145346153 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145346153 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005443 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005443 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005443 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005443 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005443 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005443 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13834.081035 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13834.081035 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13834.081035 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13834.081035 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13834.081035 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13834.081035 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -366,80 +366,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 795906 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 795906 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 795906 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 795906 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 795906 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 795906 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9426044500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9426044500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9426044500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9426044500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9426044500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9426044500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005475 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005475 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005475 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005475 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005475 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005475 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11843.163012 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11843.163012 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11843.163012 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11843.163012 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11843.163012 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11843.163012 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791091 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 791091 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 791091 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 791091 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 791091 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 791091 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9361835000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9361835000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9361835000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9361835000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9361835000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9361835000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005443 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005443 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005443 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11834.081035 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11834.081035 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11834.081035 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11834.081035 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11834.081035 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11834.081035 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3694 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.067610 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7642 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3706 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.062062 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5165748244000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.067610 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191726 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.191726 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7663 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7663 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3538 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.071073 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 7817 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3549 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.202592 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5161021529000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.071073 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191942 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.191942 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7819 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7819 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7665 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7665 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7665 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7665 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4553 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4553 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4553 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4553 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4553 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4553 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 46128000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 46128000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 46128000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 46128000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 46128000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 46128000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12216 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12216 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7821 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7821 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7821 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7821 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4399 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4399 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4399 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4399 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4399 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4399 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43289000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43289000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43289000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 43289000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43289000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 43289000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12218 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12218 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12218 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12218 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12218 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12218 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.372708 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.372708 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.372647 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.372647 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.372647 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.372647 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10131.341972 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10131.341972 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10131.341972 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10131.341972 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10131.341972 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10131.341972 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12220 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12220 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12220 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12220 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.360043 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.360043 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.359984 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.359984 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.359984 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.359984 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9840.645601 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9840.645601 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9840.645601 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9840.645601 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9840.645601 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9840.645601 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -448,78 +448,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 782 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 782 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4553 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4553 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4553 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4553 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4553 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4553 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37022000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 37022000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 37022000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37022000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37022000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37022000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.372708 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.372708 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.372647 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.372647 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.372647 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.372647 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8131.341972 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8131.341972 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8131.341972 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8131.341972 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8131.341972 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8131.341972 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 650 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 650 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4399 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4399 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4399 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4399 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4399 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4399 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34491000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34491000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34491000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34491000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34491000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34491000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.360043 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.360043 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.359984 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.359984 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.359984 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.359984 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7840.645601 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7840.645601 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7840.645601 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7840.645601 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7840.645601 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7840.645601 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 8348 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.050573 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 12635 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 8361 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.511183 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5162441732000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.050573 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315661 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.315661 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12638 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12638 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12638 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12638 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12638 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12638 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9544 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 9544 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9544 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 9544 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9544 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 9544 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 102265000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 102265000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 102265000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 102265000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 102265000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 102265000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22182 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22182 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22182 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22182 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22182 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22182 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.430259 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.430259 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.430259 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.430259 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.430259 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.430259 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10715.108969 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10715.108969 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10715.108969 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10715.108969 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10715.108969 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10715.108969 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 7602 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.053533 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 13277 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7616 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.743304 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5155312372000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.053533 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315846 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.315846 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13278 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13278 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13278 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13278 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13278 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13278 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8808 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8808 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8808 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8808 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8808 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8808 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 93210000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 93210000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 93210000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 93210000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 93210000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 93210000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22086 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22086 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22086 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22086 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22086 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22086 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398805 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398805 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398805 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398805 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398805 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398805 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10582.425068 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10582.425068 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10582.425068 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10582.425068 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10582.425068 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10582.425068 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -528,90 +528,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3309 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3309 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9544 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9544 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9544 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 9544 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9544 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 9544 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 83177000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 83177000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 83177000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 83177000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 83177000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 83177000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.430259 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.430259 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.430259 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.430259 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.430259 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.430259 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8715.108969 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8715.108969 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8715.108969 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8715.108969 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8715.108969 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8715.108969 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2984 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2984 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8808 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8808 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8808 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8808 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8808 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8808 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 75594000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 75594000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 75594000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 75594000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 75594000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 75594000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398805 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398805 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398805 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398805 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398805 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398805 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8582.425068 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8582.425068 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8582.425068 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8582.425068 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8582.425068 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8582.425068 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1620219 # number of replacements -system.cpu.dcache.tagsinuse 511.997551 # Cycle average of tags in use -system.cpu.dcache.total_refs 20041204 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1620731 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.365534 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1620743 # number of replacements +system.cpu.dcache.tagsinuse 511.997667 # Cycle average of tags in use +system.cpu.dcache.total_refs 20031616 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1621255 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.355623 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 39012000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997551 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.997667 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11996661 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11996661 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8042358 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8042358 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20039019 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20039019 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20039019 # number of overall hits -system.cpu.dcache.overall_hits::total 20039019 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1307017 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1307017 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315944 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315944 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1622961 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1622961 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1622961 # number of overall misses -system.cpu.dcache.overall_misses::total 1622961 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18338475500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18338475500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8568992000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8568992000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26907467500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26907467500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26907467500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26907467500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13303678 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13303678 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8358302 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8358302 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21661980 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21661980 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21661980 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21661980 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098245 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098245 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037800 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037800 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074922 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074922 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074922 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074922 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14030.785751 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14030.785751 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27121.869698 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27121.869698 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16579.244665 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16579.244665 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16579.244665 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16579.244665 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 11991279 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11991279 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8038109 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8038109 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20029388 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20029388 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20029388 # number of overall hits +system.cpu.dcache.overall_hits::total 20029388 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1307954 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1307954 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315546 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315546 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1623500 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1623500 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1623500 # number of overall misses +system.cpu.dcache.overall_misses::total 1623500 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18389416000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18389416000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8586143000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8586143000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26975559000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26975559000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26975559000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26975559000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13299233 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13299233 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8353655 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8353655 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21652888 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21652888 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21652888 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21652888 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098348 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098348 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037773 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037773 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074978 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074978 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074978 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074978 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14059.680998 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14059.680998 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27210.432076 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27210.432076 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16615.681552 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16615.681552 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16615.681552 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16615.681552 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -620,46 +620,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1537528 # number of writebacks -system.cpu.dcache.writebacks::total 1537528 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1307017 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1307017 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315944 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315944 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1622961 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1622961 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1622961 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1622961 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15724441500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15724441500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7937104000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7937104000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23661545500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23661545500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23661545500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23661545500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94200592000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94200592000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2523051000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2523051000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96723643000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96723643000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037800 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037800 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074922 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.074922 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074922 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074922 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12030.785751 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12030.785751 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25121.869698 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25121.869698 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14579.244665 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14579.244665 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14579.244665 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14579.244665 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1538215 # number of writebacks +system.cpu.dcache.writebacks::total 1538215 # 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