diff options
Diffstat (limited to 'tests')
23 files changed, 1932 insertions, 1916 deletions
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index bace1f0ca..cd7d66c16 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:30:58 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:35:52 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual +M5 compiled Dec 14 2008 21:47:07 +M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141 +M5 commit date Sun Dec 14 21:45:15 2008 -0800 +M5 started Dec 14 2008 21:47:53 +M5 executing on tater +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1907705350500 because m5_exit instruction encountered +Exiting @ tick 1907705384500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index cbdec272c..6cd8fa945 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -2,149 +2,149 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 4974822 # Number of BTB hits -global.BPredUnit.BTBHits 2263931 # Number of BTB hits -global.BPredUnit.BTBLookups 9262166 # Number of BTB lookups -global.BPredUnit.BTBLookups 5044198 # Number of BTB lookups -global.BPredUnit.RASInCorrect 24314 # Number of incorrect RAS predictions. -global.BPredUnit.RASInCorrect 16401 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 550360 # Number of conditional branches incorrect -global.BPredUnit.condIncorrect 327538 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 8474519 # Number of conditional branches predicted -global.BPredUnit.condPredicted 4548926 # Number of conditional branches predicted -global.BPredUnit.lookups 10092697 # Number of BP lookups -global.BPredUnit.lookups 5530798 # Number of BP lookups -global.BPredUnit.usedRAS 690318 # Number of times the RAS was used to get a target. -global.BPredUnit.usedRAS 415111 # Number of times the RAS was used to get a target. -host_inst_rate 121094 # Simulator instruction rate (inst/s) -host_mem_usage 292872 # Number of bytes of host memory used -host_seconds 463.72 # Real time elapsed on the host -host_tick_rate 4113887240 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 2050196 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 902547 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 1831551 # Number of conflicting stores. -memdepunit.memDep.conflictingStores 816276 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 7552776 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 4240735 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 4835977 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 2555030 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 4976196 # Number of BTB hits +global.BPredUnit.BTBHits 2271370 # Number of BTB hits +global.BPredUnit.BTBLookups 9270308 # Number of BTB lookups +global.BPredUnit.BTBLookups 5052293 # Number of BTB lookups +global.BPredUnit.RASInCorrect 24350 # Number of incorrect RAS predictions. +global.BPredUnit.RASInCorrect 16405 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 550496 # Number of conditional branches incorrect +global.BPredUnit.condIncorrect 327507 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 8475186 # Number of conditional branches predicted +global.BPredUnit.condPredicted 4551940 # Number of conditional branches predicted +global.BPredUnit.lookups 10093436 # Number of BP lookups +global.BPredUnit.lookups 5538388 # Number of BP lookups +global.BPredUnit.usedRAS 690374 # Number of times the RAS was used to get a target. +global.BPredUnit.usedRAS 417429 # Number of times the RAS was used to get a target. +host_inst_rate 132487 # Simulator instruction rate (inst/s) +host_mem_usage 294244 # Number of bytes of host memory used +host_seconds 424.12 # Real time elapsed on the host +host_tick_rate 4498020766 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 2050532 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 906322 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 1832540 # Number of conflicting stores. +memdepunit.memDep.conflictingStores 817104 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 7553751 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 4247428 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 4835994 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 2557361 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 56154063 # Number of instructions simulated +sim_insts 56190549 # Number of instructions simulated sim_seconds 1.907705 # Number of seconds simulated -sim_ticks 1907705350500 # Number of ticks simulated -system.cpu0.commit.COM:branches 5979955 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 670629 # number cycles where commit BW limit reached +sim_ticks 1907705384500 # Number of ticks simulated +system.cpu0.commit.COM:branches 5979895 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 670394 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu0.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle.samples 69429521 +system.cpu0.commit.COM:committed_per_cycle.samples 69432721 system.cpu0.commit.COM:committed_per_cycle.min_value 0 - 0 52132882 7508.75% - 1 7659816 1103.25% - 2 4444319 640.12% - 3 2023012 291.38% - 4 1474688 212.40% - 5 453462 65.31% - 6 276660 39.85% - 7 294053 42.35% - 8 670629 96.59% + 0 52134013 7508.57% + 1 7662361 1103.57% + 2 4443978 640.04% + 3 2023859 291.48% + 4 1473823 212.27% + 5 453847 65.37% + 6 276435 39.81% + 7 294011 42.34% + 8 670394 96.55% system.cpu0.commit.COM:committed_per_cycle.max_value 8 system.cpu0.commit.COM:committed_per_cycle.end_dist -system.cpu0.commit.COM:count 39866915 # Number of instructions committed -system.cpu0.commit.COM:loads 6404567 # Number of loads committed -system.cpu0.commit.COM:membars 151031 # Number of memory barriers committed -system.cpu0.commit.COM:refs 10831807 # Number of memory references committed +system.cpu0.commit.COM:count 39866260 # Number of instructions committed +system.cpu0.commit.COM:loads 6404474 # Number of loads committed +system.cpu0.commit.COM:membars 151021 # Number of memory barriers committed +system.cpu0.commit.COM:refs 10831640 # Number of memory references committed system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.branchMispredicts 524319 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 39866915 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 458411 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 6215021 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 37661300 # Number of Instructions Simulated -system.cpu0.committedInsts_total 37661300 # Number of Instructions Simulated -system.cpu0.cpi 2.679168 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.679168 # CPI: Total CPI of All Threads -system.cpu0.dcache.LoadLockedReq_accesses 147705 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency 15410.210138 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11873.163354 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits 135237 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 192134500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate 0.084411 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses 12468 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_hits 3212 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 109898000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.062665 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 9256 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses 6414335 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 28975.310559 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 28717.266435 # average ReadReq mshr miss latency +system.cpu0.commit.branchMispredicts 524450 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 39866260 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 458375 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 6218747 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 37660679 # Number of Instructions Simulated +system.cpu0.committedInsts_total 37660679 # Number of Instructions Simulated +system.cpu0.cpi 2.679241 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.679241 # CPI: Total CPI of All Threads +system.cpu0.dcache.LoadLockedReq_accesses 147686 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency 15414.654688 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11879.766663 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits 135219 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 192174500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate 0.084416 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses 12467 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_hits 3210 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 109971000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.062680 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_misses 9257 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses 6414696 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 28975.378056 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 28716.351233 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits 5467655 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 27430347000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.147588 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 946680 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 250995 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 19978171500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.108458 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 695685 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639869500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses 156562 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency 54665.657574 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51665.657574 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits 140541 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 875798500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate 0.102330 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses 16021 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 827735500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.102330 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 16021 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 4258124 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 48857.609779 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53932.670870 # average WriteReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 5468142 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 27426760000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.147560 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 946554 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 250845 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 19978224000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.108455 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 695709 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639862500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses 156551 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency 54667.977283 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51667.977283 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits 140528 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 875945000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate 0.102350 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses 16023 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 827876000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.102350 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_misses 16023 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 4258061 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 48857.574152 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53930.516019 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits 2612795 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 80386842240 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.386398 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 1645329 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 1362201 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 15269849238 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.066491 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 283128 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1050385997 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.avg_blocked_cycles_no_mshrs 9304.837348 # average number of cycles each access was blocked +system.cpu0.dcache.WriteReq_hits 2612712 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 80387760774 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.386408 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 1645349 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_hits 1362208 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_miss_latency 15269940236 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.066495 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 283141 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1050786497 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles_no_mshrs 9307.072518 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles_no_targets 16250 # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 9.224078 # Average number of references to valid blocks. -system.cpu0.dcache.blocked_no_mshrs 116353 # number of cycles access was blocked +system.cpu0.dcache.avg_refs 9.224260 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 116343 # number of cycles access was blocked system.cpu0.dcache.blocked_no_targets 2 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_mshrs 1082645740 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 1082812738 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_targets 32500 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 10672459 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 41595.993394 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 36010.985488 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 8080450 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 107817189240 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.242869 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 2592009 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 1613196 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 35248020738 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.091714 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 978813 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_accesses 10672757 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 41596.664989 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 36009.770890 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 8080854 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 107814520774 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.242852 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 2591903 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 1613053 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 35248164236 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.091715 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 978850 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 10672459 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 41595.993394 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 36010.985488 # average overall mshr miss latency +system.cpu0.dcache.overall_accesses 10672757 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 41596.664989 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 36009.770890 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 8080450 # number of overall hits -system.cpu0.dcache.overall_miss_latency 107817189240 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.242869 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 2592009 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 1613196 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 35248020738 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.091714 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 978813 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 1690255497 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_hits 8080854 # number of overall hits +system.cpu0.dcache.overall_miss_latency 107814520774 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.242852 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 2591903 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 1613053 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 35248164236 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.091715 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 978850 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 1690648997 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -155,105 +155,105 @@ system.cpu0.dcache.prefetcher.num_hwpf_issued 0 system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.dcache.replacements 922698 # number of replacements -system.cpu0.dcache.sampled_refs 923094 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 922726 # number of replacements +system.cpu0.dcache.sampled_refs 923123 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 442.177178 # Cycle average of tags in use -system.cpu0.dcache.total_refs 8514691 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 442.178159 # Cycle average of tags in use +system.cpu0.dcache.total_refs 8515127 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 297324 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 33637373 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:BranchMispred 26509 # Number of times decode detected a branch misprediction -system.cpu0.decode.DECODE:BranchResolved 401334 # Number of times decode resolved a branch -system.cpu0.decode.DECODE:DecodedInsts 50924220 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 25725806 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 9142179 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 1093475 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:SquashedInsts 84178 # Number of squashed instructions handled by decode -system.cpu0.decode.DECODE:UnblockCycles 924162 # Number of cycles decode is unblocking -system.cpu0.dtb.accesses 812630 # DTB accesses -system.cpu0.dtb.acv 800 # DTB access violations -system.cpu0.dtb.hits 11624529 # DTB hits -system.cpu0.dtb.misses 28502 # DTB misses -system.cpu0.dtb.read_accesses 605275 # DTB read accesses +system.cpu0.dcache.writebacks 297339 # number of writebacks +system.cpu0.decode.DECODE:BlockedCycles 33638498 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:BranchMispred 26518 # Number of times decode detected a branch misprediction +system.cpu0.decode.DECODE:BranchResolved 401379 # Number of times decode resolved a branch +system.cpu0.decode.DECODE:DecodedInsts 50930127 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 25726100 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 9143957 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 1094068 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:SquashedInsts 84180 # Number of squashed instructions handled by decode +system.cpu0.decode.DECODE:UnblockCycles 924165 # Number of cycles decode is unblocking +system.cpu0.dtb.accesses 812672 # DTB accesses +system.cpu0.dtb.acv 801 # DTB access violations +system.cpu0.dtb.hits 11625470 # DTB hits +system.cpu0.dtb.misses 28525 # DTB misses +system.cpu0.dtb.read_accesses 605265 # DTB read accesses system.cpu0.dtb.read_acv 596 # DTB read access violations -system.cpu0.dtb.read_hits 7062851 # DTB read hits -system.cpu0.dtb.read_misses 24043 # DTB read misses -system.cpu0.dtb.write_accesses 207355 # DTB write accesses -system.cpu0.dtb.write_acv 204 # DTB write access violations -system.cpu0.dtb.write_hits 4561678 # DTB write hits -system.cpu0.dtb.write_misses 4459 # DTB write misses -system.cpu0.fetch.Branches 10092697 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 6456334 # Number of cache lines fetched -system.cpu0.fetch.Cycles 16708506 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 292498 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 51999783 # Number of instructions fetch has processed -system.cpu0.fetch.MiscStallCycles 404 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.SquashCycles 660089 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.100026 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 6456334 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 5665140 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 0.515355 # Number of inst fetches per cycle +system.cpu0.dtb.read_hits 7063685 # DTB read hits +system.cpu0.dtb.read_misses 24056 # DTB read misses +system.cpu0.dtb.write_accesses 207407 # DTB write accesses +system.cpu0.dtb.write_acv 205 # DTB write access violations +system.cpu0.dtb.write_hits 4561785 # DTB write hits +system.cpu0.dtb.write_misses 4469 # DTB write misses +system.cpu0.fetch.Branches 10093436 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 6456939 # Number of cache lines fetched +system.cpu0.fetch.Cycles 16710993 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 292607 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 52006564 # Number of instructions fetch has processed +system.cpu0.fetch.MiscStallCycles 345 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.SquashCycles 660338 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.100032 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 6456939 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 5666570 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 0.515416 # Number of inst fetches per cycle system.cpu0.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist.samples 70522996 +system.cpu0.fetch.rateDist.samples 70526789 system.cpu0.fetch.rateDist.min_value 0 - 0 60301622 8550.63% - 1 760699 107.87% - 2 1434176 203.36% - 3 635243 90.08% - 4 2330465 330.45% - 5 474381 67.27% - 6 552250 78.31% - 7 815542 115.64% - 8 3218618 456.39% + 0 60303520 8550.44% + 1 761818 108.02% + 2 1433854 203.31% + 3 636079 90.19% + 4 2329702 330.33% + 5 474692 67.31% + 6 552513 78.34% + 7 815433 115.62% + 8 3219178 456.45% system.cpu0.fetch.rateDist.max_value 8 system.cpu0.fetch.rateDist.end_dist -system.cpu0.icache.ReadReq_accesses 6456334 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 15194.690740 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.490595 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 5806036 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 9881076999 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.100722 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 650298 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 29862 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 7526813499 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.096097 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 620436 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles_no_mshrs 11557.114286 # average number of cycles each access was blocked +system.cpu0.icache.ReadReq_accesses 6456939 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 15194.131269 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.657762 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 5806696 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 9879877499 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.100705 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 650243 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 29877 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 7526067999 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.096077 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 620366 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs 11808.794118 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 9.359502 # Average number of references to valid blocks. -system.cpu0.icache.blocked_no_mshrs 35 # number of cycles access was blocked +system.cpu0.icache.avg_refs 9.361637 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 34 # number of cycles access was blocked system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_mshrs 404499 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 401499 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 6456334 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 15194.690740 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12131.490595 # average overall mshr miss latency -system.cpu0.icache.demand_hits 5806036 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 9881076999 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.100722 # miss rate for demand accesses -system.cpu0.icache.demand_misses 650298 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 29862 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 7526813499 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.096097 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 620436 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_accesses 6456939 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 15194.131269 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 12131.657762 # average overall mshr miss latency +system.cpu0.icache.demand_hits 5806696 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 9879877499 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.100705 # miss rate for demand accesses +system.cpu0.icache.demand_misses 650243 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 29877 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 7526067999 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.096077 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 620366 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 6456334 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 15194.690740 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12131.490595 # average overall mshr miss latency +system.cpu0.icache.overall_accesses 6456939 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 15194.131269 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12131.657762 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 5806036 # number of overall hits -system.cpu0.icache.overall_miss_latency 9881076999 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.100722 # miss rate for overall accesses -system.cpu0.icache.overall_misses 650298 # number of overall misses -system.cpu0.icache.overall_mshr_hits 29862 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 7526813499 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.096097 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 620436 # number of overall MSHR misses +system.cpu0.icache.overall_hits 5806696 # number of overall hits +system.cpu0.icache.overall_miss_latency 9879877499 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.100705 # miss rate for overall accesses +system.cpu0.icache.overall_misses 650243 # number of overall misses +system.cpu0.icache.overall_mshr_hits 29877 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 7526067999 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.096077 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 620366 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -265,80 +265,80 @@ system.cpu0.icache.prefetcher.num_hwpf_issued 0 system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.icache.replacements 619824 # number of replacements -system.cpu0.icache.sampled_refs 620336 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 619753 # number of replacements +system.cpu0.icache.sampled_refs 620265 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 509.829045 # Cycle average of tags in use -system.cpu0.icache.total_refs 5806036 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 509.829037 # Cycle average of tags in use +system.cpu0.icache.total_refs 5806696 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 25308080000 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idleCycles 30377936 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 6436145 # Number of branches executed -system.cpu0.iew.EXEC:nop 2512619 # number of nop insts executed -system.cpu0.iew.EXEC:rate 0.402630 # Inst execution rate -system.cpu0.iew.EXEC:refs 11739664 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 4575851 # Number of stores executed +system.cpu0.idleCycles 30375232 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 6436271 # Number of branches executed +system.cpu0.iew.EXEC:nop 2512861 # number of nop insts executed +system.cpu0.iew.EXEC:rate 0.402649 # Inst execution rate +system.cpu0.iew.EXEC:refs 11740634 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 4575971 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 24160254 # num instructions consuming a value -system.cpu0.iew.WB:count 40224289 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.779043 # average fanout of values written-back +system.cpu0.iew.WB:consumers 24161361 # num instructions consuming a value +system.cpu0.iew.WB:count 40226140 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.779058 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 18821888 # num instructions producing a value -system.cpu0.iew.WB:rate 0.398651 # insts written-back per cycle -system.cpu0.iew.WB:sent 40292052 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 568729 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewBlockCycles 7177517 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 7552776 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 1229726 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 771663 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 4835977 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 46188038 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 7163813 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 359179 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 40625745 # Number of executed instructions -system.cpu0.iew.iewIQFullEvents 33838 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.WB:producers 18823101 # num instructions producing a value +system.cpu0.iew.WB:rate 0.398665 # insts written-back per cycle +system.cpu0.iew.WB:sent 40293974 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 568843 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewBlockCycles 7178022 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 7553751 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 1229599 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 771955 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 4835994 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 46191067 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 7164663 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 359395 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 40628051 # Number of executed instructions +system.cpu0.iew.iewIQFullEvents 33755 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewLSQFullEvents 4189 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 1093475 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 453457 # Number of cycles IEW is unblocking +system.cpu0.iew.iewLSQFullEvents 4184 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1094068 # Number of cycles IEW is squashing +system.cpu0.iew.iewUnblockCycles 453365 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 242605 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 357762 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread.0.ignoredResponses 8885 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread.0.cacheBlocked 243041 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread.0.forwLoads 357779 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.ignoredResponses 8886 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 33999 # Number of memory ordering violations -system.cpu0.iew.lsq.thread.0.rescheduledLoads 12233 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1148209 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 408737 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 33999 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 255829 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 312900 # Number of branches that were predicted taken incorrectly -system.cpu0.ipc 0.373250 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.373250 # IPC: Total IPC of All Threads -system.cpu0.iq.ISSUE:FU_type_0 40984924 # Type of FU issued +system.cpu0.iew.lsq.thread.0.memOrderViolation 34084 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.rescheduledLoads 12238 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread.0.squashedLoads 1149277 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 408828 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 34084 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 255799 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 313044 # Number of branches that were predicted taken incorrectly +system.cpu0.ipc 0.373240 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.373240 # IPC: Total IPC of All Threads +system.cpu0.iq.ISSUE:FU_type_0 40987446 # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0.start_dist - No_OpClass 3324 0.01% # Type of FU issued - IntAlu 28266314 68.97% # Type of FU issued - IntMult 42210 0.10% # Type of FU issued + No_OpClass 3326 0.01% # Type of FU issued + IntAlu 28267902 68.97% # Type of FU issued + IntMult 42211 0.10% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 12073 0.03% # Type of FU issued + FloatAdd 12076 0.03% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued - FloatDiv 1656 0.00% # Type of FU issued + FloatDiv 1657 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 7397265 18.05% # Type of FU issued - MemWrite 4611960 11.25% # Type of FU issued - IprAccess 650122 1.59% # Type of FU issued + MemRead 7398183 18.05% # Type of FU issued + MemWrite 4612040 11.25% # Type of FU issued + IprAccess 650051 1.59% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0.end_dist -system.cpu0.iq.ISSUE:fu_busy_cnt 290360 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.007085 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:fu_busy_cnt 290461 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.007087 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 33477 11.53% # attempts to use FU when none available + IntAlu 33502 11.53% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -347,39 +347,39 @@ system.cpu0.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 185557 63.91% # attempts to use FU when none available - MemWrite 71326 24.56% # attempts to use FU when none available + MemRead 185625 63.91% # attempts to use FU when none available + MemWrite 71334 24.56% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full.end_dist system.cpu0.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle.samples 70522996 +system.cpu0.iq.ISSUE:issued_per_cycle.samples 70526789 system.cpu0.iq.ISSUE:issued_per_cycle.min_value 0 - 0 49763845 7056.40% - 1 10504305 1489.49% - 2 4625788 655.93% - 3 2839071 402.57% - 4 1729907 245.30% - 5 663571 94.09% - 6 315326 44.71% - 7 67073 9.51% - 8 14110 2.00% + 0 49764698 7056.14% + 1 10507711 1489.89% + 2 4625293 655.82% + 3 2839060 402.55% + 4 1729945 245.29% + 5 663621 94.09% + 6 315226 44.70% + 7 67152 9.52% + 8 14083 2.00% system.cpu0.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu0.iq.ISSUE:issued_per_cycle.end_dist -system.cpu0.iq.ISSUE:rate 0.406190 # Inst issue rate -system.cpu0.iq.iqInstsAdded 42277563 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 40984924 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 1397856 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 5734915 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedInstsIssued 23390 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 939445 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 3057501 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.itb.accesses 875611 # ITB accesses -system.cpu0.itb.acv 895 # ITB acv -system.cpu0.itb.hits 845707 # ITB hits -system.cpu0.itb.misses 29904 # ITB misses -system.cpu0.kern.callpal 129595 # number of callpals executed +system.cpu0.iq.ISSUE:rate 0.406210 # Inst issue rate +system.cpu0.iq.iqInstsAdded 42280485 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 40987446 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 1397721 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 5737873 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedInstsIssued 23379 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedNonSpecRemoved 939346 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 3058467 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.itb.accesses 875811 # ITB accesses +system.cpu0.itb.acv 900 # ITB acv +system.cpu0.itb.hits 845925 # ITB hits +system.cpu0.itb.misses 29886 # ITB misses +system.cpu0.kern.callpal 129578 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal_wripir 96 0.07% 0.07% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.08% # number of callpals executed @@ -388,53 +388,53 @@ system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.08% # nu system.cpu0.kern.callpal_swpctx 2410 1.86% 1.94% # number of callpals executed system.cpu0.kern.callpal_tbi 51 0.04% 1.98% # number of callpals executed system.cpu0.kern.callpal_wrent 7 0.01% 1.98% # number of callpals executed -system.cpu0.kern.callpal_swpipl 116022 89.53% 91.51% # number of callpals executed +system.cpu0.kern.callpal_swpipl 116005 89.53% 91.51% # number of callpals executed system.cpu0.kern.callpal_rdps 6357 4.91% 96.41% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 96.41% # number of callpals executed system.cpu0.kern.callpal_wrusp 3 0.00% 96.42% # number of callpals executed system.cpu0.kern.callpal_rdusp 9 0.01% 96.42% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 96.43% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 96.42% # number of callpals executed system.cpu0.kern.callpal_rti 4116 3.18% 99.60% # number of callpals executed system.cpu0.kern.callpal_callsys 381 0.29% 99.90% # number of callpals executed system.cpu0.kern.callpal_imb 136 0.10% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 144434 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 4855 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 122325 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 47769 39.05% 39.05% # number of times we switched to this ipl +system.cpu0.kern.inst.hwrei 144417 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 4856 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 122308 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 47763 39.05% 39.05% # number of times we switched to this ipl system.cpu0.kern.ipl_count_21 239 0.20% 39.25% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 1931 1.58% 40.82% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1931 1.58% 40.83% # number of times we switched to this ipl system.cpu0.kern.ipl_count_30 17 0.01% 40.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 72369 59.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 96409 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 47119 48.87% 48.87% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count_31 72358 59.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 96397 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 47113 48.87% 48.87% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_21 239 0.25% 49.12% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 1931 2.00% 51.12% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 1931 2.00% 51.13% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_30 17 0.02% 51.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 47103 48.86% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 1907288705500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1871607298000 98.13% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 101503500 0.01% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 397998500 0.02% 98.16% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good_31 47097 48.86% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1907288793500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1871606924500 98.13% 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 101495000 0.01% 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 397995000 0.02% 98.16% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_30 9331000 0.00% 98.16% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 35172574500 1.84% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used_0 0.986393 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_ticks_31 35173048000 1.84% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.986391 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.650873 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1284 -system.cpu0.kern.mode_good_user 1284 +system.cpu0.kern.ipl_used_31 0.650889 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1283 +system.cpu0.kern.mode_good_user 1283 system.cpu0.kern.mode_good_idle 0 system.cpu0.kern.mode_switch_kernel 5894 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1284 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1283 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.217849 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.217679 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 1905144241000 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 2121161500 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1905143965500 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 2121516000 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 2411 # number of times the context was actually changed system.cpu0.kern.syscall 222 # number of syscalls executed @@ -467,138 +467,138 @@ system.cpu0.kern.syscall_98 2 0.90% 97.75% # nu system.cpu0.kern.syscall_132 1 0.45% 98.20% # number of syscalls executed system.cpu0.kern.syscall_144 2 0.90% 99.10% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.90% 100.00% # number of syscalls executed -system.cpu0.numCycles 100900932 # number of cpu cycles simulated -system.cpu0.rename.RENAME:BlockCycles 10626974 # Number of cycles rename is blocking -system.cpu0.rename.RENAME:CommittedMaps 27338376 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IQFullEvents 742955 # Number of times rename has blocked due to IQ full -system.cpu0.rename.RENAME:IdleCycles 26930007 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 1646671 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:ROBFullEvents 16625 # Number of times rename has blocked due to ROB full -system.cpu0.rename.RENAME:RenameLookups 58873396 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 48153710 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 32532330 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 9103233 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 1093475 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 3612957 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 5193954 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:serializeStallCycles 19156348 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 1163476 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 8536447 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 181426 # count of temporary serializing insts renamed -system.cpu0.timesIdled 904874 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.commit.COM:branches 2941268 # Number of branches committed -system.cpu1.commit.COM:bw_lim_events 404281 # number cycles where commit BW limit reached +system.cpu0.numCycles 100902021 # number of cpu cycles simulated +system.cpu0.rename.RENAME:BlockCycles 10627682 # Number of cycles rename is blocking +system.cpu0.rename.RENAME:CommittedMaps 27337911 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IQFullEvents 742849 # Number of times rename has blocked due to IQ full +system.cpu0.rename.RENAME:IdleCycles 26930411 # Number of cycles rename is idle +system.cpu0.rename.RENAME:LSQFullEvents 1646609 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RENAME:ROBFullEvents 16617 # Number of times rename has blocked due to ROB full +system.cpu0.rename.RENAME:RenameLookups 58880309 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 48158423 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 32535865 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 9104795 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 1094068 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 3612727 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 5197954 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 19157104 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 1163461 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 8536821 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 181475 # count of temporary serializing insts renamed +system.cpu0.timesIdled 904725 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.commit.COM:branches 2947825 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 401526 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu1.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle.samples 37417436 +system.cpu1.commit.COM:committed_per_cycle.samples 37477455 system.cpu1.commit.COM:committed_per_cycle.min_value 0 - 0 29372797 7850.03% - 1 3570649 954.27% - 2 1730450 462.47% - 3 1048421 280.20% - 4 705992 188.68% - 5 261184 69.80% - 6 182468 48.77% - 7 141194 37.73% - 8 404281 108.05% + 0 29419466 7849.91% + 1 3577484 954.57% + 2 1728132 461.11% + 3 1049888 280.14% + 4 708571 189.07% + 5 265965 70.97% + 6 180885 48.27% + 7 145538 38.83% + 8 401526 107.14% system.cpu1.commit.COM:committed_per_cycle.max_value 8 system.cpu1.commit.COM:committed_per_cycle.end_dist -system.cpu1.commit.COM:count 19624114 # Number of instructions committed -system.cpu1.commit.COM:loads 3545101 # Number of loads committed -system.cpu1.commit.COM:membars 87127 # Number of memory barriers committed -system.cpu1.commit.COM:refs 5853378 # Number of memory references committed +system.cpu1.commit.COM:count 19663805 # Number of instructions committed +system.cpu1.commit.COM:loads 3551077 # Number of loads committed +system.cpu1.commit.COM:membars 87378 # Number of memory barriers committed +system.cpu1.commit.COM:refs 5861573 # Number of memory references committed system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.branchMispredicts 311146 # The number of times a branch was mispredicted -system.cpu1.commit.commitCommittedInsts 19624114 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 255253 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 3733069 # The number of squashed insts skipped by commit -system.cpu1.committedInsts 18492763 # Number of Instructions Simulated -system.cpu1.committedInsts_total 18492763 # Number of Instructions Simulated -system.cpu1.cpi 2.312237 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.312237 # CPI: Total CPI of All Threads -system.cpu1.dcache.LoadLockedReq_accesses 72124 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency 14446.929646 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11200.613079 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits 59829 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 177625000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate 0.170470 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses 12295 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_hits 2019 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 115097500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.142477 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 10276 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses 3584183 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 15544.189729 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11996.806998 # average ReadReq mshr miss latency +system.cpu1.commit.branchMispredicts 311117 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 19663805 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 255745 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 3736987 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 18529870 # Number of Instructions Simulated +system.cpu1.committedInsts_total 18529870 # Number of Instructions Simulated +system.cpu1.cpi 2.312190 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.312190 # CPI: Total CPI of All Threads +system.cpu1.dcache.LoadLockedReq_accesses 72126 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency 14445.783133 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11202.181535 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits 59842 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 177452000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate 0.170313 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses 12284 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_hits 2016 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 115024000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.142362 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_misses 10268 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses 3589521 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 15546.334532 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11998.783257 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits 2941941 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 9983131500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.179188 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 642242 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 211143 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 5171811500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.120278 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 431099 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 283603500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses 68163 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency 54675.738585 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51675.738585 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits 51408 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 916092000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate 0.245808 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses 16755 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 865827000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.245808 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 16755 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 2232793 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 49361.665892 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54248.260288 # average WriteReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 2947311 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 9984011500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.178912 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 642210 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_hits 211141 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 5172303500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.120091 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 431069 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 298579500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.StoreCondReq_accesses 68169 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency 54676.100066 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51676.100066 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits 51420 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 915770000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate 0.245698 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses 16749 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 865523000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.245698 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_misses 16749 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 2234886 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 49366.448141 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54247.795546 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits 1538625 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 34265288889 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.310897 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 694168 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_hits 551549 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 7736832634 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.063875 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 142619 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 511356000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.avg_blocked_cycles_no_mshrs 14029.367204 # average number of cycles each access was blocked +system.cpu1.dcache.WriteReq_hits 1540754 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 34266831381 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.310589 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 694132 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_hits 551528 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_miss_latency 7735952636 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.063808 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 142604 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 526042500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles_no_mshrs 13994.026145 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles_no_targets 5000 # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 8.864535 # Average number of references to valid blocks. -system.cpu1.dcache.blocked_no_mshrs 31315 # number of cycles access was blocked +system.cpu1.dcache.avg_refs 8.879315 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 31364 # number of cycles access was blocked system.cpu1.dcache.blocked_no_targets 1 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_mshrs 439329634 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 438908636 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_targets 5000 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 5816976 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 33109.914165 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 22499.981060 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 4480566 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 44248420389 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.229743 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 1336410 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 762692 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 12908644134 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.098628 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 573718 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_accesses 5824407 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 33113.411747 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 22501.069662 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 4488065 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 44250842881 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.229438 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 1336342 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 762669 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 12908256136 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.098495 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 573673 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.overall_accesses 5816976 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 33109.914165 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 22499.981060 # average overall mshr miss latency +system.cpu1.dcache.overall_accesses 5824407 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 33113.411747 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 22501.069662 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 4480566 # number of overall hits -system.cpu1.dcache.overall_miss_latency 44248420389 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.229743 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 1336410 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 762692 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 12908644134 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.098628 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 573718 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 794959500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_hits 4488065 # number of overall hits +system.cpu1.dcache.overall_miss_latency 44250842881 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.229438 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 1336342 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 762669 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 12908256136 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.098495 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 573673 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 824622000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -609,105 +609,105 @@ system.cpu1.dcache.prefetcher.num_hwpf_issued 0 system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.dcache.replacements 531824 # number of replacements -system.cpu1.dcache.sampled_refs 532336 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 531784 # number of replacements +system.cpu1.dcache.sampled_refs 532296 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 486.799078 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4718911 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 487.083551 # Cycle average of tags in use +system.cpu1.dcache.total_refs 4726424 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 39405721000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 158256 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 17763598 # Number of cycles decode is blocked +system.cpu1.dcache.writebacks 158239 # number of writebacks +system.cpu1.decode.DECODE:BlockedCycles 17789626 # Number of cycles decode is blocked system.cpu1.decode.DECODE:BranchMispred 18017 # Number of times decode detected a branch misprediction -system.cpu1.decode.DECODE:BranchResolved 245215 # Number of times decode resolved a branch -system.cpu1.decode.DECODE:DecodedInsts 26209907 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 14707752 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 4714008 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 641031 # Number of cycles decode is squashing -system.cpu1.decode.DECODE:SquashedInsts 52760 # Number of squashed instructions handled by decode -system.cpu1.decode.DECODE:UnblockCycles 232077 # Number of cycles decode is unblocking -system.cpu1.dtb.accesses 434054 # DTB accesses -system.cpu1.dtb.acv 76 # DTB access violations -system.cpu1.dtb.hits 6272530 # DTB hits -system.cpu1.dtb.misses 17149 # DTB misses -system.cpu1.dtb.read_accesses 314239 # DTB read accesses +system.cpu1.decode.DECODE:BranchResolved 246498 # Number of times decode resolved a branch +system.cpu1.decode.DECODE:DecodedInsts 26253438 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 14731458 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 4724229 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 641522 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:SquashedInsts 52769 # Number of squashed instructions handled by decode +system.cpu1.decode.DECODE:UnblockCycles 232141 # Number of cycles decode is unblocking +system.cpu1.dtb.accesses 433929 # DTB accesses +system.cpu1.dtb.acv 77 # DTB access violations +system.cpu1.dtb.hits 6280849 # DTB hits +system.cpu1.dtb.misses 17153 # DTB misses +system.cpu1.dtb.read_accesses 314117 # DTB read accesses system.cpu1.dtb.read_acv 13 # DTB read access violations -system.cpu1.dtb.read_hits 3866975 # DTB read hits -system.cpu1.dtb.read_misses 13433 # DTB read misses -system.cpu1.dtb.write_accesses 119815 # DTB write accesses -system.cpu1.dtb.write_acv 63 # DTB write access violations -system.cpu1.dtb.write_hits 2405555 # DTB write hits -system.cpu1.dtb.write_misses 3716 # DTB write misses -system.cpu1.fetch.Branches 5530798 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 3081765 # Number of cache lines fetched -system.cpu1.fetch.Cycles 8119333 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 192779 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 26783088 # Number of instructions fetch has processed -system.cpu1.fetch.MiscStallCycles 1141 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.SquashCycles 373445 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.129346 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 3081765 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 2679042 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 0.626364 # Number of inst fetches per cycle +system.cpu1.dtb.read_hits 3872885 # DTB read hits +system.cpu1.dtb.read_misses 13436 # DTB read misses +system.cpu1.dtb.write_accesses 119812 # DTB write accesses +system.cpu1.dtb.write_acv 64 # DTB write access violations +system.cpu1.dtb.write_hits 2407964 # DTB write hits +system.cpu1.dtb.write_misses 3717 # DTB write misses +system.cpu1.fetch.Branches 5538388 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 3089103 # Number of cache lines fetched +system.cpu1.fetch.Cycles 8137043 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 192735 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 26826541 # Number of instructions fetch has processed +system.cpu1.fetch.MiscStallCycles 1090 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.SquashCycles 373513 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.129267 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 3089103 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 2688799 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 0.626136 # Number of inst fetches per cycle system.cpu1.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist.samples 38058467 +system.cpu1.fetch.rateDist.samples 38118977 system.cpu1.fetch.rateDist.min_value 0 - 0 33027824 8678.18% - 1 336540 88.43% - 2 683303 179.54% - 3 398795 104.78% - 4 792602 208.26% - 5 252574 66.36% - 6 340311 89.42% - 7 403731 106.08% - 8 1822787 478.94% + 0 33077956 8677.56% + 1 338219 88.73% + 2 684572 179.59% + 3 401330 105.28% + 4 792380 207.87% + 5 254419 66.74% + 6 341251 89.52% + 7 404733 106.18% + 8 1824117 478.53% system.cpu1.fetch.rateDist.max_value 8 system.cpu1.fetch.rateDist.end_dist -system.cpu1.icache.ReadReq_accesses 3081765 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 14557.235908 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11605.244559 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 2613676 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 6814081999 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.151890 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 468089 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 20978 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 5188832500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.145083 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 447111 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_accesses 3089103 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 14554.963245 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11604.753460 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 2620972 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 6813629499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.151543 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 468131 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 20962 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 5189286000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.144757 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 447169 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles_no_mshrs 11057.692308 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 5.846378 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 5.861938 # Average number of references to valid blocks. system.cpu1.icache.blocked_no_mshrs 26 # number of cycles access was blocked system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_mshrs 287500 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 3081765 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 14557.235908 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11605.244559 # average overall mshr miss latency -system.cpu1.icache.demand_hits 2613676 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 6814081999 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.151890 # miss rate for demand accesses -system.cpu1.icache.demand_misses 468089 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 20978 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 5188832500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.145083 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 447111 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_accesses 3089103 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 14554.963245 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11604.753460 # average overall mshr miss latency +system.cpu1.icache.demand_hits 2620972 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 6813629499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.151543 # miss rate for demand accesses +system.cpu1.icache.demand_misses 468131 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 20962 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 5189286000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.144757 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 447169 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.overall_accesses 3081765 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 14557.235908 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11605.244559 # average overall mshr miss latency +system.cpu1.icache.overall_accesses 3089103 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 14554.963245 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11604.753460 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 2613676 # number of overall hits -system.cpu1.icache.overall_miss_latency 6814081999 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.151890 # miss rate for overall accesses -system.cpu1.icache.overall_misses 468089 # number of overall misses -system.cpu1.icache.overall_mshr_hits 20978 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 5188832500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.145083 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 447111 # number of overall MSHR misses +system.cpu1.icache.overall_hits 2620972 # number of overall hits +system.cpu1.icache.overall_miss_latency 6813629499 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.151543 # miss rate for overall accesses +system.cpu1.icache.overall_misses 468131 # number of overall misses +system.cpu1.icache.overall_mshr_hits 20962 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 5189286000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.144757 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 447169 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -719,63 +719,63 @@ system.cpu1.icache.prefetcher.num_hwpf_issued 0 system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.icache.replacements 446548 # number of replacements -system.cpu1.icache.sampled_refs 447059 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 446606 # number of replacements +system.cpu1.icache.sampled_refs 447117 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 504.476146 # Cycle average of tags in use -system.cpu1.icache.total_refs 2613676 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 504.476148 # Cycle average of tags in use +system.cpu1.icache.total_refs 2620972 # Total number of references to valid blocks. system.cpu1.icache.warmup_cycle 54243392000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idleCycles 4701182 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 3208895 # Number of branches executed -system.cpu1.iew.EXEC:nop 1313637 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.474750 # Inst execution rate -system.cpu1.iew.EXEC:refs 6445371 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 2416978 # Number of stores executed +system.cpu1.idleCycles 4725605 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 3215748 # Number of branches executed +system.cpu1.iew.EXEC:nop 1316352 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.474711 # Inst execution rate +system.cpu1.iew.EXEC:refs 6453696 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 2419389 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 12350061 # num instructions consuming a value -system.cpu1.iew.WB:count 20043548 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.731488 # average fanout of values written-back +system.cpu1.iew.WB:consumers 12378269 # num instructions consuming a value +system.cpu1.iew.WB:count 20082329 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.731659 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 9033918 # num instructions producing a value -system.cpu1.iew.WB:rate 0.468749 # insts written-back per cycle -system.cpu1.iew.WB:sent 20085855 # cumulative count of insts sent to commit -system.cpu1.iew.branchMispredicts 338994 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewBlockCycles 2476901 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 4240735 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 782170 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 352959 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 2555030 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 23433163 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 4028393 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 227109 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 20300122 # Number of executed instructions -system.cpu1.iew.iewIQFullEvents 13056 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.WB:producers 9056670 # num instructions producing a value +system.cpu1.iew.WB:rate 0.468725 # insts written-back per cycle +system.cpu1.iew.WB:sent 20124761 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 338961 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewBlockCycles 2501198 # Number of cycles IEW is blocking +system.cpu1.iew.iewDispLoadInsts 4247428 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 782465 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 352902 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 2557361 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 23476813 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 4034307 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 224585 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 20338799 # Number of executed instructions +system.cpu1.iew.iewIQFullEvents 13271 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewLSQFullEvents 2312 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 641031 # Number of cycles IEW is squashing -system.cpu1.iew.iewUnblockCycles 92389 # Number of cycles IEW is unblocking +system.cpu1.iew.iewLSQFullEvents 2314 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 641522 # Number of cycles IEW is squashing +system.cpu1.iew.iewUnblockCycles 92599 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread.0.cacheBlocked 96439 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 136590 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread.0.ignoredResponses 5874 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread.0.cacheBlocked 96430 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread.0.forwLoads 136935 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.ignoredResponses 5812 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 18177 # Number of memory ordering violations -system.cpu1.iew.lsq.thread.0.rescheduledLoads 7528 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 695634 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 246753 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 18177 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 160429 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 178565 # Number of branches that were predicted taken incorrectly -system.cpu1.ipc 0.432482 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.432482 # IPC: Total IPC of All Threads -system.cpu1.iq.ISSUE:FU_type_0 20527233 # Type of FU issued +system.cpu1.iew.lsq.thread.0.memOrderViolation 18288 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.rescheduledLoads 7650 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread.0.squashedLoads 696351 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 246865 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 18288 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 160561 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 178400 # Number of branches that were predicted taken incorrectly +system.cpu1.ipc 0.432490 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.432490 # IPC: Total IPC of All Threads +system.cpu1.iq.ISSUE:FU_type_0 20563386 # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0.start_dist No_OpClass 3984 0.02% # Type of FU issued - IntAlu 13446211 65.50% # Type of FU issued - IntMult 28837 0.14% # Type of FU issued + IntAlu 13476321 65.54% # Type of FU issued + IntMult 28965 0.14% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 13702 0.07% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued @@ -783,16 +783,16 @@ system.cpu1.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 1986 0.01% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 4170434 20.32% # Type of FU issued - MemWrite 2440876 11.89% # Type of FU issued - IprAccess 421203 2.05% # Type of FU issued + MemRead 4173926 20.30% # Type of FU issued + MemWrite 2443261 11.88% # Type of FU issued + IprAccess 421241 2.05% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0.end_dist -system.cpu1.iq.ISSUE:fu_busy_cnt 220615 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.010747 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:fu_busy_cnt 221052 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.010750 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 16051 7.28% # attempts to use FU when none available + IntAlu 16139 7.30% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -801,39 +801,39 @@ system.cpu1.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 131548 59.63% # attempts to use FU when none available - MemWrite 73016 33.10% # attempts to use FU when none available + MemRead 131915 59.68% # attempts to use FU when none available + MemWrite 72998 33.02% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full.end_dist system.cpu1.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle.samples 38058467 +system.cpu1.iq.ISSUE:issued_per_cycle.samples 38118977 system.cpu1.iq.ISSUE:issued_per_cycle.min_value 0 - 0 28368882 7454.03% - 1 4650018 1221.81% - 2 1988549 522.50% - 3 1356758 356.49% - 4 973103 255.69% - 5 468416 123.08% - 6 186236 48.93% - 7 54105 14.22% - 8 12400 3.26% + 0 28405823 7451.88% + 1 4664380 1223.64% + 2 1989669 521.96% + 3 1362790 357.51% + 4 979073 256.85% + 5 465618 122.15% + 6 186895 49.03% + 7 52286 13.72% + 8 12443 3.26% system.cpu1.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu1.iq.ISSUE:issued_per_cycle.end_dist -system.cpu1.iq.ISSUE:rate 0.480061 # Inst issue rate -system.cpu1.iq.iqInstsAdded 21243619 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 20527233 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 875907 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 3479594 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 16597 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 620654 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 1771927 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.itb.accesses 525300 # ITB accesses -system.cpu1.itb.acv 103 # ITB acv -system.cpu1.itb.hits 518475 # ITB hits -system.cpu1.itb.misses 6825 # ITB misses -system.cpu1.kern.callpal 87347 # number of callpals executed +system.cpu1.iq.ISSUE:rate 0.479953 # Inst issue rate +system.cpu1.iq.iqInstsAdded 21283894 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 20563386 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 876567 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 3483485 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 16725 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedNonSpecRemoved 620822 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 1773520 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.itb.accesses 525294 # ITB accesses +system.cpu1.itb.acv 109 # ITB acv +system.cpu1.itb.hits 518481 # ITB hits +system.cpu1.itb.misses 6813 # ITB misses +system.cpu1.kern.callpal 87355 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal_wripir 17 0.02% 0.02% # number of callpals executed system.cpu1.kern.callpal_wrmces 1 0.00% 0.02% # number of callpals executed @@ -841,7 +841,7 @@ system.cpu1.kern.callpal_wrfen 1 0.00% 0.02% # nu system.cpu1.kern.callpal_swpctx 1838 2.10% 2.13% # number of callpals executed system.cpu1.kern.callpal_tbi 3 0.00% 2.13% # number of callpals executed system.cpu1.kern.callpal_wrent 7 0.01% 2.14% # number of callpals executed -system.cpu1.kern.callpal_swpipl 79676 91.22% 93.36% # number of callpals executed +system.cpu1.kern.callpal_swpipl 79684 91.22% 93.36% # number of callpals executed system.cpu1.kern.callpal_rdps 2408 2.76% 96.11% # number of callpals executed system.cpu1.kern.callpal_wrkgp 1 0.00% 96.11% # number of callpals executed system.cpu1.kern.callpal_wrusp 4 0.00% 96.12% # number of callpals executed @@ -851,40 +851,40 @@ system.cpu1.kern.callpal_callsys 136 0.16% 99.95% # nu system.cpu1.kern.callpal_imb 44 0.05% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 93957 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 3692 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 84907 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 34137 40.21% 40.21% # number of times we switched to this ipl +system.cpu1.kern.inst.hwrei 93966 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 3806 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 84915 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 34143 40.21% 40.21% # number of times we switched to this ipl system.cpu1.kern.ipl_count_22 1928 2.27% 42.48% # number of times we switched to this ipl system.cpu1.kern.ipl_count_30 96 0.11% 42.59% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 48746 57.41% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 68748 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 33410 48.60% 48.60% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count_31 48748 57.41% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 68760 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 33416 48.60% 48.60% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_22 1928 2.80% 51.40% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_30 96 0.14% 51.54% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 33314 48.46% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 1907704497000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 1872145700000 98.14% 98.14% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 351989500 0.02% 98.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 39998500 0.00% 98.16% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 35166809000 1.84% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used_0 0.978703 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_good_31 33320 48.46% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1907704531000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1871986899500 98.13% 98.13% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 352080000 0.02% 98.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 40004500 0.00% 98.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 35325547000 1.85% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.978707 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.683420 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_31 0.683515 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.mode_good_kernel 521 system.cpu1.kern.mode_good_user 463 system.cpu1.kern.mode_good_idle 58 -system.cpu1.kern.mode_switch_kernel 2303 # number of protection mode switches +system.cpu1.kern.mode_switch_kernel 2305 # number of protection mode switches system.cpu1.kern.mode_switch_user 463 # number of protection mode switches system.cpu1.kern.mode_switch_idle 2035 # number of protection mode switches -system.cpu1.kern.mode_switch_good 1.254728 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.226227 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good 1.254532 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.226030 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_idle 0.028501 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 46596073500 2.44% 2.44% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1015566000 0.05% 2.50% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 1860092849500 97.50% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_kernel 46750182500 2.45% 2.45% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1015923000 0.05% 2.50% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1859938417500 97.50% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 1839 # number of times the context was actually changed system.cpu1.kern.syscall 104 # number of syscalls executed system.cpu1.kern.syscall_3 11 10.58% 10.58% # number of syscalls executed @@ -900,25 +900,25 @@ system.cpu1.kern.syscall_59 1 0.96% 57.69% # nu system.cpu1.kern.syscall_71 31 29.81% 87.50% # number of syscalls executed system.cpu1.kern.syscall_74 10 9.62% 97.12% # number of syscalls executed system.cpu1.kern.syscall_132 3 2.88% 100.00% # number of syscalls executed -system.cpu1.numCycles 42759649 # number of cpu cycles simulated -system.cpu1.rename.RENAME:BlockCycles 3630480 # Number of cycles rename is blocking -system.cpu1.rename.RENAME:CommittedMaps 13162138 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IQFullEvents 331495 # Number of times rename has blocked due to IQ full -system.cpu1.rename.RENAME:IdleCycles 15176071 # Number of cycles rename is idle -system.cpu1.rename.RENAME:LSQFullEvents 648663 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:ROBFullEvents 1231 # Number of times rename has blocked due to ROB full -system.cpu1.rename.RENAME:RenameLookups 29369210 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 24481625 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 16150176 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 4323376 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 641031 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 1811966 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 2988036 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:serializeStallCycles 12475541 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 728332 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 4962004 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 86297 # count of temporary serializing insts renamed -system.cpu1.timesIdled 480244 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.numCycles 42844582 # number of cpu cycles simulated +system.cpu1.rename.RENAME:BlockCycles 3655834 # Number of cycles rename is blocking +system.cpu1.rename.RENAME:CommittedMaps 13191652 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IQFullEvents 331503 # Number of times rename has blocked due to IQ full +system.cpu1.rename.RENAME:IdleCycles 15199760 # Number of cycles rename is idle +system.cpu1.rename.RENAME:LSQFullEvents 648645 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RENAME:ROBFullEvents 1226 # Number of times rename has blocked due to ROB full +system.cpu1.rename.RENAME:RenameLookups 29419469 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 24525114 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 16182590 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 4333684 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 641522 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 1812010 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 2990936 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:serializeStallCycles 12476165 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 728375 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 4962161 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 86287 # count of temporary serializing insts renamed +system.cpu1.timesIdled 480520 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -932,55 +932,55 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency 115245.702857 # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63245.702857 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 20167998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_miss_latency 115331.417143 # average ReadReq miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63331.417143 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 20182998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses 175 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 11067998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 11082998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 137815.912736 # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85812.468906 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5726526806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_miss_latency 137844.166490 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85840.579852 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5727700806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3565679708 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3566847774 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 6166.359533 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_mshrs 6165.982406 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked_no_mshrs 10458 # number of cycles access was blocked system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 64487788 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64483844 # number of cycles access was blocked system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses 41727 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 137721.254919 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85717.825533 # average overall mshr miss latency +system.iocache.demand_avg_miss_latency 137749.749658 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85746.178062 # average overall mshr miss latency system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5746694804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5747883804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate 1 # miss rate for demand accesses system.iocache.demand_misses 41727 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3576747706 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3577930772 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 41727 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.overall_accesses 41727 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 137721.254919 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85717.825533 # average overall mshr miss latency +system.iocache.overall_avg_miss_latency 137749.749658 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85746.178062 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 5746694804 # number of overall miss cycles +system.iocache.overall_miss_latency 5747883804 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses system.iocache.overall_misses 41727 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3576747706 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3577930772 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 41727 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -997,80 +997,80 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 system.iocache.replacements 41697 # number of replacements system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.387818 # Cycle average of tags in use +system.iocache.tagsinuse 0.387817 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1717170509000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1717170531000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41522 # number of writebacks -system.l2c.ReadExReq_accesses 317495 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52375.723397 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40223.099381 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 16629030300 # number of ReadExReq miss cycles +system.l2c.ReadExReq_accesses 317502 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52375.567080 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40223.034620 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 16629347299 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 317495 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12770632938 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses 317502 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12770893938 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 317495 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2204283 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52067.320767 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40026.416785 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 317502 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2204255 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52067.361570 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40026.445360 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1893933 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16159093000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.140794 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 310350 # number of ReadReq misses +system.l2c.ReadReq_hits 1893900 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16159366000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.140798 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 310355 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12421518000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.140786 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 310333 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 827055500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 141956 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 51067.196822 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.595903 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 7249294992 # number of UpgradeReq miss cycles +system.l2c.ReadReq_mshr_miss_latency 12421727000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.140790 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 310338 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 840472000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 141949 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 51066.182164 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.287026 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 7248793492 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 141956 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5691526500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses 141949 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5691202000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 141956 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 141949 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1410123998 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 455580 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 455580 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1423764498 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 455578 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 455578 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 4.836093 # Average number of references to valid blocks. +system.l2c.avg_refs 4.834791 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2521778 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52223.276923 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40125.879919 # average overall mshr miss latency -system.l2c.demand_hits 1893933 # number of demand (read+write) hits -system.l2c.demand_miss_latency 32788123300 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.248969 # miss rate for demand accesses -system.l2c.demand_misses 627845 # number of demand (read+write) misses +system.l2c.demand_accesses 2521757 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52223.218502 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40125.861586 # average overall mshr miss latency +system.l2c.demand_hits 1893900 # number of demand (read+write) hits +system.l2c.demand_miss_latency 32788713299 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.248976 # miss rate for demand accesses +system.l2c.demand_misses 627857 # number of demand (read+write) misses system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 25192150938 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.248962 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 627828 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 25192620938 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.248969 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 627840 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2521778 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52223.276923 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40125.879919 # average overall mshr miss latency +system.l2c.overall_accesses 2521757 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52223.218502 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40125.861586 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1893933 # number of overall hits -system.l2c.overall_miss_latency 32788123300 # number of overall miss cycles -system.l2c.overall_miss_rate 0.248969 # miss rate for overall accesses -system.l2c.overall_misses 627845 # number of overall misses +system.l2c.overall_hits 1893900 # number of overall hits +system.l2c.overall_miss_latency 32788713299 # number of overall miss cycles +system.l2c.overall_miss_rate 0.248976 # miss rate for overall accesses +system.l2c.overall_misses 627857 # number of overall misses system.l2c.overall_mshr_hits 17 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 25192150938 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.248962 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 627828 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2237179498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 25192620938 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.248969 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 627840 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2264236498 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -1081,13 +1081,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 402113 # number of replacements -system.l2c.sampled_refs 433643 # Sample count of references to valid blocks. +system.l2c.replacements 402142 # number of replacements +system.l2c.sampled_refs 433669 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 31146.703960 # Cycle average of tags in use -system.l2c.total_refs 2097138 # Total number of references to valid blocks. +system.l2c.tagsinuse 31163.178814 # Cycle average of tags in use +system.l2c.total_refs 2096699 # Total number of references to valid blocks. system.l2c.warmup_cycle 9278348000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 124275 # number of writebacks +system.l2c.writebacks 124293 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal index d5c08c61f..6c5842787 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal @@ -61,6 +61,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
loop: loaded (max 8 devices)
nbd: registered device at major 43
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. +
PCI: Setting latency timer of device 0000:00:01.0 to 64
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
eth0: enabling optical transceiver
eth0: using 64 bit addressing. @@ -72,6 +73,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
PIIX4: IDE controller at PCI slot 0000:00:00.0
PIIX4: chipset revision 0
PIIX4: 100% native mode on irq 31 +
PCI: Setting latency timer of device 0000:00:00.0 to 64
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
hda: M5 IDE Disk, ATA DISK drive diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index f6f2f7d37..c0c3673fc 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:30:58 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:31:00 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3 +M5 compiled Dec 14 2008 21:47:07 +M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141 +M5 commit date Sun Dec 14 21:45:15 2008 -0800 +M5 started Dec 14 2008 21:47:52 +M5 executing on tater +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1867358550500 because m5_exit instruction encountered +Exiting @ tick 1867363148500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 4860b3f1d..d70f58b89 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 6932487 # Number of BTB hits -global.BPredUnit.BTBLookups 13324936 # Number of BTB lookups -global.BPredUnit.RASInCorrect 41495 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 828381 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 12127533 # Number of conditional branches predicted -global.BPredUnit.lookups 14559443 # Number of BP lookups -global.BPredUnit.usedRAS 1032470 # Number of times the RAS was used to get a target. -host_inst_rate 123231 # Simulator instruction rate (inst/s) -host_mem_usage 290820 # Number of bytes of host memory used -host_seconds 430.51 # Real time elapsed on the host -host_tick_rate 4337505567 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 3072758 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 2866670 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 11041732 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 7011041 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 6937900 # Number of BTB hits +global.BPredUnit.BTBLookups 13339861 # Number of BTB lookups +global.BPredUnit.RASInCorrect 41537 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 828629 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 12132448 # Number of conditional branches predicted +global.BPredUnit.lookups 14570242 # Number of BP lookups +global.BPredUnit.usedRAS 1034900 # Number of times the RAS was used to get a target. +host_inst_rate 133323 # Simulator instruction rate (inst/s) +host_mem_usage 292856 # Number of bytes of host memory used +host_seconds 398.21 # Real time elapsed on the host +host_tick_rate 4689394624 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 3083644 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 2877472 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 11055097 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 7027136 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 53052618 # Number of instructions simulated -sim_seconds 1.867359 # Number of seconds simulated -sim_ticks 1867358550500 # Number of ticks simulated -system.cpu.commit.COM:branches 8455188 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 973838 # number cycles where commit BW limit reached +sim_insts 53090630 # Number of instructions simulated +sim_seconds 1.867363 # Number of seconds simulated +sim_ticks 1867363148500 # Number of ticks simulated +system.cpu.commit.COM:branches 8461943 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 974606 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 100543308 +system.cpu.commit.COM:committed_per_cycle.samples 100617513 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 76317924 7590.55% - 1 10743540 1068.55% - 2 5987880 595.55% - 3 2987787 297.16% - 4 2072579 206.14% - 5 671161 66.75% - 6 395328 39.32% - 7 393271 39.11% - 8 973838 96.86% + 0 76371867 7590.32% + 1 10755813 1068.98% + 2 5991818 595.50% + 3 2987930 296.96% + 4 2074332 206.16% + 5 671621 66.75% + 6 397219 39.48% + 7 392307 38.99% + 8 974606 96.86% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 56244351 # Number of instructions committed -system.cpu.commit.COM:loads 9302477 # Number of loads committed -system.cpu.commit.COM:membars 227741 # Number of memory barriers committed -system.cpu.commit.COM:refs 15692393 # Number of memory references committed +system.cpu.commit.COM:count 56284983 # Number of instructions committed +system.cpu.commit.COM:loads 9308629 # Number of loads committed +system.cpu.commit.COM:membars 228003 # Number of memory barriers committed +system.cpu.commit.COM:refs 15700868 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 786910 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 56244351 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 667224 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 9485751 # The number of squashed insts skipped by commit -system.cpu.committedInsts 53052618 # Number of Instructions Simulated -system.cpu.committedInsts_total 53052618 # Number of Instructions Simulated -system.cpu.cpi 2.580282 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.580282 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 214227 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 15534.014065 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11815.523733 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits 192045 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 344575500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.103544 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 22182 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 4654 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207102500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.081820 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17528 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 9334533 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 23887.280277 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22764.210749 # average ReadReq mshr miss latency +system.cpu.commit.branchMispredicts 787164 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 56284983 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 667781 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 9518126 # The number of squashed insts skipped by commit +system.cpu.committedInsts 53090630 # Number of Instructions Simulated +system.cpu.committedInsts_total 53090630 # Number of Instructions Simulated +system.cpu.cpi 2.580435 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.580435 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 214297 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 15516.058460 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11817.323059 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits 192128 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 343975500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.103450 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 22169 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 4649 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207039500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.081756 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_misses 17520 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses 9342423 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 23886.371687 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22764.504418 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits 7801638 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 36616692500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.164218 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1532895 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 448100 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 24694502000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.116213 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1084795 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 889982500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses 219741 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency 56331.938098 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.938098 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits 189758 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 1689000500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate 0.136447 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses 29983 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599051500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.136447 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 29983 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6155139 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 49031.922002 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54492.269570 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_hits 7809504 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 36615873000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.164082 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1532919 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 448215 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 24692749000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.116105 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1084704 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904972000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses 219789 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency 56331.265633 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.265633 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits 189804 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 1689093000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate 0.136426 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses 29985 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599138000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.136426 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_misses 29985 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6157295 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 49032.528329 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54492.949680 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits 3924727 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 109361387216 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.362366 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2230412 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1833469 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 21630324960 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.064490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 396943 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1220847997 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles_no_mshrs 10009.541558 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_hits 3927003 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 109356855672 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.362219 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2230292 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1833354 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 21630322460 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.064466 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 396938 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235426497 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles_no_mshrs 10009.885310 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 11500 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.820405 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.828407 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 138181 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 1383128462 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 1383175962 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 23000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15489672 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 38789.840881 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 31263.844863 # average overall mshr miss latency -system.cpu.dcache.demand_hits 11726365 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 145978079716 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.242956 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3763307 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 15499718 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 38789.408479 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 31264.685707 # average overall mshr miss latency +system.cpu.dcache.demand_hits 11736507 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 145972728672 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.242792 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3763211 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 2281569 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 46324826960 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.095660 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1481738 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 46323071460 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.095592 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1481642 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15489672 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 38789.840881 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 31263.844863 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 15499718 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 38789.408479 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 31264.685707 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 11726365 # number of overall hits -system.cpu.dcache.overall_miss_latency 145978079716 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.242956 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3763307 # number of overall misses +system.cpu.dcache.overall_hits 11736507 # number of overall hits +system.cpu.dcache.overall_miss_latency 145972728672 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.242792 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3763211 # number of overall misses system.cpu.dcache.overall_mshr_hits 2281569 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 46324826960 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.095660 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1481738 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2110830497 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_miss_latency 46323071460 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.095592 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1481642 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2140398497 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -143,105 +143,105 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 1402096 # number of replacements -system.cpu.dcache.sampled_refs 1402608 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1401991 # number of replacements +system.cpu.dcache.sampled_refs 1402503 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 511.995429 # Cycle average of tags in use -system.cpu.dcache.total_refs 12371571 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 12381868 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 430429 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 48380829 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 42524 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 612955 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 72702474 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 37949237 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 13063267 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1645972 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 134798 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1149974 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 1229941 # DTB accesses -system.cpu.dtb.acv 828 # DTB access violations -system.cpu.dtb.hits 16757791 # DTB hits -system.cpu.dtb.misses 44378 # DTB misses -system.cpu.dtb.read_accesses 908364 # DTB read accesses -system.cpu.dtb.read_acv 587 # DTB read access violations -system.cpu.dtb.read_hits 10166755 # DTB read hits -system.cpu.dtb.read_misses 36227 # DTB read misses -system.cpu.dtb.write_accesses 321577 # DTB write accesses -system.cpu.dtb.write_acv 241 # DTB write access violations -system.cpu.dtb.write_hits 6591036 # DTB write hits -system.cpu.dtb.write_misses 8151 # DTB write misses -system.cpu.fetch.Branches 14559443 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 8996158 # Number of cache lines fetched -system.cpu.fetch.Cycles 23473306 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 455287 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 74247726 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 2478 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 968839 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.106358 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 8996158 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 7964957 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.542387 # Number of inst fetches per cycle +system.cpu.dcache.writebacks 430428 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 48410304 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 42525 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 614935 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 72780900 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37979006 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 13077120 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1650418 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 134762 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1151082 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 1236420 # DTB accesses +system.cpu.dtb.acv 825 # DTB access violations +system.cpu.dtb.hits 16772347 # DTB hits +system.cpu.dtb.misses 44495 # DTB misses +system.cpu.dtb.read_accesses 910052 # DTB read accesses +system.cpu.dtb.read_acv 586 # DTB read access violations +system.cpu.dtb.read_hits 10174508 # DTB read hits +system.cpu.dtb.read_misses 36219 # DTB read misses +system.cpu.dtb.write_accesses 326368 # DTB write accesses +system.cpu.dtb.write_acv 239 # DTB write access violations +system.cpu.dtb.write_hits 6597839 # DTB write hits +system.cpu.dtb.write_misses 8276 # DTB write misses +system.cpu.fetch.Branches 14570242 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 9007841 # Number of cache lines fetched +system.cpu.fetch.Cycles 23500316 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 455597 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 74326781 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 2461 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 969865 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.106355 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 9007841 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 7972800 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.542543 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 102189280 +system.cpu.fetch.rateDist.samples 102267931 system.cpu.fetch.rateDist.min_value 0 - 0 87752503 8587.25% - 1 1049427 102.69% - 2 2020193 197.69% - 3 968502 94.78% - 4 3001129 293.68% - 5 683878 66.92% - 6 831667 81.38% - 7 1217349 119.13% - 8 4664632 456.47% + 0 87815810 8586.84% + 1 1050742 102.74% + 2 2021882 197.70% + 3 969421 94.79% + 4 3003437 293.68% + 5 686434 67.12% + 6 832579 81.41% + 7 1218388 119.14% + 8 4669238 456.57% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 8996158 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 14905.477582 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.562270 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 7948798 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15611401000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.116423 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1047360 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 51971 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11852656500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.110646 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 995389 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs 11366.071429 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_accesses 9007841 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 14905.597019 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.422251 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 7960337 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15613672500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.116288 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1047504 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 51957 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11854398500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.110520 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 995547 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs 11175.438596 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 7.987119 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 56 # number of cycles access was blocked +system.cpu.icache.avg_refs 7.997460 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 57 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 636500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 637000 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 8996158 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 14905.477582 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11907.562270 # average overall mshr miss latency -system.cpu.icache.demand_hits 7948798 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15611401000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.116423 # miss rate for demand accesses -system.cpu.icache.demand_misses 1047360 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 51971 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11852656500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.110646 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 995389 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 9007841 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 14905.597019 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11907.422251 # average overall mshr miss latency +system.cpu.icache.demand_hits 7960337 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15613672500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.116288 # miss rate for demand accesses +system.cpu.icache.demand_misses 1047504 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 51957 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11854398500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.110520 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 995547 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 8996158 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 14905.477582 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11907.562270 # average overall mshr miss latency +system.cpu.icache.overall_accesses 9007841 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 14905.597019 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11907.422251 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 7948798 # number of overall hits -system.cpu.icache.overall_miss_latency 15611401000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.116423 # miss rate for overall accesses -system.cpu.icache.overall_misses 1047360 # number of overall misses -system.cpu.icache.overall_mshr_hits 51971 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11852656500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.110646 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 995389 # number of overall MSHR misses +system.cpu.icache.overall_hits 7960337 # number of overall hits +system.cpu.icache.overall_miss_latency 15613672500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.116288 # miss rate for overall accesses +system.cpu.icache.overall_misses 1047504 # number of overall misses +system.cpu.icache.overall_mshr_hits 51957 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11854398500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.110520 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 995547 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -253,63 +253,63 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 994691 # number of replacements -system.cpu.icache.sampled_refs 995202 # Sample count of references to valid blocks. +system.cpu.icache.replacements 994847 # number of replacements +system.cpu.icache.sampled_refs 995358 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 509.772494 # Cycle average of tags in use -system.cpu.icache.total_refs 7948797 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 509.772456 # Cycle average of tags in use +system.cpu.icache.total_refs 7960336 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 25306164000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 34701444 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 9157080 # Number of branches executed -system.cpu.iew.EXEC:nop 3677888 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.420385 # Inst execution rate -system.cpu.iew.EXEC:refs 17040949 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 6614103 # Number of stores executed +system.cpu.idleCycles 34729008 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 9164699 # Number of branches executed +system.cpu.iew.EXEC:nop 3680668 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.420415 # Inst execution rate +system.cpu.iew.EXEC:refs 17055609 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 6621040 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 34509874 # num instructions consuming a value -system.cpu.iew.WB:count 56954270 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.764112 # average fanout of values written-back +system.cpu.iew.WB:consumers 34548488 # num instructions consuming a value +system.cpu.iew.WB:count 57002857 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.763990 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 26369407 # num instructions producing a value -system.cpu.iew.WB:rate 0.416056 # insts written-back per cycle -system.cpu.iew.WB:sent 57054995 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 856295 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 9703619 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 11041732 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1799303 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1049063 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 7011041 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 65859525 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 10426846 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 538501 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 57546755 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 50837 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 26394693 # num instructions producing a value +system.cpu.iew.WB:rate 0.416089 # insts written-back per cycle +system.cpu.iew.WB:sent 57104330 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 856523 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 9726576 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 11055097 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1799800 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1048637 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 7027136 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 65932751 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 10434569 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 539744 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 57595615 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 50922 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 6569 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1645972 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 550293 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 6567 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1650418 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 550443 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 311312 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 426511 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 11442 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 311143 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 426303 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 11520 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 45279 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 15270 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1739255 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 621125 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 45279 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 380960 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 475335 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.387555 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.387555 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 58085258 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 46025 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 15352 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1746468 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 634897 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 46025 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 380989 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 475534 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.387532 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.387532 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 58135361 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 7284 0.01% # Type of FU issued - IntAlu 39585322 68.15% # Type of FU issued - IntMult 61995 0.11% # Type of FU issued + IntAlu 39619390 68.15% # Type of FU issued + IntMult 62115 0.11% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 25609 0.04% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued @@ -317,16 +317,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 3636 0.01% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 10781907 18.56% # Type of FU issued - MemWrite 6666291 11.48% # Type of FU issued - IprAccess 953214 1.64% # Type of FU issued + MemRead 10789898 18.56% # Type of FU issued + MemWrite 6674141 11.48% # Type of FU issued + IprAccess 953288 1.64% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 433947 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007471 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 434481 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007474 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 52004 11.98% # attempts to use FU when none available + IntAlu 52045 11.98% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -335,39 +335,39 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 278726 64.23% # attempts to use FU when none available - MemWrite 103217 23.79% # attempts to use FU when none available + MemRead 278817 64.17% # attempts to use FU when none available + MemWrite 103619 23.85% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 102189280 +system.cpu.iq.ISSUE:issued_per_cycle.samples 102267931 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 73101546 7153.54% - 1 14613738 1430.07% - 2 6411296 627.39% - 3 3930297 384.61% - 4 2526857 247.27% - 5 1033193 101.11% - 6 443511 43.40% - 7 107158 10.49% - 8 21684 2.12% + 0 73151138 7152.89% + 1 14628619 1430.42% + 2 6419666 627.73% + 3 3934330 384.71% + 4 2528894 247.28% + 5 1032607 100.97% + 6 444582 43.47% + 7 106443 10.41% + 8 21652 2.12% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.424318 # Inst issue rate -system.cpu.iq.iqInstsAdded 60130813 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 58085258 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 2050824 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8705374 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 34364 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1383600 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4697017 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 1300570 # ITB accesses -system.cpu.itb.acv 941 # ITB acv -system.cpu.itb.hits 1261136 # ITB hits -system.cpu.itb.misses 39434 # ITB misses -system.cpu.kern.callpal 192636 # number of callpals executed +system.cpu.iq.ISSUE:rate 0.424355 # Inst issue rate +system.cpu.iq.iqInstsAdded 60200389 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 58135361 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2051694 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8738375 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 34584 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1383913 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4729371 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 1303895 # ITB accesses +system.cpu.itb.acv 943 # ITB acv +system.cpu.itb.hits 1264480 # ITB hits +system.cpu.itb.misses 39415 # ITB misses +system.cpu.kern.callpal 192656 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed @@ -375,7 +375,7 @@ system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal_swpctx 4177 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal_swpipl 175664 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal_swpipl 175684 91.19% 93.39% # number of callpals executed system.cpu.kern.callpal_rdps 6794 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed @@ -385,40 +385,40 @@ system.cpu.kern.callpal_rti 5221 2.71% 99.64% # nu system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211796 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6269 # number of quiesce instructions executed -system.cpu.kern.ipl_count 183013 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 74947 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 211815 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6383 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183033 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74957 40.95% 40.95% # number of times we switched to this ipl system.cpu.kern.ipl_count_21 237 0.13% 41.08% # number of times we switched to this ipl system.cpu.kern.ipl_count_22 1890 1.03% 42.11% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 105939 57.89% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149287 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73580 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count_31 105949 57.89% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149307 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73590 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73580 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1867357676000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1824918402500 97.73% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 102745500 0.01% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 392410500 0.02% 97.75% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 41944117500 2.25% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used_0 0.981760 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good_31 73590 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1867362274000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1824759658500 97.72% 97.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 102563000 0.01% 97.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 392423000 0.02% 97.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 42107629500 2.25% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981763 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.694551 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_31 0.694579 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.mode_good_kernel 1911 system.cpu.kern.mode_good_user 1741 system.cpu.kern.mode_good_idle 170 -system.cpu.kern.mode_switch_kernel 5975 # number of protection mode switches +system.cpu.kern.mode_switch_kernel 5973 # number of protection mode switches system.cpu.kern.mode_switch_user 1741 # number of protection mode switches system.cpu.kern.mode_switch_idle 2095 # number of protection mode switches -system.cpu.kern.mode_switch_good 1.400978 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.319833 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good 1.401085 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.319940 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 31310273000 1.68% 1.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 3185721000 0.17% 1.85% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1832861674000 98.15% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_kernel 31312997500 1.68% 1.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 3190588500 0.17% 1.85% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1832858680000 98.15% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed @@ -451,25 +451,25 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.numCycles 136890724 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14253215 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 38229138 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1097271 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 39542580 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2236137 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 15711 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 83423826 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 68665910 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 46022424 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 12703530 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1645972 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5219245 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7793284 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 28824736 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1704564 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 12805073 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 256708 # count of temporary serializing insts renamed -system.cpu.timesIdled 1321430 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.numCycles 136996939 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14276861 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 38259280 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1099460 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 39573188 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2235524 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 15708 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 83522905 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 68741813 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 46071316 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 12717646 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1650418 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 5220588 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7812034 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 28829228 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1704991 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 12807732 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 256915 # count of temporary serializing insts renamed +system.cpu.timesIdled 1321478 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -483,55 +483,55 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency 115248.543353 # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_miss_latency 115277.445087 # average ReadReq miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63277.445087 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19942998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses 173 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10946998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 137791.894638 # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85788.456248 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5725528806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_miss_latency 137802.098720 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85798.754910 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5725952806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3564681934 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3565109864 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 6164.090493 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_mshrs 6162.652539 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked_no_mshrs 10476 # number of cycles access was blocked system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 64575012 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64559948 # number of cycles access was blocked system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses 41725 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 137698.425500 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85695.001366 # average overall mshr miss latency +system.iocache.demand_avg_miss_latency 137708.707106 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85705.377160 # average overall mshr miss latency system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5745466804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5745895804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate 1 # miss rate for demand accesses system.iocache.demand_misses 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3575623932 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3576056862 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.overall_accesses 41725 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 137698.425500 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85695.001366 # average overall mshr miss latency +system.iocache.overall_avg_miss_latency 137708.707106 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85705.377160 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 5745466804 # number of overall miss cycles +system.iocache.overall_miss_latency 5745895804 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses system.iocache.overall_misses 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3575623932 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3576056862 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -548,80 +548,80 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.267378 # Cycle average of tags in use +system.iocache.tagsinuse 1.267414 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1716179930000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1716180054000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 300595 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52362.159484 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40213.629621 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15739803330 # number of ReadExReq miss cycles +system.l2c.ReadExReq_accesses 300588 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52362.011561 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40213.127257 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15739392331 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 300595 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12088015996 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses 300588 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12087583496 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 300595 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2097337 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52066.027817 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40026.238880 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 300588 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2097395 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52065.516476 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40025.575526 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1786309 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16193992500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.148297 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 311028 # number of ReadReq misses +system.l2c.ReadReq_hits 1786374 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16193469000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.148289 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 311021 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12449241000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.148296 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 311027 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 797101500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 130242 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 52272.511886 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.963790 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 6808076493 # number of UpgradeReq miss cycles +system.l2c.ReadReq_mshr_miss_latency 12448754500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.148289 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 311020 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 810514000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 130249 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 52272.455021 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40098.173498 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6808434994 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 130242 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5222439000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses 130249 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5222747000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 130242 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 130249 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1102715998 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430429 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 430429 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1115855498 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 430428 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 430428 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 4.598824 # Average number of references to valid blocks. +system.l2c.avg_refs 4.596635 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2397932 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52211.567959 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40118.336155 # average overall mshr miss latency -system.l2c.demand_hits 1786309 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31933795830 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.255063 # miss rate for demand accesses -system.l2c.demand_misses 611623 # number of demand (read+write) misses +system.l2c.demand_accesses 2397983 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52211.235170 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40117.751887 # average overall mshr miss latency +system.l2c.demand_hits 1786374 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31932861331 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.255051 # miss rate for demand accesses +system.l2c.demand_misses 611609 # number of demand (read+write) misses system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24537256996 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.255062 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 611622 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 24536337996 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.255051 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 611608 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2397932 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52211.567959 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40118.336155 # average overall mshr miss latency +system.l2c.overall_accesses 2397983 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52211.235170 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40117.751887 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1786309 # number of overall hits -system.l2c.overall_miss_latency 31933795830 # number of overall miss cycles -system.l2c.overall_miss_rate 0.255063 # miss rate for overall accesses -system.l2c.overall_misses 611623 # number of overall misses +system.l2c.overall_hits 1786374 # number of overall hits +system.l2c.overall_miss_latency 31932861331 # number of overall miss cycles +system.l2c.overall_miss_rate 0.255051 # miss rate for overall accesses +system.l2c.overall_misses 611609 # number of overall misses system.l2c.overall_mshr_hits 1 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24537256996 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.255062 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 611622 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1899817498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 24536337996 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.255051 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 611608 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1926369498 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -632,13 +632,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 396037 # number of replacements -system.l2c.sampled_refs 427715 # Sample count of references to valid blocks. +system.l2c.replacements 396031 # number of replacements +system.l2c.sampled_refs 427707 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30684.696960 # Cycle average of tags in use -system.l2c.total_refs 1966986 # Total number of references to valid blocks. +system.l2c.tagsinuse 30680.970322 # Cycle average of tags in use +system.l2c.total_refs 1966013 # Total number of references to valid blocks. system.l2c.warmup_cycle 5645091000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119087 # number of writebacks +system.l2c.writebacks 119091 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal index 8a13d1a5e..1b4012ef1 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal @@ -56,6 +56,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
loop: loaded (max 8 devices)
nbd: registered device at major 43
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. +
PCI: Setting latency timer of device 0000:00:01.0 to 64
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
eth0: enabling optical transceiver
eth0: using 64 bit addressing. @@ -67,6 +68,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
PIIX4: IDE controller at PCI slot 0000:00:00.0
PIIX4: chipset revision 0
PIIX4: 100% native mode on irq 31 +
PCI: Setting latency timer of device 0000:00:00.0 to 64
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
hda: M5 IDE Disk, ATA DISK drive diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index a9bd0ea3f..2e7c9e61b 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:30:58 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:37:23 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +M5 compiled Dec 14 2008 21:47:07 +M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141 +M5 commit date Sun Dec 14 21:45:15 2008 -0800 +M5 started Dec 14 2008 21:48:26 +M5 executing on tater +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1870335522500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 1e6af66f7..55ea1f24a 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,44 +1,44 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3333474 # Simulator instruction rate (inst/s) -host_mem_usage 290708 # Number of bytes of host memory used -host_seconds 18.93 # Real time elapsed on the host -host_tick_rate 98784311223 # Simulator tick rate (ticks/s) +host_inst_rate 1560779 # Simulator instruction rate (inst/s) +host_mem_usage 292076 # Number of bytes of host memory used +host_seconds 40.46 # Real time elapsed on the host +host_tick_rate 46222973494 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 63113507 # Number of instructions simulated +sim_insts 63154034 # Number of instructions simulated sim_seconds 1.870336 # Number of seconds simulated sim_ticks 1870335522500 # Number of ticks simulated -system.cpu0.dcache.LoadLockedReq_accesses 188283 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_hits 172122 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_rate 0.085834 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses 16161 # number of LoadLockedReq misses -system.cpu0.dcache.ReadReq_accesses 8975619 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_hits 7292050 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_rate 0.187571 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 1683569 # number of ReadReq misses -system.cpu0.dcache.StoreCondReq_accesses 187323 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_hits 159821 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_rate 0.146816 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses 27502 # number of StoreCondReq misses -system.cpu0.dcache.WriteReq_accesses 5746054 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_hits 5372248 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_rate 0.065054 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 373806 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_accesses 188297 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_hits 172138 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_rate 0.085817 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses 16159 # number of LoadLockedReq misses +system.cpu0.dcache.ReadReq_accesses 8981669 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits 7298106 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_rate 0.187444 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1683563 # number of ReadReq misses +system.cpu0.dcache.StoreCondReq_accesses 187338 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_hits 159838 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_rate 0.146793 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses 27500 # number of StoreCondReq misses +system.cpu0.dcache.WriteReq_accesses 5748261 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_hits 5374453 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate 0.065030 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 373808 # number of WriteReq misses system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 6.625587 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks. system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 14721673 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses 14729930 # number of demand (read+write) accesses system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu0.dcache.demand_hits 12664298 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits 12672559 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.139751 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 2057375 # number of demand (read+write) misses +system.cpu0.dcache.demand_miss_rate 0.139673 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 2057371 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -46,14 +46,14 @@ system.cpu0.dcache.demand_mshr_misses 0 # nu system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 14721673 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses 14729930 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 12664298 # number of overall hits +system.cpu0.dcache.overall_hits 12672559 # number of overall hits system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.139751 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 2057375 # number of overall misses +system.cpu0.dcache.overall_miss_rate 0.139673 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 2057371 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -69,44 +69,44 @@ system.cpu0.dcache.prefetcher.num_hwpf_issued 0 system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.dcache.replacements 1978967 # number of replacements -system.cpu0.dcache.sampled_refs 1979479 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1978962 # number of replacements +system.cpu0.dcache.sampled_refs 1979474 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 504.827685 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13115211 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 504.827058 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13123502 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 396793 # number of writebacks system.cpu0.dtb.accesses 698037 # DTB accesses system.cpu0.dtb.acv 251 # DTB access violations -system.cpu0.dtb.hits 15082911 # DTB hits +system.cpu0.dtb.hits 15091429 # DTB hits system.cpu0.dtb.misses 7805 # DTB misses system.cpu0.dtb.read_accesses 508987 # DTB read accesses system.cpu0.dtb.read_acv 152 # DTB read access violations -system.cpu0.dtb.read_hits 9148351 # DTB read hits +system.cpu0.dtb.read_hits 9154530 # DTB read hits system.cpu0.dtb.read_misses 7079 # DTB read misses system.cpu0.dtb.write_accesses 189050 # DTB write accesses system.cpu0.dtb.write_acv 99 # DTB write access violations -system.cpu0.dtb.write_hits 5934560 # DTB write hits +system.cpu0.dtb.write_hits 5936899 # DTB write hits system.cpu0.dtb.write_misses 726 # DTB write misses -system.cpu0.icache.ReadReq_accesses 57189605 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_hits 56304737 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_rate 0.015473 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 884868 # number of ReadReq misses +system.cpu0.icache.ReadReq_accesses 57230132 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_hits 56345132 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_rate 0.015464 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 885000 # number of ReadReq misses system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 63.636703 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks. system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 57189605 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses 57230132 # number of demand (read+write) accesses system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu0.icache.demand_hits 56304737 # number of demand (read+write) hits +system.cpu0.icache.demand_hits 56345132 # number of demand (read+write) hits system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.015473 # miss rate for demand accesses -system.cpu0.icache.demand_misses 884868 # number of demand (read+write) misses +system.cpu0.icache.demand_miss_rate 0.015464 # miss rate for demand accesses +system.cpu0.icache.demand_misses 885000 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -114,14 +114,14 @@ system.cpu0.icache.demand_mshr_misses 0 # nu system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 57189605 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses 57230132 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 56304737 # number of overall hits +system.cpu0.icache.overall_hits 56345132 # number of overall hits system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.015473 # miss rate for overall accesses -system.cpu0.icache.overall_misses 884868 # number of overall misses +system.cpu0.icache.overall_miss_rate 0.015464 # miss rate for overall accesses +system.cpu0.icache.overall_misses 885000 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -137,28 +137,28 @@ system.cpu0.icache.prefetcher.num_hwpf_issued 0 system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.icache.replacements 884272 # number of replacements -system.cpu0.icache.sampled_refs 884784 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 884404 # number of replacements +system.cpu0.icache.sampled_refs 884916 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use -system.cpu0.icache.total_refs 56304737 # Total number of references to valid blocks. +system.cpu0.icache.total_refs 56345132 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles -system.cpu0.itb.accesses 3858857 # ITB accesses +system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles +system.cpu0.itb.accesses 3859041 # ITB accesses system.cpu0.itb.acv 127 # ITB acv -system.cpu0.itb.hits 3855372 # ITB hits +system.cpu0.itb.hits 3855556 # ITB hits system.cpu0.itb.misses 3485 # ITB misses -system.cpu0.kern.callpal 183274 # number of callpals executed +system.cpu0.kern.callpal 183291 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal_swpctx 3761 2.05% 2.11% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3762 2.05% 2.11% # number of callpals executed system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal_swpipl 168019 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal_swpipl 168035 91.68% 93.82% # number of callpals executed system.cpu0.kern.callpal_rdps 6150 3.36% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed @@ -168,45 +168,45 @@ system.cpu0.kern.callpal_rti 4673 2.55% 99.73% # nu system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 197103 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6167 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 174852 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 70996 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 174868 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 71004 40.60% 40.60% # number of times we switched to this ipl system.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl system.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl system.cpu0.kern.ipl_count_30 8 0.00% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 101697 58.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 141409 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 69629 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count_31 101705 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 141425 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_ticks 1870335315000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1853125830000 99.08% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 17106381500 0.91% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_ticks_0 1852989766500 99.07% 99.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.980748 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.684592 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_31 0.684617 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.mode_good_kernel 1157 system.cpu0.kern.mode_good_user 1158 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 7090 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 7091 # number of protection mode switches system.cpu0.kern.mode_switch_user 1158 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.163188 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.163165 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches system.cpu0.kern.mode_ticks_kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_user 957009000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3762 # number of times the context was actually changed +system.cpu0.kern.swap_context 3763 # number of times the context was actually changed system.cpu0.kern.syscall 226 # number of syscalls executed system.cpu0.kern.syscall_2 6 2.65% 2.65% # number of syscalls executed system.cpu0.kern.syscall_3 19 8.41% 11.06% # number of syscalls executed @@ -238,10 +238,10 @@ system.cpu0.kern.syscall_98 2 0.88% 97.35% # nu system.cpu0.kern.syscall_132 2 0.88% 98.23% # number of syscalls executed system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles +system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles system.cpu0.numCycles 3740670933 # number of cpu cycles simulated -system.cpu0.num_insts 57181549 # Number of instructions executed -system.cpu0.num_refs 15322361 # Number of memory references +system.cpu0.num_insts 57222076 # Number of instructions executed +system.cpu0.num_refs 15330887 # Number of memory references system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_miss_rate 0.078511 # miss rate for LoadLockedReq accesses @@ -306,7 +306,7 @@ system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu1.dcache.replacements 62338 # number of replacements system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 391.950049 # Cycle average of tags in use +system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 30848 # number of writebacks @@ -529,33 +529,33 @@ system.iocache.tagsinuse 0.435437 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses 306244 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses 306247 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 306244 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2724143 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1759609 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.354069 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 964534 # number of ReadReq misses -system.l2c.UpgradeReq_accesses 125010 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_misses 306247 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2724267 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1759731 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.354053 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 964536 # number of ReadReq misses +system.l2c.UpgradeReq_accesses 125007 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 125010 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses 125007 # number of UpgradeReq misses system.l2c.Writeback_accesses 427641 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits 427641 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 1.789118 # Average number of references to valid blocks. +system.l2c.avg_refs 1.788900 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 3030387 # number of demand (read+write) accesses +system.l2c.demand_accesses 3030514 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.l2c.demand_hits 1759609 # number of demand (read+write) hits +system.l2c.demand_hits 1759731 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.419345 # miss rate for demand accesses -system.l2c.demand_misses 1270778 # number of demand (read+write) misses +system.l2c.demand_miss_rate 0.419329 # miss rate for demand accesses +system.l2c.demand_misses 1270783 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -563,14 +563,14 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3030387 # number of overall (read+write) accesses +system.l2c.overall_accesses 3030514 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.l2c.overall_hits 1759609 # number of overall hits +system.l2c.overall_hits 1759731 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.419345 # miss rate for overall accesses -system.l2c.overall_misses 1270778 # number of overall misses +system.l2c.overall_miss_rate 0.419329 # miss rate for overall accesses +system.l2c.overall_misses 1270783 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -586,13 +586,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 1056800 # number of replacements -system.l2c.sampled_refs 1091449 # Sample count of references to valid blocks. +system.l2c.replacements 1056803 # number of replacements +system.l2c.sampled_refs 1091452 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30522.432687 # Cycle average of tags in use -system.l2c.total_refs 1952731 # Total number of references to valid blocks. +system.l2c.tagsinuse 30526.475636 # Cycle average of tags in use +system.l2c.total_refs 1952499 # Total number of references to valid blocks. system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 123878 # number of writebacks +system.l2c.writebacks 123882 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal index c2aeea3f1..6129834bd 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal @@ -60,6 +60,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
loop: loaded (max 8 devices)
nbd: registered device at major 43
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. +
PCI: Setting latency timer of device 0000:00:01.0 to 64
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
eth0: enabling optical transceiver
eth0: using 64 bit addressing. @@ -71,6 +72,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
PIIX4: IDE controller at PCI slot 0000:00:00.0
PIIX4: chipset revision 0
PIIX4: 100% native mode on irq 31 +
PCI: Setting latency timer of device 0000:00:00.0 to 64
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
hda: M5 IDE Disk, ATA DISK drive diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index 6989105c7..2ea90534e 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:30:58 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:37:01 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +M5 compiled Dec 14 2008 21:47:07 +M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141 +M5 commit date Sun Dec 14 21:45:15 2008 -0800 +M5 started Dec 14 2008 21:47:54 +M5 executing on tater +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1828355695500 because m5_exit instruction encountered +Exiting @ tick 1829332258000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 8c53afda6..19b0c43d9 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,44 +1,44 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2786128 # Simulator instruction rate (inst/s) -host_mem_usage 289464 # Number of bytes of host memory used -host_seconds 21.53 # Real time elapsed on the host -host_tick_rate 84905818409 # Simulator tick rate (ticks/s) +host_inst_rate 1610025 # Simulator instruction rate (inst/s) +host_mem_usage 290828 # Number of bytes of host memory used +host_seconds 37.29 # Real time elapsed on the host +host_tick_rate 49056237387 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 59995351 # Number of instructions simulated -sim_seconds 1.828356 # Number of seconds simulated -sim_ticks 1828355695500 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses 200279 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 183118 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_rate 0.085685 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 17161 # number of LoadLockedReq misses -system.cpu.dcache.ReadReq_accesses 9523053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_hits 7801372 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_rate 0.180791 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1721681 # number of ReadReq misses -system.cpu.dcache.StoreCondReq_accesses 199258 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 169391 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_rate 0.149891 # miss rate for StoreCondReq accesses +sim_insts 60038305 # Number of instructions simulated +sim_seconds 1.829332 # Number of seconds simulated +sim_ticks 1829332258000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 183141 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_rate 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 17162 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_accesses 9529487 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 7807782 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate 0.180671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1721705 # number of ReadReq misses +system.cpu.dcache.StoreCondReq_accesses 199282 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 169415 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_rate 0.149873 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_misses 29867 # number of StoreCondReq misses -system.cpu.dcache.WriteReq_accesses 6150189 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits 5750766 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate 0.064945 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 399423 # number of WriteReq misses +system.cpu.dcache.WriteReq_accesses 6152574 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits 5753150 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate 0.064920 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 399424 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 6.866519 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15673242 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 15682061 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_hits 13552138 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 13560932 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.135333 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2121104 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate 0.135258 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2121129 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -46,14 +46,14 @@ system.cpu.dcache.demand_mshr_misses 0 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15673242 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 15682061 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 13552138 # number of overall hits +system.cpu.dcache.overall_hits 13560932 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.135333 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2121104 # number of overall misses +system.cpu.dcache.overall_miss_rate 0.135258 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2121129 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -69,44 +69,44 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 2042676 # number of replacements -system.cpu.dcache.sampled_refs 2043188 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2042700 # number of replacements +system.cpu.dcache.sampled_refs 2043212 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.997800 # Cycle average of tags in use -system.cpu.dcache.total_refs 14029590 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use +system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 428892 # number of writebacks +system.cpu.dcache.writebacks 428893 # number of writebacks system.cpu.dtb.accesses 1020787 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16053817 # DTB hits +system.cpu.dtb.hits 16062925 # DTB hits system.cpu.dtb.misses 11471 # DTB misses system.cpu.dtb.read_accesses 728856 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9703849 # DTB read hits +system.cpu.dtb.read_hits 9710427 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6349968 # DTB write hits +system.cpu.dtb.write_hits 6352498 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses 60007189 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_hits 59087131 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 920058 # number of ReadReq misses +system.cpu.icache.ReadReq_accesses 60050143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits 59129922 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate 0.015324 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 920221 # number of ReadReq misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 64.229122 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 60007189 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 60050143 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_hits 59087131 # number of demand (read+write) hits +system.cpu.icache.demand_hits 59129922 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses -system.cpu.icache.demand_misses 920058 # number of demand (read+write) misses +system.cpu.icache.demand_miss_rate 0.015324 # miss rate for demand accesses +system.cpu.icache.demand_misses 920221 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -114,14 +114,14 @@ system.cpu.icache.demand_mshr_misses 0 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 60007189 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 60050143 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 59087131 # number of overall hits +system.cpu.icache.overall_hits 59129922 # number of overall hits system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses -system.cpu.icache.overall_misses 920058 # number of overall misses +system.cpu.icache.overall_miss_rate 0.015324 # miss rate for overall accesses +system.cpu.icache.overall_misses 920221 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -137,19 +137,19 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 919431 # number of replacements -system.cpu.icache.sampled_refs 919943 # Sample count of references to valid blocks. +system.cpu.icache.replacements 919594 # number of replacements +system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 511.214823 # Cycle average of tags in use -system.cpu.icache.total_refs 59087131 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 511.215243 # Cycle average of tags in use +system.cpu.icache.total_refs 59129922 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0.983588 # Percentage of idle cycles -system.cpu.itb.accesses 4979228 # ITB accesses +system.cpu.idle_fraction 0.983585 # Percentage of idle cycles +system.cpu.itb.accesses 4979654 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4974222 # ITB hits +system.cpu.itb.hits 4974648 # ITB hits system.cpu.itb.misses 5006 # ITB misses -system.cpu.kern.callpal 192140 # number of callpals executed +system.cpu.kern.callpal 192180 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed @@ -157,50 +157,50 @@ system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal_swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal_swpipl 175211 91.19% 93.40% # number of callpals executed -system.cpu.kern.callpal_rdps 6770 3.52% 96.92% # number of callpals executed +system.cpu.kern.callpal_swpipl 175249 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal_rdps 6771 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal_rti 5202 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal_rti 5203 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211278 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6240 # number of quiesce instructions executed -system.cpu.kern.ipl_count 182522 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 74815 40.99% 40.99% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed +system.cpu.kern.ipl_count 182562 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74830 40.99% 40.99% # number of times we switched to this ipl system.cpu.kern.ipl_count_21 243 0.13% 41.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1865 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 105599 57.86% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149004 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count_22 1866 1.02% 42.14% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 105623 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149035 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1828355488000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1811087822500 99.06% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 17167360500 0.94% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used_0 0.981728 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good_22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1829332050500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 80238000 0.00% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981732 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.695537 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_31 0.695521 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.mode_good_kernel 1909 system.cpu.kern.mode_good_user 1738 system.cpu.kern.mode_good_idle 171 -system.cpu.kern.mode_switch_kernel 5948 # number of protection mode switches +system.cpu.kern.mode_switch_kernel 5949 # number of protection mode switches system.cpu.kern.mode_switch_user 1738 # number of protection mode switches system.cpu.kern.mode_switch_idle 2097 # number of protection mode switches -system.cpu.kern.mode_switch_good 1.402493 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.320948 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good 1.402439 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.320894 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 26834029500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode system.cpu.kern.mode_ticks_user 1465074000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1800056383500 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed @@ -233,10 +233,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.016412 # Percentage of non-idle cycles -system.cpu.numCycles 3656711283 # number of cpu cycles simulated -system.cpu.num_insts 59995351 # Number of instructions executed -system.cpu.num_refs 16302128 # Number of memory references +system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles +system.cpu.numCycles 3658664408 # number of cpu cycles simulated +system.cpu.num_insts 60038305 # Number of instructions executed +system.cpu.num_refs 16311238 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -303,37 +303,37 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 system.iocache.replacements 41686 # number of replacements system.iocache.sampled_refs 41702 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.226225 # Cycle average of tags in use +system.iocache.tagsinuse 1.225570 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1684804097017 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 304347 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses 304346 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 304347 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2658883 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1696464 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.361964 # miss rate for ReadReq accesses +system.l2c.ReadExReq_misses 304346 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2659071 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1696652 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.361938 # miss rate for ReadReq accesses system.l2c.ReadReq_misses 962419 # number of ReadReq misses -system.l2c.UpgradeReq_accesses 124943 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses 124945 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 124943 # number of UpgradeReq misses -system.l2c.Writeback_accesses 428892 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 428892 # number of Writeback hits +system.l2c.UpgradeReq_misses 124945 # number of UpgradeReq misses +system.l2c.Writeback_accesses 428893 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 428893 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 1.726803 # Average number of references to valid blocks. +system.l2c.avg_refs 1.727246 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2963230 # number of demand (read+write) accesses +system.l2c.demand_accesses 2963417 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.l2c.demand_hits 1696464 # number of demand (read+write) hits +system.l2c.demand_hits 1696652 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.427495 # miss rate for demand accesses -system.l2c.demand_misses 1266766 # number of demand (read+write) misses +system.l2c.demand_miss_rate 0.427468 # miss rate for demand accesses +system.l2c.demand_misses 1266765 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -341,14 +341,14 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2963230 # number of overall (read+write) accesses +system.l2c.overall_accesses 2963417 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.l2c.overall_hits 1696464 # number of overall hits +system.l2c.overall_hits 1696652 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.427495 # miss rate for overall accesses -system.l2c.overall_misses 1266766 # number of overall misses +system.l2c.overall_miss_rate 0.427468 # miss rate for overall accesses +system.l2c.overall_misses 1266765 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -364,13 +364,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 1050731 # number of replacements -system.l2c.sampled_refs 1081071 # Sample count of references to valid blocks. +system.l2c.replacements 1050724 # number of replacements +system.l2c.sampled_refs 1081067 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30223.992851 # Cycle average of tags in use -system.l2c.total_refs 1866797 # Total number of references to valid blocks. +system.l2c.tagsinuse 30228.585605 # Cycle average of tags in use +system.l2c.total_refs 1867269 # Total number of references to valid blocks. system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119150 # number of writebacks +system.l2c.writebacks 119147 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal index 7930e9e46..f17158b67 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal @@ -55,6 +55,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
loop: loaded (max 8 devices)
nbd: registered device at major 43
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. +
PCI: Setting latency timer of device 0000:00:01.0 to 64
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
eth0: enabling optical transceiver
eth0: using 64 bit addressing. @@ -66,6 +67,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
PIIX4: IDE controller at PCI slot 0000:00:00.0
PIIX4: chipset revision 0
PIIX4: 100% native mode on irq 31 +
PCI: Setting latency timer of device 0000:00:00.0 to 64
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
hda: M5 IDE Disk, ATA DISK drive diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index 06723d964..9f8bf8070 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:30:58 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:38:12 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +M5 compiled Dec 14 2008 21:47:07 +M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141 +M5 commit date Sun Dec 14 21:45:15 2008 -0800 +M5 started Dec 14 2008 21:47:52 +M5 executing on tater +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1972135479000 because m5_exit instruction encountered +Exiting @ tick 1972135461000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 39aa94315..2f2449fdc 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,92 +1,92 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1388930 # Simulator instruction rate (inst/s) -host_mem_usage 287800 # Number of bytes of host memory used -host_seconds 42.75 # Real time elapsed on the host -host_tick_rate 46129218174 # Simulator tick rate (ticks/s) +host_inst_rate 741695 # Simulator instruction rate (inst/s) +host_mem_usage 289172 # Number of bytes of host memory used +host_seconds 80.11 # Real time elapsed on the host +host_tick_rate 24616375840 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 59379829 # Number of instructions simulated +sim_insts 59420593 # Number of instructions simulated sim_seconds 1.972135 # Number of seconds simulated -sim_ticks 1972135479000 # Number of ticks simulated -system.cpu0.dcache.LoadLockedReq_accesses 192618 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency 14266.203842 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11266.203842 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits 175909 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 238374000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate 0.086747 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses 16709 # number of LoadLockedReq misses +sim_ticks 1972135461000 # Number of ticks simulated +system.cpu0.dcache.LoadLockedReq_accesses 192630 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency 14259.465279 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11259.465279 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits 175911 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 238404000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate 0.086793 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses 16719 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 188247000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.086747 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 16709 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses 8482392 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 25694.187455 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22694.147984 # average ReadReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.086793 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_misses 16719 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses 8488393 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 25694.266311 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22694.226839 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits 7443656 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 26689477500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.122458 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 1038736 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 23573228500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.122458 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 1038736 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 868701000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses 191654 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency 55352.322833 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52352.322833 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits 163305 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 1569183000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate 0.147918 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses 28349 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1484136000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.147918 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 28349 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 5845269 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 55891.595936 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 52891.595936 # average WriteReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 7449690 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 26688711500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.122367 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1038703 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 23572561500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.122367 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 1038703 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 883604000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses 191666 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency 55344.484086 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52344.484086 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits 163357 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 1566747000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate 0.147700 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses 28309 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1481820000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.147700 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_misses 28309 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 5847430 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 55891.373878 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 52891.373878 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits 5466012 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 21197279000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.064883 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 379257 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_miss_latency 20059508000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.064883 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 379257 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1225890000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_hits 5468175 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 21197083000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.064858 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 379255 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 20059318000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.064858 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 379255 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1240870000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 9.984583 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 9.990826 # Average number of references to valid blocks. system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 14327661 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 33770.798939 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 30770.770025 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 12909668 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 47886756500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.098969 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 1417993 # number of demand (read+write) misses +system.cpu0.dcache.demand_accesses 14335823 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 33770.954076 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 30770.925161 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 12917865 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 47885794500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.098910 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 1417958 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 43632736500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.098969 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 1417993 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_miss_latency 43631879500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.098910 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 1417958 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 14327661 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 33770.798939 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 30770.770025 # average overall mshr miss latency +system.cpu0.dcache.overall_accesses 14335823 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 33770.954076 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 30770.925161 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 12909668 # number of overall hits -system.cpu0.dcache.overall_miss_latency 47886756500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.098969 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 1417993 # number of overall misses +system.cpu0.dcache.overall_hits 12917865 # number of overall hits +system.cpu0.dcache.overall_miss_latency 47885794500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.098910 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 1417958 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 43632736500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.098969 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 1417993 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 2094591000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_miss_latency 43631879500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.098910 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 1417958 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 2124474000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -97,69 +97,69 @@ system.cpu0.dcache.prefetcher.num_hwpf_issued 0 system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.dcache.replacements 1338626 # number of replacements -system.cpu0.dcache.sampled_refs 1339138 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1338610 # number of replacements +system.cpu0.dcache.sampled_refs 1339122 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 503.746259 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13370734 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 503.609177 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13378935 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 84055000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 403562 # number of writebacks +system.cpu0.dcache.writebacks 403520 # number of writebacks system.cpu0.dtb.accesses 719860 # DTB accesses system.cpu0.dtb.acv 289 # DTB access violations -system.cpu0.dtb.hits 14696400 # DTB hits +system.cpu0.dtb.hits 14704826 # DTB hits system.cpu0.dtb.misses 8485 # DTB misses system.cpu0.dtb.read_accesses 524201 # DTB read accesses system.cpu0.dtb.read_acv 174 # DTB read access violations -system.cpu0.dtb.read_hits 8658591 # DTB read hits +system.cpu0.dtb.read_hits 8664724 # DTB read hits system.cpu0.dtb.read_misses 7687 # DTB read misses system.cpu0.dtb.write_accesses 195659 # DTB write accesses system.cpu0.dtb.write_acv 115 # DTB write access violations -system.cpu0.dtb.write_hits 6037809 # DTB write hits +system.cpu0.dtb.write_hits 6040102 # DTB write hits system.cpu0.dtb.write_misses 798 # DTB write misses -system.cpu0.icache.ReadReq_accesses 54124252 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 14681.475669 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11680.724759 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 53208030 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 13451491000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.016928 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 916222 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_miss_latency 10702137000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.016928 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 916222 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_accesses 54164416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 14681.637172 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11680.885800 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 53248092 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 13453136500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.016917 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 916324 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_miss_latency 10703476000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.016917 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 916324 # number of ReadReq MSHR misses system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 58.081472 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 58.118732 # Average number of references to valid blocks. system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 54124252 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 14681.475669 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11680.724759 # average overall mshr miss latency -system.cpu0.icache.demand_hits 53208030 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 13451491000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.016928 # miss rate for demand accesses -system.cpu0.icache.demand_misses 916222 # number of demand (read+write) misses +system.cpu0.icache.demand_accesses 54164416 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 14681.637172 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 11680.885800 # average overall mshr miss latency +system.cpu0.icache.demand_hits 53248092 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 13453136500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.016917 # miss rate for demand accesses +system.cpu0.icache.demand_misses 916324 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 10702137000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.016928 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 916222 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_miss_latency 10703476000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.016917 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 916324 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 54124252 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 14681.475669 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11680.724759 # average overall mshr miss latency +system.cpu0.icache.overall_accesses 54164416 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 14681.637172 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11680.885800 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 53208030 # number of overall hits -system.cpu0.icache.overall_miss_latency 13451491000 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.016928 # miss rate for overall accesses -system.cpu0.icache.overall_misses 916222 # number of overall misses +system.cpu0.icache.overall_hits 53248092 # number of overall hits +system.cpu0.icache.overall_miss_latency 13453136500 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.016917 # miss rate for overall accesses +system.cpu0.icache.overall_misses 916324 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 10702137000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.016928 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 916222 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_miss_latency 10703476000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.016917 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 916324 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -171,19 +171,19 @@ system.cpu0.icache.prefetcher.num_hwpf_issued 0 system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.icache.replacements 915582 # number of replacements -system.cpu0.icache.sampled_refs 916093 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 915684 # number of replacements +system.cpu0.icache.sampled_refs 916195 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 508.642784 # Cycle average of tags in use -system.cpu0.icache.total_refs 53208030 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 508.642782 # Cycle average of tags in use +system.cpu0.icache.total_refs 53248092 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 39455749000 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idle_fraction 0.933199 # Percentage of idle cycles -system.cpu0.itb.accesses 3953623 # ITB accesses +system.cpu0.idle_fraction 0.933160 # Percentage of idle cycles +system.cpu0.itb.accesses 3953747 # ITB accesses system.cpu0.itb.acv 143 # ITB acv -system.cpu0.itb.hits 3949782 # ITB hits +system.cpu0.itb.hits 3949906 # ITB hits system.cpu0.itb.misses 3841 # ITB misses -system.cpu0.kern.callpal 187998 # number of callpals executed +system.cpu0.kern.callpal 188012 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal_wripir 91 0.05% 0.05% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed @@ -191,8 +191,8 @@ system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # nu system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed system.cpu0.kern.callpal_swpctx 3868 2.06% 2.11% # number of callpals executed system.cpu0.kern.callpal_tbi 44 0.02% 2.13% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal_swpipl 172054 91.52% 93.65% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 2.13% # number of callpals executed +system.cpu0.kern.callpal_swpipl 172068 91.52% 93.65% # number of callpals executed system.cpu0.kern.callpal_rdps 6698 3.56% 97.22% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 97.22% # number of callpals executed system.cpu0.kern.callpal_wrusp 4 0.00% 97.22% # number of callpals executed @@ -202,43 +202,43 @@ system.cpu0.kern.callpal_rti 4713 2.51% 99.73% # nu system.cpu0.kern.callpal_callsys 356 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal_imb 149 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 202882 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6254 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 178892 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 72633 40.60% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 131 0.07% 40.67% # number of times we switched to this ipl +system.cpu0.kern.inst.hwrei 202896 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6369 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 178906 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 72641 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 131 0.07% 40.68% # number of times we switched to this ipl system.cpu0.kern.ipl_count_22 1987 1.11% 41.79% # number of times we switched to this ipl system.cpu0.kern.ipl_count_30 6 0.00% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 104135 58.21% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 144646 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 71264 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count_31 104141 58.21% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 144662 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 71272 49.27% 49.27% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_22 1987 1.37% 50.73% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_30 6 0.00% 50.74% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 71258 49.26% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 1972134721000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1908424308500 96.77% 96.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 96335500 0.00% 96.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 576469500 0.03% 96.80% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 5442500 0.00% 96.80% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 63032165000 3.20% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used_0 0.981152 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good_31 71266 49.26% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1972134703000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1908230091000 96.76% 96.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 96186500 0.00% 96.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 576952000 0.03% 96.79% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 5442500 0.00% 96.79% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 63226031000 3.21% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.981154 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.684285 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1232 -system.cpu0.kern.mode_good_user 1233 +system.cpu0.kern.ipl_used_31 0.684322 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1231 +system.cpu0.kern.mode_good_user 1232 system.cpu0.kern.mode_good_idle 0 system.cpu0.kern.mode_switch_kernel 7237 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1233 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1232 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.170236 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.170098 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 1968330428000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 3804291000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1968330503000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 3804198000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3869 # number of times the context was actually changed system.cpu0.kern.syscall 224 # number of syscalls executed @@ -272,89 +272,89 @@ system.cpu0.kern.syscall_98 2 0.89% 97.77% # nu system.cpu0.kern.syscall_132 2 0.89% 98.66% # number of syscalls executed system.cpu0.kern.syscall_144 1 0.45% 99.11% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.89% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.066801 # Percentage of non-idle cycles -system.cpu0.numCycles 3944270958 # number of cpu cycles simulated -system.cpu0.num_insts 54115477 # Number of instructions executed -system.cpu0.num_refs 14937789 # Number of memory references +system.cpu0.not_idle_fraction 0.066840 # Percentage of non-idle cycles +system.cpu0.numCycles 3944270922 # number of cpu cycles simulated +system.cpu0.num_insts 54155641 # Number of instructions executed +system.cpu0.num_refs 14946215 # Number of memory references system.cpu1.dcache.LoadLockedReq_accesses 12334 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency 13393.700787 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10393.700787 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits 11318 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 13608000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate 0.082374 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses 1016 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10560000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.082374 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 1016 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses 1020508 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 15788.930188 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12788.832374 # average ReadReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency 13303.501946 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10303.501946 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits 11306 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 13676000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate 0.083347 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses 1028 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10592000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.083347 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_misses 1028 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses 1020543 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 15771.782317 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12771.684387 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits 984726 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 564959500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.035063 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 35782 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 457610000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035063 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 35782 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_hits 984803 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 563683500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.035021 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 35740 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 456460000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035021 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 35740 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 12526000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses 12269 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency 46915.603129 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 43915.603129 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits 9840 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 113958000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate 0.197979 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses 2429 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 106671000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.197979 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 2429 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 649988 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 54642.103265 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 51642.103265 # average WriteReq mshr miss latency +system.cpu1.dcache.StoreCondReq_accesses 12270 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency 46841.453344 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 43841.453344 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits 9848 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 113450000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate 0.197392 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses 2422 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 106184000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.197392 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_misses 2422 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 650008 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 54644.846691 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 51644.846691 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits 623648 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 1439273000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.040524 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 26340 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_miss_latency 1360253000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.040524 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 26340 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 303022000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_hits 623656 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 1440001000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.040541 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 26352 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 1360945000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.040541 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 26352 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 303019000 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 30.126995 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 30.141759 # Average number of references to valid blocks. system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 1670496 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 32262.845691 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 29262.789350 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 1608374 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 2004232500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.037188 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 62122 # number of demand (read+write) misses +system.cpu1.dcache.demand_accesses 1670551 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 32269.608001 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 29269.551633 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 1608459 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 2003684500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.037169 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 62092 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 1817863000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.037188 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 62122 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_miss_latency 1817405000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.037169 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 62092 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.overall_accesses 1670496 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 32262.845691 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 29262.789350 # average overall mshr miss latency +system.cpu1.dcache.overall_accesses 1670551 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 32269.608001 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 29269.551633 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 1608374 # number of overall hits -system.cpu1.dcache.overall_miss_latency 2004232500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.037188 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 62122 # number of overall misses +system.cpu1.dcache.overall_hits 1608459 # number of overall hits +system.cpu1.dcache.overall_miss_latency 2003684500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.037169 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 62092 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 1817863000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.037188 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 62122 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 315548000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_miss_latency 1817405000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.037169 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 62092 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 315545000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -365,69 +365,69 @@ system.cpu1.dcache.prefetcher.num_hwpf_issued 0 system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.dcache.replacements 53749 # number of replacements -system.cpu1.dcache.sampled_refs 54144 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 53724 # number of replacements +system.cpu1.dcache.sampled_refs 54120 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 388.873056 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1631196 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1954644714000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 26833 # number of writebacks +system.cpu1.dcache.tagsinuse 388.878897 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1631272 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1954643578000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 26831 # number of writebacks system.cpu1.dtb.accesses 302878 # DTB accesses system.cpu1.dtb.acv 84 # DTB access violations -system.cpu1.dtb.hits 1693796 # DTB hits +system.cpu1.dtb.hits 1693851 # DTB hits system.cpu1.dtb.misses 3106 # DTB misses system.cpu1.dtb.read_accesses 205838 # DTB read accesses system.cpu1.dtb.read_acv 36 # DTB read access violations -system.cpu1.dtb.read_hits 1029675 # DTB read hits +system.cpu1.dtb.read_hits 1029710 # DTB read hits system.cpu1.dtb.read_misses 2750 # DTB read misses system.cpu1.dtb.write_accesses 97040 # DTB write accesses system.cpu1.dtb.write_acv 48 # DTB write access violations -system.cpu1.dtb.write_hits 664121 # DTB write hits +system.cpu1.dtb.write_hits 664141 # DTB write hits system.cpu1.dtb.write_misses 356 # DTB write misses -system.cpu1.icache.ReadReq_accesses 5267542 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 14619.415532 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11618.958024 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 5180112 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 1278175500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.016598 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 87430 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_miss_latency 1015845500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.016598 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 87430 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_accesses 5268142 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 14617.211446 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11616.771124 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 5180706 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 1278070500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.016597 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 87436 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency 1015724000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.016597 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 87436 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 59.267660 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 59.270387 # Average number of references to valid blocks. system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 5267542 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 14619.415532 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11618.958024 # average overall mshr miss latency -system.cpu1.icache.demand_hits 5180112 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 1278175500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.016598 # miss rate for demand accesses -system.cpu1.icache.demand_misses 87430 # number of demand (read+write) misses +system.cpu1.icache.demand_accesses 5268142 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 14617.211446 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11616.771124 # average overall mshr miss latency +system.cpu1.icache.demand_hits 5180706 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 1278070500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.016597 # miss rate for demand accesses +system.cpu1.icache.demand_misses 87436 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 1015845500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.016598 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 87430 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_miss_latency 1015724000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.016597 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 87436 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.overall_accesses 5267542 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 14619.415532 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11618.958024 # average overall mshr miss latency +system.cpu1.icache.overall_accesses 5268142 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 14617.211446 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11616.771124 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 5180112 # number of overall hits -system.cpu1.icache.overall_miss_latency 1278175500 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.016598 # miss rate for overall accesses -system.cpu1.icache.overall_misses 87430 # number of overall misses +system.cpu1.icache.overall_hits 5180706 # number of overall hits +system.cpu1.icache.overall_miss_latency 1278070500 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.016597 # miss rate for overall accesses +system.cpu1.icache.overall_misses 87436 # number of overall misses system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 1015845500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.016598 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 87430 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_miss_latency 1015724000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.016597 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 87436 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -439,19 +439,19 @@ system.cpu1.icache.prefetcher.num_hwpf_issued 0 system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.icache.replacements 86890 # number of replacements -system.cpu1.icache.sampled_refs 87402 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 86896 # number of replacements +system.cpu1.icache.sampled_refs 87408 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 419.405623 # Cycle average of tags in use -system.cpu1.icache.total_refs 5180112 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1967879772000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tagsinuse 419.405627 # Cycle average of tags in use +system.cpu1.icache.total_refs 5180706 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1967880295000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks system.cpu1.idle_fraction 0.994655 # Percentage of idle cycles -system.cpu1.itb.accesses 1397499 # ITB accesses +system.cpu1.itb.accesses 1397517 # ITB accesses system.cpu1.itb.acv 41 # ITB acv -system.cpu1.itb.hits 1396253 # ITB hits +system.cpu1.itb.hits 1396271 # ITB hits system.cpu1.itb.misses 1246 # ITB misses -system.cpu1.kern.callpal 29501 # number of callpals executed +system.cpu1.kern.callpal 29503 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal_wripir 6 0.02% 0.02% # number of callpals executed system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed @@ -459,7 +459,7 @@ system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # nu system.cpu1.kern.callpal_swpctx 365 1.24% 1.27% # number of callpals executed system.cpu1.kern.callpal_tbi 10 0.03% 1.30% # number of callpals executed system.cpu1.kern.callpal_wrent 7 0.02% 1.33% # number of callpals executed -system.cpu1.kern.callpal_swpipl 24142 81.83% 83.16% # number of callpals executed +system.cpu1.kern.callpal_swpipl 24144 81.84% 83.16% # number of callpals executed system.cpu1.kern.callpal_rdps 2172 7.36% 90.52% # number of callpals executed system.cpu1.kern.callpal_wrkgp 1 0.00% 90.53% # number of callpals executed system.cpu1.kern.callpal_wrusp 3 0.01% 90.54% # number of callpals executed @@ -470,27 +470,27 @@ system.cpu1.kern.callpal_callsys 161 0.55% 99.89% # nu system.cpu1.kern.callpal_imb 31 0.11% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 36051 # number of hwrei instructions executed +system.cpu1.kern.inst.hwrei 36053 # number of hwrei instructions executed system.cpu1.kern.inst.quiesce 2351 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 28808 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 9172 31.84% 31.84% # number of times we switched to this ipl +system.cpu1.kern.ipl_count 28810 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 9173 31.84% 31.84% # number of times we switched to this ipl system.cpu1.kern.ipl_count_22 1980 6.87% 38.71% # number of times we switched to this ipl system.cpu1.kern.ipl_count_30 91 0.32% 39.03% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 17565 60.97% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 20308 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 9164 45.13% 45.13% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count_31 17566 60.97% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 20310 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 9165 45.13% 45.13% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_22 1980 9.75% 54.87% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 9073 44.68% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 9074 44.68% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_ticks 1971683837000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 1927969399500 97.78% 97.78% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 511268500 0.03% 97.81% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1927968787500 97.78% 97.78% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 511194500 0.03% 97.81% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_30 58584000 0.00% 97.81% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 43144585000 2.19% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 43145271000 2.19% 100.00% # number of cycles we spent at this ipl system.cpu1.kern.ipl_used_0 0.999128 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.516539 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_31 0.516566 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.mode_good_kernel 532 system.cpu1.kern.mode_good_user 516 system.cpu1.kern.mode_good_idle 16 @@ -501,9 +501,9 @@ system.cpu1.kern.mode_switch_good 1.612234 # fr system.cpu1.kern.mode_switch_good_kernel 0.604545 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_idle 0.007689 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 4597806000 0.23% 0.23% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1703603000 0.09% 0.32% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 1964669629000 99.68% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_kernel 4596640000 0.23% 0.23% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1703543000 0.09% 0.32% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1964670722000 99.68% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 366 # number of times the context was actually changed system.cpu1.kern.syscall 102 # number of syscalls executed system.cpu1.kern.syscall_2 2 1.96% 1.96% # number of syscalls executed @@ -529,8 +529,8 @@ system.cpu1.kern.syscall_132 2 1.96% 99.02% # nu system.cpu1.kern.syscall_144 1 0.98% 100.00% # number of syscalls executed system.cpu1.not_idle_fraction 0.005345 # Percentage of non-idle cycles system.cpu1.numCycles 3943367734 # number of cpu cycles simulated -system.cpu1.num_insts 5264352 # Number of instructions executed -system.cpu1.num_refs 1703685 # Number of memory references +system.cpu1.num_insts 5264952 # Number of instructions executed +system.cpu1.num_refs 1703740 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -553,46 +553,46 @@ system.iocache.ReadReq_mshr_miss_latency 11248998 # nu system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_misses 178 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 137906.834954 # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85903.204082 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5730304806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_miss_latency 137902.310503 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85898.702349 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5730116806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3569449936 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3569262880 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 6168.564107 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_mshrs 6169.706090 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked_no_mshrs 10459 # number of cycles access was blocked system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 64517012 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64528956 # number of cycles access was blocked system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses 41730 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 137809.964150 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85806.348766 # average overall mshr miss latency +system.iocache.demand_avg_miss_latency 137805.458998 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85801.866235 # average overall mshr miss latency system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5750809804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5750621804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate 1 # miss rate for demand accesses system.iocache.demand_misses 41730 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3580698934 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3580511878 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 41730 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.overall_accesses 41730 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 137809.964150 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85806.348766 # average overall mshr miss latency +system.iocache.overall_avg_miss_latency 137805.458998 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85801.866235 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 5750809804 # number of overall miss cycles +system.iocache.overall_miss_latency 5750621804 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses system.iocache.overall_misses 41730 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3580698934 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3580511878 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 41730 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -609,80 +609,80 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 system.iocache.replacements 41698 # number of replacements system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.582076 # Cycle average of tags in use +system.iocache.tagsinuse 0.582075 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1762323729000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1762323389000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses 306796 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52002.653229 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40002.653229 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15954206000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_accesses 306814 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52002.656333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40002.656333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15955143000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 306796 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12272654000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses 306814 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12273375000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 306796 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2090247 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52016.274350 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40016.322096 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 306814 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2090305 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52016.275832 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.323583 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1782800 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 15992247500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.147086 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 307447 # number of ReadReq misses +system.l2c.ReadReq_hits 1782886 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 15990791500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.147069 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 307419 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12302458000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.147081 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 307436 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 789200000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 127300 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 50741.146897 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40004.988217 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 6459348000 # number of UpgradeReq miss cycles +system.l2c.ReadReq_mshr_miss_latency 12301338000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.147064 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 307408 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 802543000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 127238 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 50741.170091 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.242145 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6456205000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 127300 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5092635000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses 127238 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5090187000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 127300 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 127238 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1381237000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430395 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 430395 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1394774000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 430351 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 430351 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 4.558799 # Average number of references to valid blocks. +system.l2c.avg_refs 4.554189 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2397043 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52009.471007 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40009.494784 # average overall mshr miss latency -system.l2c.demand_hits 1782800 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31946453500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.256250 # miss rate for demand accesses -system.l2c.demand_misses 614243 # number of demand (read+write) misses +system.l2c.demand_accesses 2397119 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52009.472790 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40009.496566 # average overall mshr miss latency +system.l2c.demand_hits 1782886 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31945934500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.256238 # miss rate for demand accesses +system.l2c.demand_misses 614233 # number of demand (read+write) misses system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24575112000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.256246 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 614232 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 24574713000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.256233 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 614222 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2397043 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52009.471007 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40009.494784 # average overall mshr miss latency +system.l2c.overall_accesses 2397119 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52009.472790 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40009.496566 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1782800 # number of overall hits -system.l2c.overall_miss_latency 31946453500 # number of overall miss cycles -system.l2c.overall_miss_rate 0.256250 # miss rate for overall accesses -system.l2c.overall_misses 614243 # number of overall misses +system.l2c.overall_hits 1782886 # number of overall hits +system.l2c.overall_miss_latency 31945934500 # number of overall miss cycles +system.l2c.overall_miss_rate 0.256238 # miss rate for overall accesses +system.l2c.overall_misses 614233 # number of overall misses system.l2c.overall_mshr_hits 11 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24575112000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.256246 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 614232 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2170437000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 24574713000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.256233 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 614222 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2197317000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -693,13 +693,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 399043 # number of replacements -system.l2c.sampled_refs 430765 # Sample count of references to valid blocks. +system.l2c.replacements 399005 # number of replacements +system.l2c.sampled_refs 430732 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30865.823052 # Cycle average of tags in use -system.l2c.total_refs 1963771 # Total number of references to valid blocks. +system.l2c.tagsinuse 30859.505450 # Cycle average of tags in use +system.l2c.total_refs 1961635 # Total number of references to valid blocks. system.l2c.warmup_cycle 10912833000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 123178 # number of writebacks +system.l2c.writebacks 123162 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal index 6974143c8..7399f4d84 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal @@ -61,6 +61,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
loop: loaded (max 8 devices)
nbd: registered device at major 43
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. +
PCI: Setting latency timer of device 0000:00:01.0 to 64
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
eth0: enabling optical transceiver
eth0: using 64 bit addressing. @@ -72,6 +73,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
PIIX4: IDE controller at PCI slot 0000:00:00.0
PIIX4: chipset revision 0
PIIX4: 100% native mode on irq 31 +
PCI: Setting latency timer of device 0000:00:00.0 to 64
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
hda: M5 IDE Disk, ATA DISK drive diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index b4ba00cf0..b196d52a3 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:30:58 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:37:43 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing +M5 compiled Dec 14 2008 21:47:07 +M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141 +M5 commit date Sun Dec 14 21:45:15 2008 -0800 +M5 started Dec 14 2008 21:47:59 +M5 executing on tater +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1930165791000 because m5_exit instruction encountered +Exiting @ tick 1930164593000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index bcad4cd62..76e60eed0 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,92 +1,92 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1283720 # Simulator instruction rate (inst/s) -host_mem_usage 286560 # Number of bytes of host memory used -host_seconds 43.75 # Real time elapsed on the host -host_tick_rate 44115985890 # Simulator tick rate (ticks/s) +host_inst_rate 715830 # Simulator instruction rate (inst/s) +host_mem_usage 287924 # Number of bytes of host memory used +host_seconds 78.52 # Real time elapsed on the host +host_tick_rate 24582295405 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 56165112 # Number of instructions simulated -sim_seconds 1.930166 # Number of seconds simulated -sim_ticks 1930165791000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses 200388 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 14361.212121 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.212121 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits 183063 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 248808000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.086457 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 17325 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196833000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086457 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17325 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 8882666 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 25452.857499 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.814515 # average ReadReq mshr miss latency +sim_insts 56205703 # Number of instructions simulated +sim_seconds 1.930165 # Number of seconds simulated +sim_ticks 1930164593000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses 200404 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 14361.546017 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.546017 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits 183095 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 248584000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.086371 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 17309 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196657000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086371 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_misses 17309 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses 8888653 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 25452.354477 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.311493 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits 7812517 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 27238350000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.120476 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1070149 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24027857000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.120476 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1070149 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 847845000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses 199368 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency 56004.365794 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.365794 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits 169362 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 1680467000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate 0.150506 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses 30006 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590449000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150506 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 30006 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6158164 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56004.032630 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.032630 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_hits 7818479 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 27238448000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.120398 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1070174 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 24027880000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.120398 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1070174 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 862763000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses 199383 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency 56004.366085 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.366085 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits 169379 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 1680355000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate 0.150484 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses 30004 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590343000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150484 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_misses 30004 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6160337 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56004.022652 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.022652 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits 5757309 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 22449496500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.065093 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits 5759482 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 22449492500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.065070 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 400855 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 21246931500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.065093 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_latency 21246927500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.065070 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1186275000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1201243500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 10.091593 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 10.097318 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15040830 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 33778.185851 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 30778.154580 # average overall mshr miss latency -system.cpu.dcache.demand_hits 13569826 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 49687846500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.097801 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1471004 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 15048990 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 33777.675695 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency +system.cpu.dcache.demand_hits 13577961 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 49687940500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.097749 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1471029 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 45274788500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.097801 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1471004 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 45274807500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.097749 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1471029 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15040830 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 33778.185851 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 30778.154580 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 15048990 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 33777.675695 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 13569826 # number of overall hits -system.cpu.dcache.overall_miss_latency 49687846500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.097801 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1471004 # number of overall misses +system.cpu.dcache.overall_hits 13577961 # number of overall hits +system.cpu.dcache.overall_miss_latency 49687940500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.097749 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1471029 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 45274788500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.097801 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1471004 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2034120000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_miss_latency 45274807500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.097749 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1471029 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2064006500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -97,69 +97,69 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 1391586 # number of replacements -system.cpu.dcache.sampled_refs 1392098 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1391606 # number of replacements +system.cpu.dcache.sampled_refs 1392118 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.984141 # Cycle average of tags in use -system.cpu.dcache.total_refs 14048487 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.984142 # Cycle average of tags in use +system.cpu.dcache.total_refs 14056658 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 84139000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 430461 # number of writebacks +system.cpu.dcache.writebacks 430459 # number of writebacks system.cpu.dtb.accesses 1020784 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 15421361 # DTB hits +system.cpu.dtb.hits 15429793 # DTB hits system.cpu.dtb.misses 11466 # DTB misses system.cpu.dtb.read_accesses 728853 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9063577 # DTB read hits +system.cpu.dtb.read_hits 9069700 # DTB read hits system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6357784 # DTB write hits +system.cpu.dtb.write_hits 6360093 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses 56176946 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 14711.628674 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.898216 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 55246023 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13695393500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.016571 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 930923 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 10901944500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.016571 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 930923 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 56217537 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 14711.221983 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.491665 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 55286436 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13697633500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.016562 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 931101 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 10903650500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.016562 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 931101 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 59.355692 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 59.387754 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 56176946 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 14711.628674 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11710.898216 # average overall mshr miss latency -system.cpu.icache.demand_hits 55246023 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13695393500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.016571 # miss rate for demand accesses -system.cpu.icache.demand_misses 930923 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 56217537 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 14711.221983 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency +system.cpu.icache.demand_hits 55286436 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13697633500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.016562 # miss rate for demand accesses +system.cpu.icache.demand_misses 931101 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10901944500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.016571 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 930923 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 10903650500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.016562 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 931101 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 56176946 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 14711.628674 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11710.898216 # average overall mshr miss latency +system.cpu.icache.overall_accesses 56217537 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 14711.221983 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 55246023 # number of overall hits -system.cpu.icache.overall_miss_latency 13695393500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.016571 # miss rate for overall accesses -system.cpu.icache.overall_misses 930923 # number of overall misses +system.cpu.icache.overall_hits 55286436 # number of overall hits +system.cpu.icache.overall_miss_latency 13697633500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.016562 # miss rate for overall accesses +system.cpu.icache.overall_misses 931101 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10901944500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.016571 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 930923 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 10903650500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.016562 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 931101 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -171,19 +171,19 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 930251 # number of replacements -system.cpu.icache.sampled_refs 930762 # Sample count of references to valid blocks. +system.cpu.icache.replacements 930429 # number of replacements +system.cpu.icache.sampled_refs 930940 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 508.559731 # Cycle average of tags in use -system.cpu.icache.total_refs 55246023 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 508.559728 # Cycle average of tags in use +system.cpu.icache.total_refs 55286436 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 39055604000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0.929251 # Percentage of idle cycles -system.cpu.itb.accesses 4982832 # ITB accesses +system.cpu.idle_fraction 0.929209 # Percentage of idle cycles +system.cpu.itb.accesses 4982987 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4977822 # ITB hits +system.cpu.itb.hits 4977977 # ITB hits system.cpu.itb.misses 5010 # ITB misses -system.cpu.kern.callpal 193204 # number of callpals executed +system.cpu.kern.callpal 193221 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed @@ -191,7 +191,7 @@ system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal_swpctx 4171 2.16% 2.16% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.19% # number of callpals executed -system.cpu.kern.callpal_swpipl 176240 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal_swpipl 176257 91.22% 93.41% # number of callpals executed system.cpu.kern.callpal_rdps 6844 3.54% 96.95% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed @@ -201,40 +201,40 @@ system.cpu.kern.callpal_rti 5169 2.68% 99.64% # nu system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 212308 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6258 # number of quiesce instructions executed -system.cpu.kern.ipl_count 183485 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 74993 40.87% 40.87% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 212325 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183502 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 75001 40.87% 40.87% # number of times we switched to this ipl system.cpu.kern.ipl_count_21 131 0.07% 40.94% # number of times we switched to this ipl system.cpu.kern.ipl_count_22 1944 1.06% 42.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 106417 58.00% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149327 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73626 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count_31 106426 58.00% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149343 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73634 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_22 1944 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73626 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1930165033000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1867007591000 96.73% 96.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 96059500 0.00% 96.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 565327500 0.03% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 62496055000 3.24% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used_0 0.981772 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good_31 73634 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1930163835000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1866810523000 96.72% 96.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 96331500 0.00% 96.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 565310500 0.03% 96.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 62691670000 3.25% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981774 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.691863 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1910 -system.cpu.kern.mode_good_user 1743 +system.cpu.kern.ipl_used_31 0.691880 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1911 +system.cpu.kern.mode_good_user 1744 system.cpu.kern.mode_good_idle 167 system.cpu.kern.mode_switch_kernel 5917 # number of protection mode switches -system.cpu.kern.mode_switch_user 1743 # number of protection mode switches +system.cpu.kern.mode_switch_user 1744 # number of protection mode switches system.cpu.kern.mode_switch_idle 2089 # number of protection mode switches -system.cpu.kern.mode_switch_good 1.402741 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.322799 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good 1.402910 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.322968 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_idle 0.079943 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 48448667000 2.51% 2.51% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 5540662000 0.29% 2.80% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1876175702000 97.20% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_kernel 48447088000 2.51% 2.51% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 5539986000 0.29% 2.80% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1876176759000 97.20% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4172 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed @@ -267,10 +267,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.070749 # Percentage of non-idle cycles -system.cpu.numCycles 3860331582 # number of cpu cycles simulated -system.cpu.num_insts 56165112 # Number of instructions executed -system.cpu.num_refs 15669461 # Number of memory references +system.cpu.not_idle_fraction 0.070791 # Percentage of non-idle cycles +system.cpu.numCycles 3860329186 # number of cpu cycles simulated +system.cpu.num_insts 56205703 # Number of instructions executed +system.cpu.num_refs 15677891 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -293,46 +293,46 @@ system.iocache.ReadReq_mshr_miss_latency 10942998 # nu system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 137880.578697 # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85877.091981 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5729213806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_miss_latency 137876.559636 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85873.072921 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5729046806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3568364926 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3568197926 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 6163.865928 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_mshrs 6163.674943 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked_no_mshrs 10472 # number of cycles access was blocked system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 64548004 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64546004 # number of cycles access was blocked system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses 41725 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 137786.765824 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85783.293565 # average overall mshr miss latency +system.iocache.demand_avg_miss_latency 137782.763427 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5749152804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5748985804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate 1 # miss rate for demand accesses system.iocache.demand_misses 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3579307924 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3579140924 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.overall_accesses 41725 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 137786.765824 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85783.293565 # average overall mshr miss latency +system.iocache.overall_avg_miss_latency 137782.763427 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 5749152804 # number of overall miss cycles +system.iocache.overall_miss_latency 5748985804 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses system.iocache.overall_misses 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3579307924 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3579140924 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -349,79 +349,79 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.353410 # Cycle average of tags in use +system.iocache.tagsinuse 1.353399 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1762299198000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1762299470000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 304625 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52003.272876 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40003.272876 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15841497000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_accesses 304636 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52003.289171 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40003.289171 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15842074000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 304625 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12185997000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses 304636 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12186442000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 304625 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2018377 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52016.376522 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40016.358642 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 304636 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2018564 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52016.377161 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.359280 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1710772 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16000497500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.152402 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 307605 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 12309232000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.152402 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 307605 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 759315000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 126236 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 52001.881397 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.980861 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 6564509500 # number of UpgradeReq miss cycles +system.l2c.ReadReq_hits 1710971 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 15999873500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.152382 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 307593 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 12308752000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.152382 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 307593 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 772673000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 126223 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 52001.810288 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.910175 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6563824500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 126236 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5050195000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses 126223 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5049666000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 126236 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 126223 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1071771000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430461 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 430461 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1085299500 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 430459 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 430459 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 4.436452 # Average number of references to valid blocks. +system.l2c.avg_refs 4.436562 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2323002 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52009.856590 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40009.847606 # average overall mshr miss latency -system.l2c.demand_hits 1710772 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31841994500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.263551 # miss rate for demand accesses -system.l2c.demand_misses 612230 # number of demand (read+write) misses +system.l2c.demand_accesses 2323200 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52009.864773 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency +system.l2c.demand_hits 1710971 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31841947500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.263528 # miss rate for demand accesses +system.l2c.demand_misses 612229 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24495229000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.263551 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 612230 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 24495194000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.263528 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 612229 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2323002 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52009.856590 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40009.847606 # average overall mshr miss latency +system.l2c.overall_accesses 2323200 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52009.864773 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1710772 # number of overall hits -system.l2c.overall_miss_latency 31841994500 # number of overall miss cycles -system.l2c.overall_miss_rate 0.263551 # miss rate for overall accesses -system.l2c.overall_misses 612230 # number of overall misses +system.l2c.overall_hits 1710971 # number of overall hits +system.l2c.overall_miss_latency 31841947500 # number of overall miss cycles +system.l2c.overall_miss_rate 0.263528 # miss rate for overall accesses +system.l2c.overall_misses 612229 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24495229000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.263551 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 612230 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1831086000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 24495194000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.263528 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 612229 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1857972500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -432,13 +432,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 394925 # number of replacements -system.l2c.sampled_refs 425907 # Sample count of references to valid blocks. +system.l2c.replacements 394928 # number of replacements +system.l2c.sampled_refs 425903 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30594.024615 # Cycle average of tags in use -system.l2c.total_refs 1889516 # Total number of references to valid blocks. +system.l2c.tagsinuse 30591.543942 # Cycle average of tags in use +system.l2c.total_refs 1889545 # Total number of references to valid blocks. system.l2c.warmup_cycle 6968733000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119047 # number of writebacks +system.l2c.writebacks 119060 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal index 3efa225a8..ff644ed3f 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal @@ -56,6 +56,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
loop: loaded (max 8 devices)
nbd: registered device at major 43
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. +
PCI: Setting latency timer of device 0000:00:01.0 to 64
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
eth0: enabling optical transceiver
eth0: using 64 bit addressing. @@ -67,6 +68,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
PIIX4: IDE controller at PCI slot 0000:00:00.0
PIIX4: chipset revision 0
PIIX4: 100% native mode on irq 31 +
PCI: Setting latency timer of device 0000:00:00.0 to 64
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
hda: M5 IDE Disk, ATA DISK drive diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index 3e554a663..3bf761d34 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/z/hsul/work/m5/m5-tls/configs/boot/netperf-server.rcS +readfile=/home/gblack/m5/repos/m5.x86fs/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -703,7 +703,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/z/hsul/work/m5/m5-tls/configs/boot/netperf-stream-client.rcS +readfile=/home/gblack/m5/repos/m5.x86fs/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal index 89c68d228..5501b27d6 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal @@ -55,6 +55,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
loop: loaded (max 8 devices)
nbd: registered device at major 43
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. +
PCI: Setting latency timer of device 0000:00:01.0 to 64
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
eth0: enabling optical transceiver
eth0: using 64 bit addressing. @@ -66,6 +67,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
PIIX4: IDE controller at PCI slot 0000:00:00.0
PIIX4: chipset revision 0
PIIX4: 100% native mode on irq 31 +
PCI: Setting latency timer of device 0000:00:00.0 to 64
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
hda: M5 IDE Disk, ATA DISK drive diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout index b7a61e7b4..361a090ba 100755 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:30:58 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:38:27 -M5 executing on zizzer -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic +M5 compiled Dec 14 2008 21:47:07 +M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141 +M5 commit date Sun Dec 14 21:45:15 2008 -0800 +M5 started Dec 14 2008 21:48:20 +M5 executing on tater +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Exiting @ tick 4300236804024 because checkpoint diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index 3a06809c5..80d312c00 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -139,12 +139,12 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 200792296 # Simulator instruction rate (inst/s) -host_mem_usage 476644 # Number of bytes of host memory used -host_seconds 1.36 # Real time elapsed on the host -host_tick_rate 146922204609 # Simulator tick rate (ticks/s) +host_inst_rate 184651715 # Simulator instruction rate (inst/s) +host_mem_usage 478008 # Number of bytes of host memory used +host_seconds 1.48 # Real time elapsed on the host +host_tick_rate 135077074315 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 273294177 # Number of instructions simulated +sim_insts 273374833 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated sim_ticks 200000789468 # Number of ticks simulated testsys.cpu.dtb.accesses 335402 # DTB accesses @@ -381,12 +381,12 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 214516622449 # Simulator instruction rate (inst/s) -host_mem_usage 476644 # Number of bytes of host memory used +host_inst_rate 161951915284 # Simulator instruction rate (inst/s) +host_mem_usage 478008 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 582637509 # Simulator tick rate (ticks/s) +host_tick_rate 438603795 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 273294177 # Number of instructions simulated +sim_insts 273374833 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated sim_ticks 785978 # Number of ticks simulated testsys.cpu.dtb.accesses 0 # DTB accesses diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal index c1cb6aad0..ecae2497e 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal @@ -55,6 +55,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
loop: loaded (max 8 devices)
nbd: registered device at major 43
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. +
PCI: Setting latency timer of device 0000:00:01.0 to 64
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
eth0: enabling optical transceiver
eth0: using 64 bit addressing. @@ -66,6 +67,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
PIIX4: IDE controller at PCI slot 0000:00:00.0
PIIX4: chipset revision 0
PIIX4: 100% native mode on irq 31 +
PCI: Setting latency timer of device 0000:00:00.0 to 64
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
hda: M5 IDE Disk, ATA DISK drive |