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-rw-r--r--tests/configs/inorder-timing.py2
-rw-r--r--tests/configs/memtest-ruby.py4
-rw-r--r--tests/configs/memtest.py4
-rw-r--r--tests/configs/o3-timing-checker.py2
-rw-r--r--tests/configs/o3-timing-mp.py3
-rw-r--r--tests/configs/o3-timing.py2
-rw-r--r--tests/configs/rubytest-ruby.py2
-rw-r--r--tests/configs/simple-atomic-dummychecker.py2
-rw-r--r--tests/configs/simple-atomic-mp.py5
-rw-r--r--tests/configs/simple-atomic.py2
-rw-r--r--tests/configs/simple-timing-mp-ruby.py2
-rw-r--r--tests/configs/simple-timing-mp.py3
-rw-r--r--tests/configs/simple-timing-ruby.py2
-rw-r--r--tests/configs/simple-timing.py2
14 files changed, 18 insertions, 19 deletions
diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index d6a456083..ea9c37ef9 100644
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -48,7 +48,7 @@ cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
cpu.clock = '2GHz'
system = System(cpu = cpu,
- physmem = PhysicalMemory(),
+ physmem = SimpleMemory(),
membus = Bus())
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index c69e1bf00..e668ef9ba 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -77,8 +77,8 @@ options.num_cpus = nb_cores
# system simulated
system = System(cpu = cpus,
- funcmem = PhysicalMemory(),
- physmem = PhysicalMemory())
+ funcmem = SimpleMemory(in_addr_map = False),
+ physmem = SimpleMemory())
Ruby.create_system(options, system)
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 6fface748..9876c07b9 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -56,8 +56,8 @@ nb_cores = 8
cpus = [ MemTest() for i in xrange(nb_cores) ]
# system simulated
-system = System(cpu = cpus, funcmem = PhysicalMemory(),
- physmem = PhysicalMemory(),
+system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
+ physmem = SimpleMemory(),
membus = Bus(clock="500GHz", width=16))
# l2cache & bus
diff --git a/tests/configs/o3-timing-checker.py b/tests/configs/o3-timing-checker.py
index dd68a39d7..68429de04 100644
--- a/tests/configs/o3-timing-checker.py
+++ b/tests/configs/o3-timing-checker.py
@@ -59,7 +59,7 @@ cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
cpu.clock = '2GHz'
system = System(cpu = cpu,
- physmem = PhysicalMemory(),
+ physmem = SimpleMemory(),
membus = Bus())
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 1a0718fa8..ee0f29570 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -56,8 +56,7 @@ nb_cores = 4
cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
# system simulated
-system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
-Bus())
+system = System(cpu = cpus, physmem = SimpleMemory(), membus = Bus())
# l2cache & bus
system.toL2Bus = Bus()
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 82a73a6aa..732cd2d43 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -48,7 +48,7 @@ cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
cpu.clock = '2GHz'
system = System(cpu = cpu,
- physmem = PhysicalMemory(),
+ physmem = SimpleMemory(),
membus = Bus())
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index 70deb2958..7bb7b9014 100644
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -70,7 +70,7 @@ options.l3_assoc=2
#
tester = RubyTester(checks_to_complete = 100, wakeup_frequency = 10)
-system = System(tester = tester, physmem = PhysicalMemory())
+system = System(tester = tester, physmem = SimpleMemory())
Ruby.create_system(options, system)
diff --git a/tests/configs/simple-atomic-dummychecker.py b/tests/configs/simple-atomic-dummychecker.py
index 15c287130..2e672924d 100644
--- a/tests/configs/simple-atomic-dummychecker.py
+++ b/tests/configs/simple-atomic-dummychecker.py
@@ -39,7 +39,7 @@ import m5
from m5.objects import *
system = System(cpu = AtomicSimpleCPU(cpu_id=0),
- physmem = PhysicalMemory(),
+ physmem = SimpleMemory(),
membus = Bus())
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index 376d5ee27..af9f3bc09 100644
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -55,8 +55,9 @@ nb_cores = 4
cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
# system simulated
-system = System(cpu = cpus, physmem = PhysicalMemory(range = AddrRange('1024MB')), membus =
-Bus())
+system = System(cpu = cpus,
+ physmem = SimpleMemory(range = AddrRange('1024MB')),
+ membus = Bus())
# l2cache & bus
system.toL2Bus = Bus()
diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py
index 4d3fb6580..b1aa31d80 100644
--- a/tests/configs/simple-atomic.py
+++ b/tests/configs/simple-atomic.py
@@ -30,7 +30,7 @@ import m5
from m5.objects import *
system = System(cpu = AtomicSimpleCPU(cpu_id=0),
- physmem = PhysicalMemory(),
+ physmem = SimpleMemory(),
membus = Bus())
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py
index d2f11abce..4447967a7 100644
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -70,7 +70,7 @@ cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
options.num_cpus = nb_cores
# system simulated
-system = System(cpu = cpus, physmem = PhysicalMemory())
+system = System(cpu = cpus, physmem = SimpleMemory())
Ruby.create_system(options, system)
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index f898797bb..5bb0194aa 100644
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -55,8 +55,7 @@ nb_cores = 4
cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
# system simulated
-system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
-Bus())
+system = System(cpu = cpus, physmem = SimpleMemory(), membus = Bus())
# l2cache & bus
system.toL2Bus = Bus()
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index 19e827c80..1a983510a 100644
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -66,7 +66,7 @@ options.l3_assoc=2
options.num_cpus = 1
cpu = TimingSimpleCPU(cpu_id=0)
-system = System(cpu = cpu, physmem = PhysicalMemory())
+system = System(cpu = cpu, physmem = SimpleMemory())
Ruby.create_system(options, system)
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index cd6bee863..5269f4127 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -44,7 +44,7 @@ cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
MyL1Cache(size = '256kB'),
MyCache(size = '2MB', latency='10ns'))
system = System(cpu = cpu,
- physmem = PhysicalMemory(),
+ physmem = SimpleMemory(),
membus = Bus())
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 15:10:02 +0000