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-rw-r--r--tests/SConscript3
-rw-r--r--tests/configs/base_config.py16
-rw-r--r--tests/configs/pc-switcheroo-full.py50
-rw-r--r--tests/configs/x86_generic.py8
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini1594
-rwxr-xr-xtests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr15
-rwxr-xr-xtests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout12
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt1332
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal137
9 files changed, 3157 insertions, 10 deletions
diff --git a/tests/SConscript b/tests/SConscript
index 2faa3216c..0676ee300 100644
--- a/tests/SConscript
+++ b/tests/SConscript
@@ -323,7 +323,8 @@ if env['TARGET_ISA'] == 'arm':
if env['TARGET_ISA'] == 'x86':
configs += ['pc-simple-atomic',
'pc-simple-timing',
- 'pc-o3-timing']
+ 'pc-o3-timing',
+ 'pc-switcheroo-full']
configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest',
'simple-atomic-mp', 'simple-timing-mp', 'o3-timing-mp',
diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py
index b4c400a45..29aec35e7 100644
--- a/tests/configs/base_config.py
+++ b/tests/configs/base_config.py
@@ -104,14 +104,18 @@ class BaseSystem(object):
system.l2c.mem_side = system.membus.slave
return system.toL2Bus
- def init_cpu(self, system, cpu):
+ def init_cpu(self, system, cpu, sha_bus):
"""Initialize a CPU.
Arguments:
system -- System to work on.
cpu -- CPU to initialize.
"""
- cpu.createInterruptController()
+ if not cpu.switched_out:
+ self.create_caches_private(cpu)
+ cpu.createInterruptController()
+ cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
+ system.membus)
def init_kvm(self, system):
"""Do KVM-specific system initialization.
@@ -135,13 +139,7 @@ class BaseSystem(object):
sha_bus = self.create_caches_shared(system)
for cpu in system.cpu:
- if not cpu.switched_out:
- self.create_caches_private(cpu)
- self.init_cpu(system, cpu)
- cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
- system.membus)
- else:
- self.init_cpu(system, cpu)
+ self.init_cpu(system, cpu, sha_bus)
@abstractmethod
def create_system(self):
diff --git a/tests/configs/pc-switcheroo-full.py b/tests/configs/pc-switcheroo-full.py
new file mode 100644
index 000000000..c94987638
--- /dev/null
+++ b/tests/configs/pc-switcheroo-full.py
@@ -0,0 +1,50 @@
+# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2013 Mark D. Hill and David A. Wood
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+# Nilay Vaish
+
+from m5.objects import *
+from x86_generic import *
+import switcheroo
+
+root = LinuxX86FSSwitcheroo(
+ cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU)
+ ).create_root()
+
+# Setup a custom test method that uses the switcheroo tester that
+# switches between CPU models.
+run_test = switcheroo.run_test
diff --git a/tests/configs/x86_generic.py b/tests/configs/x86_generic.py
index e9e7bff63..9a499cc60 100644
--- a/tests/configs/x86_generic.py
+++ b/tests/configs/x86_generic.py
@@ -107,3 +107,11 @@ class LinuxX86FSSystemUniprocessor(LinuxX86SystemBuilder,
L2Cache(size='4MB', assoc=8),
PageTableWalkerCache(),
PageTableWalkerCache())
+
+
+class LinuxX86FSSwitcheroo(LinuxX86SystemBuilder, BaseFSSwitcheroo):
+ """Uniprocessor X86 system prepared for CPU switching"""
+
+ def __init__(self, **kwargs):
+ BaseFSSwitcheroo.__init__(self, **kwargs)
+ LinuxX86SystemBuilder.__init__(self)
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
new file mode 100644
index 000000000..2c35efbdd
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
@@ -0,0 +1,1594 @@
+[root]
+type=Root
+children=system
+full_system=true
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxX86System
+children=acpi_description_table_pointer apicbridge bridge cpu0 cpu1 cpu2 e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
+acpi_description_table_pointer=system.acpi_description_table_pointer
+boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
+clock=1000
+e820_table=system.e820_table
+init_param=0
+intel_mp_pointer=system.intel_mp_pointer
+intel_mp_table=system.intel_mp_table
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+load_addr_mask=18446744073709551615
+mem_mode=atomic
+mem_ranges=0:134217727
+memories=system.physmem
+num_work_ids=16
+readfile=tests/halt.sh
+smbios_table=system.smbios_table
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.acpi_description_table_pointer]
+type=X86ACPIRSDP
+children=xsdt
+oem_id=
+revision=2
+rsdt=Null
+xsdt=system.acpi_description_table_pointer.xsdt
+
+[system.acpi_description_table_pointer.xsdt]
+type=X86ACPIXSDT
+creator_id=
+creator_revision=0
+entries=
+oem_id=
+oem_revision=0
+oem_table_id=
+
+[system.apicbridge]
+type=Bridge
+clock=1000
+delay=50000
+ranges=11529215046068469760:11529215046068473855
+req_size=16
+resp_size=16
+master=system.membus.slave[0]
+slave=system.iobus.master[0]
+
+[system.bridge]
+type=Bridge
+clock=1000
+delay=50000
+ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[1]
+
+[system.cpu0]
+type=AtomicSimpleCPU
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
+checker=Null
+clock=500
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu0.dtb
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+switched_out=false
+system=system
+tracer=system.cpu0.tracer
+width=1
+workload=
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=4
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu0.dtb]
+type=X86TLB
+children=walker
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
+type=X86PagetableWalker
+clock=500
+system=system
+port=system.toL2Bus.slave[3]
+
+[system.cpu0.icache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=1
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.interrupts]
+type=X86LocalApic
+clock=8000
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=100000
+system=system
+int_master=system.membus.slave[3]
+int_slave=system.membus.master[3]
+pio=system.membus.master[2]
+
+[system.cpu0.isa]
+type=X86ISA
+
+[system.cpu0.itb]
+type=X86TLB
+children=walker
+size=64
+walker=system.cpu0.itb.walker
+
+[system.cpu0.itb.walker]
+type=X86PagetableWalker
+clock=500
+system=system
+port=system.toL2Bus.slave[2]
+
+[system.cpu0.tracer]
+type=ExeTracer
+
+[system.cpu1]
+type=TimingSimpleCPU
+children=dtb isa itb tracer
+branchPred=Null
+checker=Null
+clock=500
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu1.dtb
+function_trace=false
+function_trace_start=0
+interrupts=Null
+isa=system.cpu1.isa
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+switched_out=true
+system=system
+tracer=system.cpu1.tracer
+workload=
+
+[system.cpu1.dtb]
+type=X86TLB
+children=walker
+size=64
+walker=system.cpu1.dtb.walker
+
+[system.cpu1.dtb.walker]
+type=X86PagetableWalker
+clock=500
+system=system
+
+[system.cpu1.isa]
+type=X86ISA
+
+[system.cpu1.itb]
+type=X86TLB
+children=walker
+size=64
+walker=system.cpu1.itb.walker
+
+[system.cpu1.itb.walker]
+type=X86PagetableWalker
+clock=500
+system=system
+
+[system.cpu1.tracer]
+type=ExeTracer
+
+[system.cpu2]
+type=DerivO3CPU
+children=branchPred dtb fuPool isa itb tracer
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+branchPred=system.cpu2.branchPred
+cachePorts=200
+checker=Null
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+dispatchWidth=8
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu2.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu2.fuPool
+function_trace=false
+function_trace_start=0
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+interrupts=Null
+isa=system.cpu2.isa
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu2.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+needsTSO=true
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+profile=0
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+simpoint_start_insts=
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+switched_out=true
+system=system
+tracer=system.cpu2.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=
+
+[system.cpu2.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
+[system.cpu2.dtb]
+type=X86TLB
+children=walker
+size=64
+walker=system.cpu2.dtb.walker
+
+[system.cpu2.dtb.walker]
+type=X86PagetableWalker
+clock=500
+system=system
+
+[system.cpu2.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
+
+[system.cpu2.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu2.fuPool.FUList0.opList
+
+[system.cpu2.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu2.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
+
+[system.cpu2.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu2.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu2.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2
+
+[system.cpu2.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu2.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu2.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu2.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
+
+[system.cpu2.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu2.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu2.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu2.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu2.fuPool.FUList4.opList
+
+[system.cpu2.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu2.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
+
+[system.cpu2.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu2.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu2.fuPool.FUList6.opList
+
+[system.cpu2.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu2.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
+
+[system.cpu2.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu2.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu2.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu2.fuPool.FUList8.opList
+
+[system.cpu2.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu2.isa]
+type=X86ISA
+
+[system.cpu2.itb]
+type=X86TLB
+children=walker
+size=64
+walker=system.cpu2.itb.walker
+
+[system.cpu2.itb.walker]
+type=X86PagetableWalker
+clock=500
+system=system
+
+[system.cpu2.tracer]
+type=ExeTracer
+
+[system.e820_table]
+type=X86E820Table
+children=entries0 entries1 entries2
+entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2
+
+[system.e820_table.entries0]
+type=X86E820Entry
+addr=0
+range_type=1
+size=654336
+
+[system.e820_table.entries1]
+type=X86E820Entry
+addr=654336
+range_type=2
+size=394240
+
+[system.e820_table.entries2]
+type=X86E820Entry
+addr=1048576
+range_type=1
+size=133169152
+
+[system.intel_mp_pointer]
+type=X86IntelMPFloatingPointer
+default_config=0
+imcr_present=true
+spec_rev=4
+
+[system.intel_mp_table]
+type=X86IntelMPConfigTable
+children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries
+base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32
+ext_entries=system.intel_mp_table.ext_entries
+local_apic=4276092928
+oem_id=
+oem_table_addr=0
+oem_table_size=0
+product_id=
+spec_rev=4
+
+[system.intel_mp_table.base_entries00]
+type=X86IntelMPProcessor
+bootstrap=true
+enable=true
+family=0
+feature_flags=0
+local_apic_id=0
+local_apic_version=20
+model=0
+stepping=0
+
+[system.intel_mp_table.base_entries01]
+type=X86IntelMPIOAPIC
+address=4273995776
+enable=true
+id=1
+version=17
+
+[system.intel_mp_table.base_entries02]
+type=X86IntelMPBus
+bus_id=0
+bus_type=ISA
+
+[system.intel_mp_table.base_entries03]
+type=X86IntelMPBus
+bus_id=1
+bus_type=PCI
+
+[system.intel_mp_table.base_entries04]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=16
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=1
+source_bus_irq=16
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries05]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=0
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries06]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=2
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=0
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries07]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=1
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries08]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=1
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=1
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries09]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=3
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries10]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=3
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=3
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries11]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
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+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=4
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries12]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=4
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=4
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries13]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
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+source_bus_id=0
+source_bus_irq=5
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries14]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
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+interrupt_type=INT
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+source_bus_id=0
+source_bus_irq=5
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries15]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
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+interrupt_type=ExtInt
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+source_bus_irq=6
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries16]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=6
+interrupt_type=INT
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+source_bus_irq=6
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries17]
+type=X86IntelMPIOIntAssignment
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+interrupt_type=ExtInt
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+source_bus_id=0
+source_bus_irq=7
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries18]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=7
+interrupt_type=INT
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+source_bus_id=0
+source_bus_irq=7
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries19]
+type=X86IntelMPIOIntAssignment
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+source_bus_irq=8
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries20]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=8
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=8
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries21]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=9
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries22]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=9
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=9
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries23]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
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+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=10
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries24]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=10
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=10
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries25]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=11
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries26]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=11
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=11
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries27]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=12
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries28]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=12
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=12
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries29]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=13
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries30]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=13
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=13
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries31]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
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+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=14
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries32]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
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+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=14
+trigger=ConformTrigger
+
+[system.intel_mp_table.ext_entries]
+type=X86IntelMPBusHierarchy
+bus_id=0
+parent_bus=1
+subtractive_decode=true
+
+[system.intrctrl]
+type=IntrControl
+sys=system
+
+[system.iobus]
+type=NoncoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=true
+width=8
+default=system.pc.pciconfig.pio
+master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
+slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
+
+[system.iocache]
+type=BaseCache
+addr_ranges=0:134217727
+assoc=8
+block_size=64
+clock=1000
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+size=1024
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[18]
+mem_side=system.membus.slave[4]
+
+[system.l2c]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=8
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+size=4194304
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.membus]
+type=CoherentBus
+children=badaddr_responder
+block_size=64
+clock=1000
+header_cycles=1
+system=system
+use_default_range=false
+width=8
+default=system.membus.badaddr_responder.pio
+master=system.physmem.port system.bridge.slave system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave
+slave=system.apicbridge.master system.system_port system.l2c.mem_side system.cpu0.interrupts.int_master system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.membus.default
+
+[system.pc]
+type=Pc
+children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal
+intrctrl=system.intrctrl
+system=system
+
+[system.pc.behind_pci]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=9223372036854779128
+pio_latency=100000
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+ret_bad_addr=false
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+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.pc.com_1]
+type=Uart8250
+children=terminal
+clock=1000
+pio_addr=9223372036854776824
+pio_latency=100000
+platform=system.pc
+system=system
+terminal=system.pc.com_1.terminal
+pio=system.iobus.master[13]
+
+[system.pc.com_1.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.pc.com_1.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.pc.fake_com_2]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=9223372036854776568
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+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[14]
+
+[system.pc.fake_com_3]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=9223372036854776808
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[15]
+
+[system.pc.fake_com_4]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=9223372036854776552
+pio_latency=100000
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+ret_bad_addr=false
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+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[16]
+
+[system.pc.fake_floppy]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=9223372036854776818
+pio_latency=100000
+pio_size=2
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[17]
+
+[system.pc.i_dont_exist]
+type=IsaFake
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+pio_addr=9223372036854775936
+pio_latency=100000
+pio_size=1
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[11]
+
+[system.pc.pciconfig]
+type=PciConfigAll
+bus=0
+clock=1000
+pio_latency=30000
+platform=system.pc
+size=16777216
+system=system
+pio=system.iobus.default
+
+[system.pc.south_bridge]
+type=SouthBridge
+children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
+cmos=system.pc.south_bridge.cmos
+dma1=system.pc.south_bridge.dma1
+io_apic=system.pc.south_bridge.io_apic
+keyboard=system.pc.south_bridge.keyboard
+pic1=system.pc.south_bridge.pic1
+pic2=system.pc.south_bridge.pic2
+pit=system.pc.south_bridge.pit
+platform=system.pc
+speaker=system.pc.south_bridge.speaker
+
+[system.pc.south_bridge.cmos]
+type=Cmos
+children=int_pin
+clock=1000
+int_pin=system.pc.south_bridge.cmos.int_pin
+pio_addr=9223372036854775920
+pio_latency=100000
+system=system
+time=Sun Jan 1 00:00:00 2012
+pio=system.iobus.master[1]
+
+[system.pc.south_bridge.cmos.int_pin]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.dma1]
+type=I8237
+clock=1000
+pio_addr=9223372036854775808
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.pc.south_bridge.ide]
+type=IdeController
+children=disks0 disks1
+BAR0=496
+BAR0LegacyIO=true
+BAR0Size=8
+BAR1=1012
+BAR1LegacyIO=true
+BAR1Size=3
+BAR2=368
+BAR2LegacyIO=true
+BAR2Size=8
+BAR3=884
+BAR3LegacyIO=true
+BAR3Size=3
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=14
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=128
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clock=1000
+config_latency=20000
+ctrl_offset=0
+disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
+io_shift=0
+pci_bus=0
+pci_dev=4
+pci_func=0
+pio_latency=30000
+platform=system.pc
+system=system
+config=system.iobus.master[4]
+dma=system.iobus.slave[1]
+pio=system.iobus.master[3]
+
+[system.pc.south_bridge.ide.disks0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.pc.south_bridge.ide.disks0.image
+
+[system.pc.south_bridge.ide.disks0.image]
+type=CowDiskImage
+children=child
+child=system.pc.south_bridge.ide.disks0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.pc.south_bridge.ide.disks0.image.child]
+type=RawDiskImage
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+read_only=true
+
+[system.pc.south_bridge.ide.disks1]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.pc.south_bridge.ide.disks1.image
+
+[system.pc.south_bridge.ide.disks1.image]
+type=CowDiskImage
+children=child
+child=system.pc.south_bridge.ide.disks1.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.pc.south_bridge.ide.disks1.image.child]
+type=RawDiskImage
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+read_only=true
+
+[system.pc.south_bridge.int_lines0]
+type=X86IntLine
+children=sink
+sink=system.pc.south_bridge.int_lines0.sink
+source=system.pc.south_bridge.pic1.output
+
+[system.pc.south_bridge.int_lines0.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.io_apic
+number=0
+
+[system.pc.south_bridge.int_lines1]
+type=X86IntLine
+children=sink
+sink=system.pc.south_bridge.int_lines1.sink
+source=system.pc.south_bridge.pic2.output
+
+[system.pc.south_bridge.int_lines1.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.pic1
+number=2
+
+[system.pc.south_bridge.int_lines2]
+type=X86IntLine
+children=sink
+sink=system.pc.south_bridge.int_lines2.sink
+source=system.pc.south_bridge.cmos.int_pin
+
+[system.pc.south_bridge.int_lines2.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.pic2
+number=0
+
+[system.pc.south_bridge.int_lines3]
+type=X86IntLine
+children=sink
+sink=system.pc.south_bridge.int_lines3.sink
+source=system.pc.south_bridge.pit.int_pin
+
+[system.pc.south_bridge.int_lines3.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.pic1
+number=0
+
+[system.pc.south_bridge.int_lines4]
+type=X86IntLine
+children=sink
+sink=system.pc.south_bridge.int_lines4.sink
+source=system.pc.south_bridge.pit.int_pin
+
+[system.pc.south_bridge.int_lines4.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.io_apic
+number=2
+
+[system.pc.south_bridge.int_lines5]
+type=X86IntLine
+children=sink
+sink=system.pc.south_bridge.int_lines5.sink
+source=system.pc.south_bridge.keyboard.keyboard_int_pin
+
+[system.pc.south_bridge.int_lines5.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.io_apic
+number=1
+
+[system.pc.south_bridge.int_lines6]
+type=X86IntLine
+children=sink
+sink=system.pc.south_bridge.int_lines6.sink
+source=system.pc.south_bridge.keyboard.mouse_int_pin
+
+[system.pc.south_bridge.int_lines6.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.io_apic
+number=12
+
+[system.pc.south_bridge.io_apic]
+type=I82094AA
+apic_id=1
+clock=1000
+external_int_pic=system.pc.south_bridge.pic1
+int_latency=1000
+pio_addr=4273995776
+pio_latency=100000
+system=system
+int_master=system.iobus.slave[2]
+pio=system.iobus.master[10]
+
+[system.pc.south_bridge.keyboard]
+type=I8042
+children=keyboard_int_pin mouse_int_pin
+clock=1000
+command_port=9223372036854775908
+data_port=9223372036854775904
+keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
+mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
+pio_addr=0
+pio_latency=100000
+system=system
+pio=system.iobus.master[5]
+
+[system.pc.south_bridge.keyboard.keyboard_int_pin]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.keyboard.mouse_int_pin]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.pic1]
+type=I8259
+children=output
+clock=1000
+mode=I8259Master
+output=system.pc.south_bridge.pic1.output
+pio_addr=9223372036854775840
+pio_latency=100000
+slave=system.pc.south_bridge.pic2
+system=system
+pio=system.iobus.master[6]
+
+[system.pc.south_bridge.pic1.output]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.pic2]
+type=I8259
+children=output
+clock=1000
+mode=I8259Slave
+output=system.pc.south_bridge.pic2.output
+pio_addr=9223372036854775968
+pio_latency=100000
+slave=Null
+system=system
+pio=system.iobus.master[7]
+
+[system.pc.south_bridge.pic2.output]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.pit]
+type=I8254
+children=int_pin
+clock=1000
+int_pin=system.pc.south_bridge.pit.int_pin
+pio_addr=9223372036854775872
+pio_latency=100000
+system=system
+pio=system.iobus.master[8]
+
+[system.pc.south_bridge.pit.int_pin]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.speaker]
+type=PcSpeaker
+clock=1000
+i8254=system.pc.south_bridge.pit
+pio_addr=9223372036854775905
+pio_latency=100000
+system=system
+pio=system.iobus.master[9]
+
+[system.physmem]
+type=SimpleDRAM
+activation_limit=4
+addr_mapping=RaBaChCo
+banks_per_rank=8
+channels=1
+clock=1000
+conf_table_reported=false
+in_addr_map=true
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
+null=false
+page_policy=open
+range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=5000
+tCL=13750
+tRCD=13750
+tREFI=7800000
+tRFC=300000
+tRP=13750
+tWTR=7500
+tXAW=40000
+write_buffer_size=32
+write_thresh_perc=70
+zero=false
+port=system.membus.master[0]
+
+[system.smbios_table]
+type=X86SMBiosSMBiosTable
+children=structures
+major_version=2
+minor_version=5
+structures=system.smbios_table.structures
+
+[system.smbios_table.structures]
+type=X86SMBiosBiosInformation
+characteristic_ext_bytes=
+characteristics=
+emb_cont_firmware_major=0
+emb_cont_firmware_minor=0
+major=0
+minor=0
+release_date=06/08/2008
+rom_size=0
+starting_addr_segment=0
+vendor=
+version=
+
+[system.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=500
+header_cycles=1
+system=system
+use_default_range=false
+width=8
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
new file mode 100755
index 000000000..56eeabc7e
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
@@ -0,0 +1,15 @@
+warn: add_child('terminal'): child 'terminal' already has parent
+warn: Sockets disabled, not accepting terminal connections
+warn: Reading current count from inactive timer.
+warn: Sockets disabled, not accepting gdb connections
+warn: Don't know what interrupt to clear for console.
+hack: be nice to actually delete the event here
+warn: x86 cpuid: unknown family 0xbacc
+warn: instruction 'fxsave' unimplemented
+warn: x86 cpuid: unknown family 0x8086
+warn: x86 cpuid: unknown family 0x8086
+warn: x86 cpuid: unimplemented function 8
+warn: x86 cpuid: unimplemented function 8
+warn: Tried to clear PCI interrupt 14
+warn: Unknown mouse command 0xe1.
+warn: instruction 'wbinvd' unimplemented
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
new file mode 100755
index 000000000..9d0993153
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
@@ -0,0 +1,12 @@
+Redirecting stdout to build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full/simout
+Redirecting stderr to build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Apr 22 2013 15:54:37
+gem5 started Apr 22 2013 16:25:06
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re tests/run.py build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
new file mode 100644
index 000000000..09ee5a401
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
@@ -0,0 +1,1332 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 5.133111 # Number of seconds simulated
+sim_ticks 5133110815000 # Number of ticks simulated
+final_tick 5133110815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 272926 # Simulator instruction rate (inst/s)
+host_op_rate 542191 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5733082021 # Simulator tick rate (ticks/s)
+host_mem_usage 964520 # Number of bytes of host memory used
+host_seconds 895.35 # Real time elapsed on the host
+sim_insts 244363664 # Number of instructions simulated
+sim_ops 485450482 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide 2484864 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 399872 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 5730880 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 105152 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 1659200 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 1216 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 489280 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 3010880 # Number of bytes read from this memory
+system.physmem.bytes_read::total 13881664 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 399872 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 105152 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 489280 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 994304 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9191104 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9191104 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 38826 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 6248 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 89545 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 1643 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 25925 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker 19 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 7645 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 47045 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 216901 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 143611 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 143611 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 484085 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 77901 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1116454 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 20485 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 323235 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker 237 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 95318 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 586560 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2704337 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 77901 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 20485 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 95318 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 193704 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1790552 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1790552 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1790552 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 484085 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 77901 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1116454 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 20485 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 323235 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker 237 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 95318 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 586560 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4494890 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 101193 # Total number of read requests seen
+system.physmem.writeReqs 78846 # Total number of write requests seen
+system.physmem.cpureqs 181047 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 6476352 # Total number of bytes read from memory
+system.physmem.bytesWritten 5046144 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 6476352 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 5046144 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 41 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 1005 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 6749 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 6143 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 6157 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 7514 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 6089 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 5671 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 5777 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 7080 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 6052 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 5601 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 5675 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 7038 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 5939 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 5837 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 6375 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 7455 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 5123 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 4689 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 4672 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 6199 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 4650 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 4387 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 4512 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 5830 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 4686 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 4421 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 4349 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 5631 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 4491 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 4380 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 4808 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 6018 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 3 # Number of times wr buffer was full causing retry
+system.physmem.totGap 5132091305000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 101193 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 78846 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 77214 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 8676 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 3512 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1689 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 1504 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1170 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 912 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 880 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 857 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 829 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 556 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 506 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 474 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 434 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 387 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 390 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 434 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 398 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 193 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 121 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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+system.cpu0.dcache.overall_accesses::cpu2.data 7972956 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 21732138 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.089433 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.100256 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.184577 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.127415 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036646 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.046502 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.034189 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.037593 # miss rate for WriteReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.068305 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data 0.079056 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data 0.129479 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.092675 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068305 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data 0.079056 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data 0.129479 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.092675 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14076.156000 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16575.600936 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 11062.463487 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 25515.345197 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 28142.820617 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 14662.432179 # average WriteReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 16729.813080 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17694.638445 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 11627.258037 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16729.813080 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17694.638445 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 11627.258037 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 176638 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 12002 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.717380 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes 0 # number of fast writes performed
+system.cpu0.dcache.cache_copies 0 # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks 1547018 # number of writebacks
+system.cpu0.dcache.writebacks::total 1547018 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 362388 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 362388 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 11634 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 11634 # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data 374022 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 374022 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data 374022 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 374022 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 236462 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 570074 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 806536 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 71423 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 88236 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 159659 # number of WriteReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data 307885 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data 658310 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 966195 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data 307885 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data 658310 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 966195 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2855552000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8374924000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11230476000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1679536500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2505829996 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4185366496 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4535088500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 10880753996 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 15415842496 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4535088500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 10880753996 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 15415842496 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 31206994500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33315270500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 64522265000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 372935500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 904884500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1277820000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31579930000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34220155000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65800085000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.100256 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.112844 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.060519 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.046502 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.030207 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018995 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.079056 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.082568 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.044459 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.079056 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.082568 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.044459 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12076.156000 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14690.941878 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13924.333198 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23515.345197 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 28399.179428 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26214.410061 # average WriteReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 14729.813080 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16528.313403 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15955.208313 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 14729.813080 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16528.313403 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15955.208313 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.numCycles 2604004638 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.committedInsts 34050358 # Number of instructions committed
+system.cpu1.committedOps 66241025 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 61396531 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu1.num_func_calls 0 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 6330827 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 61396531 # number of integer instructions
+system.cpu1.num_fp_insts 0 # number of float instructions
+system.cpu1.num_int_register_reads 147773528 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 79124330 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu1.num_mem_refs 4089746 # number of memory refs
+system.cpu1.num_load_insts 2551885 # Number of load instructions
+system.cpu1.num_store_insts 1537861 # Number of store instructions
+system.cpu1.num_idle_cycles 7651672288.559311 # Number of idle cycles
+system.cpu1.num_busy_cycles -5047667650.559310 # Number of busy cycles
+system.cpu1.not_idle_fraction -1.938425 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 2.938425 # Percentage of idle cycles
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.cpu2.branchPred.lookups 29453623 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 29453623 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 415098 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 27524978 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 26775027 # Number of BTB hits
+system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu2.branchPred.BTBHitPct 97.275380 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
+system.cpu2.numCycles 155984085 # number of cpu cycles simulated
+system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu2.fetch.icacheStallCycles 10604817 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 145070644 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 29453623 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 26775027 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 55443665 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 1825085 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles 101909 # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.BlockedCycles 22639923 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles 2951 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 5864 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 5243 # Number of stall cycles due to pending traps
+system.cpu2.fetch.IcacheWaitRetryStallCycles 1584 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 3406726 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 188434 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes 3455 # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples 90201759 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 3.168652 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 3.414059 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 34888289 38.68% 38.68% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 600988 0.67% 39.34% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 24050058 26.66% 66.01% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 353959 0.39% 66.40% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 625644 0.69% 67.09% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 870018 0.96% 68.06% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 382969 0.42% 68.48% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 534158 0.59% 69.07% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 27895676 30.93% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::total 90201759 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.188825 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 0.930035 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 12002495 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 21681187 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 45325562 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 1251433 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 1399062 # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts 284656362 # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts 4 # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles 1399062 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 13027629 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 13040843 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 3781171 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 45395781 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 5015320 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 283355773 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 7223 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 2405393 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents 1942678 # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.FullRegisterEvents 3127 # Number of times there has been no free registers
+system.cpu2.rename.RenamedOperands 338147018 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 617097261 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 617097023 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 238 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 325868282 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 12278736 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 148774 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 149957 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 11224608 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 6517761 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 3579821 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 461835 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 357597 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 281093420 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 441880 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 278958104 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 66093 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 8698902 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 13192307 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 82110 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 90201759 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 3.092602 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 2.393390 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 26012470 28.84% 28.84% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 6039286 6.70% 35.53% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 3951880 4.38% 39.91% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 2755931 3.06% 42.97% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 25450269 28.21% 71.18% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 1402946 1.56% 72.74% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 24246567 26.88% 99.62% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 287223 0.32% 99.94% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 55187 0.06% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 90201759 # Number of insts issued each cycle
+system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 134556 34.98% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 34.98% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 196649 51.12% 86.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 53504 13.91% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu2.iq.FU_type_0::No_OpClass 83173 0.03% 0.03% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 268863326 96.38% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 6715737 2.41% 98.82% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 3295868 1.18% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::total 278958104 # Type of FU issued
+system.cpu2.iq.rate 1.788375 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 384709 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.001379 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 648620730 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 290237963 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 277347431 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 114 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 26 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 279259593 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 47 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 629589 # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu2.iew.lsq.thread0.squashedLoads 1208294 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 7639 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 4324 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 653312 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu2.iew.lsq.thread0.rescheduledLoads 656809 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 10508 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu2.iew.iewSquashCycles 1399062 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 8628497 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 800211 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 281535300 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 104725 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 6517761 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 3579821 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 245066 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 628910 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 4050 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 4324 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 245790 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 219209 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 464999 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 278243266 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 6548770 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 714838 # Number of squashed instructions skipped in execute
+system.cpu2.iew.exec_swp 0 # number of swp insts executed
+system.cpu2.iew.exec_nop 0 # number of nop insts executed
+system.cpu2.iew.exec_refs 9760405 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 28303676 # Number of branches executed
+system.cpu2.iew.exec_stores 3211635 # Number of stores executed
+system.cpu2.iew.exec_rate 1.783793 # Inst execution rate
+system.cpu2.iew.wb_sent 278068144 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 277347457 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 216266417 # num instructions producing a value
+system.cpu2.iew.wb_consumers 353604041 # num instructions consuming a value
+system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu2.iew.wb_rate 1.778050 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.611606 # average fanout of values written-back
+system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu2.commit.commitSquashedInsts 9045420 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 359770 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 415805 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 88802697 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 3.068466 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 2.866565 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 30564443 34.42% 34.42% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 4416110 4.97% 39.39% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1290481 1.45% 40.84% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 25052940 28.21% 69.06% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 877654 0.99% 70.04% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 569019 0.64% 70.69% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 327531 0.37% 71.05% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 23624903 26.60% 97.66% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 2079616 2.34% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::total 88802697 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 138012608 # Number of instructions committed
+system.cpu2.commit.committedOps 272488038 # Number of ops (including micro ops) committed
+system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu2.commit.refs 8235976 # Number of memory references committed
+system.cpu2.commit.loads 5309467 # Number of loads committed
+system.cpu2.commit.membars 167075 # Number of memory barriers committed
+system.cpu2.commit.branches 27913254 # Number of branches committed
+system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
+system.cpu2.commit.int_insts 248812400 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 0 # Number of function calls committed.
+system.cpu2.commit.bw_lim_events 2079616 # number cycles where commit BW limit reached
+system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu2.rob.rob_reads 368229083 # The number of ROB reads
+system.cpu2.rob.rob_writes 564472103 # The number of ROB writes
+system.cpu2.timesIdled 458685 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 65782326 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 4902194189 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 138012608 # Number of Instructions Simulated
+system.cpu2.committedOps 272488038 # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total 138012608 # Number of Instructions Simulated
+system.cpu2.cpi 1.130216 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 1.130216 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.884786 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.884786 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 511223313 # number of integer regfile reads
+system.cpu2.int_regfile_writes 330894999 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 62522 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 62496 # number of floating regfile writes
+system.cpu2.misc_regfile_reads 90285732 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 129561 # number of misc regfile writes
+system.cpu2.kern.inst.arm 0 # number of arm instructions executed
+system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
new file mode 100644
index 000000000..eec6d9444
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
@@ -0,0 +1,137 @@
+Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007
+Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
+BIOS-provided physical RAM map:
+ BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
+ BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)
+ BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
+end_pfn_map = 32768
+kernel direct mapping tables up to 8000000 @ 8000-a000
+DMI 2.5 present.
+Zone PFN ranges:
+ DMA 0 -> 4096
+ DMA32 4096 -> 1048576
+ Normal 1048576 -> 1048576
+early_node_map[2] active PFN ranges
+ 0: 0 -> 159
+ 0: 256 -> 32768
+Intel MultiProcessor Specification v1.4
+MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000
+Processor #0 (Bootup-CPU)
+I/O APIC #1 at 0xFEC00000.
+Setting APIC routing to flat
+Processors: 1
+swsusp: Registered nosave memory region: 000000000009f000 - 00000000000a0000
+swsusp: Registered nosave memory region: 00000000000a0000 - 0000000000100000
+Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
+Built 1 zonelists. Total pages: 30613
+Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
+Initializing CPU#0
+PID hash table entries: 512 (order: 9, 4096 bytes)
+time.c: Detected 1999.988 MHz processor.
+Console: colour dummy device 80x25
+console handover: boot [earlyser0] -> real [ttyS0]
+Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
+Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
+Checking aperture...
+Memory: 122188k/131072k available (3742k kernel code, 8460k reserved, 1874k data, 232k init)
+Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
+Mount-cache hash table entries: 256
+CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
+CPU: L2 Cache: 1024K (64 bytes/line)
+CPU: Fake M5 x86_64 CPU stepping 01
+ACPI: Core revision 20070126
+ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
+ACPI: Unable to load the System Description Tables
+Using local APIC timer interrupts.
+result 7812471
+Detected 7.812 MHz APIC timer.
+NET: Registered protocol family 16
+PCI: Using configuration type 1
+ACPI: Interpreter disabled.
+Linux Plug and Play Support v0.97 (c) Adam Belay
+pnp: PnP ACPI: disabled
+SCSI subsystem initialized
+usbcore: registered new interface driver usbfs
+usbcore: registered new interface driver hub
+usbcore: registered new device driver usb
+PCI: Probing PCI hardware
+PCI-GART: No AMD northbridge found.
+NET: Registered protocol family 2
+Time: tsc clocksource has been installed.
+IP route cache hash table entries: 1024 (order: 1, 8192 bytes)
+TCP established hash table entries: 4096 (order: 4, 65536 bytes)
+TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
+TCP: Hash tables configured (established 4096 bind 4096)
+TCP reno registered
+Total HugeTLB memory allocated, 0
+Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
+io scheduler noop registered
+io scheduler deadline registered
+io scheduler cfq registered (default)
+Real Time Clock Driver v1.12ac
+Linux agpgart interface v0.102 (c) Dave Jones
+Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
+serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
+floppy0: no floppy controllers found
+RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
+loop: module loaded
+Intel(R) PRO/1000 Network Driver - version 7.3.20-k2
+Copyright (c) 1999-2006 Intel Corporation.
+e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI
+e100: Copyright(c) 1999-2006 Intel Corporation
+forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.
+tun: Universal TUN/TAP device driver, 1.6
+tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
+netconsole: not configured, aborting
+Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
+ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
+PIIX4: IDE controller at PCI slot 0000:00:04.0
+PCI: Enabling device 0000:00:04.0 (0000 -> 0001)
+PIIX4: chipset revision 0
+PIIX4: not 100% native mode: will probe irqs later
+ ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA
+ ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA
+hda: M5 IDE Disk, ATA DISK drive
+hdb: M5 IDE Disk, ATA DISK drive
+ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
+hda: max request size: 128KiB
+hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)
+ hda: hda1
+hdb: max request size: 128KiB
+hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
+ hdb: unknown partition table
+megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
+megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
+megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007
+Fusion MPT base driver 3.04.04
+Copyright (c) 1999-2007 LSI Logic Corporation
+Fusion MPT SPI Host driver 3.04.04
+Fusion MPT SAS Host driver 3.04.04
+ieee1394: raw1394: /dev/raw1394 device initialized
+USB Universal Host Controller Interface driver v3.0
+usbcore: registered new interface driver usblp
+drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver
+Initializing USB Mass Storage driver...
+usbcore: registered new interface driver usb-storage
+USB Mass Storage support registered.
+PNP: No PS/2 controller found. Probing ports directly.
+serio: i8042 KBD port at 0x60,0x64 irq 1
+serio: i8042 AUX port at 0x60,0x64 irq 12
+mice: PS/2 mouse device common for all mice
+input: AT Translated Set 2 keyboard as /class/input/input0
+device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com
+input: PS/2 Generic Mouse as /class/input/input1
+usbcore: registered new interface driver usbhid
+drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver
+oprofile: using timer interrupt.
+TCP cubic registered
+NET: Registered protocol family 1
+NET: Registered protocol family 10
+IPv6 over IPv4 tunneling driver
+NET: Registered protocol family 17
+EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
+VFS: Mounted root (ext2 filesystem).
+Freeing unused kernel memory: 232k freed
+ INIT: version 2.86 booting
+mounting filesystems...
+loading script...