summaryrefslogtreecommitdiff
path: root/tests
diff options
context:
space:
mode:
Diffstat (limited to 'tests')
-rw-r--r--tests/configs/base_config.py9
-rw-r--r--tests/configs/memtest-ruby.py13
-rw-r--r--tests/configs/memtest.py10
-rw-r--r--tests/configs/pc-simple-timing-ruby.py11
-rw-r--r--tests/configs/rubytest-ruby.py10
-rw-r--r--tests/configs/simple-timing-ruby.py13
-rw-r--r--tests/configs/t1000-simple-atomic.py7
-rw-r--r--tests/configs/tgen-simple-dram.py4
-rw-r--r--tests/configs/tgen-simple-mem.py4
-rw-r--r--tests/configs/twosys-tsunami-simple-atomic.py28
10 files changed, 80 insertions, 29 deletions
diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py
index d93be0d1b..9a0eb9395 100644
--- a/tests/configs/base_config.py
+++ b/tests/configs/base_config.py
@@ -151,11 +151,16 @@ class BaseSystem(object):
# Create system clock domain. This provides clock value to every
# clocked object that lies beneath it unless explicitly overwritten
# by a different clock domain.
- system.clk_domain = SrcClockDomain(clock = '1GHz')
+ system.voltage_domain = VoltageDomain()
+ system.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain =
+ system.voltage_domain)
# Create a seperate clock domain for components that should
# run at CPUs frequency
- system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
+ system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
+ voltage_domain =
+ system.voltage_domain)
@abstractmethod
def create_system(self):
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index a0500458a..004ff644a 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -80,12 +80,16 @@ options.num_cpus = nb_cores
system = System(cpu = cpus,
funcmem = SimpleMemory(in_addr_map = False),
physmem = SimpleMemory(null = True),
- funcbus = NoncoherentBus(),
- clk_domain = SrcClockDomain(clock = options.sys_clock))
+ funcbus = NoncoherentBus())
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain()
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
# Create a seperate clock domain for components that should run at
# CPUs frequency
-system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
+ voltage_domain = system.voltage_domain)
# All cpus are associated with cpu_clk_domain
for cpu in cpus:
@@ -96,7 +100,8 @@ system.mem_ranges = AddrRange('256MB')
Ruby.create_system(options, system)
# Create a separate clock domain for Ruby
-system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
+ voltage_domain = system.voltage_domain)
assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 35efe646d..fbd18b779 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -39,12 +39,16 @@ cpus = [ MemTest() for i in xrange(nb_cores) ]
system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
funcbus = NoncoherentBus(),
physmem = SimpleMemory(),
- membus = CoherentBus(width=16),
- clk_domain = SrcClockDomain(clock = '1GHz'))
+ membus = CoherentBus(width=16))
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain()
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
# Create a seperate clock domain for components that should run at
# CPUs frequency
-system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
+ voltage_domain = system.voltage_domain)
system.toL2Bus = CoherentBus(clk_domain = system.cpu_clk_domain, width=16)
system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py
index 7fd9c0b5f..fcbfd6b7f 100644
--- a/tests/configs/pc-simple-timing-ruby.py
+++ b/tests/configs/pc-simple-timing-ruby.py
@@ -57,17 +57,22 @@ options.num_cpus = 2
mdesc = SysConfig(disk = 'linux-x86.img')
system = FSConfig.makeLinuxX86System('timing', options.num_cpus,
mdesc=mdesc, Ruby=True)
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
-system.clk_domain = SrcClockDomain(clock = '1GHz')
-system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
+ voltage_domain = system.voltage_domain)
system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain)
for i in xrange(options.num_cpus)]
Ruby.create_system(options, system, system.piobus, system._dma_ports)
# Create a seperate clock domain for Ruby
-system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
+ voltage_domain = system.voltage_domain)
for (i, cpu) in enumerate(system.cpu):
# create the interrupt controller
diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index d2809f2a2..54495ab54 100644
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -77,15 +77,19 @@ if buildEnv['PROTOCOL'] == 'MOESI_hammer':
tester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
wakeup_frequency = 10, num_cpus = options.num_cpus)
-system = System(tester = tester, physmem = SimpleMemory(null = True),
- clk_domain = SrcClockDomain(clock = options.sys_clock))
+system = System(tester = tester, physmem = SimpleMemory(null = True))
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
system.mem_ranges = AddrRange('256MB')
Ruby.create_system(options, system)
# Create a separate clock domain for Ruby
-system.ruby.clk_domain = SrcClockDomain(clock = '1GHz')
+system.ruby.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index ce155c23c..df8fdf2be 100644
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -67,19 +67,24 @@ options.l3_assoc=2
options.num_cpus = 1
cpu = TimingSimpleCPU(cpu_id=0)
-system = System(cpu = cpu, physmem = SimpleMemory(null = True),
- clk_domain = SrcClockDomain(clock = '1GHz'))
+system = System(cpu = cpu, physmem = SimpleMemory(null = True))
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
# Create a seperate clock domain for components that should run at
# CPUs frequency
-system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
+system.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
+ voltage_domain = system.voltage_domain)
system.mem_ranges = AddrRange('256MB')
Ruby.create_system(options, system)
# Create a separate clock for Ruby
-system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
+ voltage_domain = system.voltage_domain)
assert(len(system.ruby._cpu_ruby_ports) == 1)
diff --git a/tests/configs/t1000-simple-atomic.py b/tests/configs/t1000-simple-atomic.py
index 64c3dc408..68bf048b6 100644
--- a/tests/configs/t1000-simple-atomic.py
+++ b/tests/configs/t1000-simple-atomic.py
@@ -32,8 +32,11 @@ m5.util.addToPath('../configs/common')
import FSConfig
system = FSConfig.makeSparcSystem('atomic')
-system.clk_domain = SrcClockDomain(clock = '1GHz')
-system.cpu_clk_domain = SrcClockDomain(clock = '1GHz')
+system.voltage_domain = VoltageDomain()
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
+system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
cpu = AtomicSimpleCPU(cpu_id=0, clk_domain = system.cpu_clk_domain)
system.cpu = cpu
# create the interrupt controller
diff --git a/tests/configs/tgen-simple-dram.py b/tests/configs/tgen-simple-dram.py
index 394aac4cb..d0d26e1f3 100644
--- a/tests/configs/tgen-simple-dram.py
+++ b/tests/configs/tgen-simple-dram.py
@@ -50,7 +50,9 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-dram.cfg")
# system simulated
system = System(cpu = cpu, physmem = DDR3_1600_x64(),
membus = NoncoherentBus(width = 16),
- clk_domain = SrcClockDomain(clock = '1GHz'))
+ clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain =
+ VoltageDomain()))
# add a communication monitor
system.monitor = CommMonitor()
diff --git a/tests/configs/tgen-simple-mem.py b/tests/configs/tgen-simple-mem.py
index 2d39a2ab0..5e241a25a 100644
--- a/tests/configs/tgen-simple-mem.py
+++ b/tests/configs/tgen-simple-mem.py
@@ -50,7 +50,9 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg")
# system simulated
system = System(cpu = cpu, physmem = SimpleMemory(),
membus = NoncoherentBus(width = 16),
- clk_domain = SrcClockDomain(clock = '1GHz'))
+ clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain =
+ VoltageDomain()))
# add a communication monitor, and also trace all the packets
system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz")
diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py
index b69e35517..e84a06aaf 100644
--- a/tests/configs/twosys-tsunami-simple-atomic.py
+++ b/tests/configs/twosys-tsunami-simple-atomic.py
@@ -35,8 +35,12 @@ from Benchmarks import *
test_sys = makeLinuxAlphaSystem('atomic',
SysConfig('netperf-stream-client.rcS'))
+# Dummy voltage domain for all test_sys clock domains
+test_sys.voltage_domain = VoltageDomain()
+
# Create the system clock domain
-test_sys.clk_domain = SrcClockDomain(clock = '1GHz')
+test_sys.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = test_sys.voltage_domain)
test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
# create the interrupt controller
@@ -45,10 +49,14 @@ test_sys.cpu.connectAllPorts(test_sys.membus)
# Create a seperate clock domain for components that should run at
# CPUs frequency
-test_sys.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
+test_sys.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
+ voltage_domain =
+ test_sys.voltage_domain)
# Create a separate clock domain for Ethernet
-test_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz')
+test_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz',
+ voltage_domain =
+ test_sys.voltage_domain)
# In contrast to the other (one-system) Tsunami configurations we do
# not have an IO cache but instead rely on an IO bridge for accesses
@@ -62,8 +70,12 @@ test_sys.physmem.port = test_sys.membus.master
drive_sys = makeLinuxAlphaSystem('atomic',
SysConfig('netperf-server.rcS'))
+# Dummy voltage domain for all drive_sys clock domains
+drive_sys.voltage_domain = VoltageDomain()
# Create the system clock domain
-drive_sys.clk_domain = SrcClockDomain(clock = '1GHz')
+drive_sys.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain =
+ drive_sys.voltage_domain)
drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
# create the interrupt controller
drive_sys.cpu.createInterruptController()
@@ -71,10 +83,14 @@ drive_sys.cpu.connectAllPorts(drive_sys.membus)
# Create a seperate clock domain for components that should run at
# CPUs frequency
-drive_sys.cpu.clk_domain = SrcClockDomain(clock = '4GHz')
+drive_sys.cpu.clk_domain = SrcClockDomain(clock = '4GHz',
+ voltage_domain =
+ drive_sys.voltage_domain)
# Create a separate clock domain for Ethernet
-drive_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz')
+drive_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz',
+ voltage_domain =
+ drive_sys.voltage_domain)
drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges)
drive_sys.iobridge.slave = drive_sys.iobus.master
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 04:30:03 +0000