diff options
Diffstat (limited to 'tests')
191 files changed, 7002 insertions, 2647 deletions
diff --git a/tests/SConscript b/tests/SConscript index 8c9029be6..24e2cad7f 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -203,9 +203,12 @@ if env['FULL_SYSTEM']: 'tsunami-simple-atomic-dual', 'tsunami-simple-timing-dual', 'twosys-tsunami-simple-atomic'] + if env['TARGET_ISA'] == 'sparc': + configs += ['t1000-simple-atomic', + 't1000-simple-timing'] else: - configs += ['simple-atomic', 'simple-timing', 'o3-timing'] + configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest'] cwd = os.getcwd() os.chdir(str(Dir('.').srcdir)) diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index 2b990418c..f56edef4a 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -53,7 +53,7 @@ class L2(BaseCache): #MAX CORES IS 8 with the fals sharing method nb_cores = 8 -cpus = [ MemTest(atomic=False, max_loads=1e12, percent_uncacheable=10, progress_interval=1000) for i in xrange(nb_cores) ] +cpus = [ MemTest() for i in xrange(nb_cores) ] # system simulated system = System(cpu = cpus, funcmem = PhysicalMemory(), diff --git a/tests/configs/t1000-simple-atomic.py b/tests/configs/t1000-simple-atomic.py new file mode 100644 index 000000000..6a078e715 --- /dev/null +++ b/tests/configs/t1000-simple-atomic.py @@ -0,0 +1,41 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ali Saidi + +import m5 +from m5.objects import * +m5.AddToPath('../configs/common') +import FSConfig + +cpu = AtomicSimpleCPU(cpu_id=0) +system = FSConfig.makeSparcSystem('atomic') +system.cpu = cpu +cpu.connectMemPorts(system.membus) + +root = Root(system=system) + +m5.ticks.setGlobalFrequency('2GHz') diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py index 4adb32868..7ed854f44 100644 --- a/tests/configs/tsunami-simple-atomic-dual.py +++ b/tests/configs/tsunami-simple-atomic-dual.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -37,4 +37,6 @@ system.cpu = cpus for c in cpus: c.connectMemPorts(system.membus) -root = Root(clock = '2GHz', system = system) +root = Root(system=system) + +m5.ticks.setGlobalFrequency('2GHz') diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py index 653df9bb0..4859f30cf 100644 --- a/tests/configs/tsunami-simple-atomic.py +++ b/tests/configs/tsunami-simple-atomic.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -36,4 +36,5 @@ system = FSConfig.makeLinuxAlphaSystem('atomic') system.cpu = cpu cpu.connectMemPorts(system.membus) -root = Root(clock = '2GHz', system = system) +root = Root(system=system) +m5.ticks.setGlobalFrequency('2GHz') diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py index bfd478969..0c8c3d523 100644 --- a/tests/configs/tsunami-simple-timing-dual.py +++ b/tests/configs/tsunami-simple-timing-dual.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -37,4 +37,5 @@ system.cpu = cpus for c in cpus: c.connectMemPorts(system.membus) -root = Root(clock = '2GHz', system = system) +root = Root(system=system) +m5.ticks.setGlobalFrequency('2GHz') diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py index 59401c040..9f532e3ae 100644 --- a/tests/configs/tsunami-simple-timing.py +++ b/tests/configs/tsunami-simple-timing.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -36,4 +36,5 @@ system = FSConfig.makeLinuxAlphaSystem('timing') system.cpu = cpu cpu.connectMemPorts(system.membus) -root = Root(clock = '2GHz', system = system) +root = Root(system=system) +m5.ticks.setGlobalFrequency('2GHz') diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index b221360e2..fa5ac1725 100644 --- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -388,7 +388,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/linux/o3-timing egid=100 env= euid=100 @@ -414,14 +414,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out index 704fa2535..8744b6907 100644 --- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out @@ -10,6 +10,7 @@ type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,7 +31,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/linux/o3-timing system=system uid=100 euid=100 @@ -366,15 +367,6 @@ clock=1000 width=64 responder_set=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - [stats] descriptions=true project_name=test @@ -392,9 +384,6 @@ dump_cycle=0 dump_period=0 ignore_events= -[random] -seed=1 - [exetrace] speculative=true print_cycle=true diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt index bd4e6c524..8303336ed 100644 --- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 4270829 # Nu global.BPredUnit.condPredicted 101462576 # Number of conditional branches predicted global.BPredUnit.lookups 108029652 # Number of BP lookups global.BPredUnit.usedRAS 1765818 # Number of times the RAS was used to get a target. -host_inst_rate 49266 # Simulator instruction rate (inst/s) -host_mem_usage 315608 # Number of bytes of host memory used -host_seconds 11479.54 # Real time elapsed on the host -host_tick_rate 147031 # Simulator tick rate (ticks/s) +host_inst_rate 64442 # Simulator instruction rate (inst/s) +host_mem_usage 296420 # Number of bytes of host memory used +host_seconds 8776.17 # Real time elapsed on the host +host_tick_rate 192322 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 20975706 # Number of conflicting loads. memdepunit.memDep.conflictingStores 18042230 # Number of conflicting stores. memdepunit.memDep.insertedLoads 207074480 # Number of loads inserted to the mem dependence unit. @@ -263,8 +263,8 @@ system.cpu.iew.lsq.thread.0.rescheduledLoads 5548 system.cpu.iew.lsq.thread.0.squashedLoads 92024970 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 17250597 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 1892 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 2705247 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 2033271 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 530187 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 4208331 # Number of branches that were predicted taken incorrectly system.cpu.ipc 0.335073 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.335073 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 752715877 # Type of FU issued @@ -335,8 +335,8 @@ system.cpu.l2cache.ReadReq_misses 26319 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 58461984 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054654 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 26319 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 337990 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 337990 # number of WriteReqNoAck|Writeback hits +system.cpu.l2cache.Writeback_accesses 337990 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 337990 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 30.138911 # Average number of references to valid blocks. @@ -362,7 +362,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 819545 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 6806.870170 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 2221.284395 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 793226 # number of overall hits system.cpu.l2cache.overall_miss_latency 179150016 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.032114 # miss rate for overall accesses diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr new file mode 100644 index 000000000..eb1796ead --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr @@ -0,0 +1,2 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout index 9aaca3eeb..9aaca3eeb 100644 --- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index 841e8766f..841e8766f 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out index b5a24e5fb..b5a24e5fb 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt index b8593d3a3..b8593d3a3 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr index 87866a2a5..87866a2a5 100644 --- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout index 9aaca3eeb..9aaca3eeb 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 48a760b08..48a760b08 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out index eddb9ff53..eddb9ff53 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt index 5e7441c54..5e7441c54 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr index 87866a2a5..87866a2a5 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout index 9aaca3eeb..9aaca3eeb 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini new file mode 100644 index 000000000..1cf7e8a9b --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -0,0 +1,64 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=workload +clock=1 +cpu_id=0 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +simulate_stalls=false +system=system +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out new file mode 100644 index 000000000..f6ace951d --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out @@ -0,0 +1,57 @@ +[root] +type=Root +dummy=0 + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 +zero=false + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip +input=cin +output=cout +env= +cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt new file mode 100644 index 000000000..6cf88af9d --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 713136 # Simulator instruction rate (inst/s) +host_mem_usage 148308 # Number of bytes of host memory used +host_seconds 2088.68 # Real time elapsed on the host +host_tick_rate 713136 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1489514860 # Number of instructions simulated +sim_seconds 0.001490 # Number of seconds simulated +sim_ticks 1489514859 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1489514860 # number of cpu cycles simulated +system.cpu.num_insts 1489514860 # Number of instructions executed +system.cpu.num_refs 569359656 # Number of memory references +system.cpu.workload.PROG:num_syscalls 19 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr new file mode 100644 index 000000000..e74a68c71 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr @@ -0,0 +1,7 @@ +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0xb4000 length 0x10. +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x0 length 0x0. +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... +warn: Ignoring request to flush register windows. diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout new file mode 100644 index 000000000..3f5dab90b --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout @@ -0,0 +1,44 @@ +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 21 2007 00:46:54 +M5 started Wed Mar 21 00:47:20 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1489514859 because target called exit() diff --git a/tests/long/00.gzip/test.py b/tests/long/00.gzip/test.py index 06ccb656b..f69914046 100644 --- a/tests/long/00.gzip/test.py +++ b/tests/long/00.gzip/test.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -29,5 +29,5 @@ m5.AddToPath('../configs/common') from cpu2000 import gzip_log -workload = gzip_log('alpha', 'tru64', 'smred') +workload = gzip_log(isa, opsys, 'smred') root.system.cpu.workload = workload.makeLiveProcess() diff --git a/tests/long/10.mcf/test.py b/tests/long/10.mcf/test.py index f545aad3d..ffe2758f1 100644 --- a/tests/long/10.mcf/test.py +++ b/tests/long/10.mcf/test.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -29,5 +29,5 @@ m5.AddToPath('../configs/common') from cpu2000 import mcf -workload = mcf('alpha', 'tru64', 'lgred') +workload = mcf(isa, opsys, 'lgred') root.system.cpu.workload = workload.makeLiveProcess() diff --git a/tests/long/20.parser/ref/alpha/linux/NOTE b/tests/long/20.parser/ref/alpha/tru64/NOTE index 5e7d8c358..5e7d8c358 100644 --- a/tests/long/20.parser/ref/alpha/linux/NOTE +++ b/tests/long/20.parser/ref/alpha/tru64/NOTE diff --git a/tests/long/20.parser/test.py b/tests/long/20.parser/test.py index 8703ae634..82ab71c90 100644 --- a/tests/long/20.parser/test.py +++ b/tests/long/20.parser/test.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -29,5 +29,5 @@ m5.AddToPath('../configs/common') from cpu2000 import parser -workload = parser('alpha', 'tru64', 'lgred') +workload = parser(isa, opsys, 'lgred') root.system.cpu.workload = workload.makeLiveProcess() diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 915a6967f..915a6967f 100644 --- a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.out b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out index 80e067401..80e067401 100644 --- a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt index 9d00cb146..9d00cb146 100644 --- a/tests/long/30.eon/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr index d414f5cfe..d414f5cfe 100644 --- a/tests/long/30.eon/ref/alpha/linux/o3-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout index 039e2d4ce..039e2d4ce 100644 --- a/tests/long/30.eon/ref/alpha/linux/o3-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini index 088cd1a9f..088cd1a9f 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out index bec900d0f..bec900d0f 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt index a308f5e36..a308f5e36 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr index 1d6957eca..1d6957eca 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout index 039e2d4ce..039e2d4ce 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini index b56d96049..452538e49 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -7,21 +7,6 @@ max_tick=0 output_file=cout progress_interval=0 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - [serialize] count=10 cycle=0 @@ -197,11 +182,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing egid=100 env= euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin output=cout @@ -223,14 +208,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out index 0af9e3f29..602da9705 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out @@ -10,6 +10,7 @@ type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -26,11 +27,11 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing system=system uid=100 euid=100 @@ -178,15 +179,6 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - [stats] descriptions=true project_name=test @@ -204,25 +196,6 @@ dump_cycle=0 dump_period=0 ignore_events= -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - [statsreset] reset_cycle=0 diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt index 28328cd0e..328856ce7 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 490401 # Simulator instruction rate (inst/s) -host_mem_usage 178744 # Number of bytes of host memory used -host_seconds 812.94 # Real time elapsed on the host -host_tick_rate 734822 # Simulator tick rate (ticks/s) +host_inst_rate 689508 # Simulator instruction rate (inst/s) +host_mem_usage 185012 # Number of bytes of host memory used +host_seconds 578.19 # Real time elapsed on the host +host_tick_rate 1033135 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664450 # Number of instructions simulated sim_seconds 0.000597 # Number of seconds simulated -sim_ticks 597363012 # Number of ticks simulated +sim_ticks 597346012 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 94754482 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 3956.610526 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2956.610526 # average ReadReq mshr miss latency @@ -19,49 +19,49 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 2808780 # system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3939.646399 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2939.646399 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73517520 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 12634446 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 3940.471580 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2940.471580 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73517525 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 12617390 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 3207 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 9427446 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 9415390 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 3207 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40478.963676 # Average number of references to valid blocks. +system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 40527.711224 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 168275209 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3943.523214 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2943.523214 # average overall mshr miss latency -system.cpu.dcache.demand_hits 168271052 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 16393226 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 3944.164258 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency +system.cpu.dcache.demand_hits 168271057 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 16376170 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_misses 4157 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 12236226 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 12224170 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4157 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 168275209 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3943.523214 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2943.523214 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 168271052 # number of overall hits -system.cpu.dcache.overall_miss_latency 16393226 # number of overall miss cycles +system.cpu.dcache.overall_avg_miss_latency 3944.164258 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 168271057 # number of overall hits +system.cpu.dcache.overall_miss_latency 16376170 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_misses 4157 # number of overall misses +system.cpu.dcache.overall_misses 4152 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 12236226 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 12224170 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4157 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -74,24 +74,24 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.sampled_refs 4157 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3222.448687 # Cycle average of tags in use -system.cpu.dcache.total_refs 168271052 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3222.413784 # Cycle average of tags in use +system.cpu.dcache.total_refs 168271057 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 625 # number of writebacks system.cpu.icache.ReadReq_accesses 398664451 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3820.892216 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2820.892216 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3820.906097 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2820.906097 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 398660777 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 14037958 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 14038009 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 3674 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 10363958 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 10364009 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 3674 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked system.cpu.icache.avg_refs 108508.649156 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 398664451 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3820.892216 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2820.892216 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3820.906097 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency system.cpu.icache.demand_hits 398660777 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 14037958 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 14038009 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses system.cpu.icache.demand_misses 3674 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10363958 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10364009 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 3674 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 398664451 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3820.892216 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2820.892216 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_miss_latency 3820.906097 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 398660777 # number of overall hits -system.cpu.icache.overall_miss_latency 14037958 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 14038009 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses system.cpu.icache.overall_misses 3674 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10363958 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10364009 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 3674 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,57 +138,57 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1770 # number of replacements system.cpu.icache.sampled_refs 3674 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1765.884663 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1765.882838 # Cycle average of tags in use system.cpu.icache.total_refs 398660777 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 7831 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2982.860028 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1924.618942 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 7826 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2983.265505 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1924.984530 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 651 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 21416935 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.916869 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 7180 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 13818764 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916869 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 7180 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 625 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 625 # number of WriteReqNoAck|Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.177716 # Average number of references to valid blocks. +system.cpu.l2cache.ReadReq_miss_latency 21404930 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.916816 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 7175 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 13811764 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916816 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 7175 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.177840 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 7831 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2982.860028 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1924.618942 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 7826 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2983.265505 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency system.cpu.l2cache.demand_hits 651 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 21416935 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.916869 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7180 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 21404930 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.916816 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7175 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 13818764 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.916869 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7180 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 13811764 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.916816 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7175 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 8456 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2982.860028 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1924.618942 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_accesses 8451 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2983.265505 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1276 # number of overall hits -system.cpu.l2cache.overall_miss_latency 21416935 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.849101 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7180 # number of overall misses +system.cpu.l2cache.overall_miss_latency 21404930 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.849012 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7175 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 13818764 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.849101 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7180 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 13811764 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.849012 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7175 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -201,14 +201,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 7180 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 7175 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 6344.085280 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 6344.042673 # Cycle average of tags in use system.cpu.l2cache.total_refs 1276 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 597363012 # number of cpu cycles simulated +system.cpu.numCycles 597346012 # number of cpu cycles simulated system.cpu.num_insts 398664450 # Number of instructions executed system.cpu.num_refs 174183390 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr index 1d6957eca..8534c55aa 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr @@ -1,3 +1,4 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... getting pixel output filename pixels_out.cook opening control file chair.control.cook diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout index 039e2d4ce..039e2d4ce 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout diff --git a/tests/long/30.eon/test.py b/tests/long/30.eon/test.py index 828b6390c..318da1049 100644 --- a/tests/long/30.eon/test.py +++ b/tests/long/30.eon/test.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -29,5 +29,5 @@ m5.AddToPath('../configs/common') from cpu2000 import eon_cook -workload = eon_cook('alpha', 'tru64', 'mdred') +workload = eon_cook(isa, opsys, 'mdred') root.system.cpu.workload = workload.makeLiveProcess() diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini index 81e1071eb..59c6e25e2 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini @@ -7,21 +7,6 @@ max_tick=0 output_file=cout progress_interval=0 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - [serialize] count=10 cycle=0 @@ -74,11 +59,11 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-atomic egid=100 env= euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin output=cout @@ -100,14 +85,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out index e5012d953..c6e4aa136 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out @@ -10,6 +10,7 @@ type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -26,11 +27,11 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-atomic system=system uid=100 euid=100 @@ -57,15 +58,6 @@ function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - [stats] descriptions=true project_name=test @@ -83,25 +75,6 @@ dump_cycle=0 dump_period=0 ignore_events= -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - [statsreset] reset_cycle=0 diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt index f553125a6..9db3f64bc 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 906784 # Simulator instruction rate (inst/s) -host_mem_usage 147280 # Number of bytes of host memory used -host_seconds 2215.51 # Real time elapsed on the host -host_tick_rate 906784 # Simulator tick rate (ticks/s) +host_inst_rate 1149393 # Simulator instruction rate (inst/s) +host_mem_usage 177516 # Number of bytes of host memory used +host_seconds 1747.87 # Real time elapsed on the host +host_tick_rate 1149393 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 2008987724 # Number of instructions simulated +sim_insts 2008987607 # Number of instructions simulated sim_seconds 0.002009 # Number of seconds simulated -sim_ticks 2008987723 # Number of ticks simulated +sim_ticks 2008987606 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2008987724 # number of cpu cycles simulated -system.cpu.num_insts 2008987724 # Number of instructions executed -system.cpu.num_refs 722390480 # Number of memory references +system.cpu.numCycles 2008987607 # number of cpu cycles simulated +system.cpu.num_insts 2008987607 # Number of instructions executed +system.cpu.num_refs 722390435 # Number of memory references system.cpu.workload.PROG:num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr index 9135960d0..bc72461c8 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr @@ -1,2 +1,3 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: ignoring syscall sigprocmask(1, 0, ...) diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout index d4a078b85..d4a078b85 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index fa4ee72da..5f64dcebd 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -7,21 +7,6 @@ max_tick=0 output_file=cout progress_interval=0 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - [serialize] count=10 cycle=0 @@ -197,11 +182,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing egid=100 env= euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin output=cout @@ -223,14 +208,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out index ea12fcb9a..6998f4828 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out @@ -10,6 +10,7 @@ type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -26,11 +27,11 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing system=system uid=100 euid=100 @@ -178,15 +179,6 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - [stats] descriptions=true project_name=test @@ -204,25 +196,6 @@ dump_cycle=0 dump_period=0 ignore_events= -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - [statsreset] reset_cycle=0 diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt index 4d20e663a..45f793ab7 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 502967 # Simulator instruction rate (inst/s) -host_mem_usage 217744 # Number of bytes of host memory used -host_seconds 3994.27 # Real time elapsed on the host -host_tick_rate 1895851 # Simulator tick rate (ticks/s) +host_inst_rate 752631 # Simulator instruction rate (inst/s) +host_mem_usage 230876 # Number of bytes of host memory used +host_seconds 2669.29 # Real time elapsed on the host +host_tick_rate 2836913 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 2008987724 # Number of instructions simulated +sim_insts 2008987607 # Number of instructions simulated sim_seconds 0.007573 # Number of seconds simulated -sim_ticks 7572549003 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 511070058 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3107.171711 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2107.171711 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 509611866 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4530852932 # number of ReadReq miss cycles +sim_ticks 7572532003 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3107.171986 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2107.171986 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4530853333 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3072660932 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3072661333 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 210794909 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3884.294897 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2884.294897 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 210722955 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 279490555 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3884.267929 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2884.267929 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 210722944 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 279480846 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 71954 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 207536555 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 71952 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 207528846 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71954 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 470.762150 # Average number of references to valid blocks. +system.cpu.dcache.WriteReq_mshr_misses 71952 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 721864967 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3143.715362 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2143.715362 # average overall mshr miss latency -system.cpu.dcache.demand_hits 720334821 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4810343487 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3143.713388 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2143.713388 # average overall mshr miss latency +system.cpu.dcache.demand_hits 720334778 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 4810334179 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1530146 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 1530144 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3280197487 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3280190179 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1530146 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1530144 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 721864967 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3143.715362 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2143.715362 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 720334821 # number of overall hits -system.cpu.dcache.overall_miss_latency 4810343487 # number of overall miss cycles +system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3143.713388 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2143.713388 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 720334778 # number of overall hits +system.cpu.dcache.overall_miss_latency 4810334179 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1530146 # number of overall misses +system.cpu.dcache.overall_misses 1530144 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3280197487 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3280190179 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1530146 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 1530144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -73,57 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 1526050 # number of replacements -system.cpu.dcache.sampled_refs 1530146 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1526048 # number of replacements +system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4087.472566 # Cycle average of tags in use -system.cpu.dcache.total_refs 720334821 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 35194000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 74591 # number of writebacks -system.cpu.icache.ReadReq_accesses 2008987725 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3103.752500 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2103.752500 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2008977127 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 32893569 # number of ReadReq miss cycles +system.cpu.dcache.tagsinuse 4087.479154 # Cycle average of tags in use +system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 35165000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 74589 # number of writebacks +system.cpu.icache.ReadReq_accesses 2008987608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3103.627312 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2103.627312 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2008977012 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 32886035 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 10598 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 22295569 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 22290035 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10598 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 189561.910455 # Average number of references to valid blocks. +system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 189597.679502 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2008987725 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3103.752500 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2103.752500 # average overall mshr miss latency -system.cpu.icache.demand_hits 2008977127 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 32893569 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 2008987608 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3103.627312 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2103.627312 # average overall mshr miss latency +system.cpu.icache.demand_hits 2008977012 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 32886035 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses -system.cpu.icache.demand_misses 10598 # number of demand (read+write) misses +system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 22295569 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 22290035 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10598 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 2008987725 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3103.752500 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2103.752500 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2008977127 # number of overall hits -system.cpu.icache.overall_miss_latency 32893569 # number of overall miss cycles +system.cpu.icache.overall_accesses 2008987608 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3103.627312 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2103.627312 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 2008977012 # number of overall hits +system.cpu.icache.overall_miss_latency 32886035 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses -system.cpu.icache.overall_misses 10598 # number of overall misses +system.cpu.icache.overall_misses 10596 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 22295569 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 22290035 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10598 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -135,64 +135,64 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 9048 # number of replacements -system.cpu.icache.sampled_refs 10598 # Sample count of references to valid blocks. +system.cpu.icache.replacements 9046 # number of replacements +system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1472.251444 # Cycle average of tags in use -system.cpu.icache.total_refs 2008977127 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1471.254279 # Cycle average of tags in use +system.cpu.icache.total_refs 2008977012 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 1540744 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2153.831026 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1111.660796 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 1540740 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2153.828221 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1111.659139 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 33878 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 3245534743 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 3245521901 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.978012 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1506866 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1675123857 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 1506862 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1675116913 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.978012 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1506866 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 74591 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 73517 # number of WriteReqNoAck|Writeback hits -system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.014399 # miss rate for WriteReqNoAck|Writeback accesses -system.cpu.l2cache.WriteReqNoAck|Writeback_misses 1074 # number of WriteReqNoAck|Writeback misses -system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.014399 # mshr miss rate for WriteReqNoAck|Writeback accesses -system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 1074 # number of WriteReqNoAck|Writeback MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.071270 # Average number of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_misses 1506862 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 73515 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.014399 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 1074 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.014399 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 1074 # number of Writeback MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.071269 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 1540744 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2153.831026 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1111.660796 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2153.828221 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1111.659139 # average overall mshr miss latency system.cpu.l2cache.demand_hits 33878 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3245534743 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 3245521901 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.978012 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1506866 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 1506862 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1675123857 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1675116913 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.978012 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1506866 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 1506862 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 1615335 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2152.297003 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1111.660796 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 107395 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3245534743 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.933515 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1507940 # number of overall misses +system.cpu.l2cache.overall_accesses 1615329 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2152.294196 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1111.659139 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 107393 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3245521901 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.933516 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1507936 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1675123857 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.932850 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1506866 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1675116913 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.932851 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1506862 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -204,17 +204,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 1474098 # number of replacements -system.cpu.l2cache.sampled_refs 1506866 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 1474094 # number of replacements +system.cpu.l2cache.sampled_refs 1506862 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 32444.673070 # Cycle average of tags in use -system.cpu.l2cache.total_refs 107395 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 164218000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 66806 # number of writebacks +system.cpu.l2cache.tagsinuse 32444.706916 # Cycle average of tags in use +system.cpu.l2cache.total_refs 107393 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 164189000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 66804 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 7572549003 # number of cpu cycles simulated -system.cpu.num_insts 2008987724 # Number of instructions executed -system.cpu.num_refs 722390480 # Number of memory references +system.cpu.numCycles 7572532003 # number of cpu cycles simulated +system.cpu.num_insts 2008987607 # Number of instructions executed +system.cpu.num_refs 722390435 # Number of memory references system.cpu.workload.PROG:num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr index 9135960d0..bc72461c8 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr @@ -1,2 +1,3 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: ignoring syscall sigprocmask(1, 0, ...) diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout index d4a078b85..d4a078b85 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout diff --git a/tests/long/40.perlbmk/test.py b/tests/long/40.perlbmk/test.py index 2f9dd0ff0..e32416265 100644 --- a/tests/long/40.perlbmk/test.py +++ b/tests/long/40.perlbmk/test.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -29,5 +29,5 @@ m5.AddToPath('../configs/common') from cpu2000 import perlbmk_makerand -workload = perlbmk_makerand('alpha', 'tru64', 'lgred') +workload = perlbmk_makerand(isa, opsys, 'lgred') root.system.cpu.workload = workload.makeLiveProcess() diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr deleted file mode 100644 index 87866a2a5..000000000 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr +++ /dev/null @@ -1 +0,0 @@ -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr deleted file mode 100644 index 87866a2a5..000000000 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr +++ /dev/null @@ -1 +0,0 @@ -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 46f72ac13..cf4e15676 100644 --- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -388,7 +388,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/o3-timing egid=100 env= euid=100 @@ -414,14 +414,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out index 9e0ede146..52c225902 100644 --- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out @@ -10,6 +10,7 @@ type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,7 +31,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/o3-timing system=system uid=100 euid=100 @@ -366,15 +367,6 @@ clock=1000 width=64 responder_set=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - [stats] descriptions=true project_name=test @@ -392,9 +384,6 @@ dump_cycle=0 dump_period=0 ignore_events= -[random] -seed=1 - [exetrace] speculative=true print_cycle=true diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt index 34a47022b..3069385f0 100644 --- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 13144986 # Number of BTB hits -global.BPredUnit.BTBLookups 21876990 # Number of BTB lookups -global.BPredUnit.RASInCorrect 30485 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 454636 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 16268422 # Number of conditional branches predicted -global.BPredUnit.lookups 26797394 # Number of BP lookups -global.BPredUnit.usedRAS 4858022 # Number of times the RAS was used to get a target. -host_inst_rate 52852 # Simulator instruction rate (inst/s) -host_mem_usage 259420 # Number of bytes of host memory used -host_seconds 1506.34 # Real time elapsed on the host -host_tick_rate 744190 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 14725219 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 11320400 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 28503669 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 16218894 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 13202034 # Number of BTB hits +global.BPredUnit.BTBLookups 22107115 # Number of BTB lookups +global.BPredUnit.RASInCorrect 30370 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 454360 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 16498204 # Number of conditional branches predicted +global.BPredUnit.lookups 27047110 # Number of BP lookups +global.BPredUnit.usedRAS 4878193 # Number of times the RAS was used to get a target. +host_inst_rate 69520 # Simulator instruction rate (inst/s) +host_mem_usage 239908 # Number of bytes of host memory used +host_seconds 1144.87 # Real time elapsed on the host +host_tick_rate 987535 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 14725847 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 11490673 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 28863760 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 16312214 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 79613339 # Number of instructions simulated -sim_seconds 0.001121 # Number of seconds simulated -sim_ticks 1121005014 # Number of ticks simulated -system.cpu.commit.COM:branches 13759853 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3902181 # number cycles where commit BW limit reached +sim_insts 79591756 # Number of instructions simulated +sim_seconds 0.001131 # Number of seconds simulated +sim_ticks 1130602014 # Number of ticks simulated +system.cpu.commit.COM:branches 13754477 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 3893678 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 88439527 +system.cpu.commit.COM:committed_per_cycle.samples 89505192 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 61749847 6982.15% - 1 8803671 995.45% - 2 5177009 585.37% - 3 3274877 370.30% - 4 2188473 247.45% - 5 1421818 160.77% - 6 1152410 130.30% - 7 769241 86.98% - 8 3902181 441.23% + 0 62882698 7025.59% + 1 8753972 978.04% + 2 5175203 578.20% + 3 3243621 362.39% + 4 2169519 242.39% + 5 1432847 160.09% + 6 1161882 129.81% + 7 791772 88.46% + 8 3893678 435.02% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 88361897 # Number of instructions committed -system.cpu.commit.COM:loads 20383045 # Number of loads committed +system.cpu.commit.COM:count 88340672 # Number of instructions committed +system.cpu.commit.COM:loads 20379399 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 35229375 # Number of memory references committed +system.cpu.commit.COM:refs 35224018 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 360073 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 88361897 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 4706 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 20725845 # The number of squashed insts skipped by commit -system.cpu.committedInsts 79613339 # Number of Instructions Simulated -system.cpu.committedInsts_total 79613339 # Number of Instructions Simulated -system.cpu.cpi 14.080618 # CPI: Cycles Per Instruction -system.cpu.cpi_total 14.080618 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 19542402 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4437.586724 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3280.646620 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 19388897 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 681191750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007855 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 153505 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 94427 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 193814041 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 59078 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 14615683 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4852.594089 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4028.169523 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 13950409 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3228304680 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.045518 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 665274 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 523305 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 571875199 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009713 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 141969 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 3068.165217 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 3779.642588 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 165.828418 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 115 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 125189 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 352839 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 473169676 # number of cycles access was blocked +system.cpu.commit.branchMispredicts 359967 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 21665941 # The number of squashed insts skipped by commit +system.cpu.committedInsts 79591756 # Number of Instructions Simulated +system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated +system.cpu.cpi 14.205014 # CPI: Cycles Per Instruction +system.cpu.cpi_total 14.205014 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 19540231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 4453.766964 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3237.815878 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 19382637 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 701886951 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.008065 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 157594 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 95950 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 199591922 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003155 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61644 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 4830.124895 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3999.409028 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 13942631 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3239786953 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.045899 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 670746 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 527274 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 573803212 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009818 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 143472 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 3332.672727 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 3759.399862 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 162.470348 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 110 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 125901 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 366594 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 473312202 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 34158085 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4774.788349 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3808.508657 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33339306 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3909496430 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.023970 # miss rate for demand accesses -system.cpu.dcache.demand_misses 818779 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 617732 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 765689240 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005886 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 201047 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 34153608 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4758.521747 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3770.525625 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33325268 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 3941673904 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.024253 # miss rate for demand accesses +system.cpu.dcache.demand_misses 828340 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 623224 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 773395134 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.006006 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 205116 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 34158085 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4774.788349 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3808.508657 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 34153608 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4758.521747 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3770.525625 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33339306 # number of overall hits -system.cpu.dcache.overall_miss_latency 3909496430 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.023970 # miss rate for overall accesses -system.cpu.dcache.overall_misses 818779 # number of overall misses -system.cpu.dcache.overall_mshr_hits 617732 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 765689240 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005886 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 201047 # number of overall MSHR misses +system.cpu.dcache.overall_hits 33325268 # number of overall hits +system.cpu.dcache.overall_miss_latency 3941673904 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.024253 # miss rate for overall accesses +system.cpu.dcache.overall_misses 828340 # number of overall misses +system.cpu.dcache.overall_mshr_hits 623224 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 773395134 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.006006 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 205116 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 196951 # number of replacements -system.cpu.dcache.sampled_refs 201047 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 201020 # number of replacements +system.cpu.dcache.sampled_refs 205116 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4057.206862 # Cycle average of tags in use -system.cpu.dcache.total_refs 33339306 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 27763000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147199 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 11824495 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 95570 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3548160 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 129766996 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 51039022 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 25179247 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 4520828 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 280755 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 396764 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 26797394 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 22435045 # Number of cache lines fetched -system.cpu.fetch.Cycles 50869599 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 152238 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 146401648 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 3850495 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.288267 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 22435045 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 18003008 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.574883 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4057.039034 # Cycle average of tags in use +system.cpu.dcache.total_refs 33325268 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 27784000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147771 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 11948269 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 95198 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3558048 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 131593428 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 51674084 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 25481309 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 4702945 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 281359 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 401531 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 27047110 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 22733117 # Number of cache lines fetched +system.cpu.fetch.Cycles 51481541 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 159026 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 148267180 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 3966980 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.287100 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 22733117 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 18080227 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.573826 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 92960356 +system.cpu.fetch.rateDist.samples 94208138 system.cpu.fetch.rateDist.min_value 0 - 0 64525729 6941.21% - 1 1650999 177.60% - 2 1736489 186.80% - 3 1914591 205.96% - 4 6963270 749.06% - 5 6073717 653.37% - 6 756313 81.36% - 7 1939629 208.65% - 8 7399619 796.00% + 0 65459635 6948.41% + 1 1687117 179.08% + 2 1748812 185.63% + 3 1938924 205.81% + 4 6981531 741.08% + 5 6100701 647.58% + 6 758078 80.47% + 7 1979150 210.08% + 8 7554190 801.86% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 22435044 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3343.146524 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2355.643274 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 22333491 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 339506559 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.004527 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 101553 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 13791 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 206735965 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.003912 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 87762 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 22733116 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3345.551905 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2359.548288 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 22631700 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 339292492 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.004461 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 101416 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 13878 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 206550138 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.003851 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 87538 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 3964.923913 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 254.480817 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles_no_targets 3731.567010 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 258.538675 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 92 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 97 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 364773 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 361962 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 22435044 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3343.146524 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2355.643274 # average overall mshr miss latency -system.cpu.icache.demand_hits 22333491 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 339506559 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.004527 # miss rate for demand accesses -system.cpu.icache.demand_misses 101553 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 13791 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 206735965 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.003912 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 87762 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 22733116 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3345.551905 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2359.548288 # average overall mshr miss latency +system.cpu.icache.demand_hits 22631700 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 339292492 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.004461 # miss rate for demand accesses +system.cpu.icache.demand_misses 101416 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 13878 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 206550138 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.003851 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 87538 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 22435044 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3343.146524 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2355.643274 # average overall mshr miss latency +system.cpu.icache.overall_accesses 22733116 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3345.551905 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2359.548288 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 22333491 # number of overall hits -system.cpu.icache.overall_miss_latency 339506559 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.004527 # miss rate for overall accesses -system.cpu.icache.overall_misses 101553 # number of overall misses -system.cpu.icache.overall_mshr_hits 13791 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 206735965 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.003912 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 87762 # number of overall MSHR misses +system.cpu.icache.overall_hits 22631700 # number of overall hits +system.cpu.icache.overall_miss_latency 339292492 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.004461 # miss rate for overall accesses +system.cpu.icache.overall_misses 101416 # number of overall misses +system.cpu.icache.overall_mshr_hits 13878 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 206550138 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.003851 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 87538 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,80 +215,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 85714 # number of replacements -system.cpu.icache.sampled_refs 87761 # Sample count of references to valid blocks. +system.cpu.icache.replacements 85490 # number of replacements +system.cpu.icache.sampled_refs 87537 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1835.660061 # Cycle average of tags in use -system.cpu.icache.total_refs 22333491 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1835.330854 # Cycle average of tags in use +system.cpu.icache.total_refs 22631700 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1028044659 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14368697 # Number of branches executed -system.cpu.iew.EXEC:nop 9207761 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.998957 # Inst execution rate -system.cpu.iew.EXEC:refs 42889191 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15296362 # Number of stores executed +system.cpu.idleCycles 1036393877 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14379719 # Number of branches executed +system.cpu.iew.EXEC:nop 9265977 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.989418 # Inst execution rate +system.cpu.iew.EXEC:refs 43156162 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15338261 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 46149810 # num instructions consuming a value -system.cpu.iew.WB:count 85978243 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.741638 # average fanout of values written-back +system.cpu.iew.WB:consumers 46157981 # num instructions consuming a value +system.cpu.iew.WB:count 86105601 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.741496 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 34226464 # num instructions producing a value -system.cpu.iew.WB:rate 0.924891 # insts written-back per cycle -system.cpu.iew.WB:sent 86043563 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 388948 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3476074 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 28503669 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 5221 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1221579 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 16218894 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 109084579 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 27592829 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 454683 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 92863355 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 28537 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 34225955 # num instructions producing a value +system.cpu.iew.WB:rate 0.913993 # insts written-back per cycle +system.cpu.iew.WB:sent 86171133 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 389534 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3213991 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 28863760 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 4784 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1402526 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 16312214 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 110003367 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 27817901 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 453087 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 93211232 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 28742 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 13436 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 4520828 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 193035 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1537 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 6697780 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 1365345 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 4018 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.iewLSQFullEvents 12962 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 4702945 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 194395 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1528 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 6922047 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 1365052 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5008 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 3952 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1537 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 8120624 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1372564 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 3952 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 217352 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 171596 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.071020 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.071020 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 93318038 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 3825 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1528 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 8484361 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1467595 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 3825 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 102872 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 286662 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.070398 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.070398 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 93664319 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 49917747 53.49% # Type of FU issued - IntMult 43212 0.05% # Type of FU issued + IntAlu 49995908 53.38% # Type of FU issued + IntMult 43196 0.05% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 123778 0.13% # Type of FU issued - FloatCmp 88 0.00% # Type of FU issued - FloatCvt 122460 0.13% # Type of FU issued - FloatMult 54 0.00% # Type of FU issued - FloatDiv 37863 0.04% # Type of FU issued + FloatAdd 123595 0.13% # Type of FU issued + FloatCmp 86 0.00% # Type of FU issued + FloatCvt 122386 0.13% # Type of FU issued + FloatMult 51 0.00% # Type of FU issued + FloatDiv 37853 0.04% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 27694961 29.68% # Type of FU issued - MemWrite 15377875 16.48% # Type of FU issued + MemRead 27919833 29.81% # Type of FU issued + MemWrite 15421411 16.46% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 1239796 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013286 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 1229792 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013130 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 81158 6.55% # attempts to use FU when none available + IntAlu 83895 6.82% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,84 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 587235 47.37% # attempts to use FU when none available - MemWrite 571403 46.09% # attempts to use FU when none available + MemRead 589327 47.92% # attempts to use FU when none available + MemWrite 556570 45.26% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 92960356 +system.cpu.iq.ISSUE:issued_per_cycle.samples 94208138 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 53328498 5736.69% - 1 13184129 1418.25% - 2 10577669 1137.87% - 3 8760562 942.40% - 4 4405028 473.86% - 5 1612052 173.41% - 6 698100 75.10% - 7 326631 35.14% - 8 67687 7.28% + 0 54322746 5766.25% + 1 13333515 1415.33% + 2 10626230 1127.95% + 3 8813553 935.54% + 4 4440243 471.32% + 5 1597603 169.58% + 6 685526 72.77% + 7 334234 35.48% + 8 54488 5.78% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.003848 # Inst issue rate -system.cpu.iq.iqInstsAdded 99871597 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 93318038 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 5221 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 20057396 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 77651 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 515 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 15480029 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 288801 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3932.513738 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2042.965502 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 119343 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 666395913 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.586764 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 169458 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 346196848 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.586764 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 169458 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 147199 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 146588 # number of WriteReqNoAck|Writeback hits -system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.004151 # miss rate for WriteReqNoAck|Writeback accesses -system.cpu.l2cache.WriteReqNoAck|Writeback_misses 611 # number of WriteReqNoAck|Writeback misses -system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.004151 # mshr miss rate for WriteReqNoAck|Writeback accesses -system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 611 # number of WriteReqNoAck|Writeback MSHR misses +system.cpu.iq.ISSUE:rate 0.994227 # Inst issue rate +system.cpu.iq.iqInstsAdded 100732606 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 93664319 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 4784 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 20911338 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 73995 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 201 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 16334966 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 292646 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3929.598028 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2043.469607 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 122985 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 666699531 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.579748 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 169661 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 346697097 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.579748 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 169661 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147771 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 147307 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.003140 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 464 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.003140 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 464 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.569313 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.593139 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 288801 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3932.513738 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2042.965502 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 119343 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 666395913 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.586764 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 169458 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 292646 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3929.598028 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2043.469607 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 122985 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 666699531 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.579748 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 169661 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 346196848 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.586764 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 169458 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 346697097 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.579748 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 169661 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 436000 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3918.385555 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2042.965502 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 440417 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3918.880417 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2043.469607 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 265931 # number of overall hits -system.cpu.l2cache.overall_miss_latency 666395913 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.390067 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 170069 # number of overall misses +system.cpu.l2cache.overall_hits 270292 # number of overall hits +system.cpu.l2cache.overall_miss_latency 666699531 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.386282 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 170125 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 346196848 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.388665 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 169458 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 346697097 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.385228 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 169661 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -386,32 +386,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 136689 # number of replacements -system.cpu.l2cache.sampled_refs 169457 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 136892 # number of replacements +system.cpu.l2cache.sampled_refs 169660 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 30306.924097 # Cycle average of tags in use -system.cpu.l2cache.total_refs 265931 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 442261000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 115687 # number of writebacks -system.cpu.numCycles 92960356 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 7634208 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 52562815 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 86713 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 51709233 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 3226687 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 2442 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 152860701 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 128373944 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 81757058 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 24895195 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 4520828 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 3457989 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 29194243 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 742903 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 5237 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 6117149 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 5235 # count of temporary serializing insts renamed -system.cpu.timesIdled 271656 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 4706 # Number of system calls +system.cpu.l2cache.tagsinuse 30349.297230 # Cycle average of tags in use +system.cpu.l2cache.total_refs 270292 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 625483000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 115938 # number of writebacks +system.cpu.numCycles 94208138 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 7563765 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 87866 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 52361095 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 3315491 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 3509 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 154857350 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 130101763 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 82913656 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 25182526 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 4702945 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 3542613 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 30366775 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 855194 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 4773 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 6398047 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 4771 # count of temporary serializing insts renamed +system.cpu.timesIdled 275758 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.msg b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg index 327142d7c..327142d7c 100644 --- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.msg +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.out b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.out index 726b45c60..726b45c60 100644 --- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.out +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.out diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr new file mode 100644 index 000000000..eb1796ead --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr @@ -0,0 +1,2 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout index e69de29bb..e69de29bb 100644 --- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini index 6d8732496..179e8ea77 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini @@ -7,21 +7,6 @@ max_tick=0 output_file=cout progress_interval=0 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - [serialize] count=10 cycle=0 @@ -74,11 +59,11 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic egid=100 env= euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin output=cout @@ -100,14 +85,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out index 38f919464..725aaed50 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out @@ -10,6 +10,7 @@ type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -26,11 +27,11 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic system=system uid=100 euid=100 @@ -57,15 +58,6 @@ function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - [stats] descriptions=true project_name=test @@ -83,25 +75,6 @@ dump_cycle=0 dump_period=0 ignore_events= -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - [statsreset] reset_cycle=0 diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt index d73ff13a7..9c60e1316 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 857494 # Simulator instruction rate (inst/s) -host_mem_usage 149092 # Number of bytes of host memory used -host_seconds 103.05 # Real time elapsed on the host -host_tick_rate 857491 # Simulator tick rate (ticks/s) +host_inst_rate 1347543 # Simulator instruction rate (inst/s) +host_mem_usage 179988 # Number of bytes of host memory used +host_seconds 65.56 # Real time elapsed on the host +host_tick_rate 1347535 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 88361899 # Number of instructions simulated +sim_insts 88340674 # Number of instructions simulated sim_seconds 0.000088 # Number of seconds simulated -sim_ticks 88361898 # Number of ticks simulated +sim_ticks 88340673 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 88361899 # number of cpu cycles simulated -system.cpu.num_insts 88361899 # Number of instructions executed -system.cpu.num_refs 35229376 # Number of memory references -system.cpu.workload.PROG:num_syscalls 4706 # Number of system calls +system.cpu.numCycles 88340674 # number of cpu cycles simulated +system.cpu.num_insts 88340674 # Number of instructions executed +system.cpu.num_refs 35224019 # Number of memory references +system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.msg b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg index 327142d7c..327142d7c 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.msg +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.out b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.out index 726b45c60..726b45c60 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.out +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.out diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr new file mode 100644 index 000000000..eb1796ead --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr @@ -0,0 +1,2 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout index e69de29bb..e69de29bb 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 3e5bdc569..0e1a3c9f1 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -7,21 +7,6 @@ max_tick=0 output_file=cout progress_interval=0 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - [serialize] count=10 cycle=0 @@ -197,11 +182,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing egid=100 env= euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin output=cout @@ -223,14 +208,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out index 9ecf4b55d..0dc85858d 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out @@ -10,6 +10,7 @@ type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -26,11 +27,11 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing system=system uid=100 euid=100 @@ -178,15 +179,6 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - [stats] descriptions=true project_name=test @@ -204,25 +196,6 @@ dump_cycle=0 dump_period=0 ignore_events= -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - [statsreset] reset_cycle=0 diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt index ae340ffef..9a9778162 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 471701 # Simulator instruction rate (inst/s) -host_mem_usage 255440 # Number of bytes of host memory used -host_seconds 187.33 # Real time elapsed on the host -host_tick_rate 6446013 # Simulator tick rate (ticks/s) +host_inst_rate 704446 # Simulator instruction rate (inst/s) +host_mem_usage 275648 # Number of bytes of host memory used +host_seconds 125.40 # Real time elapsed on the host +host_tick_rate 9716991 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 88361899 # Number of instructions simulated -sim_seconds 0.001208 # Number of seconds simulated -sim_ticks 1207510003 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 20281385 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3631.637073 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2631.637073 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20223321 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 210867375 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002863 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 58064 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 152803375 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002863 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 58064 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 14615683 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4569.538784 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3569.538784 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 14473602 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 649244640 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.009721 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 142081 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 507163640 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009721 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 142081 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 173.358930 # Average number of references to valid blocks. +sim_insts 88340674 # Number of instructions simulated +sim_seconds 0.001219 # Number of seconds simulated +sim_ticks 1218558003 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3613.021476 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2613.021476 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 219545250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 158780250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 4540.238491 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3540.238491 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 651878362 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 508300362 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 34897068 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4297.444428 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3297.444428 # average overall mshr miss latency -system.cpu.dcache.demand_hits 34696923 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 860112015 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005735 # miss rate for demand accesses -system.cpu.dcache.demand_misses 200145 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4264.514136 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency +system.cpu.dcache.demand_hits 34685672 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 871423612 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses +system.cpu.dcache.demand_misses 204343 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 659967015 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005735 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 200145 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 667080612 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 204343 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 34897068 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4297.444428 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3297.444428 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 34696923 # number of overall hits -system.cpu.dcache.overall_miss_latency 860112015 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005735 # miss rate for overall accesses -system.cpu.dcache.overall_misses 200145 # number of overall misses +system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4264.514136 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 34685672 # number of overall hits +system.cpu.dcache.overall_miss_latency 871423612 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses +system.cpu.dcache.overall_misses 204343 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 659967015 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005735 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 200145 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 667080612 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 204343 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -73,57 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 196049 # number of replacements -system.cpu.dcache.sampled_refs 200145 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200247 # number of replacements +system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4056.501584 # Cycle average of tags in use -system.cpu.dcache.total_refs 34696923 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 28890000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147135 # number of writebacks -system.cpu.icache.ReadReq_accesses 88361900 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2933.039863 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1933.039863 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 88285387 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 224415679 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000866 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 76513 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 147902679 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000866 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 76513 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1153.861265 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 4056.438323 # Cycle average of tags in use +system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 28900000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147714 # number of writebacks +system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2932.969818 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1932.969818 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 224184481 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 147748481 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1154.746965 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 88361900 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2933.039863 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1933.039863 # average overall mshr miss latency -system.cpu.icache.demand_hits 88285387 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 224415679 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000866 # miss rate for demand accesses -system.cpu.icache.demand_misses 76513 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2932.969818 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency +system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 224184481 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses +system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 147902679 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000866 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 76513 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 147748481 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 88361900 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2933.039863 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1933.039863 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 88285387 # number of overall hits -system.cpu.icache.overall_miss_latency 224415679 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000866 # miss rate for overall accesses -system.cpu.icache.overall_misses 76513 # number of overall misses +system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2932.969818 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 88264239 # number of overall hits +system.cpu.icache.overall_miss_latency 224184481 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses +system.cpu.icache.overall_misses 76436 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 147902679 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000866 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 76513 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 147748481 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -135,64 +135,64 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 74468 # number of replacements -system.cpu.icache.sampled_refs 76513 # Sample count of references to valid blocks. +system.cpu.icache.replacements 74391 # number of replacements +system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1798.721885 # Cycle average of tags in use -system.cpu.icache.total_refs 88285387 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1796.106842 # Cycle average of tags in use +system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 276658 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3650.746755 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1972.771607 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 108220 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 614924482 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.608831 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 168438 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 332289704 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.608831 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 168438 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 147135 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 146550 # number of WriteReqNoAck|Writeback hits -system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.003976 # miss rate for WriteReqNoAck|Writeback accesses -system.cpu.l2cache.WriteReqNoAck|Writeback_misses 585 # number of WriteReqNoAck|Writeback misses -system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.003976 # mshr miss rate for WriteReqNoAck|Writeback accesses -system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 585 # number of WriteReqNoAck|Writeback MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.512545 # Average number of references to valid blocks. +system.cpu.l2cache.ReadReq_accesses 280779 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3650.218185 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1972.851350 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 112101 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 615711503 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.600750 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 168678 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 332776620 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.600750 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 168678 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 147276 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.002965 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 438 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.002965 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 438 # number of Writeback MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 1.537705 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 276658 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3650.746755 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1972.771607 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 108220 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 614924482 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.608831 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 168438 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3650.218185 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 112101 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 615711503 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.600750 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 168678 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 332289704 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.608831 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 168438 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 332776620 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.600750 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 168678 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 423793 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3638.111275 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1972.771607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 254770 # number of overall hits -system.cpu.l2cache.overall_miss_latency 614924482 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.398834 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 169023 # number of overall misses +system.cpu.l2cache.overall_accesses 428493 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3640.764345 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 259377 # number of overall hits +system.cpu.l2cache.overall_miss_latency 615711503 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.394676 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 169116 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 332289704 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.397453 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 168438 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 332776620 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.393654 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 168678 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -204,17 +204,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 135670 # number of replacements -system.cpu.l2cache.sampled_refs 168438 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 135910 # number of replacements +system.cpu.l2cache.sampled_refs 168678 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 30358.430189 # Cycle average of tags in use -system.cpu.l2cache.total_refs 254770 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 475381000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 115647 # number of writebacks +system.cpu.l2cache.tagsinuse 30401.731729 # Cycle average of tags in use +system.cpu.l2cache.total_refs 259377 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 667816000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 115911 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1207510003 # number of cpu cycles simulated -system.cpu.num_insts 88361899 # Number of instructions executed -system.cpu.num_refs 35229376 # Number of memory references -system.cpu.workload.PROG:num_syscalls 4706 # Number of system calls +system.cpu.numCycles 1218558003 # number of cpu cycles simulated +system.cpu.num_insts 88340674 # Number of instructions executed +system.cpu.num_refs 35224019 # Number of memory references +system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.msg b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg index 327142d7c..327142d7c 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.msg +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.out b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.out index 726b45c60..726b45c60 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.out +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.out diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr new file mode 100644 index 000000000..eb1796ead --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr @@ -0,0 +1,2 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout index e69de29bb..e69de29bb 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini new file mode 100644 index 000000000..7dbc37b58 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -0,0 +1,64 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=workload +clock=1 +cpu_id=0 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +simulate_stalls=false +system=system +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.workload] +type=LiveProcess +cmd=vortex bendian.raw +cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out new file mode 100644 index 000000000..ee1fc877f --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out @@ -0,0 +1,57 @@ +[root] +type=Root +dummy=0 + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 +zero=false + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.workload] +type=LiveProcess +cmd=vortex bendian.raw +executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex +input=cin +output=cout +env= +cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt new file mode 100644 index 000000000..323b8a93c --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 638506 # Simulator instruction rate (inst/s) +host_mem_usage 150340 # Number of bytes of host memory used +host_seconds 213.38 # Real time elapsed on the host +host_tick_rate 638505 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 136246936 # Number of instructions simulated +sim_seconds 0.000136 # Number of seconds simulated +sim_ticks 136246935 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 136246936 # number of cpu cycles simulated +system.cpu.num_insts 136246936 # Number of instructions executed +system.cpu.num_refs 58111522 # Number of memory references +system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.msg b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.msg new file mode 100644 index 000000000..0ac2d9980 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.msg @@ -0,0 +1,158 @@ + + SYSTEM TYPE... + __ZTC__ := False + __UNIX__ := True + __RISC__ := True + SPEC_CPU2000_LP64 := False + __MAC__ := False + __BCC__ := False + __BORLANDC__ := False + __GUI__ := False + __WTC__ := False + __HP__ := False + + CODE OPTIONS... + __MACROIZE_HM__ := True + __MACROIZE_MEM__ := True + ENV01 := True + USE_HPP_STYPE_HDRS := False + USE_H_STYPE_HDRS := False + + CODE INCLUSION PARAMETERS... + INCLUDE_ALL_CODE := False + INCLUDE_DELETE_CODE := True + __SWAP_GRP_POS__ := True + __INCLUDE_MTRX__ := False + __BAD_CODE__ := False + API_INCLUDE := False + BE_CAREFUL := False + OLDWAY := False + NOTUSED := False + + SYSTEM PARAMETERS... + EXT_ENUM := 999999999L + CHUNK_CONSTANT := 55555555 + CORE_CONSTANT := 55555555 + CORE_LIMIT := 20971520 + CorePage_Size := 384000 + ALIGN_BYTES := True + CORE_BLOCK_ALIGN := 8 + FAR_MEM := False + + MEMORY MANAGEMENT PARAMETERS... + SYSTEM_ALLOC := True + SYSTEM_FREESTORE := True + __NO_DISKCACHE__ := False + __FREEZE_VCHUNKS__ := True + __FREEZE_GRP_PACKETS__ := True + __MINIMIZE_TREE_CACHE__:= True + + SYSTEM STD PARAMETERS... + __STDOUT__ := False + NULL := 0 + LPTR := False + False_Status := 1 + True_Status := 0 + LARGE := True + TWOBYTE_BOOL := False + __NOSTR__ := False + + MEMORY VALIDATION PARAMETERS... + CORE_CRC_CHECK := False + VALIDATE_MEM_CHUNKS := False + + SYSTEM DEBUG OPTIONS... + DEBUG := False + MCSTAT := False + TRACKBACK := False + FLUSH_FILES := False + DEBUG_CORE0 := False + DEBUG_RISC := False + __TREE_BUG__ := False + __TRACK_FILE_READS__ := False + PAGE_SPACE := False + LEAVE_NO_TRACE := True + NULL_TRACE_STRS := False + + TIME PARAMETERS... + CLOCK_IS_LONG := False + __DISPLAY_TIME__ := False + __TREE_TIME__ := False + __DISPLAY_ERRORS__ := False + + API MACROS... + __BMT01__ := True + OPTIMIZE := True + + END OF DEFINES. + + + + ... IMPLODE MEMORY ... + + SWAP to DiskCache := False + + FREEZE_GRP_PACKETS:= True + + QueBug := 1000 + + sizeof(boolean) = 4 + sizeof(sizetype) = 4 + sizeof(chunkstruc) = 32 + + sizeof(shorttype ) = 2 + sizeof(idtype ) = 2 + sizeof(sizetype ) = 4 + sizeof(indextype ) = 4 + sizeof(numtype ) = 4 + sizeof(handletype) = 4 + sizeof(tokentype ) = 8 + + sizeof(short ) = 2 + sizeof(int ) = 4 + + sizeof(lt64 ) = 4 + sizeof(farlongtype) = 4 + sizeof(long ) = 4 + sizeof(longaddr ) = 4 + + sizeof(float ) = 4 + sizeof(double ) = 8 + + sizeof(addrtype ) = 4 + sizeof(char * ) = 4 + ALLOC CORE_1 :: 8 + BHOOLE NATH + + OPEN File ./input/bendian.rnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 2030c0 + DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] + DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] + DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] + DB Handle Chunk's StackPtr = 20797 + + DB[ 1] LOADED; Handles= 20797 + KERNEL in CORE[ 1] Restored @ 1b4750 + + OPEN File ./input/bendian.wnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 21c40 + DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] + DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] + DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] + DB Handle Chunk's StackPtr = 17 + + DB[ 2] LOADED; Handles= 17 + VORTEx_Status == -8 || fffffff8 + + BE HERE NOW !!! + + + + ... VORTEx ON LINE ... + + + ... END OF SESSION ... diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.out b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.out new file mode 100644 index 000000000..726b45c60 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.out @@ -0,0 +1,258 @@ + CREATE Db Header and Db Primal ... + NEW DB [ 3] Created. + +VORTEX INPUT PARAMETERS:: + MESSAGE FileName: smred.msg + OUTPUT FileName: smred.out + DISK CACHE FileName: NULL + PART DB FileName: parts.db + DRAW DB FileName: draw.db + PERSON DB FileName: emp.db + PERSONS Data FileName: ./input/persons.250 + PARTS Count : 100 + OUTER Loops : 1 + INNER Loops : 1 + LOOKUP Parts : 25 + DELETE Parts : 10 + STUFF Parts : 10 + DEPTH Traverse: 5 + % DECREASE Parts : 0 + % INCREASE LookUps : 0 + % INCREASE Deletes : 0 + % INCREASE Stuffs : 0 + FREEZE_PACKETS : 1 + ALLOC_CHUNKS : 10000 + EXTEND_CHUNKS : 5000 + DELETE Draw objects : True + DELETE Part objects : False + QUE_BUG : 1000 + VOID_BOUNDARY : 67108864 + VOID_RESERVE : 1048576 + + COMMIT_DBS : False + + + + BMT TEST :: files... + EdbName := PartLib + EdbFileName := parts.db + DrwName := DrawLib + DrwFileName := draw.db + EmpName := PersonLib + EmpFileName := emp.db + + Swap to DiskCache := False + Freeze the cache := True + + + BMT TEST :: parms... + DeBug modulo := 1000 + Create Parts count:= 100 + Outer Loops := 1 + Inner Loops := 1 + Look Ups := 25 + Delete Parts := 10 + Stuff Parts := 10 + Traverse Limit := 5 + Delete Draws := True + Delete Parts := False + Delete ALL Parts := after every <mod 0>Outer Loop + + INITIALIZE LIBRARY :: + + INITIALIZE SCHEMA :: + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 4] Created. + PartLibCreate:: Db[ 4]; VpartsDir= 1 + + Part Count= 1 + + Initialize the Class maps + LIST HEADS loaded ... DbListHead_Class = 207 + DbListNode_Class = 206 + +...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. + + +...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. + + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 5] Created. + DrawLibCreate:: Db[ 5]; VpartsDir= 1 + + Initialize the Class maps of this schema. + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 6] Created. + + ***NOTE*** Persons Library Extended! + + Create <131072> Persons. + ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; + + LAST Person Read:: + ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; + + BUILD <Query0> for <Part2> class:: + + if (link[1].length >= 5) :: + + Build Query2 for <Address> class:: + + if (State == CA || State == T*) + + Build Query1 for <Person> class:: + + if (LastName >= H* && LastName <= P* && Query0(Residence)) :: + + BUILD <Query3> for <DrawObj> class:: + + if (Id >= 3000 + && (Id >= 3000 && Id <= 3001) + && Id >= 3002) + + BUILD <Query4> for <NamedDrawObj> class:: + + if (Nam == Pre* + || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post + || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) + && Id <= 7) + SEED := 1008; Swap = False; RgnEntries = 135 + + OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. + + Create 100 New Parts + Create Part 1. Token[ 4: 2]. + + < 100> Parts Created. CurrentId= 100 + + Connect each instantiated Part TO 3 unique Parts + Connect Part 1. Token[ 4: 2] + Connect Part 25. Token[ 4: 26] FromList= 26. + Connect Part 12. Token[ 4: 13] FromList= 13. + Connect Part 59. Token[ 4: 60] FromList= 60. + + SET <DrawObjs> entries:: + 1. [ 5: 5] := <1 >; @[: 6] + Iteration count = 100 + + SET <NamedDrawObjs> entries:: + 1. [ 5: 39] := <14 >; + Iteration count = 12 + + SET <LibRectangles> entries:: + 1. [ 5: 23] := <8 >; @[: 24] + Iteration count = 12 + + LIST <DbRectangles> entries:: + 1. [ 5: 23] + Iteration count = 12 + + SET <PersonNames > entries:: + Iteration count = 250 + + COMMIT All Image copies:: Release=<True>; Max Parts= 100 + < 100> Part images' Committed. + < 0> are Named. + < 50> Point images' Committed. + < 81> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. TestObj Committed. + < 0> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 0: 0]. CartesianPoint Committed. + < 0> CartesianPoint images' Committed. + + BEGIN Inner Loop Sequence::. + + INNER LOOP [ 1: 1] : + + LOOK UP 25 Random Parts and Export each Part. + + LookUp for 26 parts; Asserts = 8 + <Part2 > Asserts = 2; NULL Asserts = 3. + <DrawObj > Asserts = 0; NULL Asserts = 5. + <NamedObj > Asserts = 0; NULL Asserts = 0. + <Person > Asserts = 0; NULL Asserts = 5. + <TestObj > Asserts = 60; NULL Asserts = 0. + + DELETE 10 Random Parts. + + PartDelete :: Token[ 4: 91]. + PartDisconnect:: Token[ 4: 91] id:= 90 for each link. + DisConnect link [ 0]:= 50; PartToken[ 51: 51]. + DisConnect link [ 1]:= 17; PartToken[ 18: 18]. + DisConnect link [ 2]:= 72; PartToken[ 73: 73]. + DeleteFromList:: Vchunk[ 4: 91]. (* 1) + DisConnect FromList[ 0]:= 56; Token[ 57: 57]. + Vlists[ 89] := 100; + + Delete for 11 parts; + + Traverse Count= 0 + + TRAVERSE PartId[ 6] and all Connections to 5 Levels + SEED In Traverse Part [ 4: 65] @ Level = 4. + + Traverse Count= 357 + Traverse Asserts = 5. True Tests = 1 + < 5> DrawObj objects DELETED. + < 2> are Named. + < 2> Point objects DELETED. + + CREATE 10 Additional Parts + + Create 10 New Parts + Create Part 101. Token[ 4: 102]. + + < 10> Parts Created. CurrentId= 110 + + Connect each instantiated Part TO 3 unique Parts + + COMMIT All Image copies:: Release=<True>; Max Parts= 110 + < 81> Part images' Committed. + < 0> are Named. + < 38> Point images' Committed. + < 31> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Committed. + < 15> TestObj images' Committed. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Committed. + < 16> CartesianPoint images' Committed. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + ItNum 0. Token[ 3: 4]. TestObj Deleted. + < 15> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. + < 16> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + + END INNER LOOP [ 1: 1]. + + DELETE All TestObj objects; + + Delete TestObj_Class in <Primal> DB. + < 0> TestObj objects Deleted. + + Commit CartesianPoint_Class in <Primal> DB. + < 0> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + STATUS= -201 +V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr new file mode 100644 index 000000000..c0f1c1fbb --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr @@ -0,0 +1,569 @@ +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x1838c0 length 0x10. +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x0 length 0x0. +0: system.remote_gdb.listener: listening for remote gdb on port 7001 +warn: Entering event queue @ 0. Starting simulation... +warn: Ignoring request to flush register windows. +warn: ignoring syscall time(4026527856, 4026528256, ...) +warn: ignoring syscall time(4026527408, 1375098, ...) +warn: ignoring syscall time(4026527320, 1, ...) +warn: ignoring syscall time(4026527056, 413, ...) +warn: ignoring syscall time(4026527056, 414, ...) +warn: ignoring syscall time(4026527296, 4026527696, ...) +warn: ignoring syscall time(4026526848, 1375098, ...) +warn: Increasing stack size by one page. +warn: ignoring syscall time(4026527056, 409, ...) +warn: ignoring syscall time(4026527056, 409, ...) +warn: ignoring syscall time(4026526968, 409, ...) +warn: ignoring syscall time(4026527048, 409, ...) +warn: ignoring syscall time(4026527008, 409, ...) +warn: ignoring syscall time(4026526992, 409, ...) +warn: ignoring syscall time(4026526992, 409, ...) +warn: ignoring syscall time(4026526880, 409, ...) +warn: ignoring syscall time(4026526320, 19045, ...) +warn: ignoring syscall time(4026526840, 409, ...) +warn: ignoring syscall time(4026526880, 409, ...) +warn: ignoring syscall time(4026526880, 409, ...) +warn: ignoring syscall time(4026526856, 409, ...) +warn: ignoring syscall time(4026526848, 409, ...) +warn: ignoring syscall time(4026526880, 409, ...) +warn: ignoring syscall time(4026526864, 409, ...) +warn: ignoring syscall time(4026526856, 409, ...) +warn: ignoring syscall time(4026526944, 409, ...) +warn: ignoring syscall time(4026527016, 4026527416, ...) +warn: ignoring syscall time(4026526568, 1375098, ...) +warn: ignoring syscall time(4026527192, 18732, ...) +warn: ignoring syscall time(4026526640, 409, ...) +warn: ignoring syscall time(4026526744, 0, ...) +warn: ignoring syscall time(4026527328, 0, ...) +warn: ignoring syscall time(4026527752, 225, ...) +warn: ignoring syscall time(4026527056, 409, ...) +warn: ignoring syscall time(4026526864, 409, ...) +warn: ignoring syscall time(4026526880, 409, ...) +warn: ignoring syscall time(4026527104, 4026527504, ...) +warn: ignoring syscall time(4026526656, 1375098, ...) +warn: ignoring syscall time(4026526832, 0, ...) +warn: ignoring syscall time(4026527328, 0, ...) +warn: ignoring syscall time(4026527192, 1879089152, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall times(4026527736, 246, ...) +warn: ignoring syscall time(4026527480, 1595768, ...) +warn: ignoring syscall time(4026526920, 17300, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026526920, 19045, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026527480, 0, ...) +warn: ignoring syscall time(4026526920, 19045, ...) +warn: ignoring syscall time(4026526920, 17300, ...) +warn: ignoring syscall time(4026525976, 20500, ...) +warn: ignoring syscall time(4026525976, 4026526444, ...) +warn: ignoring syscall time(4026526064, 7004192, ...) +warn: ignoring syscall time(4026527520, 4, ...) +warn: ignoring syscall time(4026525768, 0, ...) diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout new file mode 100644 index 000000000..8e5f7bf90 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout @@ -0,0 +1,13 @@ +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 21 2007 00:48:18 +M5 started Wed Mar 21 00:48:40 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic tests/run.py long/50.vortex/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 136246935 because target called exit() diff --git a/tests/long/50.vortex/test.py b/tests/long/50.vortex/test.py index bd57ef6e6..fbf0dc081 100644 --- a/tests/long/50.vortex/test.py +++ b/tests/long/50.vortex/test.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -29,5 +29,5 @@ m5.AddToPath('../configs/common') from cpu2000 import vortex -workload = vortex('alpha', 'tru64', 'smred') +workload = vortex(isa, opsys, 'smred') root.system.cpu.workload = workload.makeLiveProcess() diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr deleted file mode 100644 index 87866a2a5..000000000 --- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr +++ /dev/null @@ -1 +0,0 @@ -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr deleted file mode 100644 index 87866a2a5..000000000 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr +++ /dev/null @@ -1 +0,0 @@ -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr deleted file mode 100644 index 87866a2a5..000000000 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr +++ /dev/null @@ -1 +0,0 @@ -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 7a3bd9383..9ae62655d 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -388,7 +388,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/linux/o3-timing egid=100 env= euid=100 @@ -414,14 +414,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out index 1077b5dd7..690cc5723 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out @@ -10,6 +10,7 @@ type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,7 +31,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/linux/o3-timing system=system uid=100 euid=100 @@ -366,15 +367,6 @@ clock=1000 width=64 responder_set=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - [stats] descriptions=true project_name=test @@ -392,9 +384,6 @@ dump_cycle=0 dump_period=0 ignore_events= -[random] -seed=1 - [exetrace] speculative=true print_cycle=true diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt index 73d6efd18..bc6866525 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 20658855 # Nu global.BPredUnit.condPredicted 1028649695 # Number of conditional branches predicted global.BPredUnit.lookups 1098978166 # Number of BP lookups global.BPredUnit.usedRAS 20738311 # Number of times the RAS was used to get a target. -host_inst_rate 27542 # Simulator instruction rate (inst/s) -host_mem_usage 1254844 # Number of bytes of host memory used -host_seconds 63032.08 # Real time elapsed on the host -host_tick_rate 395232 # Simulator tick rate (ticks/s) +host_inst_rate 28281 # Simulator instruction rate (inst/s) +host_mem_usage 1256892 # Number of bytes of host memory used +host_seconds 61385.49 # Real time elapsed on the host +host_tick_rate 405833 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 114920109 # Number of conflicting loads. memdepunit.memDep.conflictingStores 60881817 # Number of conflicting stores. memdepunit.memDep.insertedLoads 938731548 # Number of loads inserted to the mem dependence unit. @@ -263,8 +263,8 @@ system.cpu.iew.lsq.thread.0.rescheduledLoads 8 system.cpu.iew.lsq.thread.0.squashedLoads 493065187 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 228404712 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 47985 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 11190791 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 10765863 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 726441 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 21230213 # Number of branches that were predicted taken incorrectly system.cpu.ipc 0.069686 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.069686 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 3011765231 # Type of FU issued @@ -335,12 +335,12 @@ system.cpu.l2cache.ReadReq_misses 2169165 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 4503266483 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236340 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 2169165 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 2244715 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 2215400 # number of WriteReqNoAck|Writeback hits -system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.013060 # miss rate for WriteReqNoAck|Writeback accesses -system.cpu.l2cache.WriteReqNoAck|Writeback_misses 29315 # number of WriteReqNoAck|Writeback misses -system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.013060 # mshr miss rate for WriteReqNoAck|Writeback accesses -system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 29315 # number of WriteReqNoAck|Writeback MSHR misses +system.cpu.l2cache.Writeback_accesses 2244715 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2215400 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.013060 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 29315 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.013060 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 29315 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 4.252507 # Average number of references to valid blocks. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr new file mode 100644 index 000000000..cdd59eda7 --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr @@ -0,0 +1,2 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7006 +warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout index 0c5c00118..0c5c00118 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini index ad57a5293..ad57a5293 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out index 891519c26..891519c26 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt index 7422e3ae7..7422e3ae7 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr index 87866a2a5..87866a2a5 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout index 0c5c00118..0c5c00118 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 0a123d4a4..0a123d4a4 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out index 4692c5d40..4692c5d40 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt index 45b7beb7c..45b7beb7c 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr index 87866a2a5..87866a2a5 100644 --- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout index 0c5c00118..0c5c00118 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout diff --git a/tests/long/60.bzip2/test.py b/tests/long/60.bzip2/test.py index 362ca524e..7fa3d1a07 100644 --- a/tests/long/60.bzip2/test.py +++ b/tests/long/60.bzip2/test.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -29,5 +29,5 @@ m5.AddToPath('../configs/common') from cpu2000 import bzip2_source -workload = bzip2_source('alpha', 'tru64', 'lgred') +workload = bzip2_source(isa, opsys, 'lgred') root.system.cpu.workload = workload.makeLiveProcess() diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr b/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr deleted file mode 100644 index 87866a2a5..000000000 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr +++ /dev/null @@ -1 +0,0 @@ -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr deleted file mode 100644 index 87866a2a5..000000000 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr +++ /dev/null @@ -1 +0,0 @@ -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr deleted file mode 100644 index 87866a2a5..000000000 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr +++ /dev/null @@ -1 +0,0 @@ -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index fb3d24c55..5604f880f 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -7,43 +7,6 @@ max_tick=0 output_file=cout progress_interval=0 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt - [system] type=System children=cpu membus physmem @@ -388,11 +351,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/o3-timing egid=100 env= euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin output=cout @@ -414,14 +377,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out index e4ed95acf..a78c52d7f 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out @@ -10,6 +10,7 @@ type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -26,11 +27,11 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=twolf smred -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/twolf input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/o3-timing system=system uid=100 euid=100 @@ -366,51 +367,3 @@ clock=1000 width=64 responder_set=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt index dfa1fbe0b..c77face31 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 11837684 # Number of BTB hits -global.BPredUnit.BTBLookups 15197122 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1217 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1998573 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 12917224 # Number of conditional branches predicted -global.BPredUnit.lookups 17533197 # Number of BP lookups -global.BPredUnit.usedRAS 1687018 # Number of times the RAS was used to get a target. -host_inst_rate 57997 # Simulator instruction rate (inst/s) -host_mem_usage 178748 # Number of bytes of host memory used -host_seconds 1423.90 # Real time elapsed on the host -host_tick_rate 73521 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 10104667 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 3292311 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 29530804 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 9370879 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 11848811 # Number of BTB hits +global.BPredUnit.BTBLookups 15227898 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1227 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 2015952 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 12943595 # Number of conditional branches predicted +global.BPredUnit.lookups 17560137 # Number of BP lookups +global.BPredUnit.usedRAS 1685355 # Number of times the RAS was used to get a target. +host_inst_rate 110871 # Simulator instruction rate (inst/s) +host_mem_usage 184176 # Number of bytes of host memory used +host_seconds 759.26 # Real time elapsed on the host +host_tick_rate 138735 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 9867030 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 3328836 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 29553768 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 9396457 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 82582323 # Number of instructions simulated +sim_insts 84179709 # Number of instructions simulated sim_seconds 0.000105 # Number of seconds simulated -sim_ticks 104686099 # Number of ticks simulated -system.cpu.commit.COM:branches 10071057 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3175901 # number cycles where commit BW limit reached +sim_ticks 105335101 # Number of ticks simulated +system.cpu.commit.COM:branches 10240685 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 3300349 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 65490840 +system.cpu.commit.COM:committed_per_cycle.samples 65617496 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 32034998 4891.52% - 1 13785472 2104.95% - 2 8057025 1230.25% - 3 3669149 560.25% - 4 1988059 303.56% - 5 1377349 210.31% - 6 785420 119.93% - 7 617467 94.28% - 8 3175901 484.94% + 0 32041205 4883.03% + 1 13628356 2076.94% + 2 7878182 1200.62% + 3 3859920 588.25% + 4 2040157 310.92% + 5 1456623 221.99% + 6 796888 121.44% + 7 615816 93.85% + 8 3300349 502.97% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 90187947 # Number of instructions committed -system.cpu.commit.COM:loads 19613586 # Number of loads committed +system.cpu.commit.COM:count 91903055 # Number of instructions committed +system.cpu.commit.COM:loads 20034413 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 25981086 # Number of memory references committed +system.cpu.commit.COM:refs 26537108 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1985168 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 90187947 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 387 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 40679620 # The number of squashed insts skipped by commit -system.cpu.committedInsts 82582323 # Number of Instructions Simulated -system.cpu.committedInsts_total 82582323 # Number of Instructions Simulated -system.cpu.cpi 1.267657 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.267657 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 22673452 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5439.841232 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4838.693712 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 22672608 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4591226 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 844 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 351 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2385476 # number of ReadReq MSHR miss cycles +system.cpu.commit.branchMispredicts 2003468 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 39205061 # The number of squashed insts skipped by commit +system.cpu.committedInsts 84179709 # Number of Instructions Simulated +system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated +system.cpu.cpi 1.251312 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.251312 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 23022109 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5495.207331 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4910.485944 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23021236 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4797316 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 873 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 375 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2445422 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 493 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6365908 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 5074.130393 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4849.051425 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6360739 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 26228180 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000812 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 5169 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 3555 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 7826369 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000254 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1614 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 2811.600000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 3114.692857 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13779.471761 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 700 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 28116 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 2180285 # number of cycles access was blocked +system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 4880.722363 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4578.932720 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6495178 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 28918280 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000911 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 5925 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 4186 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 7962764 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1739 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 2807.125000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 3125.260571 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 13194.641931 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 8 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 875 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 22457 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 2734603 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29039360 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 5125.462498 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 4846.627907 # average overall mshr miss latency -system.cpu.dcache.demand_hits 29033347 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 30819406 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000207 # miss rate for demand accesses -system.cpu.dcache.demand_misses 6013 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 3906 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10211845 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000073 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2107 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 29523212 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4959.634598 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4652.742959 # average overall mshr miss latency +system.cpu.dcache.demand_hits 29516414 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 33715596 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000230 # miss rate for demand accesses +system.cpu.dcache.demand_misses 6798 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 4561 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 10408186 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000076 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2237 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 29039360 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 5125.462498 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 4846.627907 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 29033347 # number of overall hits -system.cpu.dcache.overall_miss_latency 30819406 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000207 # miss rate for overall accesses -system.cpu.dcache.overall_misses 6013 # number of overall misses -system.cpu.dcache.overall_mshr_hits 3906 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10211845 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000073 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2107 # number of overall MSHR misses +system.cpu.dcache.overall_accesses 29523212 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4959.634598 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4652.742959 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 29516414 # number of overall hits +system.cpu.dcache.overall_miss_latency 33715596 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000230 # miss rate for overall accesses +system.cpu.dcache.overall_misses 6798 # number of overall misses +system.cpu.dcache.overall_mshr_hits 4561 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 10408186 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000076 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2237 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 104 # number of replacements -system.cpu.dcache.sampled_refs 2107 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 158 # number of replacements +system.cpu.dcache.sampled_refs 2237 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1404.053454 # Cycle average of tags in use -system.cpu.dcache.total_refs 29033347 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1400.647488 # Cycle average of tags in use +system.cpu.dcache.total_refs 29516414 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 75 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 2221252 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 13564 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 2815361 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 145659694 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 36080141 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 27108364 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 6243203 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 50032 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 81084 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 17533197 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 17509399 # Number of cache lines fetched -system.cpu.fetch.Cycles 45531133 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 484323 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 150299775 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2040341 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.244419 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 17509399 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 13524702 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.095236 # Number of inst fetches per cycle +system.cpu.dcache.writebacks 105 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 2047370 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 12661 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 2829477 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 146297095 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 36266329 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 27223403 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 6075840 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 45354 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 80395 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 17560137 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 17576948 # Number of cache lines fetched +system.cpu.fetch.Cycles 45711428 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 479088 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 150837354 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2061309 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.244934 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 17576948 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 13534166 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.103924 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 71734044 +system.cpu.fetch.rateDist.samples 71693337 system.cpu.fetch.rateDist.min_value 0 - 0 43713095 6093.77% - 1 2792314 389.26% - 2 2129360 296.84% - 3 3194083 445.27% - 4 4028588 561.60% - 5 1363321 190.05% - 6 1870461 260.75% - 7 1629807 227.20% - 8 11013015 1535.26% + 0 43559639 6075.83% + 1 2788432 388.94% + 2 2133609 297.60% + 3 3200202 446.37% + 4 4098889 571.73% + 5 1363717 190.22% + 6 1885995 263.06% + 7 1651845 230.40% + 8 11011009 1535.85% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 17509399 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3388.211547 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2494.269154 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 17495889 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 45774738 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000772 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 13510 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 3486 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 25002554 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_accesses 17576948 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3407.568545 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2506.978423 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 17563424 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 46083957 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000769 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 13524 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 3467 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 25212682 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000572 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10024 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 3400.454545 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1745.399940 # Average number of references to valid blocks. +system.cpu.icache.ReadReq_mshr_misses 10057 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets 3513.269231 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1746.387988 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 22 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 26 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 74810 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 91345 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 17509399 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3388.211547 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2494.269154 # average overall mshr miss latency -system.cpu.icache.demand_hits 17495889 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 45774738 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000772 # miss rate for demand accesses -system.cpu.icache.demand_misses 13510 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 3486 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 25002554 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_accesses 17576948 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3407.568545 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2506.978423 # average overall mshr miss latency +system.cpu.icache.demand_hits 17563424 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 46083957 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000769 # miss rate for demand accesses +system.cpu.icache.demand_misses 13524 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 3467 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 25212682 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000572 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10024 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 10057 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 17509399 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3388.211547 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2494.269154 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 17495889 # number of overall hits -system.cpu.icache.overall_miss_latency 45774738 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000772 # miss rate for overall accesses -system.cpu.icache.overall_misses 13510 # number of overall misses -system.cpu.icache.overall_mshr_hits 3486 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 25002554 # number of overall MSHR miss cycles +system.cpu.icache.overall_accesses 17576948 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3407.568545 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2506.978423 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 17563424 # number of overall hits +system.cpu.icache.overall_miss_latency 46083957 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000769 # miss rate for overall accesses +system.cpu.icache.overall_misses 13524 # number of overall misses +system.cpu.icache.overall_mshr_hits 3467 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 25212682 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000572 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10024 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 10057 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,162 +215,162 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 8115 # number of replacements -system.cpu.icache.sampled_refs 10024 # Sample count of references to valid blocks. +system.cpu.icache.replacements 8145 # number of replacements +system.cpu.icache.sampled_refs 10057 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1481.631027 # Cycle average of tags in use -system.cpu.icache.total_refs 17495889 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1487.085502 # Cycle average of tags in use +system.cpu.icache.total_refs 17563424 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 32952056 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 12456785 # Number of branches executed -system.cpu.iew.EXEC:nop 11559797 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.365191 # Inst execution rate -system.cpu.iew.EXEC:refs 30958353 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7006627 # Number of stores executed +system.cpu.idleCycles 33641765 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 12581618 # Number of branches executed +system.cpu.iew.EXEC:nop 11617565 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.388001 # Inst execution rate +system.cpu.iew.EXEC:refs 31473535 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7134398 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 86914579 # num instructions consuming a value -system.cpu.iew.WB:count 96291361 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.729319 # average fanout of values written-back +system.cpu.iew.WB:consumers 88408054 # num instructions consuming a value +system.cpu.iew.WB:count 97920299 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.731090 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 63388475 # num instructions producing a value -system.cpu.iew.WB:rate 1.342338 # insts written-back per cycle -system.cpu.iew.WB:sent 96947832 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2153450 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 156060 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 29530804 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 437 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2057217 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 9370879 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 130866464 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 23951726 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2095770 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 97930658 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 43929 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 64634219 # num instructions producing a value +system.cpu.iew.WB:rate 1.365821 # insts written-back per cycle +system.cpu.iew.WB:sent 98494929 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2154192 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 104376 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 29553768 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 436 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2191495 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 9396457 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 131107086 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 24339137 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2193063 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 99510422 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 16363 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 720 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 6243203 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 62133 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 9874 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 40553 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 855538 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 3321 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.iewLSQFullEvents 879 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 6075840 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 34734 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 9915 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 36009 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 941599 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 3004 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 18493 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9874 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 9917218 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 3003379 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 18493 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1143572 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1009878 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.788857 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.788857 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 100026428 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 23070 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9915 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 9519355 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 2893762 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 23070 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 196104 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1958088 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.799161 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.799161 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 101703485 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 7 0.00% # Type of FU issued - IntAlu 61666427 61.65% # Type of FU issued - IntMult 468908 0.47% # Type of FU issued + IntAlu 62578225 61.53% # Type of FU issued + IntMult 472394 0.46% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2704055 2.70% # Type of FU issued - FloatCmp 112834 0.11% # Type of FU issued - FloatCvt 2307257 2.31% # Type of FU issued - FloatMult 295394 0.30% # Type of FU issued - FloatDiv 735688 0.74% # Type of FU issued - FloatSqrt 122 0.00% # Type of FU issued - MemRead 24586382 24.58% # Type of FU issued - MemWrite 7149354 7.15% # Type of FU issued + FloatAdd 2776755 2.73% # Type of FU issued + FloatCmp 115486 0.11% # Type of FU issued + FloatCvt 2376016 2.34% # Type of FU issued + FloatMult 302348 0.30% # Type of FU issued + FloatDiv 754954 0.74% # Type of FU issued + FloatSqrt 321 0.00% # Type of FU issued + MemRead 25019338 24.60% # Type of FU issued + MemWrite 7307641 7.19% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 1620744 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.016203 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 1392706 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013694 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 195067 12.04% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 1678 0.10% # attempts to use FU when none available - FloatCmp 197 0.01% # attempts to use FU when none available - FloatCvt 4552 0.28% # attempts to use FU when none available - FloatMult 2392 0.15% # attempts to use FU when none available - FloatDiv 951463 58.71% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 401417 24.77% # attempts to use FU when none available - MemWrite 63978 3.95% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available +(null) 0 0.00% # attempts to use FU when none available +IntAlu 193189 13.87% # attempts to use FU when none available +IntMult 0 0.00% # attempts to use FU when none available +IntDiv 0 0.00% # attempts to use FU when none available +FloatAdd 1883 0.14% # attempts to use FU when none available +FloatCmp 96 0.01% # attempts to use FU when none available +FloatCvt 2836 0.20% # attempts to use FU when none available +FloatMult 2464 0.18% # attempts to use FU when none available +FloatDiv 659899 47.38% # attempts to use FU when none available +FloatSqrt 0 0.00% # attempts to use FU when none available +MemRead 465101 33.40% # attempts to use FU when none available +MemWrite 67238 4.83% # attempts to use FU when none available +IprAccess 0 0.00% # attempts to use FU when none available +InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 71734044 +system.cpu.iq.ISSUE:issued_per_cycle.samples 71693337 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 28631398 3991.33% - 1 15448994 2153.65% - 2 12333631 1719.36% - 3 7046540 982.31% - 4 4503539 627.81% - 5 2295007 319.93% - 6 1113179 155.18% - 7 291761 40.67% - 8 69995 9.76% + 0 27977053 3902.32% + 1 15408153 2149.18% + 2 12854527 1792.99% + 3 7056557 984.27% + 4 4494209 626.87% + 5 2427532 338.60% + 6 1097338 153.06% + 7 305661 42.63% + 8 72307 10.09% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.394407 # Inst issue rate -system.cpu.iq.iqInstsAdded 119306230 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 100026428 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 437 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 35838359 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 150449 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 50 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 30462150 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 12131 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3919.717352 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2067.943230 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7146 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19539791 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.410931 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4985 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10308697 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.410931 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4985 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 75 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 75 # number of WriteReqNoAck|Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.448546 # Average number of references to valid blocks. +system.cpu.iq.ISSUE:rate 1.418590 # Inst issue rate +system.cpu.iq.iqInstsAdded 119489085 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 101703485 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 436 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 34413373 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 132312 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 28441004 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 12293 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3855.809345 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2071.040418 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7221 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 19556665 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.412593 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 5072 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 10504317 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.412593 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 5072 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 1.444401 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12131 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3919.717352 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2067.943230 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7146 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 19539791 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.410931 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4985 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12293 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3855.809345 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2071.040418 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7221 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 19556665 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.412593 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5072 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 10308697 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.410931 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4985 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 10504317 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.412593 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5072 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 12206 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3919.717352 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2067.943230 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7221 # number of overall hits -system.cpu.l2cache.overall_miss_latency 19539791 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.408406 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4985 # number of overall misses +system.cpu.l2cache.overall_accesses 12398 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3855.809345 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2071.040418 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 7326 # number of overall hits +system.cpu.l2cache.overall_miss_latency 19556665 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.409098 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5072 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 10308697 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.408406 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4985 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 10504317 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.409098 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5072 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -383,31 +383,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 4985 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 5072 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3244.539242 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7221 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3261.872945 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7326 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 71734044 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 969328 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 67122956 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 411688 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 37058676 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 742595 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 109 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 181728449 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 141044897 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 103457127 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 26196123 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 6243203 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1187915 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 36334171 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 78799 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 513 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2731208 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 502 # count of temporary serializing insts renamed -system.cpu.timesIdled 10186 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 387 # Number of system calls +system.cpu.numCycles 71693337 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 812700 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 369396 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 37208342 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 772307 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 122 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 182866276 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 141908898 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 104156212 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 26334995 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 6075840 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1200845 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 35728851 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 60615 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 555 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2896644 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 544 # count of temporary serializing insts renamed +system.cpu.timesIdled 10380 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.out b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out index 00387ae5c..00387ae5c 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.out +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pin b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pin index 62b922e4e..62b922e4e 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pin +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pin diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl1 b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 index bdc569e39..bdc569e39 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl1 +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl2 b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 index 6e2601e82..6e2601e82 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl2 +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sav b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sav index 04c8e9935..04c8e9935 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sav +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sav diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sv2 b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 index 9dd68ecdb..9dd68ecdb 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sv2 +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.twf b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.twf index a4c2eac35..a4c2eac35 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.twf +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.twf diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr new file mode 100644 index 000000000..eb1796ead --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr @@ -0,0 +1,2 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout index f32f0a972..f32f0a972 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index fbf8dd865..789f77815 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -7,21 +7,6 @@ max_tick=0 output_file=cout progress_interval=0 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - [serialize] count=10 cycle=0 @@ -74,7 +59,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-atomic egid=100 env= euid=100 @@ -100,14 +85,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out index 5375d2a8f..b4087eb1c 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out @@ -10,6 +10,7 @@ type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,7 +31,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-atomic system=system uid=100 euid=100 @@ -57,15 +58,6 @@ function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - [stats] descriptions=true project_name=test @@ -83,25 +75,6 @@ dump_cycle=0 dump_period=0 ignore_events= -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - [statsreset] reset_cycle=0 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt index e5e0a4991..2cd5a06bf 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 827042 # Simulator instruction rate (inst/s) -host_mem_usage 146736 # Number of bytes of host memory used -host_seconds 111.12 # Real time elapsed on the host -host_tick_rate 827039 # Simulator tick rate (ticks/s) +host_inst_rate 1013473 # Simulator instruction rate (inst/s) +host_mem_usage 151596 # Number of bytes of host memory used +host_seconds 90.68 # Real time elapsed on the host +host_tick_rate 1013469 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 91900700 # Number of instructions simulated +sim_insts 91903057 # Number of instructions simulated sim_seconds 0.000092 # Number of seconds simulated -sim_ticks 91900699 # Number of ticks simulated +sim_ticks 91903056 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 91900700 # number of cpu cycles simulated -system.cpu.num_insts 91900700 # Number of instructions executed -system.cpu.num_refs 26536244 # Number of memory references -system.cpu.workload.PROG:num_syscalls 387 # Number of system calls +system.cpu.numCycles 91903057 # number of cpu cycles simulated +system.cpu.num_insts 91903057 # Number of instructions executed +system.cpu.num_refs 26537109 # Number of memory references +system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.out b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out index 00387ae5c..00387ae5c 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pin b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin index 62b922e4e..62b922e4e 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pin +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl1 b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 index bdc569e39..bdc569e39 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl1 +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl2 b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 index 6e2601e82..6e2601e82 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl2 +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sav b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav index 04c8e9935..04c8e9935 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sav +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sv2 b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 index 9dd68ecdb..9dd68ecdb 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sv2 +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.twf b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf index a4c2eac35..a4c2eac35 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.twf +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr new file mode 100644 index 000000000..eb1796ead --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr @@ -0,0 +1,2 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout index f32f0a972..f32f0a972 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index 9f6151e4d..e2265235e 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -7,21 +7,6 @@ max_tick=0 output_file=cout progress_interval=0 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - [serialize] count=10 cycle=0 @@ -197,7 +182,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-timing egid=100 env= euid=100 @@ -223,14 +208,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out index c27975bcb..fcf06c7db 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out @@ -10,6 +10,7 @@ type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,7 +31,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-timing system=system uid=100 euid=100 @@ -178,15 +179,6 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - [stats] descriptions=true project_name=test @@ -204,25 +196,6 @@ dump_cycle=0 dump_period=0 ignore_events= -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - [statsreset] reset_cycle=0 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt index 3926b2de9..5cdae9c4a 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 460435 # Simulator instruction rate (inst/s) -host_mem_usage 178124 # Number of bytes of host memory used -host_seconds 199.60 # Real time elapsed on the host -host_tick_rate 765898 # Simulator tick rate (ticks/s) +host_inst_rate 607322 # Simulator instruction rate (inst/s) +host_mem_usage 157212 # Number of bytes of host memory used +host_seconds 151.33 # Real time elapsed on the host +host_tick_rate 1013960 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 91900700 # Number of instructions simulated +sim_insts 91903057 # Number of instructions simulated sim_seconds 0.000153 # Number of seconds simulated -sim_ticks 152870012 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 19995627 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3765.212314 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2765.212314 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 19995156 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1773415 # number of ReadReq miss cycles +sim_ticks 153438012 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3701.356540 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2701.356540 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1754443 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 471 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1302415 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 1280443 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 471 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6500813 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3867.178372 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2867.178372 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6499204 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 6222290 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000248 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1609 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 4613290 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000248 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1609 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3869.070366 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2869.070366 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 6763135 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5015135 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12737.673077 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11923.977948 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 26496440 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3844.088942 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2844.088942 # average overall mshr miss latency -system.cpu.dcache.demand_hits 26494360 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 7995705 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2080 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3833.293429 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2833.293429 # average overall mshr miss latency +system.cpu.dcache.demand_hits 26495079 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 8517578 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2222 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5915705 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2080 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 6295578 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2222 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 26496440 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3844.088942 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2844.088942 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3833.293429 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2833.293429 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 26494360 # number of overall hits -system.cpu.dcache.overall_miss_latency 7995705 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2080 # number of overall misses +system.cpu.dcache.overall_hits 26495079 # number of overall hits +system.cpu.dcache.overall_miss_latency 8517578 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2222 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5915705 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2080 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 6295578 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2222 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -73,57 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 103 # number of replacements -system.cpu.dcache.sampled_refs 2080 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 157 # number of replacements +system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1399.324024 # Cycle average of tags in use -system.cpu.dcache.total_refs 26494360 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1398.130089 # Cycle average of tags in use +system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 74 # number of writebacks -system.cpu.icache.ReadReq_accesses 91900701 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3116.205529 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2116.205529 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 91892201 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 26487747 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000092 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 8500 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 17987747 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000092 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 8500 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks 104 # number of writebacks +system.cpu.icache.ReadReq_accesses 91903058 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3117.603760 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2117.603760 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 91894548 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 26530808 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 18020808 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 10810.847176 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 10798.419271 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 91900701 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3116.205529 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2116.205529 # average overall mshr miss latency -system.cpu.icache.demand_hits 91892201 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 26487747 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000092 # miss rate for demand accesses -system.cpu.icache.demand_misses 8500 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 91903058 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3117.603760 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2117.603760 # average overall mshr miss latency +system.cpu.icache.demand_hits 91894548 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 26530808 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses +system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 17987747 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000092 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 8500 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 18020808 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 91900701 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3116.205529 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2116.205529 # average overall mshr miss latency +system.cpu.icache.overall_accesses 91903058 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3117.603760 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2117.603760 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 91892201 # number of overall hits -system.cpu.icache.overall_miss_latency 26487747 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000092 # miss rate for overall accesses -system.cpu.icache.overall_misses 8500 # number of overall misses +system.cpu.icache.overall_hits 91894548 # number of overall hits +system.cpu.icache.overall_miss_latency 26530808 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses +system.cpu.icache.overall_misses 8510 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 17987747 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000092 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 8500 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 18020808 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -135,60 +135,60 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 6677 # number of replacements -system.cpu.icache.sampled_refs 8500 # Sample count of references to valid blocks. +system.cpu.icache.replacements 6681 # number of replacements +system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1370.015418 # Cycle average of tags in use -system.cpu.icache.total_refs 91892201 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1374.520503 # Cycle average of tags in use +system.cpu.icache.total_refs 91894548 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 10580 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2883.751500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1878.799057 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5912 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 13461352 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.441210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4668 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 8770234 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.441210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4668 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 74 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 74 # number of WriteReqNoAck|Writeback hits +system.cpu.l2cache.ReadReq_accesses 10732 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2892.483207 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1885.503778 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5968 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 13779790 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.443906 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4764 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 8982540 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.443906 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4764 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.282348 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.274559 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 10580 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2883.751500 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1878.799057 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5912 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 13461352 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.441210 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4668 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2892.483207 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1885.503778 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 13779790 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.443906 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 4764 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 8770234 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.441210 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4668 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 8982540 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.443906 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 4764 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 10654 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2883.751500 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1878.799057 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 10836 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2892.483207 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1885.503778 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5986 # number of overall hits -system.cpu.l2cache.overall_miss_latency 13461352 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.438145 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4668 # number of overall misses +system.cpu.l2cache.overall_hits 6072 # number of overall hits +system.cpu.l2cache.overall_miss_latency 13779790 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.439646 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 4764 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 8770234 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.438145 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4668 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 8982540 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.439646 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 4764 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -201,16 +201,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 4668 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 4764 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3056.777484 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5986 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3073.845977 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6072 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 152870012 # number of cpu cycles simulated -system.cpu.num_insts 91900700 # Number of instructions executed -system.cpu.num_refs 26536244 # Number of memory references -system.cpu.workload.PROG:num_syscalls 387 # Number of system calls +system.cpu.numCycles 153438012 # number of cpu cycles simulated +system.cpu.num_insts 91903057 # Number of instructions executed +system.cpu.num_refs 26537109 # Number of memory references +system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.out b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out index 00387ae5c..00387ae5c 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pin b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pin index 62b922e4e..62b922e4e 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pin +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pin diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl1 b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 index bdc569e39..bdc569e39 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl1 +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl2 b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 index 6e2601e82..6e2601e82 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl2 +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sav b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sav index 04c8e9935..04c8e9935 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sav +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sav diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sv2 b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 index 9dd68ecdb..9dd68ecdb 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sv2 +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.twf b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.twf index a4c2eac35..a4c2eac35 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.twf +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.twf diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr new file mode 100644 index 000000000..eb1796ead --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr @@ -0,0 +1,2 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout index f32f0a972..f32f0a972 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini new file mode 100644 index 000000000..2a1613fa1 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -0,0 +1,64 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=workload +clock=1 +cpu_id=0 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +simulate_stalls=false +system=system +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out new file mode 100644 index 000000000..d24c09793 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out @@ -0,0 +1,57 @@ +[root] +type=Root +dummy=0 + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 +zero=false + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf +input=cin +output=cout +env= +cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt new file mode 100644 index 000000000..45fd6b479 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 676464 # Simulator instruction rate (inst/s) +host_mem_usage 149916 # Number of bytes of host memory used +host_seconds 285.95 # Real time elapsed on the host +host_tick_rate 676463 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 193435973 # Number of instructions simulated +sim_seconds 0.000193 # Number of seconds simulated +sim_ticks 193435972 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 193435973 # number of cpu cycles simulated +system.cpu.num_insts 193435973 # Number of instructions executed +system.cpu.num_refs 76732959 # Number of memory references +system.cpu.workload.PROG:num_syscalls 396 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.out b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.out new file mode 100644 index 000000000..00387ae5c --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.out @@ -0,0 +1,276 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + + +NOTE: Restart file .rs2 not used + +TimberWolf will perform a global route step +rowSep: 1.000000 +feedThruWidth: 4 + +****************** +BLOCK DATA +block:1 desire:85 +block:2 desire:85 +Total Desired Length: 170 +total cell length: 168 +total block length: 168 +block x-span:84 block y-span:78 +implicit feed thru range: -84 +Using default value of bin.penalty.control:1.000000 +numBins automatically set to:5 +binWidth = average_cell_width + 0 sigma= 17 +average_cell_width is:16 +standard deviation of cell length is:23.6305 +TimberWolfSC starting from the beginning + + + +THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 +The number of nets with 1 pin is 4 +The number of nets with 2 pin is 9 +The number of nets with 3 pin is 0 +The number of nets with 4 pin is 2 +The number of nets with 5 pin is 0 +The number of nets with 6 pin is 0 +The number of nets with 7 pin is 0 +The number of nets with 8 pin is 0 +The number of nets with 9 pin is 0 +The number of nets with 10 pin or more is 0 + +New Cost Function: Initial Horizontal Cost:242 +New Cost Function: FEEDS:0 MISSING_ROWS:-46 + +bdxlen:86 bdylen:78 +l:0 t:78 r:86 b:0 + + + +THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 + + + +THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 + +The rand generator seed was at utemp() : 1 + + + tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 + tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 + tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 + tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 + + I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs + 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 + 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 + 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 + 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 + 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 + 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 + 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 + 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 + 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 + 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 + 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 + 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 + 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 + 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 + 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 + 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 + 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 + 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 + 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 + 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 + 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 + 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 + 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 + 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 + 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 + 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 + 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 + 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 + 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 + 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 + 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 + 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 + 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 + 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 + 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 + 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 + 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 + 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 + 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 + 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 + 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 + 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 + 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 + 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 + 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 + 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 + 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 + 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 + 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 + 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 + 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 + 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 + 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 + 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 + 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 + 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 + 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 + 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 + 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 + 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 + 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 + 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 + 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 + 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 + 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 + 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 + 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 + 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 + 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 + 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 + 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 + 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 + 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 + 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 + 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 + 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 + 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 + 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 + 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 + 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 + 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 + 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 + 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 + 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 + 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 + 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 + 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 + 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 + 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 + 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 + 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 + 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 + 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 + 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 + 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 +100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 +101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 +102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 +103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 +104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 +105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 +106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 +107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 +108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 +109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 +110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 +111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 +112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 +113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 +114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 +115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 +116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 +117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 +118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 +119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 +120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 +121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 + +Initial Wiring Cost: 645 Final Wiring Cost: 732 +############## Percent Wire Cost Reduction: -13 + + +Initial Wire Length: 645 Final Wire Length: 732 +************** Percent Wire Length Reduction: -13 + + +Initial Horiz. Wire: 216 Final Horiz. Wire: 147 +$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 + + +Initial Vert. Wire: 429 Final Vert. Wire: 585 +@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 + +Before Feeds are Added: +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 82 -20 + 2 86 -16 + +LONGEST Block is:2 Its length is:86 +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 86 -16 + 2 86 -16 + +LONGEST Block is:1 Its length is:86 +Added: 1 feed-through cells + +Removed the cell overlaps --- Will do neighbor interchanges only now + +TOTAL INTERCONNECT LENGTH: 994 +OVERLAP PENALTY: 0 + +initialRowControl: 1.650 +finalRowControl: 0.300 +iter T Wire accept + 122 0.001 976 16% + 123 0.001 971 0% + 124 0.001 971 0% +Total Feed-Alignment Movement (Pass 1): 0 +Total Feed-Alignment Movement (Pass 2): 0 +Total Feed-Alignment Movement (Pass 3): 0 +Total Feed-Alignment Movement (Pass 4): 0 +Total Feed-Alignment Movement (Pass 5): 0 +Total Feed-Alignment Movement (Pass 6): 0 +Total Feed-Alignment Movement (Pass 7): 0 +Total Feed-Alignment Movement (Pass 8): 0 + +The rand generator seed was at globroute() : 987654321 + + +Total Number of Net Segments: 9 +Number of Switchable Net Segments: 0 + +Number of channels: 3 + + + +THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 + + +no. of accepted flips: 0 +no. of attempted flips: 0 +THIS IS THE NUMBER OF TRACKS: 5 + + + +FINAL NUMBER OF ROUTING TRACKS: 5 + +MAX OF CHANNEL: 1 is: 0 +MAX OF CHANNEL: 2 is: 4 +MAX OF CHANNEL: 3 is: 1 +FINAL TOTAL INTERCONNECT LENGTH: 978 +FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 +MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 + + +cost_scale_factor:3.90616 + +Number of Feed Thrus: 0 +Number of Implicit Feed Thrus: 0 + +Statistics: +Number of Standard Cells: 10 +Number of Pads: 0 +Number of Nets: 15 +Number of Pins: 46 +Usage statistics not available diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pin b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pin new file mode 100644 index 000000000..62b922e4e --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pin @@ -0,0 +1,17 @@ +$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 +$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 +B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 +B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 +B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1 b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1 new file mode 100644 index 000000000..bdc569e39 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1 @@ -0,0 +1,11 @@ +$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 +$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 +$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 +ACOUNT_1 14 0 18 26 2 1 +twfeed1 18 0 22 26 0 1 +$COUNT_1/$FJK3_1 22 0 86 26 0 1 +$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 +$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 +$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 +$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 +$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2 b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2 new file mode 100644 index 000000000..6e2601e82 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2 @@ -0,0 +1,2 @@ +1 0 0 86 26 0 0 +2 0 52 86 78 0 0 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sav b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sav new file mode 100644 index 000000000..04c8e9935 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sav @@ -0,0 +1,18 @@ +0.009592 +121 +0 +1 +0.000000 +0.500000 +3.906156 +1 +1 1 2 37 13 +2 2 0 34 65 +3 2 2 63 65 +4 1 0 59 13 +5 1 2 32 13 +6 2 0 23 65 +7 1 2 12 13 +8 2 0 6 65 +9 1 0 70 13 +10 2 0 70 65 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2 b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2 new file mode 100644 index 000000000..9dd68ecdb --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2 @@ -0,0 +1,19 @@ +0.001000 +123 +0 +2 +0.000000 +0.500000 +3.906156 +1 +1 1 2 16 13 +2 2 2 19 65 +3 2 2 14 65 +4 1 0 11 13 +5 1 2 6 13 +6 2 0 3 65 +7 1 0 2 13 +8 2 2 9 65 +9 1 0 50 13 +10 2 0 54 65 +11 1 0 84 13 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.twf b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.twf new file mode 100644 index 000000000..a4c2eac35 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.twf @@ -0,0 +1,29 @@ +net 1 +segment channel 2 + pin1 1 pin2 7 0 0 +net 2 +segment channel 3 +pin1 41 pin2 42 0 0 +segment channel 2 +pin1 12 pin2 3 0 0 +net 3 +segment channel 2 +pin1 35 pin2 36 0 0 +segment channel 2 +pin1 19 pin2 35 0 0 +net 4 +segment channel 2 + pin1 5 pin2 38 0 0 +net 5 +net 7 +segment channel 2 + pin1 14 pin2 43 0 0 +net 8 +segment channel 2 + pin1 23 pin2 17 0 0 +net 9 +net 11 +segment channel 2 + pin1 25 pin2 31 0 0 +net 14 +net 15 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr new file mode 100644 index 000000000..94662b6e8 --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr @@ -0,0 +1,8 @@ +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x11e394 length 0x10. +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x0 length 0x0. +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... +warn: Ignoring request to flush register windows. +warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout new file mode 100644 index 000000000..7c0e5ba5f --- /dev/null +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout @@ -0,0 +1,28 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 12 2007 16:53:49 +M5 started Mon Mar 12 17:37:07 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 193435972 because target called exit() diff --git a/tests/long/70.twolf/test.py b/tests/long/70.twolf/test.py index c105a17e2..b2a2dc0b6 100644 --- a/tests/long/70.twolf/test.py +++ b/tests/long/70.twolf/test.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -28,6 +28,20 @@ m5.AddToPath('../configs/common') from cpu2000 import twolf +import os -workload = twolf('alpha', 'tru64', 'smred') +workload = twolf(isa, opsys, 'smred') root.system.cpu.workload = workload.makeLiveProcess() +cwd = root.system.cpu.workload.cwd + +#Remove two files who's presence or absence affects execution +sav_file = os.path.join(cwd, workload.input_set + '.sav') +sv2_file = os.path.join(cwd, workload.input_set + '.sv2') +try: + os.unlink(sav_file) +except: + print "Couldn't unlink ", sav_file +try: + os.unlink(sv2_file) +except: + print "Couldn't unlink ", sv2_file diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini new file mode 100644 index 000000000..4ef8952f1 --- /dev/null +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini @@ -0,0 +1,454 @@ +[root] +type=Root +children=system +checkpoint= +clock=2000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[system] +type=SparcSystem +children=bridge cpu disk0 hypervisor_desc intrctrl iobus membus nvram partition_desc physmem physmem2 rom t1000 +boot_cpu_frequency=1 +boot_osflags=a +hypervisor_addr=1099243257856 +hypervisor_bin=/dist/m5/system/binaries/q_new.bin +hypervisor_desc=system.hypervisor_desc +hypervisor_desc_addr=133446500352 +hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin +init_param=0 +kernel= +mem_mode=atomic +nvram=system.nvram +nvram_addr=133429198848 +nvram_bin=/dist/m5/system/binaries/nvram1 +openboot_addr=1099243716608 +openboot_bin=/dist/m5/system/binaries/openboot_new.bin +partition_desc=system.partition_desc +partition_desc_addr=133445976064 +partition_desc_bin=/dist/m5/system/binaries/1up-md.bin +physmem=system.physmem +readfile=tests/halt.sh +reset_addr=1099243192320 +reset_bin=/dist/m5/system/binaries/reset_new.bin +rom=system.rom +symbolfile= + +[system.bridge] +type=Bridge +delay=0 +queue_size_a=16 +queue_size_b=16 +write_ack=false +side_a=system.iobus.port[14] +side_b=system.membus.port[2] + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb +clock=1 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +profile=0 +progress_interval=0 +simulate_stalls=false +system=system +width=1 +dcache_port=system.membus.port[10] +icache_port=system.membus.port[9] + +[system.cpu.dtb] +type=SparcDTB +size=64 + +[system.cpu.itb] +type=SparcITB +size=64 + +[system.disk0] +type=MmDisk +children=image +image=system.disk0.image +pio_addr=134217728000 +pio_latency=2 +platform=system.t1000 +system=system +pio=system.iobus.port[15] + +[system.disk0.image] +type=CowDiskImage +children=child +child=system.disk0.image.child +read_only=false +table_size=65536 + +[system.disk0.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/disk.s10hw2 +read_only=true + +[system.hypervisor_desc] +type=PhysicalMemory +file= +latency=1 +range=133446500352:133446508543 +zero=false +port=system.membus.port[7] + +[system.intrctrl] +type=IntrControl +sys=system + +[system.iobus] +type=Bus +children=responder +bus_id=0 +clock=2 +responder_set=false +width=64 +default=system.iobus.responder.pio +port=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.bridge.side_a system.disk0.pio + +[system.iobus.responder] +type=IsaFake +pio_addr=0 +pio_latency=0 +pio_size=8 +platform=system.t1000 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.default + +[system.membus] +type=Bus +children=responder +bus_id=1 +clock=2 +responder_set=false +width=64 +default=system.membus.responder.pio +port=system.t1000.iob.pio system.t1000.htod.pio system.bridge.side_b system.physmem.port system.physmem2.port system.rom.port system.nvram.port system.hypervisor_desc.port system.partition_desc.port system.cpu.icache_port system.cpu.dcache_port + +[system.membus.responder] +type=IsaFake +pio_addr=0 +pio_latency=0 +pio_size=8 +platform=system.t1000 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.membus.default + +[system.nvram] +type=PhysicalMemory +file= +latency=1 +range=133429198848:133429207039 +zero=false +port=system.membus.port[6] + +[system.partition_desc] +type=PhysicalMemory +file= +latency=1 +range=133445976064:133445984255 +zero=false +port=system.membus.port[8] + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=1048576:68157439 +zero=true +port=system.membus.port[3] + +[system.physmem2] +type=PhysicalMemory +file= +latency=1 +range=2147483648:2415919103 +zero=true +port=system.membus.port[4] + +[system.rom] +type=PhysicalMemory +file= +latency=1 +range=1099243192320:1099251580927 +zero=false +port=system.membus.port[5] + +[system.t1000] +type=T1000 +children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hconsole htod hvuart iob pconsole puart0 +intrctrl=system.intrctrl +system=system + +[system.t1000.fake_clk] +type=IsaFake +pio_addr=644245094400 +pio_latency=2 +pio_size=4294967296 +platform=system.t1000 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[0] + +[system.t1000.fake_jbi] +type=IsaFake +pio_addr=549755813888 +pio_latency=2 +pio_size=4294967296 +platform=system.t1000 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[11] + +[system.t1000.fake_l2_1] +type=IsaFake +pio_addr=725849473024 +pio_latency=2 +pio_size=8 +platform=system.t1000 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=1 +ret_data8=255 +system=system +update_data=true +warn_access= +pio=system.iobus.port[2] + +[system.t1000.fake_l2_2] +type=IsaFake +pio_addr=725849473088 +pio_latency=2 +pio_size=8 +platform=system.t1000 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=1 +ret_data8=255 +system=system +update_data=true +warn_access= +pio=system.iobus.port[3] + +[system.t1000.fake_l2_3] +type=IsaFake +pio_addr=725849473152 +pio_latency=2 +pio_size=8 +platform=system.t1000 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=1 +ret_data8=255 +system=system +update_data=true +warn_access= +pio=system.iobus.port[4] + +[system.t1000.fake_l2_4] +type=IsaFake +pio_addr=725849473216 +pio_latency=2 +pio_size=8 +platform=system.t1000 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=1 +ret_data8=255 +system=system +update_data=true +warn_access= +pio=system.iobus.port[5] + +[system.t1000.fake_l2esr_1] +type=IsaFake +pio_addr=734439407616 +pio_latency=2 +pio_size=8 +platform=system.t1000 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=0 +ret_data8=255 +system=system +update_data=true +warn_access= +pio=system.iobus.port[6] + +[system.t1000.fake_l2esr_2] +type=IsaFake +pio_addr=734439407680 +pio_latency=2 +pio_size=8 +platform=system.t1000 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=0 +ret_data8=255 +system=system +update_data=true +warn_access= +pio=system.iobus.port[7] + +[system.t1000.fake_l2esr_3] +type=IsaFake +pio_addr=734439407744 +pio_latency=2 +pio_size=8 +platform=system.t1000 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=0 +ret_data8=255 +system=system +update_data=true +warn_access= +pio=system.iobus.port[8] + +[system.t1000.fake_l2esr_4] +type=IsaFake +pio_addr=734439407808 +pio_latency=2 +pio_size=8 +platform=system.t1000 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=0 +ret_data8=255 +system=system +update_data=true +warn_access= +pio=system.iobus.port[9] + +[system.t1000.fake_membnks] +type=IsaFake +pio_addr=648540061696 +pio_latency=2 +pio_size=16384 +platform=system.t1000 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=0 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[1] + +[system.t1000.fake_ssi] +type=IsaFake +pio_addr=1095216660480 +pio_latency=2 +pio_size=268435456 +platform=system.t1000 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[10] + +[system.t1000.hconsole] +type=SimConsole +append_name=true +intr_control=system.intrctrl +number=0 +output=console +port=3456 + +[system.t1000.htod] +type=DumbTOD +pio_addr=1099255906296 +pio_latency=2 +platform=system.t1000 +system=system +time=2009 1 1 0 0 0 3 1 +pio=system.membus.port[1] + +[system.t1000.hvuart] +type=Uart8250 +pio_addr=1099255955456 +pio_latency=2 +platform=system.t1000 +sim_console=system.t1000.hconsole +system=system +pio=system.iobus.port[13] + +[system.t1000.iob] +type=Iob +pio_latency=2 +platform=system.t1000 +system=system +pio=system.membus.port[0] + +[system.t1000.pconsole] +type=SimConsole +append_name=true +intr_control=system.intrctrl +number=0 +output=console +port=3456 + +[system.t1000.puart0] +type=Uart8250 +pio_addr=133412421632 +pio_latency=2 +platform=system.t1000 +sim_console=system.t1000.pconsole +system=system +pio=system.iobus.port[12] + diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.out b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.out new file mode 100644 index 000000000..90deb9963 --- /dev/null +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.out @@ -0,0 +1,413 @@ +[root] +type=Root +clock=2000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[1048576,68157439] +latency=1 +zero=true + +[system.rom] +type=PhysicalMemory +file= +range=[1099243192320,1099251580927] +latency=1 +zero=false + +[system.nvram] +type=PhysicalMemory +file= +range=[133429198848,133429207039] +latency=1 +zero=false + +[system.hypervisor_desc] +type=PhysicalMemory +file= +range=[133446500352,133446508543] +latency=1 +zero=false + +[system.partition_desc] +type=PhysicalMemory +file= +range=[133445976064,133445984255] +latency=1 +zero=false + +[system] +type=SparcSystem +physmem=system.physmem +rom=system.rom +nvram=system.nvram +hypervisor_desc=system.hypervisor_desc +partition_desc=system.partition_desc +mem_mode=atomic +reset_addr=1099243192320 +hypervisor_addr=1099243257856 +openboot_addr=1099243716608 +nvram_addr=133429198848 +hypervisor_desc_addr=133446500352 +partition_desc_addr=133445976064 +kernel= +reset_bin=/dist/m5/system/binaries/reset_new.bin +hypervisor_bin=/dist/m5/system/binaries/q_new.bin +openboot_bin=/dist/m5/system/binaries/openboot_new.bin +nvram_bin=/dist/m5/system/binaries/nvram1 +hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin +partition_desc_bin=/dist/m5/system/binaries/1up-md.bin +boot_cpu_frequency=1 +boot_osflags=a +readfile=tests/halt.sh +init_param=0 + +[system.membus] +type=Bus +bus_id=1 +clock=2 +width=64 +responder_set=false + +[system.intrctrl] +type=IntrControl +sys=system + +[system.t1000] +type=T1000 +system=system +intrctrl=system.intrctrl + +[system.membus.responder] +type=IsaFake +pio_addr=0 +pio_latency=0 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.t1000 +system=system + +[system.physmem2] +type=PhysicalMemory +file= +range=[2147483648,2415919103] +latency=1 +zero=true + +[system.bridge] +type=Bridge +queue_size_a=16 +queue_size_b=16 +delay=0 +write_ack=false + +[system.disk0.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/disk.s10hw2 +read_only=true + +[system.disk0.image] +type=CowDiskImage +child=system.disk0.image.child +image_file= +table_size=65536 +read_only=false + +[system.disk0] +type=MmDisk +pio_addr=134217728000 +pio_latency=2 +// pio_size not specified +platform=system.t1000 +system=system +image=system.disk0.image + +[system.t1000.hconsole] +type=SimConsole +intr_control=system.intrctrl +output=console +port=3456 +append_name=true +number=0 + +[system.t1000.hvuart] +type=Uart8250 +pio_addr=1099255955456 +pio_latency=2 +platform=system.t1000 +sim_console=system.t1000.hconsole +system=system + +[system.t1000.htod] +type=DumbTOD +pio_addr=1099255906296 +pio_latency=2 +platform=system.t1000 +system=system +time=2009 1 1 0 0 0 3 1 + +[system.t1000.pconsole] +type=SimConsole +intr_control=system.intrctrl +output=console +port=3456 +append_name=true +number=0 + +[system.t1000.puart0] +type=Uart8250 +pio_addr=133412421632 +pio_latency=2 +platform=system.t1000 +sim_console=system.t1000.pconsole +system=system + +[system.t1000.fake_membnks] +type=IsaFake +pio_addr=648540061696 +pio_latency=2 +pio_size=16384 +ret_bad_addr=false +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=0 +platform=system.t1000 +system=system + +[system.t1000.fake_ssi] +type=IsaFake +pio_addr=1095216660480 +pio_latency=2 +pio_size=268435456 +ret_bad_addr=false +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.t1000 +system=system + +[system.t1000.fake_l2_4] +type=IsaFake +pio_addr=725849473216 +pio_latency=2 +pio_size=8 +ret_bad_addr=false +update_data=true +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=1 +platform=system.t1000 +system=system + +[system.t1000.fake_l2_1] +type=IsaFake +pio_addr=725849473024 +pio_latency=2 +pio_size=8 +ret_bad_addr=false +update_data=true +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=1 +platform=system.t1000 +system=system + +[system.t1000.fake_l2_2] +type=IsaFake +pio_addr=725849473088 +pio_latency=2 +pio_size=8 +ret_bad_addr=false +update_data=true +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=1 +platform=system.t1000 +system=system + +[system.t1000.fake_l2_3] +type=IsaFake +pio_addr=725849473152 +pio_latency=2 +pio_size=8 +ret_bad_addr=false +update_data=true +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=1 +platform=system.t1000 +system=system + +[system.t1000.fake_l2esr_3] +type=IsaFake +pio_addr=734439407744 +pio_latency=2 +pio_size=8 +ret_bad_addr=false +update_data=true +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=0 +platform=system.t1000 +system=system + +[system.t1000.fake_l2esr_2] +type=IsaFake +pio_addr=734439407680 +pio_latency=2 +pio_size=8 +ret_bad_addr=false +update_data=true +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=0 +platform=system.t1000 +system=system + +[system.t1000.fake_l2esr_1] +type=IsaFake +pio_addr=734439407616 +pio_latency=2 +pio_size=8 +ret_bad_addr=false +update_data=true +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=0 +platform=system.t1000 +system=system + +[system.t1000.fake_l2esr_4] +type=IsaFake +pio_addr=734439407808 +pio_latency=2 +pio_size=8 +ret_bad_addr=false +update_data=true +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=0 +platform=system.t1000 +system=system + +[system.t1000.iob] +type=Iob +pio_latency=2 +platform=system.t1000 +system=system + +[system.t1000.fake_clk] +type=IsaFake +pio_addr=644245094400 +pio_latency=2 +pio_size=4294967296 +ret_bad_addr=false +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.t1000 +system=system + +[system.t1000.fake_jbi] +type=IsaFake +pio_addr=549755813888 +pio_latency=2 +pio_size=4294967296 +ret_bad_addr=false +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.t1000 +system=system + +[system.iobus] +type=Bus +bus_id=0 +clock=2 +width=64 +responder_set=false + +[system.iobus.responder] +type=IsaFake +pio_addr=0 +pio_latency=0 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.t1000 +system=system + +[system.cpu.itb] +type=SparcITB +size=64 + +[system.cpu.dtb] +type=SparcDTB +size=64 + +[system.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +itb=system.cpu.itb +dtb=system.cpu.dtb +profile=0 +do_quiesce=true +do_checkpoint_insts=true +do_statistics_insts=true +clock=1 +phase=0 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.hconsole b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.hconsole new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.hconsole diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.pconsole b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.pconsole new file mode 100644 index 000000000..a31449664 --- /dev/null +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.pconsole @@ -0,0 +1,48 @@ +cpu + +Sun Fire T2000, No Keyboard +Copyright 2006 Sun Microsystems, Inc. All rights reserved. +OpenBoot 4.23.0, 256 MB memory available, Serial #1122867. +[saidi obp #30] +Ethernet address 0:80:3:de:ad:3, Host ID: 80112233. + + + +Boot device: /virtual-devices/disk@0 File and args: -vV +Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54. +FCode UFS Reader 1.12 00/07/17 15:48:16. +Loading: /platform/SUNW,Sun-Fire-T2000/ufsboot +Loading: /platform/sun4v/ufsboot +device path '/virtual-devices@100/disk@0:a' +The boot filesystem is logging. +The ufs log is empty and will not be used. +standalone = `kernel/sparcv9/unix', args = `-v' +|Elf64 client +Size: /-\|/-\|0x76e40+/-\|/-\|/-\|/-\0x1c872+|/-\0x3123a Bytes +modpath: /platform/sun4v/kernel /kernel /usr/kernel +|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-module /platform/sun4v/kernel/sparcv9/unix: text at [0x1000000, 0x1076e3f] data at 0x1800000 +module misc/sparcv9/krtld: text at [0x1076e40, 0x108f737] data at 0x184dab0 +module /platform/sun4v/kernel/sparcv9/genunix: text at [0x108f738, 0x11dd437] data at 0x18531c0 +module /platform/sun4v/kernel/misc/sparcv9/platmod: text at [0x11dd438, 0x11dd43f] data at 0x18a4be0 +module /platform/sun4v/kernel/cpu/sparcv9/SUNW,UltraSPARC-T1: text at [0x11dd440, 0x11e06ff] data at 0x18a5300 +\
SunOS Release 5.10 Version Generic_118822-23 64-bit +Copyright 1983-2005 Sun Microsystems, Inc. All rights reserved. +Use is subject to license terms. +|/-\|/-\|/-\|/-\|/-Ethernet address = 0:80:3:de:ad:3 +\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/mem = 262144K (0x10000000) +avail mem = 237879296 +root nexus = Sun Fire T2000 +pseudo0 at root +pseudo0 is /pseudo +scsi_vhci0 at root +scsi_vhci0 is /scsi_vhci +virtual-device: hsimd0 +hsimd0 is /virtual-devices@100/disk@0 +root on /virtual-devices@100/disk@0:a fstype ufs +pseudo-device: dld0 +dld0 is /pseudo/dld@0 +cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz) +iscsi0 at root +iscsi0 is /iscsi +Hostname: unknown +Loading M5 readfile script... diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt new file mode 100644 index 000000000..48d2b83c5 --- /dev/null +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt @@ -0,0 +1,19 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1214495 # Simulator instruction rate (inst/s) +host_mem_usage 409828 # Number of bytes of host memory used +host_seconds 1828.73 # Real time elapsed on the host +host_tick_rate 1214601 # Simulator tick rate (ticks/s) +sim_freq 2000000000 # Frequency of simulated ticks +sim_insts 2220985165 # Number of instructions simulated +sim_seconds 1.110589 # Number of seconds simulated +sim_ticks 2221178828 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 2221178829 # number of cpu cycles simulated +system.cpu.num_insts 2220985165 # Number of instructions executed +system.cpu.num_refs 545896474 # Number of memory references + +---------- End Simulation Statistics ---------- diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr new file mode 100644 index 000000000..cf3ec3bba --- /dev/null +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr @@ -0,0 +1,12 @@ +Warning: rounding error > tolerance + 0.002000 rounded to 0 +Warning: rounding error > tolerance + 0.002000 rounded to 0 +warn: No kernel set for full system simulation. Assuming you know what you're doing... +Listening for t1000 connection on port 3456 +Listening for t1000 connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... +warn: Ignoring write to SPARC ERROR regsiter +warn: Ignoring write to SPARC ERROR regsiter +warn: Don't know what interrupt to clear for console. diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout new file mode 100644 index 000000000..c464fa957 --- /dev/null +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout @@ -0,0 +1,12 @@ +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 3 2007 19:48:02 +M5 started Sat Mar 3 19:58:15 2007 +M5 executing on zeep +command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic +Exiting @ tick 2221178828 because m5_exit instruction encountered diff --git a/tests/long/80.solaris-boot/test.py b/tests/long/80.solaris-boot/test.py new file mode 100644 index 000000000..1b9a4c255 --- /dev/null +++ b/tests/long/80.solaris-boot/test.py @@ -0,0 +1,29 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ali Saidi + +root.system.readfile = os.path.join(tests_root, 'halt.sh') diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini new file mode 100644 index 000000000..ccb504cd3 --- /dev/null +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -0,0 +1,68 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=workload +clock=1 +cpu_id=0 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +simulate_stalls=false +system=system +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +egid=100 +env= +euid=100 +executable=tests/test-progs/insttest/bin/sparc/linux/insttest +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out new file mode 100644 index 000000000..392fec336 --- /dev/null +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out @@ -0,0 +1,60 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 +zero=false + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +executable=tests/test-progs/insttest/bin/sparc/linux/insttest +input=cin +output=cout +env= +cwd= +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt new file mode 100644 index 000000000..4fe3d3732 --- /dev/null +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 104057 # Simulator instruction rate (inst/s) +host_mem_usage 179368 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 103746 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 10367 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 10366 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 10367 # number of cpu cycles simulated +system.cpu.num_insts 10367 # Number of instructions executed +system.cpu.num_refs 2607 # Number of memory references +system.cpu.workload.PROG:num_syscalls 8 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr new file mode 100644 index 000000000..a3b9f045a --- /dev/null +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr @@ -0,0 +1,4 @@ +warn: More than two loadable segments in ELF object. +warn: Ignoring segment @ 0x0 length 0x0. +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout new file mode 100644 index 000000000..567033922 --- /dev/null +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout @@ -0,0 +1,22 @@ +Begining test of difficult SPARC instructions... +LDSTUB: Passed +SWAP: Passed +CAS FAIL: Passed +CAS WORK: Passed +CASX FAIL: Passed +CASX WORK: Passed +LDTX: Passed +LDTW: Passed +Done +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 6 2007 15:43:35 +M5 started Tue Mar 6 15:52:39 2007 +M5 executing on zeep +command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic +Exiting @ tick 10366 because target called exit() diff --git a/tests/quick/02.insttest/test.py b/tests/quick/02.insttest/test.py new file mode 100644 index 000000000..93664fbef --- /dev/null +++ b/tests/quick/02.insttest/test.py @@ -0,0 +1,30 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ali Saidi + +root.system.cpu.workload = LiveProcess(cmd = 'insttest', + executable = binpath('insttest')) diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 034ed9fa0..ce952d718 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -7,43 +7,6 @@ max_tick=0 output_file=cout progress_interval=0 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt - [system] type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami @@ -177,7 +140,7 @@ read_only=true [system.intrctrl] type=IntrControl -cpu=system.cpu0 +sys=system [system.iobus] type=Bus @@ -224,15 +187,10 @@ port=system.membus.port[1] [system.sim_console] type=SimConsole -children=listener append_name=true intr_control=system.intrctrl -listener=system.sim_console.listener number=0 output=console - -[system.sim_console.listener] -type=ConsoleListener port=3456 [system.simple_disk] @@ -748,12 +706,3 @@ sim_console=system.sim_console system=system pio=system.iobus.port[24] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out index 35abc9f24..313620c59 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out @@ -34,40 +34,9 @@ clock=2 width=64 responder_set=false -[system.cpu0.itb] -type=AlphaITB -size=48 - -[system.cpu0.dtb] -type=AlphaDTB -size=64 - -[system.cpu0] -type=AtomicSimpleCPU -max_insts_any_thread=0 -max_insts_all_threads=0 -max_loads_any_thread=0 -max_loads_all_threads=0 -progress_interval=0 -system=system -cpu_id=0 -itb=system.cpu0.itb -dtb=system.cpu0.dtb -profile=0 -do_quiesce=true -do_checkpoint_insts=true -do_statistics_insts=true -clock=1 -phase=0 -defer_registration=false -width=1 -function_trace=false -function_trace_start=0 -simulate_stalls=false - [system.intrctrl] type=IntrControl -cpu=system.cpu0 +sys=system [system.tsunami] type=Tsunami @@ -132,6 +101,37 @@ image=system.disk2.image driveID=master delay=2000 +[system.cpu0.itb] +type=AlphaITB +size=48 + +[system.cpu0.dtb] +type=AlphaDTB +size=64 + +[system.cpu0] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +itb=system.cpu0.itb +dtb=system.cpu0.dtb +profile=0 +do_quiesce=true +do_checkpoint_insts=true +do_statistics_insts=true +clock=1 +phase=0 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + [system.cpu1.itb] type=AlphaITB size=48 @@ -275,15 +275,11 @@ size=16777216 platform=system.tsunami system=system -[system.sim_console.listener] -type=ConsoleListener -port=3456 - [system.sim_console] type=SimConsole -listener=system.sim_console.listener intr_control=system.intrctrl output=console +port=3456 append_name=true number=0 @@ -654,51 +650,3 @@ clock=2 width=64 responder_set=true -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index fbc68db88..8cb8b6cbd 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -7,43 +7,6 @@ max_tick=0 output_file=cout progress_interval=0 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt - [system] type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami @@ -143,7 +106,7 @@ read_only=true [system.intrctrl] type=IntrControl -cpu=system.cpu +sys=system [system.iobus] type=Bus @@ -190,15 +153,10 @@ port=system.membus.port[1] [system.sim_console] type=SimConsole -children=listener append_name=true intr_control=system.intrctrl -listener=system.sim_console.listener number=0 output=console - -[system.sim_console.listener] -type=ConsoleListener port=3456 [system.simple_disk] @@ -714,12 +672,3 @@ sim_console=system.sim_console system=system pio=system.iobus.port[24] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out index 673f2c89c..ab56c5d90 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out @@ -34,40 +34,9 @@ clock=2 width=64 responder_set=false -[system.cpu.itb] -type=AlphaITB -size=48 - -[system.cpu.dtb] -type=AlphaDTB -size=64 - -[system.cpu] -type=AtomicSimpleCPU -max_insts_any_thread=0 -max_insts_all_threads=0 -max_loads_any_thread=0 -max_loads_all_threads=0 -progress_interval=0 -system=system -cpu_id=0 -itb=system.cpu.itb -dtb=system.cpu.dtb -profile=0 -do_quiesce=true -do_checkpoint_insts=true -do_statistics_insts=true -clock=1 -phase=0 -defer_registration=false -width=1 -function_trace=false -function_trace_start=0 -simulate_stalls=false - [system.intrctrl] type=IntrControl -cpu=system.cpu +sys=system [system.tsunami] type=Tsunami @@ -244,18 +213,45 @@ size=16777216 platform=system.tsunami system=system -[system.sim_console.listener] -type=ConsoleListener -port=3456 - [system.sim_console] type=SimConsole -listener=system.sim_console.listener intr_control=system.intrctrl output=console +port=3456 append_name=true number=0 +[system.cpu.itb] +type=AlphaITB +size=48 + +[system.cpu.dtb] +type=AlphaDTB +size=64 + +[system.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +itb=system.cpu.itb +dtb=system.cpu.dtb +profile=0 +do_quiesce=true +do_checkpoint_insts=true +do_statistics_insts=true +clock=1 +phase=0 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + [system.tsunami.console] type=AlphaConsole sim_console=system.sim_console @@ -623,51 +619,3 @@ clock=2 width=64 responder_set=true -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 5a824717f..856856ae8 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -7,43 +7,6 @@ max_tick=0 output_file=cout progress_interval=0 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt - [system] type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami @@ -173,7 +136,7 @@ read_only=true [system.intrctrl] type=IntrControl -cpu=system.cpu0 +sys=system [system.iobus] type=Bus @@ -220,15 +183,10 @@ port=system.membus.port[1] [system.sim_console] type=SimConsole -children=listener append_name=true intr_control=system.intrctrl -listener=system.sim_console.listener number=0 output=console - -[system.sim_console.listener] -type=ConsoleListener port=3456 [system.simple_disk] @@ -744,12 +702,3 @@ sim_console=system.sim_console system=system pio=system.iobus.port[24] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out index c1e5baadb..a4dd003e4 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out @@ -34,40 +34,9 @@ clock=2 width=64 responder_set=false -[system.cpu0.itb] -type=AlphaITB -size=48 - -[system.cpu0.dtb] -type=AlphaDTB -size=64 - -[system.cpu0] -type=TimingSimpleCPU -max_insts_any_thread=0 -max_insts_all_threads=0 -max_loads_any_thread=0 -max_loads_all_threads=0 -progress_interval=0 -system=system -cpu_id=0 -itb=system.cpu0.itb -dtb=system.cpu0.dtb -profile=0 -do_quiesce=true -do_checkpoint_insts=true -do_statistics_insts=true -clock=1 -phase=0 -defer_registration=false -// width not specified -function_trace=false -function_trace_start=0 -// simulate_stalls not specified - [system.intrctrl] type=IntrControl -cpu=system.cpu0 +sys=system [system.tsunami] type=Tsunami @@ -132,6 +101,37 @@ image=system.disk2.image driveID=master delay=2000 +[system.cpu0.itb] +type=AlphaITB +size=48 + +[system.cpu0.dtb] +type=AlphaDTB +size=64 + +[system.cpu0] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +itb=system.cpu0.itb +dtb=system.cpu0.dtb +profile=0 +do_quiesce=true +do_checkpoint_insts=true +do_statistics_insts=true +clock=1 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + [system.cpu1.itb] type=AlphaITB size=48 @@ -275,15 +275,11 @@ size=16777216 platform=system.tsunami system=system -[system.sim_console.listener] -type=ConsoleListener -port=3456 - [system.sim_console] type=SimConsole -listener=system.sim_console.listener intr_control=system.intrctrl output=console +port=3456 append_name=true number=0 @@ -654,51 +650,3 @@ clock=2 width=64 responder_set=true -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 104bbce36..6f48977b0 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -7,43 +7,6 @@ max_tick=0 output_file=cout progress_interval=0 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt - [system] type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami @@ -141,7 +104,7 @@ read_only=true [system.intrctrl] type=IntrControl -cpu=system.cpu +sys=system [system.iobus] type=Bus @@ -188,15 +151,10 @@ port=system.membus.port[1] [system.sim_console] type=SimConsole -children=listener append_name=true intr_control=system.intrctrl -listener=system.sim_console.listener number=0 output=console - -[system.sim_console.listener] -type=ConsoleListener port=3456 [system.simple_disk] @@ -712,12 +670,3 @@ sim_console=system.sim_console system=system pio=system.iobus.port[24] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out index 8791359a1..a99b59ae7 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out @@ -34,40 +34,9 @@ clock=2 width=64 responder_set=false -[system.cpu.itb] -type=AlphaITB -size=48 - -[system.cpu.dtb] -type=AlphaDTB -size=64 - -[system.cpu] -type=TimingSimpleCPU -max_insts_any_thread=0 -max_insts_all_threads=0 -max_loads_any_thread=0 -max_loads_all_threads=0 -progress_interval=0 -system=system -cpu_id=0 -itb=system.cpu.itb -dtb=system.cpu.dtb -profile=0 -do_quiesce=true -do_checkpoint_insts=true -do_statistics_insts=true -clock=1 -phase=0 -defer_registration=false -// width not specified -function_trace=false -function_trace_start=0 -// simulate_stalls not specified - [system.intrctrl] type=IntrControl -cpu=system.cpu +sys=system [system.tsunami] type=Tsunami @@ -244,18 +213,45 @@ size=16777216 platform=system.tsunami system=system -[system.sim_console.listener] -type=ConsoleListener -port=3456 - [system.sim_console] type=SimConsole -listener=system.sim_console.listener intr_control=system.intrctrl output=console +port=3456 append_name=true number=0 +[system.cpu.itb] +type=AlphaITB +size=48 + +[system.cpu.dtb] +type=AlphaDTB +size=64 + +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +itb=system.cpu.itb +dtb=system.cpu.dtb +profile=0 +do_quiesce=true +do_checkpoint_insts=true +do_statistics_insts=true +clock=1 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + [system.tsunami.console] type=AlphaConsole sim_console=system.sim_console @@ -623,51 +619,3 @@ clock=2 width=64 responder_set=true -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini new file mode 100644 index 000000000..05eb91461 --- /dev/null +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -0,0 +1,621 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[exetrace] +intel_format=false +legion_lockstep=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem l2c membus physmem toL2Bus +mem_mode=timing +physmem=system.physmem + +[system.cpu0] +type=MemTest +children=l1c +atomic=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +trace_addr=0 +functional=system.funcmem.port +test=system.cpu0.l1c.cpu_side + +[system.cpu0.l1c] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=12 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu0.l1c.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.test +mem_side=system.toL2Bus.port[1] + +[system.cpu0.l1c.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + +[system.cpu1] +type=MemTest +children=l1c +atomic=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +trace_addr=0 +functional=system.funcmem.functional +test=system.cpu1.l1c.cpu_side + +[system.cpu1.l1c] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=12 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu1.l1c.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.test +mem_side=system.toL2Bus.port[2] + +[system.cpu1.l1c.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + +[system.cpu2] +type=MemTest +children=l1c +atomic=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +trace_addr=0 +functional=system.funcmem.functional +test=system.cpu2.l1c.cpu_side + +[system.cpu2.l1c] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=12 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu2.l1c.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.test +mem_side=system.toL2Bus.port[3] + +[system.cpu2.l1c.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + +[system.cpu3] +type=MemTest +children=l1c +atomic=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +trace_addr=0 +functional=system.funcmem.functional +test=system.cpu3.l1c.cpu_side + +[system.cpu3.l1c] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=12 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu3.l1c.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.test +mem_side=system.toL2Bus.port[4] + +[system.cpu3.l1c.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + +[system.cpu4] +type=MemTest +children=l1c +atomic=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +trace_addr=0 +functional=system.funcmem.functional +test=system.cpu4.l1c.cpu_side + +[system.cpu4.l1c] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=12 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu4.l1c.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu4.test +mem_side=system.toL2Bus.port[5] + +[system.cpu4.l1c.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + +[system.cpu5] +type=MemTest +children=l1c +atomic=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +trace_addr=0 +functional=system.funcmem.functional +test=system.cpu5.l1c.cpu_side + +[system.cpu5.l1c] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=12 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu5.l1c.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu5.test +mem_side=system.toL2Bus.port[6] + +[system.cpu5.l1c.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + +[system.cpu6] +type=MemTest +children=l1c +atomic=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +trace_addr=0 +functional=system.funcmem.functional +test=system.cpu6.l1c.cpu_side + +[system.cpu6.l1c] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=12 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu6.l1c.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu6.test +mem_side=system.toL2Bus.port[7] + +[system.cpu6.l1c.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + +[system.cpu7] +type=MemTest +children=l1c +atomic=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +trace_addr=0 +functional=system.funcmem.functional +test=system.cpu7.l1c.cpu_side + +[system.cpu7.l1c] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=12 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu7.l1c.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu7.test +mem_side=system.toL2Bus.port[8] + +[system.cpu7.l1c.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + +[system.funcmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +functional=system.cpu7.functional +port=system.cpu0.functional + +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=10 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=65536 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[0] + +[system.membus] +type=Bus +bus_id=0 +clock=2 +responder_set=false +width=16 +port=system.l2c.mem_side system.physmem.port + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[1] + +[system.toL2Bus] +type=Bus +bus_id=0 +clock=2 +responder_set=false +width=16 +port=system.l2c.cpu_side system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side + +[trace] +bufsize=0 +cycle=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out new file mode 100644 index 000000000..b8ae04bc0 --- /dev/null +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out @@ -0,0 +1,574 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 +zero=false + +[system] +type=System +physmem=system.physmem +mem_mode=timing + +[system.membus] +type=Bus +bus_id=0 +clock=2 +width=16 +responder_set=false + +[system.l2c] +type=BaseCache +size=65536 +assoc=8 +block_size=64 +latency=10 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu6] +type=MemTest +memory_size=65536 +percent_reads=65 +percent_functional=50 +percent_uncacheable=10 +progress_interval=10000 +percent_source_unaligned=50 +percent_dest_unaligned=50 +trace_addr=0 +max_loads=100000 +atomic=false + +[system.cpu6.l1c.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu6.l1c] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1 +mshrs=12 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu6.l1c.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu4] +type=MemTest +memory_size=65536 +percent_reads=65 +percent_functional=50 +percent_uncacheable=10 +progress_interval=10000 +percent_source_unaligned=50 +percent_dest_unaligned=50 +trace_addr=0 +max_loads=100000 +atomic=false + +[system.cpu4.l1c.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu4.l1c] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1 +mshrs=12 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu4.l1c.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu5] +type=MemTest +memory_size=65536 +percent_reads=65 +percent_functional=50 +percent_uncacheable=10 +progress_interval=10000 +percent_source_unaligned=50 +percent_dest_unaligned=50 +trace_addr=0 +max_loads=100000 +atomic=false + +[system.cpu5.l1c.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu5.l1c] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1 +mshrs=12 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu5.l1c.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu2] +type=MemTest +memory_size=65536 +percent_reads=65 +percent_functional=50 +percent_uncacheable=10 +progress_interval=10000 +percent_source_unaligned=50 +percent_dest_unaligned=50 +trace_addr=0 +max_loads=100000 +atomic=false + +[system.cpu2.l1c.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu2.l1c] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1 +mshrs=12 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu2.l1c.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu3] +type=MemTest +memory_size=65536 +percent_reads=65 +percent_functional=50 +percent_uncacheable=10 +progress_interval=10000 +percent_source_unaligned=50 +percent_dest_unaligned=50 +trace_addr=0 +max_loads=100000 +atomic=false + +[system.cpu3.l1c.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu3.l1c] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1 +mshrs=12 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu3.l1c.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu0] +type=MemTest +memory_size=65536 +percent_reads=65 +percent_functional=50 +percent_uncacheable=10 +progress_interval=10000 +percent_source_unaligned=50 +percent_dest_unaligned=50 +trace_addr=0 +max_loads=100000 +atomic=false + +[system.cpu0.l1c.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu0.l1c] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1 +mshrs=12 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu0.l1c.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu1] +type=MemTest +memory_size=65536 +percent_reads=65 +percent_functional=50 +percent_uncacheable=10 +progress_interval=10000 +percent_source_unaligned=50 +percent_dest_unaligned=50 +trace_addr=0 +max_loads=100000 +atomic=false + +[system.cpu1.l1c.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu1.l1c] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1 +mshrs=12 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu1.l1c.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.funcmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 +zero=false + +[system.cpu7] +type=MemTest +memory_size=65536 +percent_reads=65 +percent_functional=50 +percent_uncacheable=10 +progress_interval=10000 +percent_source_unaligned=50 +percent_dest_unaligned=50 +trace_addr=0 +max_loads=100000 +atomic=false + +[system.cpu7.l1c.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu7.l1c] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1 +mshrs=12 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu7.l1c.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.toL2Bus] +type=Bus +bus_id=0 +clock=2 +width=16 +responder_set=false + +[trace] +flags= +start=0 +cycle=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +legion_lockstep=false +trace_system=client + +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt new file mode 100644 index 000000000..a65b235b0 --- /dev/null +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt @@ -0,0 +1,952 @@ + +---------- Begin Simulation Statistics ---------- +host_mem_usage 435124 # Number of bytes of host memory used +host_seconds 28.46 # Real time elapsed on the host +host_tick_rate 202211 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_seconds 0.000006 # Number of seconds simulated +sim_ticks 5755736 # Number of ticks simulated +system.cpu0.l1c.ReadReq_accesses 45048 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_avg_miss_latency 959.688548 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 884.132516 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_hits 7543 # number of ReadReq hits +system.cpu0.l1c.ReadReq_miss_latency 35993119 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_rate 0.832556 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_misses 37505 # number of ReadReq misses +system.cpu0.l1c.ReadReq_mshr_miss_latency 33159390 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate 0.832556 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_misses 37505 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable 9815 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu0.l1c.ReadResp_mshr_uncacheable_latency 17521633 # number of ReadResp MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_accesses 24308 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_avg_miss_latency 862.246942 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 778.821396 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_hits 1173 # number of WriteReq hits +system.cpu0.l1c.WriteReq_miss_latency 19948083 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_rate 0.951744 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_misses 23135 # number of WriteReq misses +system.cpu0.l1c.WriteReq_mshr_miss_latency 18018033 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_rate 0.951744 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_misses 23135 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_uncacheable 5428 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu0.l1c.WriteResp_mshr_uncacheable_latency 10755873 # number of WriteResp MSHR uncacheable cycles +system.cpu0.l1c.avg_blocked_cycles_no_mshrs 81.366905 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.l1c.avg_refs 0.417208 # Average number of references to valid blocks. +system.cpu0.l1c.blocked_no_mshrs 69811 # number of cycles access was blocked +system.cpu0.l1c.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.l1c.blocked_cycles_no_mshrs 5680305 # number of cycles access was blocked +system.cpu0.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.l1c.cache_copies 0 # number of cache copies performed +system.cpu0.l1c.demand_accesses 69356 # number of demand (read+write) accesses +system.cpu0.l1c.demand_avg_miss_latency 922.513226 # average overall miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency 843.954865 # average overall mshr miss latency +system.cpu0.l1c.demand_hits 8716 # number of demand (read+write) hits +system.cpu0.l1c.demand_miss_latency 55941202 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_rate 0.874330 # miss rate for demand accesses +system.cpu0.l1c.demand_misses 60640 # number of demand (read+write) misses +system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.l1c.demand_mshr_miss_latency 51177423 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_rate 0.874330 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_misses 60640 # number of demand (read+write) MSHR misses +system.cpu0.l1c.fast_writes 0 # number of fast writes performed +system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.l1c.overall_accesses 69356 # number of overall (read+write) accesses +system.cpu0.l1c.overall_avg_miss_latency 922.513226 # average overall miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency 843.954865 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_hits 8716 # number of overall hits +system.cpu0.l1c.overall_miss_latency 55941202 # number of overall miss cycles +system.cpu0.l1c.overall_miss_rate 0.874330 # miss rate for overall accesses +system.cpu0.l1c.overall_misses 60640 # number of overall misses +system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.l1c.overall_mshr_miss_latency 51177423 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_rate 0.874330 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_misses 60640 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_misses 15243 # number of overall MSHR uncacheable misses +system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu0.l1c.protocol.read_invalid 109554 # read misses to invalid blocks +system.cpu0.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu0.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu0.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu0.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu0.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu0.l1c.protocol.snoop_read_exclusive 2807 # read snoops on exclusive blocks +system.cpu0.l1c.protocol.snoop_read_modified 12380 # read snoops on modified blocks +system.cpu0.l1c.protocol.snoop_read_owned 7157 # read snoops on owned blocks +system.cpu0.l1c.protocol.snoop_read_shared 22767 # read snoops on shared blocks +system.cpu0.l1c.protocol.snoop_readex_exclusive 1535 # readEx snoops on exclusive blocks +system.cpu0.l1c.protocol.snoop_readex_modified 6851 # readEx snoops on modified blocks +system.cpu0.l1c.protocol.snoop_readex_owned 3877 # readEx snoops on owned blocks +system.cpu0.l1c.protocol.snoop_readex_shared 12465 # readEx snoops on shared blocks +system.cpu0.l1c.protocol.snoop_upgrade_owned 887 # upgrade snoops on owned blocks +system.cpu0.l1c.protocol.snoop_upgrade_shared 2994 # upgradee snoops on shared blocks +system.cpu0.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu0.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu0.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu0.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu0.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu0.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu0.l1c.protocol.write_invalid 60706 # write misses to invalid blocks +system.cpu0.l1c.protocol.write_owned 1361 # write misses to owned blocks +system.cpu0.l1c.protocol.write_shared 4416 # write misses to shared blocks +system.cpu0.l1c.replacements 27529 # number of replacements +system.cpu0.l1c.sampled_refs 27883 # Sample count of references to valid blocks. +system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.l1c.tagsinuse 342.460043 # Cycle average of tags in use +system.cpu0.l1c.total_refs 11633 # Total number of references to valid blocks. +system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.l1c.writebacks 10915 # number of writebacks +system.cpu0.num_copies 0 # number of copy accesses completed +system.cpu0.num_reads 99586 # number of read accesses completed +system.cpu0.num_writes 53803 # number of write accesses completed +system.cpu1.l1c.ReadReq_accesses 44416 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_avg_miss_latency 969.343786 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 893.327484 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_hits 7486 # number of ReadReq hits +system.cpu1.l1c.ReadReq_miss_latency 35797866 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_rate 0.831457 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_misses 36930 # number of ReadReq misses +system.cpu1.l1c.ReadReq_mshr_miss_latency 32990584 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate 0.831457 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_misses 36930 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable 9894 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu1.l1c.ReadResp_mshr_uncacheable_latency 17663360 # number of ReadResp MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_accesses 24084 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_avg_miss_latency 871.179293 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 786.258930 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_hits 1155 # number of WriteReq hits +system.cpu1.l1c.WriteReq_miss_latency 19975270 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_rate 0.952043 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_misses 22929 # number of WriteReq misses +system.cpu1.l1c.WriteReq_mshr_miss_latency 18028131 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_rate 0.952043 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_misses 22929 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_uncacheable 5271 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu1.l1c.WriteResp_mshr_uncacheable_latency 10523322 # number of WriteResp MSHR uncacheable cycles +system.cpu1.l1c.avg_blocked_cycles_no_mshrs 82.260179 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.l1c.avg_refs 0.414867 # Average number of references to valid blocks. +system.cpu1.l1c.blocked_no_mshrs 68941 # number of cycles access was blocked +system.cpu1.l1c.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.l1c.blocked_cycles_no_mshrs 5671099 # number of cycles access was blocked +system.cpu1.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.l1c.cache_copies 0 # number of cache copies performed +system.cpu1.l1c.demand_accesses 68500 # number of demand (read+write) accesses +system.cpu1.l1c.demand_avg_miss_latency 931.741860 # average overall miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency 852.314857 # average overall mshr miss latency +system.cpu1.l1c.demand_hits 8641 # number of demand (read+write) hits +system.cpu1.l1c.demand_miss_latency 55773136 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_rate 0.873854 # miss rate for demand accesses +system.cpu1.l1c.demand_misses 59859 # number of demand (read+write) misses +system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.l1c.demand_mshr_miss_latency 51018715 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_rate 0.873854 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_misses 59859 # number of demand (read+write) MSHR misses +system.cpu1.l1c.fast_writes 0 # number of fast writes performed +system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.l1c.overall_accesses 68500 # number of overall (read+write) accesses +system.cpu1.l1c.overall_avg_miss_latency 931.741860 # average overall miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency 852.314857 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_hits 8641 # number of overall hits +system.cpu1.l1c.overall_miss_latency 55773136 # number of overall miss cycles +system.cpu1.l1c.overall_miss_rate 0.873854 # miss rate for overall accesses +system.cpu1.l1c.overall_misses 59859 # number of overall misses +system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.l1c.overall_mshr_miss_latency 51018715 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_rate 0.873854 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_misses 59859 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_misses 15165 # number of overall MSHR uncacheable misses +system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu1.l1c.protocol.read_invalid 114228 # read misses to invalid blocks +system.cpu1.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu1.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu1.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu1.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu1.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu1.l1c.protocol.snoop_read_exclusive 2718 # read snoops on exclusive blocks +system.cpu1.l1c.protocol.snoop_read_modified 12396 # read snoops on modified blocks +system.cpu1.l1c.protocol.snoop_read_owned 7348 # read snoops on owned blocks +system.cpu1.l1c.protocol.snoop_read_shared 23222 # read snoops on shared blocks +system.cpu1.l1c.protocol.snoop_readex_exclusive 1497 # readEx snoops on exclusive blocks +system.cpu1.l1c.protocol.snoop_readex_modified 6706 # readEx snoops on modified blocks +system.cpu1.l1c.protocol.snoop_readex_owned 3865 # readEx snoops on owned blocks +system.cpu1.l1c.protocol.snoop_readex_shared 12512 # readEx snoops on shared blocks +system.cpu1.l1c.protocol.snoop_upgrade_owned 852 # upgrade snoops on owned blocks +system.cpu1.l1c.protocol.snoop_upgrade_shared 2973 # upgradee snoops on shared blocks +system.cpu1.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu1.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu1.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu1.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu1.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu1.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu1.l1c.protocol.write_invalid 61595 # write misses to invalid blocks +system.cpu1.l1c.protocol.write_owned 1320 # write misses to owned blocks +system.cpu1.l1c.protocol.write_shared 4183 # write misses to shared blocks +system.cpu1.l1c.replacements 27139 # number of replacements +system.cpu1.l1c.sampled_refs 27498 # Sample count of references to valid blocks. +system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.l1c.tagsinuse 341.113569 # Cycle average of tags in use +system.cpu1.l1c.total_refs 11408 # Total number of references to valid blocks. +system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.l1c.writebacks 10884 # number of writebacks +system.cpu1.num_copies 0 # number of copy accesses completed +system.cpu1.num_reads 98821 # number of read accesses completed +system.cpu1.num_writes 53366 # number of write accesses completed +system.cpu2.l1c.ReadReq_accesses 45016 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_avg_miss_latency 956.031371 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 880.781951 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_hits 7529 # number of ReadReq hits +system.cpu2.l1c.ReadReq_miss_latency 35838748 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_rate 0.832748 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_misses 37487 # number of ReadReq misses +system.cpu2.l1c.ReadReq_mshr_miss_latency 33017873 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832748 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_misses 37487 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable 9887 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu2.l1c.ReadResp_mshr_uncacheable_latency 17582637 # number of ReadResp MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_accesses 24456 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_avg_miss_latency 859.707355 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 777.777296 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_hits 1165 # number of WriteReq hits +system.cpu2.l1c.WriteReq_miss_latency 20023444 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_rate 0.952363 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_misses 23291 # number of WriteReq misses +system.cpu2.l1c.WriteReq_mshr_miss_latency 18115211 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_rate 0.952363 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_misses 23291 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_uncacheable 5362 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu2.l1c.WriteResp_mshr_uncacheable_latency 10583136 # number of WriteResp MSHR uncacheable cycles +system.cpu2.l1c.avg_blocked_cycles_no_mshrs 81.152375 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.l1c.avg_refs 0.404365 # Average number of references to valid blocks. +system.cpu2.l1c.blocked_no_mshrs 69867 # number of cycles access was blocked +system.cpu2.l1c.blocked_no_targets 0 # number of cycles access was blocked +system.cpu2.l1c.blocked_cycles_no_mshrs 5669873 # number of cycles access was blocked +system.cpu2.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.l1c.cache_copies 0 # number of cache copies performed +system.cpu2.l1c.demand_accesses 69472 # number of demand (read+write) accesses +system.cpu2.l1c.demand_avg_miss_latency 919.118628 # average overall miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency 841.309092 # average overall mshr miss latency +system.cpu2.l1c.demand_hits 8694 # number of demand (read+write) hits +system.cpu2.l1c.demand_miss_latency 55862192 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_rate 0.874856 # miss rate for demand accesses +system.cpu2.l1c.demand_misses 60778 # number of demand (read+write) misses +system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu2.l1c.demand_mshr_miss_latency 51133084 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_rate 0.874856 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_misses 60778 # number of demand (read+write) MSHR misses +system.cpu2.l1c.fast_writes 0 # number of fast writes performed +system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.l1c.overall_accesses 69472 # number of overall (read+write) accesses +system.cpu2.l1c.overall_avg_miss_latency 919.118628 # average overall miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency 841.309092 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_hits 8694 # number of overall hits +system.cpu2.l1c.overall_miss_latency 55862192 # number of overall miss cycles +system.cpu2.l1c.overall_miss_rate 0.874856 # miss rate for overall accesses +system.cpu2.l1c.overall_misses 60778 # number of overall misses +system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu2.l1c.overall_mshr_miss_latency 51133084 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_rate 0.874856 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_misses 60778 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_misses 15249 # number of overall MSHR uncacheable misses +system.cpu2.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu2.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu2.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu2.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu2.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu2.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu2.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu2.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu2.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu2.l1c.protocol.read_invalid 111528 # read misses to invalid blocks +system.cpu2.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu2.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu2.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu2.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu2.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu2.l1c.protocol.snoop_read_exclusive 2757 # read snoops on exclusive blocks +system.cpu2.l1c.protocol.snoop_read_modified 12587 # read snoops on modified blocks +system.cpu2.l1c.protocol.snoop_read_owned 7252 # read snoops on owned blocks +system.cpu2.l1c.protocol.snoop_read_shared 22967 # read snoops on shared blocks +system.cpu2.l1c.protocol.snoop_readex_exclusive 1579 # readEx snoops on exclusive blocks +system.cpu2.l1c.protocol.snoop_readex_modified 6680 # readEx snoops on modified blocks +system.cpu2.l1c.protocol.snoop_readex_owned 3891 # readEx snoops on owned blocks +system.cpu2.l1c.protocol.snoop_readex_shared 12468 # readEx snoops on shared blocks +system.cpu2.l1c.protocol.snoop_upgrade_owned 850 # upgrade snoops on owned blocks +system.cpu2.l1c.protocol.snoop_upgrade_shared 2951 # upgradee snoops on shared blocks +system.cpu2.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu2.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu2.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu2.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu2.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu2.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu2.l1c.protocol.write_invalid 57618 # write misses to invalid blocks +system.cpu2.l1c.protocol.write_owned 1263 # write misses to owned blocks +system.cpu2.l1c.protocol.write_shared 4251 # write misses to shared blocks +system.cpu2.l1c.replacements 28062 # number of replacements +system.cpu2.l1c.sampled_refs 28405 # Sample count of references to valid blocks. +system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.l1c.tagsinuse 344.040679 # Cycle average of tags in use +system.cpu2.l1c.total_refs 11486 # Total number of references to valid blocks. +system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.l1c.writebacks 11295 # number of writebacks +system.cpu2.num_copies 0 # number of copy accesses completed +system.cpu2.num_reads 100000 # number of read accesses completed +system.cpu2.num_writes 54133 # number of write accesses completed +system.cpu3.l1c.ReadReq_accesses 44504 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_avg_miss_latency 968.772953 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 892.914985 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_hits 7428 # number of ReadReq hits +system.cpu3.l1c.ReadReq_miss_latency 35918226 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_rate 0.833094 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_misses 37076 # number of ReadReq misses +system.cpu3.l1c.ReadReq_mshr_miss_latency 33105716 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate 0.833094 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_misses 37076 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable 9876 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu3.l1c.ReadResp_mshr_uncacheable_latency 17594905 # number of ReadResp MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_accesses 24087 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_avg_miss_latency 868.499565 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 784.537397 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_hits 1117 # number of WriteReq hits +system.cpu3.l1c.WriteReq_miss_latency 19949435 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_rate 0.953626 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_misses 22970 # number of WriteReq misses +system.cpu3.l1c.WriteReq_mshr_miss_latency 18020824 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_rate 0.953626 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_misses 22970 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_uncacheable 5355 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu3.l1c.WriteResp_mshr_uncacheable_latency 10637792 # number of WriteResp MSHR uncacheable cycles +system.cpu3.l1c.avg_blocked_cycles_no_mshrs 82.097897 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.l1c.avg_refs 0.411489 # Average number of references to valid blocks. +system.cpu3.l1c.blocked_no_mshrs 69124 # number of cycles access was blocked +system.cpu3.l1c.blocked_no_targets 0 # number of cycles access was blocked +system.cpu3.l1c.blocked_cycles_no_mshrs 5674935 # number of cycles access was blocked +system.cpu3.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.l1c.cache_copies 0 # number of cache copies performed +system.cpu3.l1c.demand_accesses 68591 # number of demand (read+write) accesses +system.cpu3.l1c.demand_avg_miss_latency 930.414366 # average overall miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency 851.456217 # average overall mshr miss latency +system.cpu3.l1c.demand_hits 8545 # number of demand (read+write) hits +system.cpu3.l1c.demand_miss_latency 55867661 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_rate 0.875421 # miss rate for demand accesses +system.cpu3.l1c.demand_misses 60046 # number of demand (read+write) misses +system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu3.l1c.demand_mshr_miss_latency 51126540 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_rate 0.875421 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_misses 60046 # number of demand (read+write) MSHR misses +system.cpu3.l1c.fast_writes 0 # number of fast writes performed +system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.l1c.overall_accesses 68591 # number of overall (read+write) accesses +system.cpu3.l1c.overall_avg_miss_latency 930.414366 # average overall miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency 851.456217 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_hits 8545 # number of overall hits +system.cpu3.l1c.overall_miss_latency 55867661 # number of overall miss cycles +system.cpu3.l1c.overall_miss_rate 0.875421 # miss rate for overall accesses +system.cpu3.l1c.overall_misses 60046 # number of overall misses +system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu3.l1c.overall_mshr_miss_latency 51126540 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_rate 0.875421 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_misses 60046 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_misses 15231 # number of overall MSHR uncacheable misses +system.cpu3.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu3.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu3.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu3.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu3.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu3.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu3.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu3.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu3.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu3.l1c.protocol.read_invalid 110901 # read misses to invalid blocks +system.cpu3.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu3.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu3.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu3.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu3.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu3.l1c.protocol.snoop_read_exclusive 2843 # read snoops on exclusive blocks +system.cpu3.l1c.protocol.snoop_read_modified 12490 # read snoops on modified blocks +system.cpu3.l1c.protocol.snoop_read_owned 7235 # read snoops on owned blocks +system.cpu3.l1c.protocol.snoop_read_shared 23011 # read snoops on shared blocks +system.cpu3.l1c.protocol.snoop_readex_exclusive 1535 # readEx snoops on exclusive blocks +system.cpu3.l1c.protocol.snoop_readex_modified 6732 # readEx snoops on modified blocks +system.cpu3.l1c.protocol.snoop_readex_owned 3954 # readEx snoops on owned blocks +system.cpu3.l1c.protocol.snoop_readex_shared 12354 # readEx snoops on shared blocks +system.cpu3.l1c.protocol.snoop_upgrade_owned 858 # upgrade snoops on owned blocks +system.cpu3.l1c.protocol.snoop_upgrade_shared 3087 # upgradee snoops on shared blocks +system.cpu3.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu3.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu3.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu3.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu3.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu3.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu3.l1c.protocol.write_invalid 59061 # write misses to invalid blocks +system.cpu3.l1c.protocol.write_owned 1261 # write misses to owned blocks +system.cpu3.l1c.protocol.write_shared 4235 # write misses to shared blocks +system.cpu3.l1c.replacements 27216 # number of replacements +system.cpu3.l1c.sampled_refs 27556 # Sample count of references to valid blocks. +system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.l1c.tagsinuse 341.602377 # Cycle average of tags in use +system.cpu3.l1c.total_refs 11339 # Total number of references to valid blocks. +system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.l1c.writebacks 10831 # number of writebacks +system.cpu3.num_copies 0 # number of copy accesses completed +system.cpu3.num_reads 98893 # number of read accesses completed +system.cpu3.num_writes 53654 # number of write accesses completed +system.cpu4.l1c.ReadReq_accesses 44272 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_avg_miss_latency 976.655364 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 901.292278 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_hits 7468 # number of ReadReq hits +system.cpu4.l1c.ReadReq_miss_latency 35944824 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_rate 0.831316 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_misses 36804 # number of ReadReq misses +system.cpu4.l1c.ReadReq_mshr_miss_latency 33171161 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate 0.831316 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_misses 36804 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable 9822 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu4.l1c.ReadResp_mshr_uncacheable_latency 17532387 # number of ReadResp MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_accesses 23994 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_avg_miss_latency 874.063859 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 788.017488 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_hits 1178 # number of WriteReq hits +system.cpu4.l1c.WriteReq_miss_latency 19942641 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_rate 0.950904 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_misses 22816 # number of WriteReq misses +system.cpu4.l1c.WriteReq_mshr_miss_latency 17979407 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_rate 0.950904 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_misses 22816 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_uncacheable 5315 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu4.l1c.WriteResp_mshr_uncacheable_latency 10563676 # number of WriteResp MSHR uncacheable cycles +system.cpu4.l1c.avg_blocked_cycles_no_mshrs 82.703233 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu4.l1c.avg_refs 0.416368 # Average number of references to valid blocks. +system.cpu4.l1c.blocked_no_mshrs 68707 # number of cycles access was blocked +system.cpu4.l1c.blocked_no_targets 0 # number of cycles access was blocked +system.cpu4.l1c.blocked_cycles_no_mshrs 5682291 # number of cycles access was blocked +system.cpu4.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu4.l1c.cache_copies 0 # number of cache copies performed +system.cpu4.l1c.demand_accesses 68266 # number of demand (read+write) accesses +system.cpu4.l1c.demand_avg_miss_latency 937.394582 # average overall miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency 857.943106 # average overall mshr miss latency +system.cpu4.l1c.demand_hits 8646 # number of demand (read+write) hits +system.cpu4.l1c.demand_miss_latency 55887465 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_rate 0.873348 # miss rate for demand accesses +system.cpu4.l1c.demand_misses 59620 # number of demand (read+write) misses +system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu4.l1c.demand_mshr_miss_latency 51150568 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_rate 0.873348 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_misses 59620 # number of demand (read+write) MSHR misses +system.cpu4.l1c.fast_writes 0 # number of fast writes performed +system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu4.l1c.overall_accesses 68266 # number of overall (read+write) accesses +system.cpu4.l1c.overall_avg_miss_latency 937.394582 # average overall miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency 857.943106 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_hits 8646 # number of overall hits +system.cpu4.l1c.overall_miss_latency 55887465 # number of overall miss cycles +system.cpu4.l1c.overall_miss_rate 0.873348 # miss rate for overall accesses +system.cpu4.l1c.overall_misses 59620 # number of overall misses +system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu4.l1c.overall_mshr_miss_latency 51150568 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_rate 0.873348 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_misses 59620 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_misses 15137 # number of overall MSHR uncacheable misses +system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu4.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu4.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu4.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu4.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu4.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu4.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu4.l1c.protocol.read_invalid 113154 # read misses to invalid blocks +system.cpu4.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu4.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu4.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu4.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu4.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu4.l1c.protocol.snoop_read_exclusive 2804 # read snoops on exclusive blocks +system.cpu4.l1c.protocol.snoop_read_modified 12453 # read snoops on modified blocks +system.cpu4.l1c.protocol.snoop_read_owned 7418 # read snoops on owned blocks +system.cpu4.l1c.protocol.snoop_read_shared 23136 # read snoops on shared blocks +system.cpu4.l1c.protocol.snoop_readex_exclusive 1528 # readEx snoops on exclusive blocks +system.cpu4.l1c.protocol.snoop_readex_modified 6607 # readEx snoops on modified blocks +system.cpu4.l1c.protocol.snoop_readex_owned 3922 # readEx snoops on owned blocks +system.cpu4.l1c.protocol.snoop_readex_shared 12524 # readEx snoops on shared blocks +system.cpu4.l1c.protocol.snoop_upgrade_owned 843 # upgrade snoops on owned blocks +system.cpu4.l1c.protocol.snoop_upgrade_shared 2904 # upgradee snoops on shared blocks +system.cpu4.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu4.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu4.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu4.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu4.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu4.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu4.l1c.protocol.write_invalid 59622 # write misses to invalid blocks +system.cpu4.l1c.protocol.write_owned 1265 # write misses to owned blocks +system.cpu4.l1c.protocol.write_shared 4187 # write misses to shared blocks +system.cpu4.l1c.replacements 27000 # number of replacements +system.cpu4.l1c.sampled_refs 27346 # Sample count of references to valid blocks. +system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu4.l1c.tagsinuse 342.121323 # Cycle average of tags in use +system.cpu4.l1c.total_refs 11386 # Total number of references to valid blocks. +system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu4.l1c.writebacks 10847 # number of writebacks +system.cpu4.num_copies 0 # number of copy accesses completed +system.cpu4.num_reads 98882 # number of read accesses completed +system.cpu4.num_writes 53288 # number of write accesses completed +system.cpu5.l1c.ReadReq_accesses 44218 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_avg_miss_latency 975.652027 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 898.818359 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_hits 7310 # number of ReadReq hits +system.cpu5.l1c.ReadReq_miss_latency 36009365 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_rate 0.834683 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_misses 36908 # number of ReadReq misses +system.cpu5.l1c.ReadReq_mshr_miss_latency 33173588 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate 0.834683 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_misses 36908 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable 9866 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu5.l1c.ReadResp_mshr_uncacheable_latency 17625443 # number of ReadResp MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_accesses 23923 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_avg_miss_latency 873.308611 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 788.173188 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_hits 1150 # number of WriteReq hits +system.cpu5.l1c.WriteReq_miss_latency 19887857 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_rate 0.951929 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_misses 22773 # number of WriteReq misses +system.cpu5.l1c.WriteReq_mshr_miss_latency 17949068 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_rate 0.951929 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_misses 22773 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_uncacheable 5207 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu5.l1c.WriteResp_mshr_uncacheable_latency 10374807 # number of WriteResp MSHR uncacheable cycles +system.cpu5.l1c.avg_blocked_cycles_no_mshrs 82.590363 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu5.l1c.avg_refs 0.413664 # Average number of references to valid blocks. +system.cpu5.l1c.blocked_no_mshrs 68944 # number of cycles access was blocked +system.cpu5.l1c.blocked_no_targets 0 # number of cycles access was blocked +system.cpu5.l1c.blocked_cycles_no_mshrs 5694110 # number of cycles access was blocked +system.cpu5.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu5.l1c.cache_copies 0 # number of cache copies performed +system.cpu5.l1c.demand_accesses 68141 # number of demand (read+write) accesses +system.cpu5.l1c.demand_avg_miss_latency 936.599956 # average overall miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency 856.598515 # average overall mshr miss latency +system.cpu5.l1c.demand_hits 8460 # number of demand (read+write) hits +system.cpu5.l1c.demand_miss_latency 55897222 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_rate 0.875846 # miss rate for demand accesses +system.cpu5.l1c.demand_misses 59681 # number of demand (read+write) misses +system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu5.l1c.demand_mshr_miss_latency 51122656 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_rate 0.875846 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_misses 59681 # number of demand (read+write) MSHR misses +system.cpu5.l1c.fast_writes 0 # number of fast writes performed +system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu5.l1c.overall_accesses 68141 # number of overall (read+write) accesses +system.cpu5.l1c.overall_avg_miss_latency 936.599956 # average overall miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency 856.598515 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_hits 8460 # number of overall hits +system.cpu5.l1c.overall_miss_latency 55897222 # number of overall miss cycles +system.cpu5.l1c.overall_miss_rate 0.875846 # miss rate for overall accesses +system.cpu5.l1c.overall_misses 59681 # number of overall misses +system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu5.l1c.overall_mshr_miss_latency 51122656 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_rate 0.875846 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_misses 59681 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_misses 15073 # number of overall MSHR uncacheable misses +system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu5.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu5.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu5.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu5.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu5.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu5.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu5.l1c.protocol.read_invalid 114279 # read misses to invalid blocks +system.cpu5.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu5.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu5.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu5.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu5.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu5.l1c.protocol.snoop_read_exclusive 2860 # read snoops on exclusive blocks +system.cpu5.l1c.protocol.snoop_read_modified 12253 # read snoops on modified blocks +system.cpu5.l1c.protocol.snoop_read_owned 7231 # read snoops on owned blocks +system.cpu5.l1c.protocol.snoop_read_shared 23182 # read snoops on shared blocks +system.cpu5.l1c.protocol.snoop_readex_exclusive 1499 # readEx snoops on exclusive blocks +system.cpu5.l1c.protocol.snoop_readex_modified 6757 # readEx snoops on modified blocks +system.cpu5.l1c.protocol.snoop_readex_owned 3896 # readEx snoops on owned blocks +system.cpu5.l1c.protocol.snoop_readex_shared 12461 # readEx snoops on shared blocks +system.cpu5.l1c.protocol.snoop_upgrade_owned 887 # upgrade snoops on owned blocks +system.cpu5.l1c.protocol.snoop_upgrade_shared 3020 # upgradee snoops on shared blocks +system.cpu5.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu5.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu5.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu5.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu5.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu5.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu5.l1c.protocol.write_invalid 60969 # write misses to invalid blocks +system.cpu5.l1c.protocol.write_owned 1349 # write misses to owned blocks +system.cpu5.l1c.protocol.write_shared 4191 # write misses to shared blocks +system.cpu5.l1c.replacements 26828 # number of replacements +system.cpu5.l1c.sampled_refs 27196 # Sample count of references to valid blocks. +system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu5.l1c.tagsinuse 340.865502 # Cycle average of tags in use +system.cpu5.l1c.total_refs 11250 # Total number of references to valid blocks. +system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu5.l1c.writebacks 10567 # number of writebacks +system.cpu5.num_copies 0 # number of copy accesses completed +system.cpu5.num_reads 97882 # number of read accesses completed +system.cpu5.num_writes 52965 # number of write accesses completed +system.cpu6.l1c.ReadReq_accesses 44971 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_avg_miss_latency 967.006541 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 890.563660 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_hits 7514 # number of ReadReq hits +system.cpu6.l1c.ReadReq_miss_latency 36221164 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_rate 0.832915 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_misses 37457 # number of ReadReq misses +system.cpu6.l1c.ReadReq_mshr_miss_latency 33357843 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate 0.832915 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_misses 37457 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable 9684 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu6.l1c.ReadResp_mshr_uncacheable_latency 17275344 # number of ReadResp MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_accesses 23996 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_avg_miss_latency 873.777515 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 790.631514 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_hits 1181 # number of WriteReq hits +system.cpu6.l1c.WriteReq_miss_latency 19935234 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_rate 0.950783 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_misses 22815 # number of WriteReq misses +system.cpu6.l1c.WriteReq_mshr_miss_latency 18038258 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_rate 0.950783 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_misses 22815 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_uncacheable 5345 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu6.l1c.WriteResp_mshr_uncacheable_latency 10602140 # number of WriteResp MSHR uncacheable cycles +system.cpu6.l1c.avg_blocked_cycles_no_mshrs 82.071085 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu6.l1c.avg_refs 0.412251 # Average number of references to valid blocks. +system.cpu6.l1c.blocked_no_mshrs 69157 # number of cycles access was blocked +system.cpu6.l1c.blocked_no_targets 0 # number of cycles access was blocked +system.cpu6.l1c.blocked_cycles_no_mshrs 5675790 # number of cycles access was blocked +system.cpu6.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu6.l1c.cache_copies 0 # number of cache copies performed +system.cpu6.l1c.demand_accesses 68967 # number of demand (read+write) accesses +system.cpu6.l1c.demand_avg_miss_latency 931.716187 # average overall miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency 852.735947 # average overall mshr miss latency +system.cpu6.l1c.demand_hits 8695 # number of demand (read+write) hits +system.cpu6.l1c.demand_miss_latency 56156398 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_rate 0.873925 # miss rate for demand accesses +system.cpu6.l1c.demand_misses 60272 # number of demand (read+write) misses +system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu6.l1c.demand_mshr_miss_latency 51396101 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_rate 0.873925 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_misses 60272 # number of demand (read+write) MSHR misses +system.cpu6.l1c.fast_writes 0 # number of fast writes performed +system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu6.l1c.overall_accesses 68967 # number of overall (read+write) accesses +system.cpu6.l1c.overall_avg_miss_latency 931.716187 # average overall miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency 852.735947 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_hits 8695 # number of overall hits +system.cpu6.l1c.overall_miss_latency 56156398 # number of overall miss cycles +system.cpu6.l1c.overall_miss_rate 0.873925 # miss rate for overall accesses +system.cpu6.l1c.overall_misses 60272 # number of overall misses +system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu6.l1c.overall_mshr_miss_latency 51396101 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_rate 0.873925 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_misses 60272 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_misses 15029 # number of overall MSHR uncacheable misses +system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu6.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu6.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu6.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu6.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu6.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu6.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu6.l1c.protocol.read_invalid 114488 # read misses to invalid blocks +system.cpu6.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu6.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu6.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu6.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu6.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu6.l1c.protocol.snoop_read_exclusive 2876 # read snoops on exclusive blocks +system.cpu6.l1c.protocol.snoop_read_modified 12371 # read snoops on modified blocks +system.cpu6.l1c.protocol.snoop_read_owned 7223 # read snoops on owned blocks +system.cpu6.l1c.protocol.snoop_read_shared 23305 # read snoops on shared blocks +system.cpu6.l1c.protocol.snoop_readex_exclusive 1616 # readEx snoops on exclusive blocks +system.cpu6.l1c.protocol.snoop_readex_modified 6693 # readEx snoops on modified blocks +system.cpu6.l1c.protocol.snoop_readex_owned 3909 # readEx snoops on owned blocks +system.cpu6.l1c.protocol.snoop_readex_shared 12446 # readEx snoops on shared blocks +system.cpu6.l1c.protocol.snoop_upgrade_owned 833 # upgrade snoops on owned blocks +system.cpu6.l1c.protocol.snoop_upgrade_shared 2948 # upgradee snoops on shared blocks +system.cpu6.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu6.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu6.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu6.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu6.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu6.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu6.l1c.protocol.write_invalid 58413 # write misses to invalid blocks +system.cpu6.l1c.protocol.write_owned 1374 # write misses to owned blocks +system.cpu6.l1c.protocol.write_shared 4109 # write misses to shared blocks +system.cpu6.l1c.replacements 27477 # number of replacements +system.cpu6.l1c.sampled_refs 27835 # Sample count of references to valid blocks. +system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu6.l1c.tagsinuse 342.134742 # Cycle average of tags in use +system.cpu6.l1c.total_refs 11475 # Total number of references to valid blocks. +system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu6.l1c.writebacks 10759 # number of writebacks +system.cpu6.num_copies 0 # number of copy accesses completed +system.cpu6.num_reads 99303 # number of read accesses completed +system.cpu6.num_writes 53385 # number of write accesses completed +system.cpu7.l1c.ReadReq_accesses 44438 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_avg_miss_latency 975.306986 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 899.340271 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_hits 7394 # number of ReadReq hits +system.cpu7.l1c.ReadReq_miss_latency 36129272 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_rate 0.833611 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_misses 37044 # number of ReadReq misses +system.cpu7.l1c.ReadReq_mshr_miss_latency 33315161 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate 0.833611 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_misses 37044 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable 9861 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu7.l1c.ReadResp_mshr_uncacheable_latency 17576395 # number of ReadResp MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_accesses 23999 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_avg_miss_latency 861.568979 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 776.580264 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_hits 1137 # number of WriteReq hits +system.cpu7.l1c.WriteReq_miss_latency 19697190 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_rate 0.952623 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_misses 22862 # number of WriteReq misses +system.cpu7.l1c.WriteReq_mshr_miss_latency 17754178 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_rate 0.952623 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_misses 22862 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_uncacheable 5386 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu7.l1c.WriteResp_mshr_uncacheable_latency 10720857 # number of WriteResp MSHR uncacheable cycles +system.cpu7.l1c.avg_blocked_cycles_no_mshrs 82.167211 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu7.l1c.avg_refs 0.419292 # Average number of references to valid blocks. +system.cpu7.l1c.blocked_no_mshrs 68907 # number of cycles access was blocked +system.cpu7.l1c.blocked_no_targets 0 # number of cycles access was blocked +system.cpu7.l1c.blocked_cycles_no_mshrs 5661896 # number of cycles access was blocked +system.cpu7.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu7.l1c.cache_copies 0 # number of cache copies performed +system.cpu7.l1c.demand_accesses 68437 # number of demand (read+write) accesses +system.cpu7.l1c.demand_avg_miss_latency 931.901012 # average overall miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency 852.491220 # average overall mshr miss latency +system.cpu7.l1c.demand_hits 8531 # number of demand (read+write) hits +system.cpu7.l1c.demand_miss_latency 55826462 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_rate 0.875345 # miss rate for demand accesses +system.cpu7.l1c.demand_misses 59906 # number of demand (read+write) misses +system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu7.l1c.demand_mshr_miss_latency 51069339 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_rate 0.875345 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_misses 59906 # number of demand (read+write) MSHR misses +system.cpu7.l1c.fast_writes 0 # number of fast writes performed +system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu7.l1c.overall_accesses 68437 # number of overall (read+write) accesses +system.cpu7.l1c.overall_avg_miss_latency 931.901012 # average overall miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency 852.491220 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_hits 8531 # number of overall hits +system.cpu7.l1c.overall_miss_latency 55826462 # number of overall miss cycles +system.cpu7.l1c.overall_miss_rate 0.875345 # miss rate for overall accesses +system.cpu7.l1c.overall_misses 59906 # number of overall misses +system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu7.l1c.overall_mshr_miss_latency 51069339 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_rate 0.875345 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_misses 59906 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_misses 15247 # number of overall MSHR uncacheable misses +system.cpu7.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu7.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu7.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu7.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu7.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu7.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu7.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu7.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu7.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu7.l1c.protocol.read_invalid 115064 # read misses to invalid blocks +system.cpu7.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu7.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu7.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu7.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu7.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu7.l1c.protocol.snoop_read_exclusive 2793 # read snoops on exclusive blocks +system.cpu7.l1c.protocol.snoop_read_modified 12588 # read snoops on modified blocks +system.cpu7.l1c.protocol.snoop_read_owned 7412 # read snoops on owned blocks +system.cpu7.l1c.protocol.snoop_read_shared 23048 # read snoops on shared blocks +system.cpu7.l1c.protocol.snoop_readex_exclusive 1548 # readEx snoops on exclusive blocks +system.cpu7.l1c.protocol.snoop_readex_modified 6593 # readEx snoops on modified blocks +system.cpu7.l1c.protocol.snoop_readex_owned 3944 # readEx snoops on owned blocks +system.cpu7.l1c.protocol.snoop_readex_shared 12404 # readEx snoops on shared blocks +system.cpu7.l1c.protocol.snoop_upgrade_owned 919 # upgrade snoops on owned blocks +system.cpu7.l1c.protocol.snoop_upgrade_shared 2959 # upgradee snoops on shared blocks +system.cpu7.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu7.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu7.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu7.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu7.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu7.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu7.l1c.protocol.write_invalid 58173 # write misses to invalid blocks +system.cpu7.l1c.protocol.write_owned 1351 # write misses to owned blocks +system.cpu7.l1c.protocol.write_shared 4494 # write misses to shared blocks +system.cpu7.l1c.replacements 27080 # number of replacements +system.cpu7.l1c.sampled_refs 27420 # Sample count of references to valid blocks. +system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu7.l1c.tagsinuse 342.061742 # Cycle average of tags in use +system.cpu7.l1c.total_refs 11497 # Total number of references to valid blocks. +system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu7.l1c.writebacks 10789 # number of writebacks +system.cpu7.num_copies 0 # number of copy accesses completed +system.cpu7.num_reads 98350 # number of read accesses completed +system.cpu7.num_writes 53282 # number of write accesses completed +system.l2c.ReadExReq_accesses 75399 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 89.483714 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 6.467886 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits 39632 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 3200564 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 0.474370 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 35767 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_hits 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_miss_latency 231311 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 0.474317 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 35763 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 138997 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 89.683271 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 6.196645 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits 72568 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 5957570 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.477917 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 66429 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 411544 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.477809 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 66414 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable 78703 # number of ReadReq MSHR uncacheable +system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.l2c.ReadResp_mshr_uncacheable_latency 420484 # number of ReadResp MSHR uncacheable cycles +system.l2c.WriteReqNoAck|Writeback_accesses 86614 # number of WriteReqNoAck|Writeback accesses(hits+misses) +system.l2c.WriteReqNoAck|Writeback_hits 18299 # number of WriteReqNoAck|Writeback hits +system.l2c.WriteReqNoAck|Writeback_miss_rate 0.788729 # miss rate for WriteReqNoAck|Writeback accesses +system.l2c.WriteReqNoAck|Writeback_misses 68315 # number of WriteReqNoAck|Writeback misses +system.l2c.WriteReqNoAck|Writeback_mshr_miss_rate 0.788729 # mshr miss rate for WriteReqNoAck|Writeback accesses +system.l2c.WriteReqNoAck|Writeback_mshr_misses 68315 # number of WriteReqNoAck|Writeback MSHR misses +system.l2c.WriteReq_mshr_uncacheable 42661 # number of WriteReq MSHR uncacheable +system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.l2c.WriteResp_mshr_uncacheable_latency 298282 # number of WriteResp MSHR uncacheable cycles +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 1.277186 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 138997 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 89.683271 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 6.196645 # average overall mshr miss latency +system.l2c.demand_hits 72568 # number of demand (read+write) hits +system.l2c.demand_miss_latency 5957570 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.477917 # miss rate for demand accesses +system.l2c.demand_misses 66429 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 15 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 411544 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.477809 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 66414 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 225611 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 44.213991 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 6.196645 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.l2c.overall_hits 90867 # number of overall hits +system.l2c.overall_miss_latency 5957570 # number of overall miss cycles +system.l2c.overall_miss_rate 0.597240 # miss rate for overall accesses +system.l2c.overall_misses 134744 # number of overall misses +system.l2c.overall_mshr_hits 15 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 411544 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.294374 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 66414 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 121364 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 101153 # number of replacements +system.l2c.sampled_refs 102177 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 1022.647312 # Cycle average of tags in use +system.l2c.total_refs 130499 # Total number of references to valid blocks. +system.l2c.warmup_cycle 31838 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 15786 # number of writebacks + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr new file mode 100644 index 000000000..16580296b --- /dev/null +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr @@ -0,0 +1,74 @@ +warn: Entering event queue @ 0. Starting simulation... +system.cpu2: completed 10000 read accesses @573559 +system.cpu1: completed 10000 read accesses @574452 +system.cpu4: completed 10000 read accesses @578704 +system.cpu6: completed 10000 read accesses @579414 +system.cpu0: completed 10000 read accesses @588706 +system.cpu5: completed 10000 read accesses @590846 +system.cpu7: completed 10000 read accesses @592958 +system.cpu3: completed 10000 read accesses @604807 +system.cpu2: completed 20000 read accesses @1142209 +system.cpu1: completed 20000 read accesses @1143294 +system.cpu6: completed 20000 read accesses @1150506 +system.cpu4: completed 20000 read accesses @1152288 +system.cpu0: completed 20000 read accesses @1160537 +system.cpu3: completed 20000 read accesses @1175338 +system.cpu5: completed 20000 read accesses @1175648 +system.cpu7: completed 20000 read accesses @1180960 +system.cpu6: completed 30000 read accesses @1716218 +system.cpu3: completed 30000 read accesses @1728281 +system.cpu1: completed 30000 read accesses @1735983 +system.cpu0: completed 30000 read accesses @1736422 +system.cpu2: completed 30000 read accesses @1739692 +system.cpu4: completed 30000 read accesses @1746362 +system.cpu5: completed 30000 read accesses @1766199 +system.cpu7: completed 30000 read accesses @1783424 +system.cpu6: completed 40000 read accesses @2281651 +system.cpu0: completed 40000 read accesses @2300760 +system.cpu3: completed 40000 read accesses @2312993 +system.cpu2: completed 40000 read accesses @2314026 +system.cpu4: completed 40000 read accesses @2332178 +system.cpu1: completed 40000 read accesses @2336380 +system.cpu5: completed 40000 read accesses @2349370 +system.cpu7: completed 40000 read accesses @2365352 +system.cpu6: completed 50000 read accesses @2863317 +system.cpu0: completed 50000 read accesses @2878182 +system.cpu2: completed 50000 read accesses @2884989 +system.cpu3: completed 50000 read accesses @2897940 +system.cpu4: completed 50000 read accesses @2918842 +system.cpu1: completed 50000 read accesses @2929102 +system.cpu5: completed 50000 read accesses @2938269 +system.cpu7: completed 50000 read accesses @2944872 +system.cpu6: completed 60000 read accesses @3435715 +system.cpu2: completed 60000 read accesses @3454809 +system.cpu0: completed 60000 read accesses @3462986 +system.cpu3: completed 60000 read accesses @3485243 +system.cpu4: completed 60000 read accesses @3498361 +system.cpu1: completed 60000 read accesses @3501000 +system.cpu5: completed 60000 read accesses @3516984 +system.cpu7: completed 60000 read accesses @3517323 +system.cpu6: completed 70000 read accesses @4032530 +system.cpu0: completed 70000 read accesses @4041457 +system.cpu2: completed 70000 read accesses @4043695 +system.cpu7: completed 70000 read accesses @4070977 +system.cpu1: completed 70000 read accesses @4075964 +system.cpu4: completed 70000 read accesses @4076518 +system.cpu3: completed 70000 read accesses @4082470 +system.cpu5: completed 70000 read accesses @4104778 +system.cpu0: completed 80000 read accesses @4610101 +system.cpu2: completed 80000 read accesses @4622528 +system.cpu6: completed 80000 read accesses @4627690 +system.cpu1: completed 80000 read accesses @4654033 +system.cpu4: completed 80000 read accesses @4661016 +system.cpu3: completed 80000 read accesses @4662752 +system.cpu7: completed 80000 read accesses @4668924 +system.cpu5: completed 80000 read accesses @4689767 +system.cpu2: completed 90000 read accesses @5186824 +system.cpu0: completed 90000 read accesses @5189006 +system.cpu6: completed 90000 read accesses @5214829 +system.cpu1: completed 90000 read accesses @5229787 +system.cpu3: completed 90000 read accesses @5235400 +system.cpu4: completed 90000 read accesses @5240445 +system.cpu7: completed 90000 read accesses @5254426 +system.cpu5: completed 90000 read accesses @5292462 +system.cpu2: completed 100000 read accesses @5755736 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout new file mode 100644 index 000000000..3d3289d71 --- /dev/null +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout @@ -0,0 +1,18 @@ +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 6 2007 20:30:01 +M5 started Tue Feb 6 21:04:07 2007 +M5 executing on vm1 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest +warning: overwriting port funcmem.functional value cpu1.functional with cpu2.functional +warning: overwriting port funcmem.functional value cpu2.functional with cpu3.functional +warning: overwriting port funcmem.functional value cpu3.functional with cpu4.functional +warning: overwriting port funcmem.functional value cpu4.functional with cpu5.functional +warning: overwriting port funcmem.functional value cpu5.functional with cpu6.functional +warning: overwriting port funcmem.functional value cpu6.functional with cpu7.functional +Exiting @ tick 5755736 because Maximum number of loads reached! diff --git a/tests/quick/50.memtest/test.py b/tests/quick/50.memtest/test.py index e894b8fb8..90beae0c6 100644 --- a/tests/quick/50.memtest/test.py +++ b/tests/quick/50.memtest/test.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -26,3 +26,5 @@ # # Authors: Ron Dreslinski +MemTest.max_loads=1e5 +MemTest.progress_interval=1e4 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index 67632ca08..2750dd3c0 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -18,7 +18,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/y/binkertn/research/m5/rtc/configs/boot/netperf-server.rcS +readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -106,7 +106,7 @@ read_only=true [drivesys.intrctrl] type=IntrControl -cpu=drivesys.cpu +sys=drivesys [drivesys.iobus] type=Bus @@ -153,15 +153,10 @@ port=drivesys.membus.port[1] [drivesys.sim_console] type=SimConsole -children=listener append_name=true intr_control=drivesys.intrctrl -listener=drivesys.sim_console.listener number=0 output=console - -[drivesys.sim_console.listener] -type=ConsoleListener port=3456 [drivesys.simple_disk] @@ -691,43 +686,6 @@ int1=testsys.tsunami.etherint int2=drivesys.tsunami.etherint speed=8000.000000 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt - [testsys] type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami @@ -739,7 +697,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/y/binkertn/research/m5/rtc/configs/boot/netperf-stream-client.rcS +readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 @@ -827,7 +785,7 @@ read_only=true [testsys.intrctrl] type=IntrControl -cpu=testsys.cpu +sys=testsys [testsys.iobus] type=Bus @@ -874,15 +832,10 @@ port=testsys.membus.port[1] [testsys.sim_console] type=SimConsole -children=listener append_name=true intr_control=testsys.intrctrl -listener=testsys.sim_console.listener number=0 output=console - -[testsys.sim_console.listener] -type=ConsoleListener port=3456 [testsys.simple_disk] @@ -1398,12 +1351,3 @@ sim_console=testsys.sim_console system=testsys pio=testsys.iobus.port[24] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out index 7ef28f570..c422f07ac 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out @@ -21,273 +21,28 @@ kernel=/dist/m5/system/binaries/vmlinux console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 -readfile=/y/binkertn/research/m5/rtc/configs/boot/netperf-stream-client.rcS +readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-stream-client.rcS symbolfile= init_param=0 system_type=34 system_rev=1024 -[testsys.cpu.itb] -type=AlphaITB -size=48 - -[testsys.cpu.dtb] -type=AlphaDTB -size=64 - -[testsys.cpu] -type=AtomicSimpleCPU -max_insts_any_thread=0 -max_insts_all_threads=0 -max_loads_any_thread=0 -max_loads_all_threads=0 -progress_interval=0 -system=testsys -cpu_id=0 -itb=testsys.cpu.itb -dtb=testsys.cpu.dtb -profile=0 -do_quiesce=true -do_checkpoint_insts=true -do_statistics_insts=true -clock=1 -phase=0 -defer_registration=false -width=1 -function_trace=false -function_trace_start=0 -simulate_stalls=false +[testsys.membus] +type=Bus +bus_id=1 +clock=1000 +width=64 +responder_set=false [testsys.intrctrl] type=IntrControl -cpu=testsys.cpu +sys=testsys [testsys.tsunami] type=Tsunami system=testsys intrctrl=testsys.intrctrl -[testsys.tsunami.ethernet.configdata] -type=PciConfigData -VendorID=4107 -DeviceID=34 -Command=0 -Status=656 -Revision=0 -ProgIF=0 -SubClassCode=0 -ClassCode=2 -CacheLineSize=0 -LatencyTimer=0 -HeaderType=0 -BIST=0 -BAR0=1 -BAR1=0 -BAR2=0 -BAR3=0 -BAR4=0 -BAR5=0 -CardbusCIS=0 -SubsystemVendorID=0 -SubsystemID=0 -ExpansionROM=0 -InterruptLine=30 -InterruptPin=1 -MinimumGrant=176 -MaximumLatency=52 -BAR0Size=256 -BAR1Size=4096 -BAR2Size=0 -BAR3Size=0 -BAR4Size=0 -BAR5Size=0 - -[testsys.tsunami.ethernet] -type=NSGigE -system=testsys -platform=testsys.tsunami -configdata=testsys.tsunami.ethernet.configdata -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=1000 -config_latency=20000 -clock=0 -dma_desc_free=false -dma_data_free=false -dma_read_delay=0 -dma_write_delay=0 -dma_read_factor=0 -dma_write_factor=0 -dma_no_allocate=true -intr_delay=10000000 -rx_delay=1000000 -tx_delay=1000000 -rx_fifo_size=524288 -tx_fifo_size=524288 -rx_filter=true -hardware_address=00:90:00:00:00:02 -rx_thread=false -tx_thread=false -rss=false - -[testsys.tsunami.etherint] -type=NSGigEInt -peer=null -device=testsys.tsunami.ethernet - -[drivesys.physmem] -type=PhysicalMemory -file= -range=[0,134217727] -latency=1 -zero=false - -[drivesys] -type=LinuxAlphaSystem -boot_cpu_frequency=1 -physmem=drivesys.physmem -mem_mode=atomic -kernel=/dist/m5/system/binaries/vmlinux -console=/dist/m5/system/binaries/console -pal=/dist/m5/system/binaries/ts_osfpal -boot_osflags=root=/dev/hda1 console=ttyS0 -readfile=/y/binkertn/research/m5/rtc/configs/boot/netperf-server.rcS -symbolfile= -init_param=0 -system_type=34 -system_rev=1024 - -[drivesys.cpu.itb] -type=AlphaITB -size=48 - -[drivesys.cpu.dtb] -type=AlphaDTB -size=64 - -[drivesys.cpu] -type=AtomicSimpleCPU -max_insts_any_thread=0 -max_insts_all_threads=0 -max_loads_any_thread=0 -max_loads_all_threads=0 -progress_interval=0 -system=drivesys -cpu_id=0 -itb=drivesys.cpu.itb -dtb=drivesys.cpu.dtb -profile=0 -do_quiesce=true -do_checkpoint_insts=true -do_statistics_insts=true -clock=1 -phase=0 -defer_registration=false -width=1 -function_trace=false -function_trace_start=0 -simulate_stalls=false - -[drivesys.intrctrl] -type=IntrControl -cpu=drivesys.cpu - -[drivesys.tsunami] -type=Tsunami -system=drivesys -intrctrl=drivesys.intrctrl - -[drivesys.tsunami.ethernet.configdata] -type=PciConfigData -VendorID=4107 -DeviceID=34 -Command=0 -Status=656 -Revision=0 -ProgIF=0 -SubClassCode=0 -ClassCode=2 -CacheLineSize=0 -LatencyTimer=0 -HeaderType=0 -BIST=0 -BAR0=1 -BAR1=0 -BAR2=0 -BAR3=0 -BAR4=0 -BAR5=0 -CardbusCIS=0 -SubsystemVendorID=0 -SubsystemID=0 -ExpansionROM=0 -InterruptLine=30 -InterruptPin=1 -MinimumGrant=176 -MaximumLatency=52 -BAR0Size=256 -BAR1Size=4096 -BAR2Size=0 -BAR3Size=0 -BAR4Size=0 -BAR5Size=0 - -[drivesys.tsunami.ethernet] -type=NSGigE -system=drivesys -platform=drivesys.tsunami -configdata=drivesys.tsunami.ethernet.configdata -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=1000 -config_latency=20000 -clock=0 -dma_desc_free=false -dma_data_free=false -dma_read_delay=0 -dma_write_delay=0 -dma_read_factor=0 -dma_write_factor=0 -dma_no_allocate=true -intr_delay=10000000 -rx_delay=1000000 -tx_delay=1000000 -rx_fifo_size=524288 -tx_fifo_size=524288 -rx_filter=true -hardware_address=00:90:00:00:00:02 -rx_thread=false -tx_thread=false -rss=false - -[drivesys.tsunami.etherint] -type=NSGigEInt -peer=null -device=drivesys.tsunami.ethernet - -[etherdump] -type=EtherDump -file=ethertrace -maxlen=96 - -[etherlink] -type=EtherLink -int1=testsys.tsunami.etherint -int2=drivesys.tsunami.etherint -speed=8000 -delay=0 -delay_var=0 -dump=etherdump - -[testsys.membus] -type=Bus -bus_id=1 -clock=1000 -width=64 -responder_set=false - [testsys.membus.responder] type=IsaFake pio_addr=0 @@ -458,18 +213,45 @@ size=16777216 platform=testsys.tsunami system=testsys -[testsys.sim_console.listener] -type=ConsoleListener -port=3456 - [testsys.sim_console] type=SimConsole -listener=testsys.sim_console.listener intr_control=testsys.intrctrl output=console +port=3456 append_name=true number=0 +[testsys.cpu.itb] +type=AlphaITB +size=48 + +[testsys.cpu.dtb] +type=AlphaDTB +size=64 + +[testsys.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=testsys +cpu_id=0 +itb=testsys.cpu.itb +dtb=testsys.cpu.dtb +profile=0 +do_quiesce=true +do_checkpoint_insts=true +do_statistics_insts=true +clock=1 +phase=0 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + [testsys.tsunami.console] type=AlphaConsole sim_console=testsys.sim_console @@ -661,6 +443,75 @@ system=testsys platform=testsys.tsunami pio_latency=1000 +[testsys.tsunami.ethernet.configdata] +type=PciConfigData +VendorID=4107 +DeviceID=34 +Command=0 +Status=656 +Revision=0 +ProgIF=0 +SubClassCode=0 +ClassCode=2 +CacheLineSize=0 +LatencyTimer=0 +HeaderType=0 +BIST=0 +BAR0=1 +BAR1=0 +BAR2=0 +BAR3=0 +BAR4=0 +BAR5=0 +CardbusCIS=0 +SubsystemVendorID=0 +SubsystemID=0 +ExpansionROM=0 +InterruptLine=30 +InterruptPin=1 +MinimumGrant=176 +MaximumLatency=52 +BAR0Size=256 +BAR1Size=4096 +BAR2Size=0 +BAR3Size=0 +BAR4Size=0 +BAR5Size=0 + +[testsys.tsunami.ethernet] +type=NSGigE +system=testsys +platform=testsys.tsunami +configdata=testsys.tsunami.ethernet.configdata +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=1000 +config_latency=20000 +clock=0 +dma_desc_free=false +dma_data_free=false +dma_read_delay=0 +dma_write_delay=0 +dma_read_factor=0 +dma_write_factor=0 +dma_no_allocate=true +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 +rx_fifo_size=524288 +tx_fifo_size=524288 +rx_filter=true +hardware_address=00:90:00:00:00:02 +rx_thread=false +tx_thread=false +rss=false + +[testsys.tsunami.etherint] +type=NSGigEInt +peer=null +device=testsys.tsunami.ethernet + [testsys.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 @@ -768,6 +619,120 @@ clock=1000 width=64 responder_set=true +[drivesys.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 +zero=false + +[drivesys] +type=LinuxAlphaSystem +boot_cpu_frequency=1 +physmem=drivesys.physmem +mem_mode=atomic +kernel=/dist/m5/system/binaries/vmlinux +console=/dist/m5/system/binaries/console +pal=/dist/m5/system/binaries/ts_osfpal +boot_osflags=root=/dev/hda1 console=ttyS0 +readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-server.rcS +symbolfile= +init_param=0 +system_type=34 +system_rev=1024 + +[drivesys.intrctrl] +type=IntrControl +sys=drivesys + +[drivesys.tsunami] +type=Tsunami +system=drivesys +intrctrl=drivesys.intrctrl + +[drivesys.tsunami.ethernet.configdata] +type=PciConfigData +VendorID=4107 +DeviceID=34 +Command=0 +Status=656 +Revision=0 +ProgIF=0 +SubClassCode=0 +ClassCode=2 +CacheLineSize=0 +LatencyTimer=0 +HeaderType=0 +BIST=0 +BAR0=1 +BAR1=0 +BAR2=0 +BAR3=0 +BAR4=0 +BAR5=0 +CardbusCIS=0 +SubsystemVendorID=0 +SubsystemID=0 +ExpansionROM=0 +InterruptLine=30 +InterruptPin=1 +MinimumGrant=176 +MaximumLatency=52 +BAR0Size=256 +BAR1Size=4096 +BAR2Size=0 +BAR3Size=0 +BAR4Size=0 +BAR5Size=0 + +[drivesys.tsunami.ethernet] +type=NSGigE +system=drivesys +platform=drivesys.tsunami +configdata=drivesys.tsunami.ethernet.configdata +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=1000 +config_latency=20000 +clock=0 +dma_desc_free=false +dma_data_free=false +dma_read_delay=0 +dma_write_delay=0 +dma_read_factor=0 +dma_write_factor=0 +dma_no_allocate=true +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 +rx_fifo_size=524288 +tx_fifo_size=524288 +rx_filter=true +hardware_address=00:90:00:00:00:02 +rx_thread=false +tx_thread=false +rss=false + +[drivesys.tsunami.etherint] +type=NSGigEInt +peer=null +device=drivesys.tsunami.ethernet + +[etherdump] +type=EtherDump +file=ethertrace +maxlen=96 + +[etherlink] +type=EtherLink +int1=testsys.tsunami.etherint +int2=drivesys.tsunami.etherint +speed=8000 +delay=0 +delay_var=0 +dump=etherdump + [drivesys.membus] type=Bus bus_id=1 @@ -945,18 +910,45 @@ size=16777216 platform=drivesys.tsunami system=drivesys -[drivesys.sim_console.listener] -type=ConsoleListener -port=3456 - [drivesys.sim_console] type=SimConsole -listener=drivesys.sim_console.listener intr_control=drivesys.intrctrl output=console +port=3456 append_name=true number=0 +[drivesys.cpu.itb] +type=AlphaITB +size=48 + +[drivesys.cpu.dtb] +type=AlphaDTB +size=64 + +[drivesys.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=drivesys +cpu_id=0 +itb=drivesys.cpu.itb +dtb=drivesys.cpu.dtb +profile=0 +do_quiesce=true +do_checkpoint_insts=true +do_statistics_insts=true +clock=1 +phase=0 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + [drivesys.tsunami.console] type=AlphaConsole sim_console=drivesys.sim_console @@ -1255,51 +1247,3 @@ clock=1000 width=64 responder_set=true -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/test-progs/hello/bin/x86/linux/hello b/tests/test-progs/hello/bin/x86/linux/hello Binary files differnew file mode 100755 index 000000000..a3ec8dcdb --- /dev/null +++ b/tests/test-progs/hello/bin/x86/linux/hello |