diff options
Diffstat (limited to 'tests')
61 files changed, 22378 insertions, 21785 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 40315f031..8dbc85977 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,146 +1,133 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.898811 # Number of seconds simulated -sim_ticks 1898811181000 # Number of ticks simulated -final_tick 1898811181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.899762 # Number of seconds simulated +sim_ticks 1899762444000 # Number of ticks simulated +final_tick 1899762444000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163774 # Simulator instruction rate (inst/s) -host_op_rate 163774 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5540525376 # Simulator tick rate (ticks/s) -host_mem_usage 339592 # Number of bytes of host memory used -host_seconds 342.71 # Real time elapsed on the host -sim_insts 56127436 # Number of instructions simulated -sim_ops 56127436 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 739584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24165760 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 241984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1058688 # Number of bytes read from this memory -system.physmem.bytes_read::total 28856384 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 739584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 241984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 981568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7824192 # Number of bytes written to this memory -system.physmem.bytes_written::total 7824192 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11556 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 377590 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41412 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3781 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16542 # Number of read requests responded to by this memory -system.physmem.num_reads::total 450881 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122253 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122253 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 389498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12726784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1395804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 127440 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 557553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15197079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 389498 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 127440 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 516938 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4120574 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4120574 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4120574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 389498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12726784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1395804 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 127440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 557553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19317653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 450881 # Total number of read requests seen -system.physmem.writeReqs 122253 # Total number of write requests seen -system.physmem.cpureqs 582476 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28856384 # Total number of bytes read from memory -system.physmem.bytesWritten 7824192 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28856384 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7824192 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 66 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3389 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28644 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28625 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28393 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28253 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28243 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28343 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 28155 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27999 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28056 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27988 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28022 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27871 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27898 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8087 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7991 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7846 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7763 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7721 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7658 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7765 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7698 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7705 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7559 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7625 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7394 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7457 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7400 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7239 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7345 # Track writes on a per bank basis +host_inst_rate 165662 # Simulator instruction rate (inst/s) +host_op_rate 165662 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5547317951 # Simulator tick rate (ticks/s) +host_mem_usage 338604 # Number of bytes of host memory used +host_seconds 342.47 # Real time elapsed on the host +sim_insts 56733550 # Number of instructions simulated +sim_ops 56733550 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 853120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24660608 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2651648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 123456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 536896 # Number of bytes read from this memory +system.physmem.bytes_read::total 28825728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 853120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 123456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 976576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7795456 # Number of bytes written to this memory +system.physmem.bytes_written::total 7795456 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13330 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385322 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41432 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8389 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450402 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121804 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121804 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 449067 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12980890 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1395779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 64985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 282612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15173333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 449067 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 64985 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 514052 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4103385 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4103385 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4103385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 449067 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12980890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1395779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 64985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 282612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19276718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450402 # Total number of read requests seen +system.physmem.writeReqs 121804 # Total number of write requests seen +system.physmem.cpureqs 579957 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28825728 # Total number of bytes read from memory +system.physmem.bytesWritten 7795456 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28825728 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7795456 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 61 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 5038 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28521 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28327 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28189 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28015 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28417 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28335 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28297 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 28180 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28276 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28045 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28104 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27882 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27807 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28046 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27946 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27954 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7786 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7706 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7580 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7839 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7697 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7703 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7676 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7799 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7587 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7619 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7293 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7271 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7481 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7325 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7481 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1873 # Number of times wr buffer was full causing retry -system.physmem.totGap 1898811160000 # Total gap between requests +system.physmem.numWrRetry 2713 # Number of times wr buffer was full causing retry +system.physmem.totGap 1899757983000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 450881 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 124126 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 3389 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 320280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 33102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7745 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2644 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1519 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1446 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1411 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 924 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 760 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.readPktSize::6 450402 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 121804 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 319830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 33225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2685 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1441 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1640 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 770 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -151,226 +138,224 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 8261632913 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 16092226663 # Sum of mem lat for all requests -system.physmem.totBusLat 2254075000 # Total cycles spent in databus access -system.physmem.totBankLat 5576518750 # Total cycles spent in bank access -system.physmem.avgQLat 18325.99 # Average queueing delay per request -system.physmem.avgBankLat 12369.86 # Average bank access latency per request +system.physmem.wrQLenPdf::0 3182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 19 # What write queue length does an incoming req see +system.physmem.totQLat 7756175500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15561175500 # Sum of mem lat for all requests +system.physmem.totBusLat 2251705000 # Total cycles spent in databus access +system.physmem.totBankLat 5553295000 # Total cycles spent in bank access +system.physmem.avgQLat 17222.89 # Average queueing delay per request +system.physmem.avgBankLat 12331.31 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 35695.85 # Average memory access latency -system.physmem.avgRdBW 15.20 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.20 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.12 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 34554.21 # Average memory access latency +system.physmem.avgRdBW 15.17 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.17 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.10 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 8.51 # Average write queue length over time -system.physmem.readRowHits 422765 # Number of row buffer hits during reads -system.physmem.writeRowHits 93696 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.64 # Row buffer hit rate for writes -system.physmem.avgGap 3313031.79 # Average gap between requests -system.l2c.replacements 343964 # number of replacements -system.l2c.tagsinuse 65331.328526 # Cycle average of tags in use -system.l2c.total_refs 2620978 # Total number of references to valid blocks. -system.l2c.sampled_refs 408975 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.408651 # Average number of references to valid blocks. -system.l2c.warmup_cycle 5576145752 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53755.791166 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4185.940391 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 5467.030556 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 1355.812299 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 566.754114 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.820248 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.063872 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.083420 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.020688 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.008648 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996877 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 717909 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 533580 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 356656 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 291510 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1899655 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 844133 # number of Writeback hits -system.l2c.Writeback_hits::total 844133 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 124 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 89 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 213 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 33 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 33 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 138119 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 53788 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 191907 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 717909 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 671699 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 356656 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 345298 # number of demand (read+write) hits -system.l2c.demand_hits::total 2091562 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 717909 # number of overall hits -system.l2c.overall_hits::cpu0.data 671699 # number of overall hits -system.l2c.overall_hits::cpu1.inst 356656 # number of overall hits -system.l2c.overall_hits::cpu1.data 345298 # number of overall hits -system.l2c.overall_hits::total 2091562 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11558 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 272086 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3797 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1924 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289365 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2537 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 537 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3074 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 59 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 99 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 158 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 105872 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 14967 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 120839 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 11558 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 377958 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3797 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16891 # number of demand (read+write) misses -system.l2c.demand_misses::total 410204 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11558 # number of overall misses -system.l2c.overall_misses::cpu0.data 377958 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3797 # number of overall misses -system.l2c.overall_misses::cpu1.data 16891 # number of overall misses -system.l2c.overall_misses::total 410204 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 785741000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 12284482500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 291007000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 130325998 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 13491556498 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 572500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1115999 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1688499 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 252000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 68000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 320000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6919340499 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1319798500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 8239138999 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 785741000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 19203822999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 291007000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1450124498 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21730695497 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 785741000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 19203822999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 291007000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1450124498 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21730695497 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 729467 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 805666 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 360453 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 293434 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2189020 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 844133 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 844133 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2661 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 626 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3287 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 92 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 132 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 224 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 243991 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 68755 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 312746 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 729467 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1049657 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 360453 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 362189 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2501766 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 729467 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1049657 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 360453 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 362189 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2501766 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015844 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.337716 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010534 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.006557 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.132189 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.953401 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.857827 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.935199 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.641304 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.750000 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.705357 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.433918 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.217686 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.386381 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015844 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.360078 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010534 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.046636 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.163966 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015844 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.360078 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010534 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.046636 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.163966 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 67982.436408 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 45149.263468 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76641.295760 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 67737.005198 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 46624.700631 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 225.660229 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2078.210428 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 549.283995 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4271.186441 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 686.868687 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 2025.316456 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65355.717272 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 88180.563907 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 68182.780385 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 67982.436408 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 50809.410038 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 76641.295760 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 85851.903262 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52975.337873 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 67982.436408 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 50809.410038 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 76641.295760 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 85851.903262 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52975.337873 # average overall miss latency +system.physmem.avgWrQLen 10.95 # Average write queue length over time +system.physmem.readRowHits 422281 # Number of row buffer hits during reads +system.physmem.writeRowHits 93689 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.77 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 76.92 # Row buffer hit rate for writes +system.physmem.avgGap 3320059.53 # Average gap between requests +system.l2c.replacements 343507 # number of replacements +system.l2c.tagsinuse 65280.658491 # Cycle average of tags in use +system.l2c.total_refs 2577629 # Total number of references to valid blocks. +system.l2c.sampled_refs 408521 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.309661 # Average number of references to valid blocks. +system.l2c.warmup_cycle 5466319751 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 53803.217874 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5298.496684 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 5899.097985 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 206.030699 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 73.815249 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.820972 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.080849 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.090013 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.003144 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.001126 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996104 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 850473 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 731190 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 225422 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 71980 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1879065 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 820673 # number of Writeback hits +system.l2c.Writeback_hits::total 820673 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 170 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 273 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 443 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 45 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 153356 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 26453 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 179809 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 850473 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 884546 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 225422 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 98433 # number of demand (read+write) hits +system.l2c.demand_hits::total 2058874 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 850473 # number of overall hits +system.l2c.overall_hits::cpu0.data 884546 # number of overall hits +system.l2c.overall_hits::cpu1.inst 225422 # number of overall hits +system.l2c.overall_hits::cpu1.data 98433 # number of overall hits +system.l2c.overall_hits::total 2058874 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 13332 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 273019 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1945 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 885 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289181 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2705 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1140 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3845 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 440 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 460 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 900 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 112844 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 7619 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 120463 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 13332 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 385863 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1945 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 8504 # number of demand (read+write) misses +system.l2c.demand_misses::total 409644 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13332 # number of overall misses +system.l2c.overall_misses::cpu0.data 385863 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1945 # number of overall misses +system.l2c.overall_misses::cpu1.data 8504 # number of overall misses +system.l2c.overall_misses::total 409644 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 919052500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 11905171000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 147649500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 64290999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 13036163999 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1055000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 5020958 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 6075958 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1147998 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 159000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1306998 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 7474090498 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 738521500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 8212611998 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 919052500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 19379261498 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 147649500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 802812499 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21248775997 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 919052500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 19379261498 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 147649500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 802812499 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21248775997 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 863805 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1004209 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 227367 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 72865 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2168246 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 820673 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 820673 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2875 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1413 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4288 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 485 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 483 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 968 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 266200 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 34072 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300272 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 863805 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1270409 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 227367 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 106937 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2468518 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 863805 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1270409 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 227367 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 106937 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2468518 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015434 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.271875 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.008554 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.012146 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.133371 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.940870 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.806794 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.896688 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.907216 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.952381 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.929752 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.423907 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.223615 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.401180 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015434 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.303731 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.008554 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.079523 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.165947 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015434 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.303731 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.008554 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.079523 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.165947 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68935.831083 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 43605.650156 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75912.339332 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 72645.196610 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 45079.600662 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 390.018484 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4404.349123 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1580.223147 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2609.086364 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 345.652174 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1452.220000 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66233.831644 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 96931.552697 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 68175.389937 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 68935.831083 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 50223.165989 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 75912.339332 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 94404.103833 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 51871.322409 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 68935.831083 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 50223.165989 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 75912.339332 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 94404.103833 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 51871.322409 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,8 +364,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 80731 # number of writebacks -system.l2c.writebacks::total 80731 # number of writebacks +system.l2c.writebacks::writebacks 80284 # number of writebacks +system.l2c.writebacks::total 80284 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 16 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits @@ -393,111 +378,111 @@ system.l2c.overall_mshr_hits::cpu0.inst 1 # nu system.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 11557 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 272086 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 3781 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1923 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 289347 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2537 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 537 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3074 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 59 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 99 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 158 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 105872 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 14967 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 120839 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 11557 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 377958 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 3781 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 16890 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 410186 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 11557 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 377958 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 3781 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 16890 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 410186 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 641619734 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8951011686 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 243130799 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 134913103 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 9970675322 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25435503 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5378029 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 30813532 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 621055 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1001098 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 1622153 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5629376132 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1136913783 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 6766289915 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 641619734 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 14580387818 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 243130799 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1271826886 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16736965237 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 641619734 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 14580387818 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 243130799 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1271826886 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16736965237 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 929565000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 460091000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1389656000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1573030500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 890243000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2463273500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2502595500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1350334000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 3852929500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015843 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.337716 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010490 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006553 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.132181 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.953401 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.857827 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.935199 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.641304 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.750000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.705357 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.433918 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.217686 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.386381 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015843 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.360078 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010490 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.046633 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.163959 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015843 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.360078 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010490 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.046633 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.163959 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55517.844942 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 32897.729710 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64303.305739 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70157.619865 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 34459.231725 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10025.819078 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10014.951583 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10023.920625 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10526.355932 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10112.101010 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10266.791139 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53171.529130 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 75961.367208 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 55994.256118 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55517.844942 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38576.740850 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64303.305739 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75300.585317 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40803.355641 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55517.844942 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38576.740850 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64303.305739 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75300.585317 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40803.355641 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 13331 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 273019 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1929 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 884 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 289163 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2705 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1140 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3845 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 440 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 460 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 900 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 112844 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 7619 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 120463 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13331 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 385863 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1929 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 8503 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 409626 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13331 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 385863 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1929 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 8503 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 409626 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 752774551 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8562507308 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122885880 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 53311432 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 9491479171 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 27258667 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 11426097 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 38684764 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 4415934 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4604459 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 9020393 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6098954840 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 645340483 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 6744295323 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 752774551 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 14661462148 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 122885880 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 698651915 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16235774494 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 752774551 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 14661462148 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 122885880 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 698651915 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16235774494 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1363373000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28764500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1392137500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2009193000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 611400000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2620593000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3372566000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 640164500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4012730500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015433 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.271875 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.008484 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.012132 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.133363 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940870 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.806794 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.896688 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.907216 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.952381 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.929752 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.423907 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.223615 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.401180 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015433 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.303731 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008484 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.079514 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.165940 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015433 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.303731 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008484 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.079514 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.165940 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56467.973220 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 31362.312909 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63704.447900 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 60307.049774 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 32823.975305 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10077.141220 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10022.892105 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10061.056957 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10036.213636 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.693478 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10022.658889 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54047.666159 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84701.467778 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 55986.446652 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56467.973220 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37996.548381 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63704.447900 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 82165.343408 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39635.605391 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56467.973220 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37996.548381 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63704.447900 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 82165.343408 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39635.605391 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -508,39 +493,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41698 # number of replacements -system.iocache.tagsinuse 0.398700 # Cycle average of tags in use +system.iocache.replacements 41697 # number of replacements +system.iocache.tagsinuse 0.501565 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1706437655000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.398700 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.024919 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.024919 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses -system.iocache.ReadReq_misses::total 176 # number of ReadReq misses +system.iocache.warmup_cycle 1705456155000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.501565 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.031348 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.031348 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses +system.iocache.ReadReq_misses::total 177 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses -system.iocache.demand_misses::total 41728 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses -system.iocache.overall_misses::total 41728 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21267998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21267998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10658856806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10658856806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10680124804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10680124804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10680124804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10680124804 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses +system.iocache.demand_misses::total 41729 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses +system.iocache.overall_misses::total 41729 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21380998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21380998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10589255806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10589255806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10610636804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10610636804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10610636804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10610636804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -549,40 +534,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120840.897727 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120840.897727 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256518.502262 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 256518.502262 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 255946.242427 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 255946.242427 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 255946.242427 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 255946.242427 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 284980 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120796.598870 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120796.598870 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 254843.468570 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 254843.468570 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 254274.888063 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 254274.888063 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 254274.888063 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 254274.888063 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 281737 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27128 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 26988 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.505013 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.439343 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41522 # number of writebacks -system.iocache.writebacks::total 41522 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 41520 # number of writebacks +system.iocache.writebacks::total 41520 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12115250 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12115250 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8496857845 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8496857845 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8508973095 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8508973095 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8508973095 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8508973095 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12176249 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12176249 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8427244570 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8427244570 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8439420819 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8439420819 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8439420819 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8439420819 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -591,14 +576,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68836.647727 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68836.647727 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204487.337433 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 204487.337433 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203915.191119 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 203915.191119 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203915.191119 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 203915.191119 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68792.367232 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68792.367232 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 202812.008327 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 202812.008327 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202243.543315 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 202243.543315 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202243.543315 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 202243.543315 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -612,35 +597,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 10581841 # Number of BP lookups -system.cpu0.branchPred.condPredicted 8959361 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 281985 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 7046138 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4567974 # Number of BTB hits +system.cpu0.branchPred.lookups 12335027 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10393813 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 330568 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 7867422 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5239774 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 64.829471 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 656046 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 29257 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 66.600902 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 784891 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 32664 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7560815 # DTB read hits -system.cpu0.dtb.read_misses 30461 # DTB read misses -system.cpu0.dtb.read_acv 538 # DTB read access violations -system.cpu0.dtb.read_accesses 623625 # DTB read accesses -system.cpu0.dtb.write_hits 5040625 # DTB write hits -system.cpu0.dtb.write_misses 7520 # DTB write misses -system.cpu0.dtb.write_acv 334 # DTB write access violations -system.cpu0.dtb.write_accesses 206551 # DTB write accesses -system.cpu0.dtb.data_hits 12601440 # DTB hits -system.cpu0.dtb.data_misses 37981 # DTB misses -system.cpu0.dtb.data_acv 872 # DTB access violations -system.cpu0.dtb.data_accesses 830176 # DTB accesses -system.cpu0.itb.fetch_hits 911527 # ITB hits -system.cpu0.itb.fetch_misses 30644 # ITB misses -system.cpu0.itb.fetch_acv 921 # ITB acv -system.cpu0.itb.fetch_accesses 942171 # ITB accesses +system.cpu0.dtb.read_hits 8753494 # DTB read hits +system.cpu0.dtb.read_misses 29787 # DTB read misses +system.cpu0.dtb.read_acv 536 # DTB read access violations +system.cpu0.dtb.read_accesses 623801 # DTB read accesses +system.cpu0.dtb.write_hits 5745053 # DTB write hits +system.cpu0.dtb.write_misses 8131 # DTB write misses +system.cpu0.dtb.write_acv 346 # DTB write access violations +system.cpu0.dtb.write_accesses 207769 # DTB write accesses +system.cpu0.dtb.data_hits 14498547 # DTB hits +system.cpu0.dtb.data_misses 37918 # DTB misses +system.cpu0.dtb.data_acv 882 # DTB access violations +system.cpu0.dtb.data_accesses 831570 # DTB accesses +system.cpu0.itb.fetch_hits 986254 # ITB hits +system.cpu0.itb.fetch_misses 27996 # ITB misses +system.cpu0.itb.fetch_acv 985 # ITB acv +system.cpu0.itb.fetch_accesses 1014250 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -653,269 +638,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 89753559 # number of cpu cycles simulated +system.cpu0.numCycles 101860002 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 21107693 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 54367118 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 10581841 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5224020 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10262063 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1458036 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 30903552 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 30207 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 199263 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 186050 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 96 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6657299 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 195043 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 63623646 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.854511 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.189260 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 24837828 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 63180848 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12335027 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6024665 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11886569 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1686741 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 36619319 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 32566 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 195803 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 292498 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 224 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7637223 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 223881 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 74953254 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.842937 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.180655 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 53361583 83.87% 83.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 672459 1.06% 84.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1316592 2.07% 87.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 583007 0.92% 87.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2295308 3.61% 91.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 445844 0.70% 92.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 472664 0.74% 92.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 743494 1.17% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3732695 5.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 63066685 84.14% 84.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 761791 1.02% 85.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1555671 2.08% 87.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 698950 0.93% 88.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2562608 3.42% 91.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 513718 0.69% 92.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 568258 0.76% 93.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 822289 1.10% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4403284 5.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 63623646 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.117899 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.605738 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 22232367 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 30357900 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9303163 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 825009 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 905206 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 419214 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 29823 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 53368764 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 92723 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 905206 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 23093913 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 11627753 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 15736016 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8768275 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3492481 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 50503220 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6655 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 393829 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1341574 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 33876980 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 61564678 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 61250531 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 314147 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 29813717 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4063255 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1268860 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 187899 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 9409132 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7922191 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5257693 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 964170 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 651506 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 44858999 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1558626 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 43884207 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 67322 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 4967350 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2566909 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1055206 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 63623646 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.689747 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.329677 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 74953254 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.121098 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.620271 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26053984 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 36115594 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10809914 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 920077 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1053684 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 507198 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35097 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 62027396 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 105101 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1053684 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27061357 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 14627985 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18001405 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10130422 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4078399 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 58721682 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6643 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 642092 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1424191 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 39329555 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 71492090 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 71110334 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 381756 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34559979 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4769568 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1435328 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 208629 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11112444 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9161053 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6009456 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1123532 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 742915 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 52110985 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1787265 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 50968553 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 87650 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5843461 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2979197 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1210641 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 74953254 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.680005 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.329199 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 43919799 69.03% 69.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9075335 14.26% 83.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4098408 6.44% 89.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2614119 4.11% 93.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2006211 3.15% 97.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1055812 1.66% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 551217 0.87% 99.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 263467 0.41% 99.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 39278 0.06% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 52302643 69.78% 69.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10307098 13.75% 83.53% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4640048 6.19% 89.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3056236 4.08% 93.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2433864 3.25% 97.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1212107 1.62% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 643283 0.86% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 306838 0.41% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 51137 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 63623646 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 74953254 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 62740 10.88% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 271097 47.03% 57.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 242616 42.09% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 83602 12.51% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 310944 46.54% 59.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 273567 40.95% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3777 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 30137882 68.68% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 45897 0.10% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 14285 0.03% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 7870096 17.93% 86.76% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5096964 11.61% 98.37% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 713427 1.63% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35163137 68.99% 69.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56167 0.11% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15648 0.03% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9108259 17.87% 87.01% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5813234 11.41% 98.42% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 806455 1.58% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 43884207 # Type of FU issued -system.cpu0.iq.rate 0.488941 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 576453 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013136 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 151584762 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 51176195 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43017955 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 451072 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 219118 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 212749 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 44220901 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 235982 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 487348 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 50968553 # Type of FU issued +system.cpu0.iq.rate 0.500378 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 668113 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013108 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 177097926 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59488760 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 49954313 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 548196 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 265355 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 258816 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 51345953 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 286939 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 543981 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 958085 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2941 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 10552 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 366818 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1095536 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3484 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12649 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 447527 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 13186 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 117811 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18428 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 123543 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 905206 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8069118 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 677733 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 49115212 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 536411 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7922191 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5257693 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1375945 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 564143 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4652 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 10552 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 138850 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 301409 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 440259 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 43556869 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 7611218 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 327337 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1053684 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10434033 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 794004 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 57098821 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 607587 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9161053 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6009456 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1574353 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 581874 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5211 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12649 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 164505 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 346352 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 510857 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 50581166 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8806339 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 387386 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 2697587 # number of nop insts executed -system.cpu0.iew.exec_refs 12670581 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6879787 # Number of branches executed -system.cpu0.iew.exec_stores 5059363 # Number of stores executed -system.cpu0.iew.exec_rate 0.485294 # Inst execution rate -system.cpu0.iew.wb_sent 43311636 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43230704 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 21537449 # num instructions producing a value -system.cpu0.iew.wb_consumers 28771492 # num instructions consuming a value +system.cpu0.iew.exec_nop 3200571 # number of nop insts executed +system.cpu0.iew.exec_refs 14573024 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8058196 # Number of branches executed +system.cpu0.iew.exec_stores 5766685 # Number of stores executed +system.cpu0.iew.exec_rate 0.496575 # Inst execution rate +system.cpu0.iew.wb_sent 50300704 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 50213129 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25063994 # num instructions producing a value +system.cpu0.iew.wb_consumers 33773959 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.481660 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.748569 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.492962 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742110 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 5358562 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 503420 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 412035 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 62718440 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.696169 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.614251 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6307351 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 576624 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 477479 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 73899570 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.685982 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.603952 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 46279929 73.79% 73.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6945490 11.07% 84.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3654930 5.83% 90.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2050520 3.27% 93.96% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1130391 1.80% 95.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 454158 0.72% 96.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 393863 0.63% 97.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 373108 0.59% 97.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1436051 2.29% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 54870784 74.25% 74.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7931577 10.73% 84.98% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4331737 5.86% 90.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2351789 3.18% 94.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1313178 1.78% 95.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 548800 0.74% 96.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 466874 0.63% 97.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 433224 0.59% 97.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1651607 2.23% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 62718440 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 43662606 # Number of instructions committed -system.cpu0.commit.committedOps 43662606 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 73899570 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 50693798 # Number of instructions committed +system.cpu0.commit.committedOps 50693798 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11854981 # Number of memory references committed -system.cpu0.commit.loads 6964106 # Number of loads committed -system.cpu0.commit.membars 168172 # Number of memory barriers committed -system.cpu0.commit.branches 6551324 # Number of branches committed -system.cpu0.commit.fp_insts 210613 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 40489033 # Number of committed integer instructions. -system.cpu0.commit.function_calls 540020 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1436051 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13627446 # Number of memory references committed +system.cpu0.commit.loads 8065517 # Number of loads committed +system.cpu0.commit.membars 196376 # Number of memory barriers committed +system.cpu0.commit.branches 7658577 # Number of branches committed +system.cpu0.commit.fp_insts 256550 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 46944411 # Number of committed integer instructions. +system.cpu0.commit.function_calls 646517 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1651607 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 110111593 # The number of ROB reads -system.cpu0.rob.rob_writes 98948174 # The number of ROB writes -system.cpu0.timesIdled 879648 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26129913 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3707863967 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 41199881 # Number of Instructions Simulated -system.cpu0.committedOps 41199881 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 41199881 # Number of Instructions Simulated -system.cpu0.cpi 2.178491 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.178491 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.459033 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.459033 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 57370310 # number of integer regfile reads -system.cpu0.int_regfile_writes 31317782 # number of integer regfile writes -system.cpu0.fp_regfile_reads 104569 # number of floating regfile reads -system.cpu0.fp_regfile_writes 105332 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1463769 # number of misc regfile reads -system.cpu0.misc_regfile_writes 718581 # number of misc regfile writes +system.cpu0.rob.rob_reads 129054613 # The number of ROB reads +system.cpu0.rob.rob_writes 115056832 # The number of ROB writes +system.cpu0.timesIdled 1051988 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26906748 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3697658339 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 47774945 # Number of Instructions Simulated +system.cpu0.committedOps 47774945 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 47774945 # Number of Instructions Simulated +system.cpu0.cpi 2.132080 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.132080 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.469026 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.469026 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 66569976 # number of integer regfile reads +system.cpu0.int_regfile_writes 36353057 # number of integer regfile writes +system.cpu0.fp_regfile_reads 127037 # number of floating regfile reads +system.cpu0.fp_regfile_writes 128676 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1691103 # number of misc regfile reads +system.cpu0.misc_regfile_writes 806046 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -947,245 +932,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 728874 # number of replacements -system.cpu0.icache.tagsinuse 510.265304 # Cycle average of tags in use -system.cpu0.icache.total_refs 5890439 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 729383 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.075920 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 20962478000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.265304 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996612 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996612 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5890439 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5890439 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5890439 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5890439 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5890439 # number of overall hits -system.cpu0.icache.overall_hits::total 5890439 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 766860 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 766860 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 766860 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 766860 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 766860 # number of overall misses -system.cpu0.icache.overall_misses::total 766860 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10795349496 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10795349496 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10795349496 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10795349496 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10795349496 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10795349496 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6657299 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6657299 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6657299 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6657299 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6657299 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6657299 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.115191 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.115191 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.115191 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.115191 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.115191 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.115191 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14077.340709 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14077.340709 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14077.340709 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14077.340709 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14077.340709 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14077.340709 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2177 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 468 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 128 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.007812 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 468 # average number of cycles each access was blocked +system.cpu0.icache.replacements 863258 # number of replacements +system.cpu0.icache.tagsinuse 510.308888 # Cycle average of tags in use +system.cpu0.icache.total_refs 6729374 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 863770 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.790701 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 20507557000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.308888 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996697 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996697 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6729374 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6729374 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6729374 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6729374 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6729374 # number of overall hits +system.cpu0.icache.overall_hits::total 6729374 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 907848 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 907848 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 907848 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 907848 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 907848 # number of overall misses +system.cpu0.icache.overall_misses::total 907848 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12809117491 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12809117491 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12809117491 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12809117491 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12809117491 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12809117491 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7637222 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7637222 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7637222 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7637222 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7637222 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7637222 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118871 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.118871 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118871 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.118871 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118871 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.118871 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14109.319502 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14109.319502 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14109.319502 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14109.319502 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14109.319502 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14109.319502 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5737 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 161 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 35.633540 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37318 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 37318 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 37318 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 37318 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 37318 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 37318 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 729542 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 729542 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 729542 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 729542 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 729542 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 729542 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8901782997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8901782997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8901782997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8901782997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8901782997 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8901782997 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.109585 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.109585 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.109585 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12201.878709 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12201.878709 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12201.878709 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43927 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 43927 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 43927 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 43927 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 43927 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 43927 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 863921 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 863921 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 863921 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 863921 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 863921 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 863921 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10545414492 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10545414492 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10545414492 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10545414492 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10545414492 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10545414492 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113120 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113120 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113120 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.113120 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113120 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.113120 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12206.456947 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12206.456947 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12206.456947 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12206.456947 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12206.456947 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12206.456947 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1051655 # number of replacements -system.cpu0.dcache.tagsinuse 479.291529 # Cycle average of tags in use -system.cpu0.dcache.total_refs 8945957 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1052167 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.502412 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1272639 # number of replacements +system.cpu0.dcache.tagsinuse 505.727163 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10328741 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1273151 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.112738 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 22123000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 479.291529 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.936116 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.936116 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5529733 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5529733 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3096724 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3096724 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 145068 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 145068 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 167974 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 167974 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8626457 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8626457 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8626457 # number of overall hits -system.cpu0.dcache.overall_hits::total 8626457 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1297164 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1297164 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1613226 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1613226 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 15668 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 15668 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 766 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 766 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2910390 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2910390 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2910390 # number of overall misses -system.cpu0.dcache.overall_misses::total 2910390 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 30009249500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 30009249500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 61556935480 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 61556935480 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 231982500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 231982500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4680500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4680500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 91566184980 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 91566184980 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 91566184980 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 91566184980 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6826897 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6826897 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4709950 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4709950 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160736 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 160736 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 168740 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 168740 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11536847 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11536847 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11536847 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11536847 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.190008 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.190008 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.342514 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.342514 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.097477 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.097477 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004540 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004540 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.252269 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.252269 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.252269 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.252269 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23134.506893 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 23134.506893 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38157.663886 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38157.663886 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14806.133521 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14806.133521 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6110.313316 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6110.313316 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31461.826415 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 31461.826415 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31461.826415 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31461.826415 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2024468 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 671 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 45038 # number of cycles access was blocked +system.cpu0.dcache.occ_blocks::cpu0.data 505.727163 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.987748 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.987748 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6350419 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6350419 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3622179 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3622179 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 160143 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 160143 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 184450 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 184450 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9972598 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9972598 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9972598 # number of overall hits +system.cpu0.dcache.overall_hits::total 9972598 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1584754 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1584754 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1737731 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1737731 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20393 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20393 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2991 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2991 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3322485 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3322485 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3322485 # number of overall misses +system.cpu0.dcache.overall_misses::total 3322485 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34254700500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 34254700500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 66543857651 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 66543857651 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 293744000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 293744000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 21938000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 21938000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 100798558151 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 100798558151 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 100798558151 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 100798558151 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7935173 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7935173 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5359910 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5359910 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 180536 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 180536 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187441 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 187441 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13295083 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13295083 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13295083 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13295083 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199713 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.199713 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324209 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.324209 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112958 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112958 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015957 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015957 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249903 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.249903 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249903 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.249903 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21615.153204 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 21615.153204 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38293.531997 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38293.531997 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14404.158290 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14404.158290 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7334.670679 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7334.670679 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30338.303454 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 30338.303454 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30338.303454 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 30338.303454 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2157066 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2274 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 48232 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.950220 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 95.857143 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.722715 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 324.857143 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 554167 # number of writebacks -system.cpu0.dcache.writebacks::total 554167 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 497870 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 497870 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1365575 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1365575 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3772 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3772 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1863445 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1863445 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1863445 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1863445 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 799294 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 799294 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 247651 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 247651 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 11896 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11896 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 766 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 766 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1046945 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1046945 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1046945 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1046945 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19199342000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19199342000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8924614838 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8924614838 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 148344000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148344000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3148500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3148500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 28123956838 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 28123956838 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 28123956838 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 28123956838 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 991461500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 991461500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1668991999 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1668991999 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2660453499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2660453499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117080 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117080 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052580 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052580 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.074010 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.074010 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004540 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004540 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090748 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.090748 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090748 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.090748 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24020.375481 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24020.375481 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36037.063602 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36037.063602 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12470.073974 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12470.073974 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4110.313316 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4110.313316 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26862.878984 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26862.878984 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26862.878984 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26862.878984 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 748565 # number of writebacks +system.cpu0.dcache.writebacks::total 748565 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 585493 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 585493 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1465453 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1465453 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4489 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4489 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2050946 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2050946 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2050946 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2050946 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 999261 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 999261 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 272278 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 272278 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15904 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15904 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2991 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2991 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1271539 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1271539 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1271539 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1271539 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21490960000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21490960000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9698199220 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9698199220 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183494500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183494500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15956000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15956000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31189159220 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 31189159220 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31189159220 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 31189159220 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1454907000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1454907000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2130479499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2130479499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3585386499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3585386499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125928 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125928 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050799 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050799 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088093 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088093 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015957 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015957 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095640 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.095640 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095640 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.095640 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21506.853565 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21506.853565 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35618.739744 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35618.739744 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11537.632042 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11537.632042 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5334.670679 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5334.670679 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24528.668975 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24528.668975 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24528.668975 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24528.668975 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1193,35 +1178,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 4327546 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3555815 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 137782 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2736457 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1529937 # Number of BTB hits +system.cpu1.branchPred.lookups 2650086 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2188228 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 78181 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1530727 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 883629 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 55.909411 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 311519 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 14646 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 57.726100 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 184091 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 8336 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 3068448 # DTB read hits -system.cpu1.dtb.read_misses 13337 # DTB read misses -system.cpu1.dtb.read_acv 21 # DTB read access violations -system.cpu1.dtb.read_accesses 325420 # DTB read accesses -system.cpu1.dtb.write_hits 1915630 # DTB write hits -system.cpu1.dtb.write_misses 2521 # DTB write misses -system.cpu1.dtb.write_acv 68 # DTB write access violations -system.cpu1.dtb.write_accesses 132592 # DTB write accesses -system.cpu1.dtb.data_hits 4984078 # DTB hits -system.cpu1.dtb.data_misses 15858 # DTB misses -system.cpu1.dtb.data_acv 89 # DTB access violations -system.cpu1.dtb.data_accesses 458012 # DTB accesses -system.cpu1.itb.fetch_hits 498592 # ITB hits -system.cpu1.itb.fetch_misses 6957 # ITB misses -system.cpu1.itb.fetch_acv 210 # ITB acv -system.cpu1.itb.fetch_accesses 505549 # ITB accesses +system.cpu1.dtb.read_hits 1963408 # DTB read hits +system.cpu1.dtb.read_misses 10761 # DTB read misses +system.cpu1.dtb.read_acv 27 # DTB read access violations +system.cpu1.dtb.read_accesses 325022 # DTB read accesses +system.cpu1.dtb.write_hits 1266270 # DTB write hits +system.cpu1.dtb.write_misses 2185 # DTB write misses +system.cpu1.dtb.write_acv 66 # DTB write access violations +system.cpu1.dtb.write_accesses 133146 # DTB write accesses +system.cpu1.dtb.data_hits 3229678 # DTB hits +system.cpu1.dtb.data_misses 12946 # DTB misses +system.cpu1.dtb.data_acv 93 # DTB access violations +system.cpu1.dtb.data_accesses 458168 # DTB accesses +system.cpu1.itb.fetch_hits 437746 # ITB hits +system.cpu1.itb.fetch_misses 6892 # ITB misses +system.cpu1.itb.fetch_acv 236 # ITB acv +system.cpu1.itb.fetch_accesses 444638 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1234,508 +1219,508 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 28341850 # number of cpu cycles simulated +system.cpu1.numCycles 16144974 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 9666058 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 20746660 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4327546 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1841456 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 3769607 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 667538 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 11516910 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 24752 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65971 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 157862 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 117 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 2430728 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 90320 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 25638274 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.809207 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.171586 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 6121442 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 12493756 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2650086 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1067720 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2240899 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 409596 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 6344466 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 26232 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65860 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 57508 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1513677 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 52961 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 15118787 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.826373 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.200485 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 21868667 85.30% 85.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 217825 0.85% 86.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 471767 1.84% 87.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 290566 1.13% 89.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 572691 2.23% 91.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 192619 0.75% 92.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 225020 0.88% 92.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 283328 1.11% 94.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1515791 5.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 12877888 85.18% 85.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 143885 0.95% 86.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 241695 1.60% 87.73% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 180531 1.19% 88.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 309762 2.05% 90.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 120449 0.80% 91.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 135595 0.90% 92.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 201831 1.33% 94.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 907151 6.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 25638274 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.152691 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.732015 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 9733408 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 11767392 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 3496252 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 218180 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 423041 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 197160 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 14107 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 20339380 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 42509 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 423041 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 10090973 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 3436285 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 7189136 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 3265501 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1233336 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 19035683 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 265 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 302354 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 266371 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 12573410 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 22727510 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 22552449 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 175061 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 10671795 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1901615 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 598380 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 62207 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 3655619 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 3246585 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 2021315 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 341799 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 191681 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 16730301 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 718132 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 16236732 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 38678 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2401085 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1178363 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 514161 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 25638274 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.633301 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.313801 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 15118787 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.164143 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.773848 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 6052870 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6602402 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2094481 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 114057 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 254976 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 116126 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7500 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 12249807 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22555 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 254976 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 6262682 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 497209 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5456490 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1996397 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 651031 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 11355545 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 50 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 56660 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 160008 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 7474719 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 13559101 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 13415671 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 143430 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 6386740 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1087979 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 456269 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 43986 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2005882 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2076975 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1341554 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 190968 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 103806 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 9970569 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 502731 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 9700952 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 30075 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1449475 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 723922 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 361264 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 15118787 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.641649 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.316312 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 18618463 72.62% 72.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 3106773 12.12% 84.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1368758 5.34% 90.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 986929 3.85% 93.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 856057 3.34% 97.26% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 349630 1.36% 98.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 219211 0.86% 99.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 115612 0.45% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 16841 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 10852712 71.78% 71.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1956314 12.94% 84.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 839077 5.55% 90.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 560111 3.70% 93.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 472963 3.13% 97.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 218451 1.44% 98.55% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 140254 0.93% 99.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 70720 0.47% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 8185 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 25638274 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 15118787 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 22162 7.89% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 144030 51.29% 59.18% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 114619 40.82% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3675 1.85% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 107078 53.97% 55.83% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 87636 44.17% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3527 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 10692350 65.85% 65.87% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 24766 0.15% 66.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.03% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 11484 0.07% 66.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 3204356 19.74% 85.84% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1945149 11.98% 97.82% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 353337 2.18% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 6050828 62.37% 62.41% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 16408 0.17% 62.58% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.58% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10849 0.11% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2054303 21.18% 83.89% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1289929 13.30% 97.18% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 273346 2.82% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 16236732 # Type of FU issued -system.cpu1.iq.rate 0.572889 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 280811 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.017295 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 58178646 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 19730507 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 15830008 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 252581 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 122599 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 119620 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 16382145 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 131871 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 151965 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 9700952 # Type of FU issued +system.cpu1.iq.rate 0.600865 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 198389 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020450 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 34541883 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 11823308 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 9430294 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 207272 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 101213 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 98067 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 9787736 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 108079 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 94689 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 456957 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 998 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 3692 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 187617 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 288018 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 887 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1813 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 126704 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 5626 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 16438 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 386 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 10289 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 423041 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2638422 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 162147 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 18437863 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 211636 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 3246585 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 2021315 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 643129 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 60084 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2152 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 3692 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 66784 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 149088 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 215872 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 16080551 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 3090638 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 156181 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 254976 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 327284 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 41516 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 10988492 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 148711 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2076975 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1341554 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 455253 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 34417 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1886 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1813 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 35814 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 100493 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 136307 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 9610649 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1981550 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 90303 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 989430 # number of nop insts executed -system.cpu1.iew.exec_refs 5015230 # number of memory reference insts executed -system.cpu1.iew.exec_branches 2535241 # Number of branches executed -system.cpu1.iew.exec_stores 1924592 # Number of stores executed -system.cpu1.iew.exec_rate 0.567378 # Inst execution rate -system.cpu1.iew.wb_sent 15988482 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 15949628 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 7724743 # num instructions producing a value -system.cpu1.iew.wb_consumers 10881499 # num instructions consuming a value +system.cpu1.iew.exec_nop 515192 # number of nop insts executed +system.cpu1.iew.exec_refs 3256018 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1435370 # Number of branches executed +system.cpu1.iew.exec_stores 1274468 # Number of stores executed +system.cpu1.iew.exec_rate 0.595272 # Inst execution rate +system.cpu1.iew.wb_sent 9557675 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 9528361 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4461159 # num instructions producing a value +system.cpu1.iew.wb_consumers 6259469 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.562759 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.709897 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.590175 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.712706 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 2575173 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 203971 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 201824 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 25215233 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.626683 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.561616 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1504147 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 141467 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 128937 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 14863811 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.633307 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.576989 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 19361338 76.78% 76.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2499341 9.91% 86.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1261575 5.00% 91.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 645749 2.56% 94.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 410067 1.63% 95.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 193046 0.77% 96.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 184525 0.73% 97.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 147171 0.58% 97.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 512421 2.03% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 11340708 76.30% 76.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1645490 11.07% 87.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 614395 4.13% 91.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 372484 2.51% 94.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 264045 1.78% 95.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 106401 0.72% 96.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 110365 0.74% 97.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 108140 0.73% 97.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 301783 2.03% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 25215233 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 15801951 # Number of instructions committed -system.cpu1.commit.committedOps 15801951 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 14863811 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 9413351 # Number of instructions committed +system.cpu1.commit.committedOps 9413351 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 4623326 # Number of memory references committed -system.cpu1.commit.loads 2789628 # Number of loads committed -system.cpu1.commit.membars 68640 # Number of memory barriers committed -system.cpu1.commit.branches 2366242 # Number of branches committed -system.cpu1.commit.fp_insts 118314 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 14589318 # Number of committed integer instructions. -system.cpu1.commit.function_calls 250839 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 512421 # number cycles where commit BW limit reached +system.cpu1.commit.refs 3003807 # Number of memory references committed +system.cpu1.commit.loads 1788957 # Number of loads committed +system.cpu1.commit.membars 45075 # Number of memory barriers committed +system.cpu1.commit.branches 1347256 # Number of branches committed +system.cpu1.commit.fp_insts 96765 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 8723626 # Number of committed integer instructions. +system.cpu1.commit.function_calls 150668 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 301783 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 42991260 # The number of ROB reads -system.cpu1.rob.rob_writes 37176651 # The number of ROB writes -system.cpu1.timesIdled 292999 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2703576 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3768655732 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 14927555 # Number of Instructions Simulated -system.cpu1.committedOps 14927555 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 14927555 # Number of Instructions Simulated -system.cpu1.cpi 1.898626 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.898626 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.526697 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.526697 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 20802804 # number of integer regfile reads -system.cpu1.int_regfile_writes 11409368 # number of integer regfile writes -system.cpu1.fp_regfile_reads 63889 # number of floating regfile reads -system.cpu1.fp_regfile_writes 64169 # number of floating regfile writes -system.cpu1.misc_regfile_reads 688257 # number of misc regfile reads -system.cpu1.misc_regfile_writes 294653 # number of misc regfile writes -system.cpu1.icache.replacements 359909 # number of replacements -system.cpu1.icache.tagsinuse 505.656535 # Cycle average of tags in use -system.cpu1.icache.total_refs 2054105 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 360421 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.699182 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 43308699500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 505.656535 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.987610 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.987610 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 2054105 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 2054105 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 2054105 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 2054105 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 2054105 # number of overall hits -system.cpu1.icache.overall_hits::total 2054105 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 376623 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 376623 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 376623 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 376623 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 376623 # number of overall misses -system.cpu1.icache.overall_misses::total 376623 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5258660997 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5258660997 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5258660997 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5258660997 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5258660997 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5258660997 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 2430728 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 2430728 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 2430728 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 2430728 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 2430728 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 2430728 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154942 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.154942 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.154942 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.154942 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.154942 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.154942 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13962.665575 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13962.665575 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13962.665575 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13962.665575 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13962.665575 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13962.665575 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2479 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 1476 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 54 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 45.907407 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 1476 # average number of cycles each access was blocked +system.cpu1.rob.rob_reads 25388124 # The number of ROB reads +system.cpu1.rob.rob_writes 22088528 # The number of ROB writes +system.cpu1.timesIdled 132804 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1026187 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3782762516 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 8958605 # Number of Instructions Simulated +system.cpu1.committedOps 8958605 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 8958605 # Number of Instructions Simulated +system.cpu1.cpi 1.802175 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.802175 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.554885 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.554885 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 12390777 # number of integer regfile reads +system.cpu1.int_regfile_writes 6781957 # number of integer regfile writes +system.cpu1.fp_regfile_reads 53541 # number of floating regfile reads +system.cpu1.fp_regfile_writes 53239 # number of floating regfile writes +system.cpu1.misc_regfile_reads 527070 # number of misc regfile reads +system.cpu1.misc_regfile_writes 221606 # number of misc regfile writes +system.cpu1.icache.replacements 226821 # number of replacements +system.cpu1.icache.tagsinuse 470.843395 # Cycle average of tags in use +system.cpu1.icache.total_refs 1277714 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 227333 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.620451 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1874198606000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 470.843395 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.919616 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.919616 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1277714 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1277714 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1277714 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1277714 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1277714 # number of overall hits +system.cpu1.icache.overall_hits::total 1277714 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 235963 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 235963 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 235963 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 235963 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 235963 # number of overall misses +system.cpu1.icache.overall_misses::total 235963 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3262757999 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3262757999 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3262757999 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3262757999 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3262757999 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3262757999 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1513677 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1513677 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1513677 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1513677 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1513677 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1513677 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.155887 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.155887 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.155887 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.155887 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.155887 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.155887 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13827.413616 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13827.413616 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13827.413616 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13827.413616 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13827.413616 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13827.413616 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 255 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 17 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 15 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 16134 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 16134 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 16134 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 16134 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 16134 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 16134 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 360489 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 360489 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 360489 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 360489 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 360489 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 360489 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4342433998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4342433998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4342433998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4342433998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4342433998 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4342433998 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.148305 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.148305 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.148305 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.148305 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.148305 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.148305 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12045.954240 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12045.954240 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12045.954240 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12045.954240 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12045.954240 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12045.954240 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8568 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 8568 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 8568 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 8568 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 8568 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 8568 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 227395 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 227395 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 227395 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 227395 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 227395 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 227395 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2711257499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2711257499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2711257499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2711257499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2711257499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2711257499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.150227 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.150227 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.150227 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.150227 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.150227 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.150227 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11923.118358 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11923.118358 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11923.118358 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11923.118358 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11923.118358 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11923.118358 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 377681 # number of replacements -system.cpu1.dcache.tagsinuse 497.778191 # Cycle average of tags in use -system.cpu1.dcache.total_refs 3769592 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 378084 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 9.970250 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 35370260000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 497.778191 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.972223 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.972223 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 2307913 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2307913 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1365825 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1365825 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47088 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 47088 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50932 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50932 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3673738 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3673738 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3673738 # number of overall hits -system.cpu1.dcache.overall_hits::total 3673738 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 542018 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 542018 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 408775 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 408775 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9102 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9102 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 780 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 780 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 950793 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 950793 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 950793 # number of overall misses -system.cpu1.dcache.overall_misses::total 950793 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8456828000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 8456828000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13523509258 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 13523509258 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 132387000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 132387000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5554000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5554000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 21980337258 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 21980337258 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 21980337258 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 21980337258 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2849931 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2849931 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1774600 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1774600 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56190 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 56190 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 51712 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 51712 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4624531 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4624531 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4624531 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4624531 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.190186 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.190186 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.230348 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.230348 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.161986 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.161986 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.015084 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.015084 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.205598 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.205598 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.205598 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.205598 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15602.485526 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15602.485526 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33083.014514 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 33083.014514 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14544.825313 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14544.825313 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7120.512821 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7120.512821 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23117.899751 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23117.899751 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23117.899751 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23117.899751 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 393760 # number of cycles access was blocked +system.cpu1.dcache.replacements 108831 # number of replacements +system.cpu1.dcache.tagsinuse 491.507176 # Cycle average of tags in use +system.cpu1.dcache.total_refs 2642897 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 109233 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 24.195042 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 39074075000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 491.507176 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.959975 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.959975 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1619180 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1619180 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 952866 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 952866 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 33989 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 33989 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 32614 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 32614 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2572046 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2572046 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2572046 # number of overall hits +system.cpu1.dcache.overall_hits::total 2572046 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 209251 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 209251 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 220110 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 220110 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5396 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5396 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3146 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3146 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 429361 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 429361 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 429361 # number of overall misses +system.cpu1.dcache.overall_misses::total 429361 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3173212000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3173212000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7555840185 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 7555840185 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 56288500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 56288500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22631500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 22631500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 10729052185 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 10729052185 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 10729052185 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 10729052185 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1828431 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1828431 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1172976 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1172976 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 39385 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 39385 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 35760 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 35760 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3001407 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3001407 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3001407 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3001407 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114443 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.114443 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.187651 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.187651 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137006 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137006 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087975 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087975 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.143053 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.143053 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143053 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.143053 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15164.620480 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15164.620480 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34327.564331 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34327.564331 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10431.523351 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10431.523351 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7193.738080 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7193.738080 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24988.418103 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24988.418103 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24988.418103 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24988.418103 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 240297 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 7994 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3869 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 49.256943 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 62.108297 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 289966 # number of writebacks -system.cpu1.dcache.writebacks::total 289966 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 235266 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 235266 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 338145 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 338145 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1764 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1764 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 573411 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 573411 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 573411 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 573411 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 306752 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 306752 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 70630 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 70630 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7338 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7338 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 780 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 780 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 377382 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 377382 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 377382 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 377382 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4029157000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4029157000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2036960738 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2036960738 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87414000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87414000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3994000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3994000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6066117738 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6066117738 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6066117738 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6066117738 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 491781000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 491781000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 942840000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 942840000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1434621000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1434621000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.107635 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.107635 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.039801 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.039801 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130593 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130593 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.015084 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.015084 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.081604 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.081604 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.081604 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.081604 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13134.900506 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13134.900506 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28839.880193 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28839.880193 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11912.510221 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11912.510221 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5120.512821 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5120.512821 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16074.210582 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16074.210582 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16074.210582 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16074.210582 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 72108 # number of writebacks +system.cpu1.dcache.writebacks::total 72108 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 129790 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 129790 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 180827 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 180827 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 598 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 598 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 310617 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 310617 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 310617 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 310617 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 79461 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 79461 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 39283 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 39283 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4798 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4798 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3146 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 3146 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 118744 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 118744 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 118744 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 118744 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 970446000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 970446000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1118523985 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1118523985 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38903500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38903500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16339500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16339500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2088969985 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2088969985 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2088969985 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2088969985 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30978500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30978500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 647630000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 647630000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 678608500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 678608500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043459 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043459 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033490 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033490 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.121823 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.121823 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087975 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087975 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039563 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.039563 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039563 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.039563 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12212.859138 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12212.859138 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28473.486877 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28473.486877 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8108.274281 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8108.274281 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5193.738080 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5193.738080 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17592.215059 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17592.215059 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17592.215059 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17592.215059 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1744,32 +1729,32 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4837 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 159566 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 54412 39.60% 39.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.10% 39.69% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1925 1.40% 41.09% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 16 0.01% 41.10% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 80931 58.90% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 137415 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 53531 49.06% 49.06% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.12% 49.18% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1925 1.76% 50.94% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 16 0.01% 50.96% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 53515 49.04% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 109118 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1866933879000 98.32% 98.32% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 62852000 0.00% 98.32% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 558860500 0.03% 98.35% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 8730000 0.00% 98.35% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 31246000500 1.65% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1898810322000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983809 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6548 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 181674 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 64152 40.43% 40.43% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 136 0.09% 40.52% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1926 1.21% 41.73% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 194 0.12% 41.86% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 92254 58.14% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 158662 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 63162 49.20% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 136 0.11% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1926 1.50% 50.80% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 194 0.15% 50.95% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 62971 49.05% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 128389 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1864385169000 98.14% 98.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63278000 0.00% 98.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 567602000 0.03% 98.17% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 94599000 0.00% 98.18% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 34650950500 1.82% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1899761598500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984568 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.661242 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.794076 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.682583 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.809198 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed @@ -1801,60 +1786,60 @@ system.cpu0.kern.syscall::144 1 0.50% 99.01% # nu system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 202 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 107 0.07% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2838 1.96% 2.03% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.07% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.07% # number of callpals executed -system.cpu0.kern.callpal::swpipl 131134 90.46% 92.54% # number of callpals executed -system.cpu0.kern.callpal::rdps 6127 4.23% 96.76% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.77% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.01% 96.77% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed -system.cpu0.kern.callpal::rti 4208 2.90% 99.68% # number of callpals executed -system.cpu0.kern.callpal::callsys 333 0.23% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 144957 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6180 # number of protection mode switches +system.cpu0.kern.callpal::wripir 297 0.18% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3469 2.08% 2.26% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.29% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed +system.cpu0.kern.callpal::swpipl 151918 91.03% 93.32% # number of callpals executed +system.cpu0.kern.callpal::rdps 6167 3.70% 97.02% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.02% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 97.02% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed +system.cpu0.kern.callpal::rti 4490 2.69% 99.72% # number of callpals executed +system.cpu0.kern.callpal::callsys 333 0.20% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 166884 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6992 # number of protection mode switches system.cpu0.kern.mode_switch::user 1258 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1257 system.cpu0.kern.mode_good::user 1258 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.203398 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.179777 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.338129 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1896878389500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1931924500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.304848 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1897853280000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1908310500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2839 # number of times the context was actually changed +system.cpu0.kern.swap_context 3470 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3835 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 77998 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27220 39.42% 39.42% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1923 2.78% 42.20% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 107 0.15% 42.36% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 39804 57.64% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69054 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26724 48.26% 48.26% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1923 3.47% 51.74% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 107 0.19% 51.93% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 26617 48.07% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 55371 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1869610475000 98.48% 98.48% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533425500 0.03% 98.51% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 50588500 0.00% 98.51% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 28306196500 1.49% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1898500685500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.981778 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2463 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 58134 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 18218 36.94% 36.94% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 3.90% 40.84% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 297 0.60% 41.45% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 28877 58.55% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 49317 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 17831 47.44% 47.44% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 5.12% 52.56% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 297 0.79% 53.35% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 17534 46.65% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 37587 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1874537930000 98.69% 98.69% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 532213500 0.03% 98.72% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 134642000 0.01% 98.72% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 24250176000 1.28% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1899454961500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.978757 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.668702 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.801851 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.607196 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.762151 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed @@ -1878,36 +1863,36 @@ system.cpu1.kern.syscall::132 3 2.42% 99.19% # nu system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 124 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1407 1.97% 2.00% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.01% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.02% # number of callpals executed -system.cpu1.kern.callpal::swpipl 64017 89.75% 91.76% # number of callpals executed -system.cpu1.kern.callpal::rdps 2632 3.69% 95.45% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 95.45% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 95.46% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 95.46% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 95.47% # number of callpals executed -system.cpu1.kern.callpal::rti 3006 4.21% 99.68% # number of callpals executed -system.cpu1.kern.callpal::callsys 184 0.26% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 194 0.38% 0.38% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1140 2.22% 2.61% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 2.62% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.63% # number of callpals executed +system.cpu1.kern.callpal::swpipl 43997 85.81% 88.44% # number of callpals executed +system.cpu1.kern.callpal::rdps 2594 5.06% 93.50% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.50% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.51% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.51% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.52% # number of callpals executed +system.cpu1.kern.callpal::rti 3097 6.04% 99.56% # number of callpals executed +system.cpu1.kern.callpal::callsys 184 0.36% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71331 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1876 # number of protection mode switches +system.cpu1.kern.callpal::total 51275 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1424 # number of protection mode switches system.cpu1.kern.mode_switch::user 488 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2061 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 557 +system.cpu1.kern.mode_switch::idle 2438 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 709 system.cpu1.kern.mode_good::user 488 -system.cpu1.kern.mode_good::idle 69 -system.cpu1.kern.mode_switch_good::kernel 0.296908 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 221 +system.cpu1.kern.mode_switch_good::kernel 0.497893 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.033479 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.251751 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 39690497500 2.09% 2.09% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 850597000 0.04% 2.14% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1857949530000 97.86% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1408 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.090648 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.325977 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4822300000 0.25% 0.25% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 832322500 0.04% 0.30% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893789827000 99.70% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1141 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 02dc83699..856de11b9 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,137 +1,124 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.854310 # Number of seconds simulated -sim_ticks 1854310111000 # Number of ticks simulated -final_tick 1854310111000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.854307 # Number of seconds simulated +sim_ticks 1854307399500 # Number of ticks simulated +final_tick 1854307399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145253 # Simulator instruction rate (inst/s) -host_op_rate 145253 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5083862253 # Simulator tick rate (ticks/s) -host_mem_usage 332668 # Number of bytes of host memory used -host_seconds 364.74 # Real time elapsed on the host -sim_insts 52980262 # Number of instructions simulated -sim_ops 52980262 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 964224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24877184 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28493696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 964224 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 964224 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7514944 # Number of bytes written to this memory -system.physmem.bytes_written::total 7514944 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15066 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388706 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445214 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117421 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117421 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 519991 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13415870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1430337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15366198 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 519991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 519991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4052690 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4052690 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4052690 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 519991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13415870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1430337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19418888 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445214 # Total number of read requests seen -system.physmem.writeReqs 117421 # Total number of write requests seen -system.physmem.cpureqs 564314 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28493696 # Total number of bytes read from memory -system.physmem.bytesWritten 7514944 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28493696 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7514944 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 174 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28116 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27866 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27714 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27520 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27750 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27793 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27726 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27564 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28224 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27918 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27999 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27794 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27705 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27923 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27829 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27717 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7633 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7399 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7274 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7170 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7277 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7235 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7211 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7144 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7765 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7469 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7552 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7291 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7210 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7327 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7200 # Track writes on a per bank basis +host_inst_rate 106006 # Simulator instruction rate (inst/s) +host_op_rate 106006 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3711029376 # Simulator tick rate (ticks/s) +host_mem_usage 333480 # Number of bytes of host memory used +host_seconds 499.67 # Real time elapsed on the host +sim_insts 52968721 # Number of instructions simulated +sim_ops 52968721 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 963456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24875584 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory +system.physmem.bytes_read::total 28491392 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 963456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 963456 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7501184 # Number of bytes written to this memory +system.physmem.bytes_written::total 7501184 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15054 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388681 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory +system.physmem.num_reads::total 445178 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117206 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117206 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 519577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13415027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1430373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15364978 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 519577 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 519577 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4045275 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4045275 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4045275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 519577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13415027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1430373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19410253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445178 # Total number of read requests seen +system.physmem.writeReqs 117206 # Total number of write requests seen +system.physmem.cpureqs 565467 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28491392 # Total number of bytes read from memory +system.physmem.bytesWritten 7501184 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28491392 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7501184 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 59 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 176 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28014 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27748 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27561 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27303 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27866 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27961 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27981 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27784 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28083 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27812 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27967 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27770 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27785 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27982 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27794 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27708 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7541 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7132 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6966 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7344 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7366 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7434 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7324 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7647 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7361 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7507 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7242 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7283 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7386 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7202 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7186 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 946 # Number of times wr buffer was full causing retry -system.physmem.totGap 1854304705000 # Total gap between requests +system.physmem.numWrRetry 2907 # Number of times wr buffer was full causing retry +system.physmem.totGap 1854301986000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445214 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 118367 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 174 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 323357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7564 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2710 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2705 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2662 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1463 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1393 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1481 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.readPktSize::6 445178 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 117206 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 323486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64269 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2705 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2704 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2606 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1536 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1475 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1357 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1492 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 769 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -141,70 +128,68 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1402 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 7913395266 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15649662766 # Sum of mem lat for all requests -system.physmem.totBusLat 2225790000 # Total cycles spent in databus access -system.physmem.totBankLat 5510477500 # Total cycles spent in bank access -system.physmem.avgQLat 17776.60 # Average queueing delay per request -system.physmem.avgBankLat 12378.70 # Average bank access latency per request +system.physmem.wrQLenPdf::26 881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see +system.physmem.totQLat 7499469250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15210035500 # Sum of mem lat for all requests +system.physmem.totBusLat 2225595000 # Total cycles spent in databus access +system.physmem.totBankLat 5484971250 # Total cycles spent in bank access +system.physmem.avgQLat 16848.23 # Average queueing delay per request +system.physmem.avgBankLat 12322.48 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 35155.30 # Average memory access latency -system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 34170.72 # Average memory access latency +system.physmem.avgRdBW 15.36 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.36 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 11.52 # Average write queue length over time -system.physmem.readRowHits 417628 # Number of row buffer hits during reads -system.physmem.writeRowHits 91533 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.95 # Row buffer hit rate for writes -system.physmem.avgGap 3295750.72 # Average gap between requests +system.physmem.avgWrQLen 14.44 # Average write queue length over time +system.physmem.readRowHits 417746 # Number of row buffer hits during reads +system.physmem.writeRowHits 91351 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.85 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.94 # Row buffer hit rate for writes +system.physmem.avgGap 3297216.82 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.265053 # Cycle average of tags in use +system.iocache.tagsinuse 1.265036 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1704474436000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.265053 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079066 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079066 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1704474218000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.265036 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079065 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079065 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -215,12 +200,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10610366806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10610366806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10631294804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10631294804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10631294804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10631294804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10707310806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10707310806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10728238804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10728238804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10728238804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10728238804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -239,17 +224,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255351.530757 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 255351.530757 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 254794.363188 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 254794.363188 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 254794.363188 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 254794.363188 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 282772 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 257684.607384 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 257684.607384 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 257117.766423 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 257117.766423 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 257117.766423 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 257117.766423 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 287181 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27194 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27254 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.398323 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.537206 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -263,14 +248,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931250 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11931250 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8448369274 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8448369274 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8460300524 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8460300524 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8460300524 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8460300524 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8545305081 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8545305081 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8557236330 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8557236330 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8557236330 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8557236330 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -279,14 +264,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203320.400318 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 203320.400318 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202763.343895 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 202763.343895 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202763.343895 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 202763.343895 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 205653.279770 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 205653.279770 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 205086.550749 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 205086.550749 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 205086.550749 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 205086.550749 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -300,35 +285,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13838840 # Number of BP lookups -system.cpu.branchPred.condPredicted 11607895 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 399412 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9524270 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5814876 # Number of BTB hits +system.cpu.branchPred.lookups 13852347 # Number of BP lookups +system.cpu.branchPred.condPredicted 11625691 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 399405 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9419832 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5813293 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.053246 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 905729 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 39052 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.713341 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 901451 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 38715 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9926019 # DTB read hits -system.cpu.dtb.read_misses 41533 # DTB read misses -system.cpu.dtb.read_acv 530 # DTB read access violations -system.cpu.dtb.read_accesses 942239 # DTB read accesses -system.cpu.dtb.write_hits 6593693 # DTB write hits -system.cpu.dtb.write_misses 10528 # DTB write misses -system.cpu.dtb.write_acv 400 # DTB write access violations -system.cpu.dtb.write_accesses 337995 # DTB write accesses -system.cpu.dtb.data_hits 16519712 # DTB hits -system.cpu.dtb.data_misses 52061 # DTB misses -system.cpu.dtb.data_acv 930 # DTB access violations -system.cpu.dtb.data_accesses 1280234 # DTB accesses -system.cpu.itb.fetch_hits 1304342 # ITB hits -system.cpu.itb.fetch_misses 39856 # ITB misses -system.cpu.itb.fetch_acv 1022 # ITB acv -system.cpu.itb.fetch_accesses 1344198 # ITB accesses +system.cpu.dtb.read_hits 9912757 # DTB read hits +system.cpu.dtb.read_misses 41466 # DTB read misses +system.cpu.dtb.read_acv 543 # DTB read access violations +system.cpu.dtb.read_accesses 941271 # DTB read accesses +system.cpu.dtb.write_hits 6601987 # DTB write hits +system.cpu.dtb.write_misses 10361 # DTB write misses +system.cpu.dtb.write_acv 401 # DTB write access violations +system.cpu.dtb.write_accesses 337783 # DTB write accesses +system.cpu.dtb.data_hits 16514744 # DTB hits +system.cpu.dtb.data_misses 51827 # DTB misses +system.cpu.dtb.data_acv 944 # DTB access violations +system.cpu.dtb.data_accesses 1279054 # DTB accesses +system.cpu.itb.fetch_hits 1307981 # ITB hits +system.cpu.itb.fetch_misses 36519 # ITB misses +system.cpu.itb.fetch_acv 1105 # ITB acv +system.cpu.itb.fetch_accesses 1344500 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -341,269 +326,269 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 109629781 # number of cpu cycles simulated +system.cpu.numCycles 108624305 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28054548 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70673295 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13838840 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6720605 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13244077 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1985157 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37404215 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 256282 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 293547 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8545648 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 265175 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80570729 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.877158 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.220803 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28031603 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70677368 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13852347 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6714744 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13246931 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1983028 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37386086 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 31591 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 253691 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 294769 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 735 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8549977 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 266732 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80529349 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.877660 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.221433 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67326652 83.56% 83.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 851821 1.06% 84.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1698513 2.11% 86.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 825554 1.02% 87.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2751975 3.42% 91.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 562639 0.70% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 645154 0.80% 92.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1011601 1.26% 93.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4896820 6.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67282418 83.55% 83.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 855134 1.06% 84.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1701405 2.11% 86.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 823363 1.02% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2750758 3.42% 91.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 561116 0.70% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 645464 0.80% 92.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1009589 1.25% 93.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4900102 6.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80570729 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126232 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.644654 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29191187 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37065229 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12109046 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962419 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1242847 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 584292 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42668 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69380603 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129620 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1242847 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30314558 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13623750 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19784463 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11341758 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4263351 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65627824 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6945 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 510530 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1483365 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43820100 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79668795 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79189543 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479252 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38180356 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5639736 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682796 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 239926 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12145356 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10440685 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6902590 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1325482 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 872752 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58180873 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2047058 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56813064 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 111741 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6883646 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3532849 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1386082 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80570729 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.705133 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.366225 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80529349 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.127525 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.650659 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29153342 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37060255 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12110722 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 963448 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1241581 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 585928 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42780 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69380340 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129844 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1241581 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30275533 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13620847 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19786861 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11346001 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4258524 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65625141 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6921 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 508210 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1478954 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43830191 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79653139 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79174156 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 478983 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38170900 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5659283 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1683041 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 240056 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12113189 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10427468 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6890622 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1312006 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 847421 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58167835 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2052016 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56809344 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 88346 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6890448 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3503635 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1391090 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80529349 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.705449 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.366907 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55925631 69.41% 69.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10804122 13.41% 82.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5164072 6.41% 89.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3379310 4.19% 93.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2651147 3.29% 96.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1461283 1.81% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 759145 0.94% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 331157 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 94862 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55889300 69.40% 69.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10803861 13.42% 82.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5162711 6.41% 89.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3375118 4.19% 93.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2651639 3.29% 96.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1461034 1.81% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 755339 0.94% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 331829 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 98518 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80570729 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80529349 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 89963 11.41% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 373446 47.37% 58.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 325006 41.22% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91375 11.51% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 373733 47.09% 58.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 328605 41.40% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38735893 68.18% 68.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61716 0.11% 68.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38736276 68.19% 68.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61707 0.11% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10357569 18.23% 86.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6672257 11.74% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949100 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10345170 18.21% 86.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6680665 11.76% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948997 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56813064 # Type of FU issued -system.cpu.iq.rate 0.518227 # Inst issue rate -system.cpu.iq.fu_busy_cnt 788415 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013877 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 194404430 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66788743 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55573367 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692582 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336629 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327887 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57232794 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361399 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 600057 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56809344 # Type of FU issued +system.cpu.iq.rate 0.522989 # Inst issue rate +system.cpu.iq.fu_busy_cnt 793713 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013972 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 194336981 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66788043 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55575971 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 693114 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336007 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327916 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57233562 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 362209 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 600992 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1348422 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4157 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14125 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 524715 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1337423 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4170 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14100 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 513944 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17951 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 174954 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17964 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 173464 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1242847 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9951157 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 684131 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63754506 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 676985 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10440685 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6902590 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1803123 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512112 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18418 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14125 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 202045 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 411832 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 613877 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56345945 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9995759 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 467118 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1241581 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9950428 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 684284 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63748308 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 674797 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10427468 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6890622 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1807435 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512768 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18119 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14100 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 203235 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412070 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 615305 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56339118 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 9982368 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 470225 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3526575 # number of nop insts executed -system.cpu.iew.exec_refs 16615200 # number of memory reference insts executed -system.cpu.iew.exec_branches 8926807 # Number of branches executed -system.cpu.iew.exec_stores 6619441 # Number of stores executed -system.cpu.iew.exec_rate 0.513966 # Inst execution rate -system.cpu.iew.wb_sent 56016691 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55901254 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27769565 # num instructions producing a value -system.cpu.iew.wb_consumers 37614191 # num instructions consuming a value +system.cpu.iew.exec_nop 3528457 # number of nop insts executed +system.cpu.iew.exec_refs 16609952 # number of memory reference insts executed +system.cpu.iew.exec_branches 8925181 # Number of branches executed +system.cpu.iew.exec_stores 6627584 # Number of stores executed +system.cpu.iew.exec_rate 0.518660 # Inst execution rate +system.cpu.iew.wb_sent 56017641 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55903887 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27773544 # num instructions producing a value +system.cpu.iew.wb_consumers 37603829 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.509909 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738274 # average fanout of values written-back +system.cpu.iew.wb_rate 0.514654 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738583 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7465102 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660976 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 568169 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 79327882 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.708087 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.637784 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7472187 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660926 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 568042 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79287768 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.708292 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.638038 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58561818 73.82% 73.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8602415 10.84% 84.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4601651 5.80% 90.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2532853 3.19% 93.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1516154 1.91% 95.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 607730 0.77% 96.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 522045 0.66% 97.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 534524 0.67% 97.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1848692 2.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58526272 73.82% 73.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8600403 10.85% 84.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4599837 5.80% 90.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2533746 3.20% 93.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1516837 1.91% 95.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 606860 0.77% 96.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 524643 0.66% 97.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 525259 0.66% 97.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1853911 2.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 79327882 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56171016 # Number of instructions committed -system.cpu.commit.committedOps 56171016 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79287768 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56158922 # Number of instructions committed +system.cpu.commit.committedOps 56158922 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15470138 # Number of memory references committed -system.cpu.commit.loads 9092263 # Number of loads committed -system.cpu.commit.membars 226349 # Number of memory barriers committed -system.cpu.commit.branches 8440338 # Number of branches committed +system.cpu.commit.refs 15466723 # Number of memory references committed +system.cpu.commit.loads 9090045 # Number of loads committed +system.cpu.commit.membars 226335 # Number of memory barriers committed +system.cpu.commit.branches 8439344 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52020652 # Number of committed integer instructions. -system.cpu.commit.function_calls 740552 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1848692 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52009184 # Number of committed integer instructions. +system.cpu.commit.function_calls 740395 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1853911 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 140865752 # The number of ROB reads -system.cpu.rob.rob_writes 128516921 # The number of ROB writes -system.cpu.timesIdled 1179002 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29059052 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3598984001 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52980262 # Number of Instructions Simulated -system.cpu.committedOps 52980262 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52980262 # Number of Instructions Simulated -system.cpu.cpi 2.069257 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.069257 # CPI: Total CPI of All Threads -system.cpu.ipc 0.483265 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.483265 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73880365 # number of integer regfile reads -system.cpu.int_regfile_writes 40316413 # number of integer regfile writes -system.cpu.fp_regfile_reads 166011 # number of floating regfile reads -system.cpu.fp_regfile_writes 167446 # number of floating regfile writes -system.cpu.misc_regfile_reads 1987331 # number of misc regfile reads -system.cpu.misc_regfile_writes 938994 # number of misc regfile writes +system.cpu.rob.rob_reads 140815408 # The number of ROB reads +system.cpu.rob.rob_writes 128505533 # The number of ROB writes +system.cpu.timesIdled 1178112 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28094956 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599984053 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52968721 # Number of Instructions Simulated +system.cpu.committedOps 52968721 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52968721 # Number of Instructions Simulated +system.cpu.cpi 2.050725 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.050725 # CPI: Total CPI of All Threads +system.cpu.ipc 0.487632 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.487632 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73881531 # number of integer regfile reads +system.cpu.int_regfile_writes 40312822 # number of integer regfile writes +system.cpu.fp_regfile_reads 166061 # number of floating regfile reads +system.cpu.fp_regfile_writes 167429 # number of floating regfile writes +system.cpu.misc_regfile_reads 1987886 # number of misc regfile reads +system.cpu.misc_regfile_writes 938918 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -635,189 +620,197 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1008798 # number of replacements -system.cpu.icache.tagsinuse 510.238342 # Cycle average of tags in use -system.cpu.icache.total_refs 7480626 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1009306 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.411653 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 20723156000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.238342 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996559 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996559 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7480627 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7480627 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7480627 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7480627 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7480627 # number of overall hits -system.cpu.icache.overall_hits::total 7480627 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1065018 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1065018 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1065018 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1065018 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1065018 # number of overall misses -system.cpu.icache.overall_misses::total 1065018 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14700112992 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14700112992 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14700112992 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14700112992 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14700112992 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14700112992 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8545645 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8545645 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8545645 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8545645 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8545645 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8545645 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124627 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124627 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124627 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124627 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124627 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124627 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13802.689712 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13802.689712 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13802.689712 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13802.689712 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13802.689712 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13802.689712 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5838 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 237 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.758621 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 237 # average number of cycles each access was blocked +system.cpu.icache.replacements 1008795 # number of replacements +system.cpu.icache.tagsinuse 510.288576 # Cycle average of tags in use +system.cpu.icache.total_refs 7484836 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1009303 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.415846 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 20267575000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.288576 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996657 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996657 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7484837 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7484837 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7484837 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7484837 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7484837 # number of overall hits +system.cpu.icache.overall_hits::total 7484837 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1065140 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1065140 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1065140 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1065140 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1065140 # number of overall misses +system.cpu.icache.overall_misses::total 1065140 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14678664495 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14678664495 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14678664495 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14678664495 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14678664495 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14678664495 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8549977 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8549977 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8549977 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8549977 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8549977 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8549977 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124578 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.124578 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.124578 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.124578 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.124578 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.124578 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13780.971980 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13780.971980 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13780.971980 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13780.971980 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13780.971980 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13780.971980 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7122 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1606 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 164 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 43.426829 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 803 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55491 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 55491 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 55491 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 55491 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 55491 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 55491 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009527 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1009527 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1009527 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1009527 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1009527 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1009527 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12048771993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12048771993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12048771993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12048771993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12048771993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12048771993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118134 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118134 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118134 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.118134 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118134 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.118134 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11935.066613 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11935.066613 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11935.066613 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11935.066613 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11935.066613 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11935.066613 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55619 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 55619 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 55619 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 55619 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 55619 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 55619 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009521 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1009521 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1009521 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1009521 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1009521 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1009521 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12035617996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12035617996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12035617996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12035617996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12035617996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12035617996 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118073 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118073 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118073 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.118073 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118073 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.118073 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11922.107609 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11922.107609 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11922.107609 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11922.107609 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11922.107609 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11922.107609 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 338275 # number of replacements -system.cpu.l2cache.tagsinuse 65364.674694 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2545615 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 403441 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.309758 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 4180772752 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 54011.059986 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 5325.208257 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6028.406451 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.824143 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.081256 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.091986 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997386 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 994342 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 827132 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1821474 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 840875 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 840875 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 185593 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 185593 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 994342 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1012725 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2007067 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 994342 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1012725 # number of overall hits -system.cpu.l2cache.overall_hits::total 2007067 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 15068 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 273766 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 288834 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 35 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 35 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 115432 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 115432 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15068 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389198 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404266 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15068 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389198 # number of overall misses -system.cpu.l2cache.overall_misses::total 404266 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1052241000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12408474500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13460715500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 274500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 274500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7669350500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7669350500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1052241000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20077825000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21130066000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1052241000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20077825000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21130066000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1009410 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1100898 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2110308 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 840875 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 840875 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 61 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 61 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 301025 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 301025 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1009410 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1401923 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2411333 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1009410 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1401923 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2411333 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014928 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248675 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.136868 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.573770 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.573770 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383463 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383463 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014928 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.277617 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.167652 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014928 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.277617 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.167652 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69832.824529 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45325.111592 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 46603.639115 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7842.857143 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7842.857143 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66440.419468 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66440.419468 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69832.824529 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51587.688015 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52267.729663 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69832.824529 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51587.688015 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52267.729663 # average overall miss latency +system.cpu.l2cache.replacements 338260 # number of replacements +system.cpu.l2cache.tagsinuse 65365.866515 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2544525 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 403426 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.307291 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 4078120751 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 53972.516540 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 5322.981591 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6070.368385 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.823555 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.081222 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.092626 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.997404 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 994349 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 826677 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1821026 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 840320 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 840320 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 24 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 24 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 185342 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 185342 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 994349 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1012019 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2006368 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 994349 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1012019 # number of overall hits +system.cpu.l2cache.overall_hits::total 2006368 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 15056 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 273775 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 288831 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 39 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 39 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 115395 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 115395 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 15056 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 389170 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404226 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 15056 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 389170 # number of overall misses +system.cpu.l2cache.overall_misses::total 404226 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1039366500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11945940500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12985307000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 290000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 290000 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 23000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 23000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7619154000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7619154000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1039366500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 19565094500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20604461000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1039366500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 19565094500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20604461000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1009405 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1100452 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2109857 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 840320 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 840320 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 63 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 63 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 300737 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 300737 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1009405 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1401189 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2410594 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1009405 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1401189 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2410594 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014916 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248784 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.136896 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.619048 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.619048 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383707 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383707 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014916 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.277743 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.167687 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014916 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.277743 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.167687 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69033.375399 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43634.153959 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 44958.148537 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7435.897436 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7435.897436 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 11500 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 11500 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66026.725595 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66026.725595 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69033.375399 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50273.902151 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 50972.626699 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69033.375399 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50273.902151 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 50972.626699 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -826,72 +819,80 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75909 # number of writebacks -system.cpu.l2cache.writebacks::total 75909 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 75694 # number of writebacks +system.cpu.l2cache.writebacks::total 75694 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15067 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273766 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 288833 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115432 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115432 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15067 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389198 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404265 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15067 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389198 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404265 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 864374583 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9058859411 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9923233994 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 514531 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 514531 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6259293268 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6259293268 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 864374583 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15318152679 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16182527262 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 864374583 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15318152679 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16182527262 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333805500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333805500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882511000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882511000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216316500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216316500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014927 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248675 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136868 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.573770 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.573770 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383463 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383463 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014927 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277617 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.167652 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014927 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277617 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.167652 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57368.725227 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33089.789861 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34356.302756 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14700.885714 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14700.885714 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54224.939947 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54224.939947 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57368.725227 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39358.251273 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40029.503573 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57368.725227 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39358.251273 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40029.503573 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15055 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273775 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288830 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 39 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 39 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115395 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115395 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15055 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389170 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404225 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15055 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389170 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404225 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 851622750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8594985001 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9446607751 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 547534 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 547534 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6209572959 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6209572959 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 851622750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14804557960 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15656180710 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 851622750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14804557960 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15656180710 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333813500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333813500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882743500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882743500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216557000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216557000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014915 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248784 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136896 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.619048 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.619048 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383707 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383707 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014915 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277743 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.167687 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014915 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277743 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.167687 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56567.436068 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31394.338420 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32706.463148 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14039.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14039.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53811.455947 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53811.455947 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56567.436068 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38041.364853 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38731.351871 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56567.436068 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38041.364853 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38731.351871 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -899,161 +900,161 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1401332 # number of replacements -system.cpu.dcache.tagsinuse 511.995159 # Cycle average of tags in use -system.cpu.dcache.total_refs 11818848 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1401844 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.430930 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1400597 # number of replacements +system.cpu.dcache.tagsinuse 511.995158 # Cycle average of tags in use +system.cpu.dcache.total_refs 11804639 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1401109 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.425211 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 21807000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.995159 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.995158 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7212145 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7212145 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4204906 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4204906 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186063 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186063 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215520 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215520 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11417051 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11417051 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11417051 # number of overall hits -system.cpu.dcache.overall_hits::total 11417051 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1802577 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1802577 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1942748 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1942748 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22749 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22749 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3745325 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3745325 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3745325 # number of overall misses -system.cpu.dcache.overall_misses::total 3745325 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 34332308500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 34332308500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 65131487898 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 65131487898 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306015000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 306015000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 99463796398 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 99463796398 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 99463796398 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 99463796398 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9014722 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9014722 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147654 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147654 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208812 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 208812 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215521 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215521 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15162376 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15162376 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15162376 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15162376 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199959 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.199959 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316015 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316015 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108945 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108945 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247014 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247014 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247014 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247014 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19046.236860 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19046.236860 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33525.443289 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33525.443289 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13451.800079 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13451.800079 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26556.786500 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26556.786500 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26556.786500 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26556.786500 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2193487 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 506 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 95928 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.865972 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 72.285714 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 7199170 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7199170 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4203355 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4203355 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186385 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186385 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215505 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215505 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11402525 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11402525 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11402525 # number of overall hits +system.cpu.dcache.overall_hits::total 11402525 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1802469 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1802469 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1943114 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1943114 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22653 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22653 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3745583 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3745583 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3745583 # number of overall misses +system.cpu.dcache.overall_misses::total 3745583 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33840497500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33840497500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64776324525 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64776324525 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306197000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 306197000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 76500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 76500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 98616822025 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 98616822025 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 98616822025 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 98616822025 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9001639 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9001639 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6146469 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6146469 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209038 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209038 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215509 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215509 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15148108 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15148108 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15148108 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15148108 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200238 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.200238 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316135 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316135 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108368 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108368 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000019 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000019 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.247264 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247264 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247264 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247264 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18774.524000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18774.524000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33336.348009 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33336.348009 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13516.841037 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13516.841037 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19125 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19125 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26328.831059 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26328.831059 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26328.831059 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26328.831059 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2181836 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 774 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 95774 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 6 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.781089 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 129 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840875 # number of writebacks -system.cpu.dcache.writebacks::total 840875 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 718560 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 718560 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642321 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1642321 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5210 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5210 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2360881 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2360881 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2360881 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2360881 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084017 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1084017 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300427 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300427 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17539 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17539 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384444 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384444 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384444 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384444 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21793042000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21793042000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9888893772 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9888893772 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199306000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199306000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31681935772 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31681935772 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31681935772 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31681935772 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423882500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423882500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997678998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997678998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421561498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421561498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120250 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120250 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048869 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048869 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083994 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083994 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091308 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091308 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091308 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091308 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20103.967004 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20103.967004 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32916.128617 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32916.128617 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11363.589714 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11363.589714 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22884.230617 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22884.230617 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22884.230617 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22884.230617 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 840320 # number of writebacks +system.cpu.dcache.writebacks::total 840320 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 718906 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 718906 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642971 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1642971 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5109 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5109 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2361877 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2361877 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2361877 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2361877 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083563 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083563 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300143 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300143 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17544 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17544 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1383706 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1383706 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1383706 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1383706 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21325000500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21325000500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9835893766 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9835893766 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200292500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200292500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 68500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 68500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31160894266 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31160894266 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31160894266 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31160894266 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423890500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423890500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997911498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997911498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421801998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421801998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120374 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120374 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048832 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048832 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083927 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083927 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000019 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091345 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091345 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091345 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091345 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19680.443592 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19680.443592 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32770.691857 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32770.691857 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11416.581167 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11416.581167 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17125 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17125 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22519.880861 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22519.880861 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22519.880861 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22519.880861 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1062,28 +1063,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211025 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74671 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 210999 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105575 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182256 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73304 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105559 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182230 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73304 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817868211500 98.03% 98.03% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 63824000 0.00% 98.04% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 559692500 0.03% 98.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 35817544000 1.93% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1854309272000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818335798500 98.06% 98.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 63864000 0.00% 98.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 549180000 0.03% 98.09% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 35357724000 1.91% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1854306566500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694331 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815435 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694342 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815442 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1122,7 +1123,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175141 91.23% 93.44% # number of callpals executed +system.cpu.kern.callpal::swpipl 175115 91.23% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1131,7 +1132,7 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191985 # number of callpals executed +system.cpu.kern.callpal::total 191959 # number of callpals executed system.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches system.cpu.kern.mode_switch::user 1740 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches @@ -1142,9 +1143,9 @@ system.cpu.kern.mode_switch_good::kernel 0.326552 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29467227000 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2708568500 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1822133468500 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 29457551500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2704315000 0.15% 1.73% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1822144692000 98.27% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 014619ced..1f0f241e7 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,154 +1,141 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.841686 # Number of seconds simulated -sim_ticks 1841685645500 # Number of ticks simulated -final_tick 1841685645500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1841685557500 # Number of ticks simulated +final_tick 1841685557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 300759 # Simulator instruction rate (inst/s) -host_op_rate 300759 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7981184825 # Simulator tick rate (ticks/s) -host_mem_usage 313952 # Number of bytes of host memory used -host_seconds 230.75 # Real time elapsed on the host -sim_insts 69401254 # Number of instructions simulated -sim_ops 69401254 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 474368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 19389440 # Number of bytes read from this memory +host_inst_rate 244491 # Simulator instruction rate (inst/s) +host_op_rate 244491 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6478446279 # Simulator tick rate (ticks/s) +host_mem_usage 315916 # Number of bytes of host memory used +host_seconds 284.28 # Real time elapsed on the host +sim_insts 69503534 # Number of instructions simulated +sim_ops 69503534 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 474240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 19348096 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 150272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2812736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 293952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2665600 # Number of bytes read from this memory -system.physmem.bytes_read::total 28438656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 474368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 150272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 293952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 918592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7476160 # Number of bytes written to this memory -system.physmem.bytes_written::total 7476160 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7412 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 302960 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 150080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2814720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 294912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2705088 # Number of bytes read from this memory +system.physmem.bytes_read::total 28439424 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 474240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 150080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 294912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 919232 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7476992 # Number of bytes written to this memory +system.physmem.bytes_written::total 7476992 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7410 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 302314 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2348 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 43949 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4593 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 41650 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444354 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116815 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116815 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 257573 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10528094 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 2345 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 43980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4608 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 42267 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444366 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116828 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116828 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 257503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10505646 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 1440142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 81595 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1527262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 159610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1447370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15441645 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 257573 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 81595 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 159610 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498778 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4059412 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4059412 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4059412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 257573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10528094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 81491 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1528339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 160132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1468811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15442063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 257503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 81491 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 160132 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 499125 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4059864 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4059864 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4059864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 257503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10505646 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1440142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 81595 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1527262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 159610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1447370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19501057 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 109303 # Total number of read requests seen -system.physmem.writeReqs 45531 # Total number of write requests seen -system.physmem.cpureqs 156037 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 6995392 # Total number of bytes read from memory -system.physmem.bytesWritten 2913984 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 6995392 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2913984 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.inst 81491 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1528339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 160132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1468811 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19501926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 109963 # Total number of read requests seen +system.physmem.writeReqs 45515 # Total number of write requests seen +system.physmem.cpureqs 155620 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 7037632 # Total number of bytes read from memory +system.physmem.bytesWritten 2912960 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 7037632 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2912960 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 6 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 41 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6941 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6714 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6576 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6492 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 6845 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 6834 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 6769 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 6799 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7016 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6828 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7161 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6927 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 6799 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6925 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6890 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6781 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2987 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2793 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2679 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 2608 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2843 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2755 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2723 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2826 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 3041 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2937 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 3162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2868 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 2817 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2876 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2850 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2766 # Track writes on a per bank basis +system.physmem.neitherReadNorWrite 40 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 6991 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 6778 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 6646 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 6540 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 6897 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 6863 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 6800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 6833 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7049 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 6858 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 7191 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6954 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 6826 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 6963 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6923 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6845 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 2979 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2790 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2684 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2595 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2850 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 2752 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2726 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2828 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3044 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2935 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 3156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2867 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 2811 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 2879 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2851 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 2768 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1002 # Number of times wr buffer was full causing retry -system.physmem.totGap 1840673558000 # Total gap between requests +system.physmem.numWrRetry 102 # Number of times wr buffer was full causing retry +system.physmem.totGap 1840673470000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 109303 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 46533 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 41 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 80133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1099 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1079 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1052 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 596 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see +system.physmem.readPktSize::6 109963 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 45515 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 80954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5332 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1081 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 559 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 664 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 319 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -161,240 +148,242 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 1275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1974 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1965 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 1964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2420387927 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4417690427 # Sum of mem lat for all requests -system.physmem.totBusLat 546485000 # Total cycles spent in databus access -system.physmem.totBankLat 1450817500 # Total cycles spent in bank access -system.physmem.avgQLat 22145.05 # Average queueing delay per request -system.physmem.avgBankLat 13274.08 # Average bank access latency per request +system.physmem.wrQLenPdf::18 1963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see +system.physmem.totQLat 2376401250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4386835000 # Sum of mem lat for all requests +system.physmem.totBusLat 549785000 # Total cycles spent in databus access +system.physmem.totBankLat 1460648750 # Total cycles spent in bank access +system.physmem.avgQLat 21612.10 # Average queueing delay per request +system.physmem.avgBankLat 13283.82 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 40419.14 # Average memory access latency -system.physmem.avgRdBW 3.80 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 39895.91 # Average memory access latency +system.physmem.avgRdBW 3.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.80 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.82 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.58 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.16 # Average write queue length over time -system.physmem.readRowHits 99113 # Number of row buffer hits during reads -system.physmem.writeRowHits 34331 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.40 # Row buffer hit rate for writes -system.physmem.avgGap 11888044.99 # Average gap between requests -system.l2c.replacements 337419 # number of replacements -system.l2c.tagsinuse 65421.239766 # Cycle average of tags in use -system.l2c.total_refs 2475144 # Total number of references to valid blocks. -system.l2c.sampled_refs 402581 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.148189 # Average number of references to valid blocks. +system.physmem.readRowHits 99744 # Number of row buffer hits during reads +system.physmem.writeRowHits 34338 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.44 # Row buffer hit rate for writes +system.physmem.avgGap 11838803.37 # Average gap between requests +system.l2c.replacements 337431 # number of replacements +system.l2c.tagsinuse 65421.769821 # Cycle average of tags in use +system.l2c.total_refs 2476371 # Total number of references to valid blocks. +system.l2c.sampled_refs 402593 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.151053 # Average number of references to valid blocks. system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 54789.025804 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2312.416873 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2671.189079 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 589.820867 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 668.130775 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 2247.184130 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 2143.472240 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.836014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.035285 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.040759 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.009000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.010195 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.034289 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.032707 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.998249 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 513915 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 491176 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 126581 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 82893 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 298492 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 243008 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1756065 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 836144 # number of Writeback hits -system.l2c.Writeback_hits::total 836144 # number of Writeback hits +system.l2c.occ_blocks::writebacks 54783.846469 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 2311.752265 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2671.563738 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 585.881665 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 667.174389 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 2255.430098 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 2146.121197 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.835935 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.035275 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.040765 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.008940 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.010180 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.034415 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.032747 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.998257 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 514621 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 491109 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 126725 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 83687 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 298608 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 242406 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1757156 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 836280 # number of Writeback hits +system.l2c.Writeback_hits::total 836280 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 4 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 8 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 92052 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 27044 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 67842 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186938 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 513915 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 583228 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 126581 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 109937 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 298492 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 310850 # number of demand (read+write) hits -system.l2c.demand_hits::total 1943003 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 513915 # number of overall hits -system.l2c.overall_hits::cpu0.data 583228 # number of overall hits -system.l2c.overall_hits::cpu1.inst 126581 # number of overall hits -system.l2c.overall_hits::cpu1.data 109937 # number of overall hits -system.l2c.overall_hits::cpu2.inst 298492 # number of overall hits -system.l2c.overall_hits::cpu2.data 310850 # number of overall hits -system.l2c.overall_hits::total 1943003 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 7412 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 226081 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2348 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 22980 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 4593 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 24148 # number of ReadReq misses -system.l2c.ReadReq_misses::total 287562 # number of ReadReq misses +system.l2c.SCUpgradeReq_hits::cpu2.data 1 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 92033 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 27042 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 67840 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 186915 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 514621 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 583142 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 126725 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 110729 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 298608 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 310246 # number of demand (read+write) hits +system.l2c.demand_hits::total 1944071 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 514621 # number of overall hits +system.l2c.overall_hits::cpu0.data 583142 # number of overall hits +system.l2c.overall_hits::cpu1.inst 126725 # number of overall hits +system.l2c.overall_hits::cpu1.data 110729 # number of overall hits +system.l2c.overall_hits::cpu2.inst 298608 # number of overall hits +system.l2c.overall_hits::cpu2.data 310246 # number of overall hits +system.l2c.overall_hits::total 1944071 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 7410 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 225248 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2345 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 23010 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 4608 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 24959 # number of ReadReq misses +system.l2c.ReadReq_misses::total 287580 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 11 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 19 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 77155 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 21018 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 17603 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 115776 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 7412 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 303236 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2348 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 43998 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 4593 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 41751 # number of demand (read+write) misses -system.l2c.demand_misses::total 403338 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 7412 # number of overall misses -system.l2c.overall_misses::cpu0.data 303236 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2348 # number of overall misses -system.l2c.overall_misses::cpu1.data 43998 # number of overall misses -system.l2c.overall_misses::cpu2.inst 4593 # number of overall misses -system.l2c.overall_misses::cpu2.data 41751 # number of overall misses -system.l2c.overall_misses::total 403338 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.inst 154067000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 1052058500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 311896500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 1117922000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2635944000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_misses::cpu2.data 10 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 18 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 77341 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 21020 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 17409 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 115770 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 7410 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 302589 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2345 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 44030 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 4608 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 42368 # number of demand (read+write) misses +system.l2c.demand_misses::total 403350 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 7410 # number of overall misses +system.l2c.overall_misses::cpu0.data 302589 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2345 # number of overall misses +system.l2c.overall_misses::cpu1.data 44030 # number of overall misses +system.l2c.overall_misses::cpu2.inst 4608 # number of overall misses +system.l2c.overall_misses::cpu2.data 42368 # number of overall misses +system.l2c.overall_misses::total 403350 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.inst 151883500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 1053888000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 310106500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 1117642500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2633520500 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu2.data 295000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 295000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 978614500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1291616000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2270230500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.inst 154067000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2030673000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 311896500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 2409538000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 4906174500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.inst 154067000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2030673000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 311896500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 2409538000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 4906174500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 521327 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 717257 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 128929 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 105873 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 303085 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 267156 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2043627 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 836144 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 836144 # number of Writeback accesses(hits+misses) +system.l2c.ReadExReq_miss_latency::cpu1.data 979969000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1286505500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2266474500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 151883500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2033857000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 310106500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 2404148000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 4899995000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 151883500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2033857000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 310106500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 2404148000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 4899995000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 522031 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 716357 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 129070 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 106697 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 303216 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 267365 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2044736 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 836280 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 836280 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 27 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 169207 # number of ReadExReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 14 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 26 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu2.data 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 169374 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 48062 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 85445 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 302714 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 521327 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 886464 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 128929 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 153935 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 303085 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 352601 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2346341 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 521327 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 886464 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 128929 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 153935 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 303085 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 352601 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2346341 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014218 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.315202 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.018212 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.217053 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.015154 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.090389 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.140712 # miss rate for ReadReq accesses +system.l2c.ReadExReq_accesses::cpu2.data 85249 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 302685 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 522031 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 885731 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 129070 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 154759 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 303216 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 352614 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2347421 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 522031 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 885731 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 129070 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 154759 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 303216 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 352614 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2347421 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014195 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.314435 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.018168 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.215657 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.015197 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.093352 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.140644 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.733333 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.703704 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.455980 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.437310 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.206016 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.382460 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014218 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.342074 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.018212 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.285822 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.015154 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.118409 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.171901 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014218 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.342074 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.018212 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.285822 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.015154 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.118409 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.171901 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 65616.269165 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 45781.483899 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 67906.923579 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 46294.599967 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 9166.524089 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 26818.181818 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 15526.315789 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 46560.781235 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 73374.765665 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 19608.817890 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 65616.269165 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 46153.756989 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 67906.923579 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 57712.102704 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 12163.928269 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 65616.269165 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 46153.756989 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 67906.923579 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 57712.102704 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 12163.928269 # average overall miss latency +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.714286 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.692308 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.456629 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.437352 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.204214 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.382477 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014195 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.341626 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.018168 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.284507 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.015197 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.120154 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.171827 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014195 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.341626 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.018168 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.284507 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.015197 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.120154 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.171827 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 64769.083156 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 45801.303781 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 67297.417535 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 44779.137786 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 9157.523124 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 29500 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 16388.888889 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 46620.789724 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 73898.874146 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 19577.390516 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 64769.083156 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 46192.527822 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 67297.417535 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 56744.429758 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 12148.245940 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 64769.083156 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 46192.527822 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 67297.417535 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 56744.429758 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 12148.245940 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -403,97 +392,97 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 75303 # number of writebacks -system.l2c.writebacks::total 75303 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu1.inst 2348 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 22980 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 4593 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 24148 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 54069 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 11 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 21018 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 17603 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 38621 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2348 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 43998 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 4593 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 41751 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 92690 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2348 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 43998 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 4593 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 41751 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 92690 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 124527350 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 769462495 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 254598394 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 825079853 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1973668092 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 271507 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 271507 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 718879972 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1076725373 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1795605345 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 124527350 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1488342467 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 254598394 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 1901805226 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 3769273437 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 124527350 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1488342467 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 254598394 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 1901805226 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 3769273437 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 269404000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 320097000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 589501000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 337106000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 394521000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 731627000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 606510000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 714618000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1321128000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018212 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.217053 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015154 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090389 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.026457 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.733333 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.407407 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.437310 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.206016 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.127582 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018212 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.285822 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015154 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.118409 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.039504 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018212 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.285822 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015154 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.118409 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.039504 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 53035.498296 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 33484.007615 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 55431.829741 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 34167.626843 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 36502.766687 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 24682.454545 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 24682.454545 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34203.062708 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61167.151792 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 46492.979079 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 53035.498296 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33827.502773 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 55431.829741 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 45551.129937 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40665.373147 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 53035.498296 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33827.502773 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 55431.829741 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 45551.129937 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40665.373147 # average overall mshr miss latency +system.l2c.writebacks::writebacks 75316 # number of writebacks +system.l2c.writebacks::total 75316 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu1.inst 2345 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 23010 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 4608 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 24959 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 54922 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 10 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 21020 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 17409 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 38429 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2345 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 44030 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 4608 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 42368 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 93351 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2345 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 44030 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 4608 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 42368 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 93351 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122370842 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 770894982 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 252658268 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 814852254 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1960776346 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 261506 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 261506 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 720185758 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1074026983 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1794212741 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 122370842 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1491080740 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 252658268 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1888879237 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 3754989087 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 122370842 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1491080740 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 252658268 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1888879237 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 3754989087 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 269544000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 323045500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 592589500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 337247500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 397454500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 734702000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 606791500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 720500000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1327291500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018168 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.215657 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015197 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.093352 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.026860 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.714286 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.437352 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.204214 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.126960 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018168 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.284507 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015197 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.120154 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.039767 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018168 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.284507 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015197 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.120154 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.039767 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 52183.727932 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 33502.606780 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 54830.353299 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 32647.632277 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 35701.109683 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 26150.600000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 26150.600000 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34261.929496 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61693.778103 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 46689.030186 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 52183.727932 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33865.108789 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 54830.353299 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 44582.685919 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40224.412026 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52183.727932 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33865.108789 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 54830.353299 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 44582.685919 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40224.412026 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -505,12 +494,12 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.255467 # Cycle average of tags in use +system.iocache.tagsinuse 1.255479 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1693876367000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.255467 # Average occupied blocks per requestor +system.iocache.warmup_cycle 1693875860000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.255479 # Average occupied blocks per requestor system.iocache.occ_percent::tsunami.ide 0.078467 # Average percentage of cache occupancy system.iocache.occ_percent::total 0.078467 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses @@ -521,14 +510,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 10497998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 10497998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 4320435904 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 4320435904 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4330933902 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4330933902 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4330933902 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4330933902 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9177998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9177998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 4305588904 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 4305588904 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4314766902 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4314766902 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4314766902 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4314766902 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -545,19 +534,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 60682.069364 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 60682.069364 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 103976.605314 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 103976.605314 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 103797.097711 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 103797.097711 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 103797.097711 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 103797.097711 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 116360 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53052.011561 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 53052.011561 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 103619.293993 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 103619.293993 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 103409.632163 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 103409.632163 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 103409.632163 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 103409.632163 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 116041 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11123 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11151 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.461207 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.406331 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -571,14 +560,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 16837 system.iocache.demand_mshr_misses::total 16837 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 16837 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 16837 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6909249 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 6909249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3447972406 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3447972406 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3454881655 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3454881655 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3454881655 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3454881655 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5589249 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5589249 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3433126461 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3433126461 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3438715710 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3438715710 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3438715710 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3438715710 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.403543 # mshr miss rate for WriteReq accesses @@ -587,14 +576,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 0.403523 system.iocache.demand_mshr_miss_rate::total 0.403523 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.403523 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 100134.043478 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 100134.043478 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 205628.125358 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 205628.125358 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 205195.798242 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 205195.798242 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 205195.798242 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 205195.798242 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81003.608696 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 81003.608696 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204742.751729 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204742.751729 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204235.654214 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 204235.654214 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204235.654214 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 204235.654214 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -612,22 +601,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4870222 # DTB read hits -system.cpu0.dtb.read_misses 6004 # DTB read misses -system.cpu0.dtb.read_acv 119 # DTB read access violations -system.cpu0.dtb.read_accesses 427226 # DTB read accesses -system.cpu0.dtb.write_hits 3495920 # DTB write hits -system.cpu0.dtb.write_misses 662 # DTB write misses +system.cpu0.dtb.read_hits 4874109 # DTB read hits +system.cpu0.dtb.read_misses 5989 # DTB read misses +system.cpu0.dtb.read_acv 118 # DTB read access violations +system.cpu0.dtb.read_accesses 427176 # DTB read accesses +system.cpu0.dtb.write_hits 3500725 # DTB write hits +system.cpu0.dtb.write_misses 661 # DTB write misses system.cpu0.dtb.write_acv 82 # DTB write access violations -system.cpu0.dtb.write_accesses 162893 # DTB write accesses -system.cpu0.dtb.data_hits 8366142 # DTB hits -system.cpu0.dtb.data_misses 6666 # DTB misses -system.cpu0.dtb.data_acv 201 # DTB access violations -system.cpu0.dtb.data_accesses 590119 # DTB accesses -system.cpu0.itb.fetch_hits 2742252 # ITB hits -system.cpu0.itb.fetch_misses 2999 # ITB misses -system.cpu0.itb.fetch_acv 100 # ITB acv -system.cpu0.itb.fetch_accesses 2745251 # ITB accesses +system.cpu0.dtb.write_accesses 162885 # DTB write accesses +system.cpu0.dtb.data_hits 8374834 # DTB hits +system.cpu0.dtb.data_misses 6650 # DTB misses +system.cpu0.dtb.data_acv 200 # DTB access violations +system.cpu0.dtb.data_accesses 590061 # DTB accesses +system.cpu0.itb.fetch_hits 2743092 # ITB hits +system.cpu0.itb.fetch_misses 2995 # ITB misses +system.cpu0.itb.fetch_acv 98 # ITB acv +system.cpu0.itb.fetch_accesses 2746087 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -640,51 +629,51 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928524557 # number of cpu cycles simulated +system.cpu0.numCycles 928539725 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32346409 # Number of instructions committed -system.cpu0.committedOps 32346409 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 30227600 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 167714 # Number of float alu accesses -system.cpu0.num_func_calls 807221 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4255838 # number of instructions that are conditional controls -system.cpu0.num_int_insts 30227600 # number of integer instructions -system.cpu0.num_fp_insts 167714 # number of float instructions -system.cpu0.num_int_register_reads 42120330 # number of times the integer registers were read -system.cpu0.num_int_register_writes 22107857 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 86620 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 88185 # number of times the floating registers were written -system.cpu0.num_mem_refs 8395829 # number of memory refs -system.cpu0.num_load_insts 4891258 # Number of load instructions -system.cpu0.num_store_insts 3504571 # Number of store instructions -system.cpu0.num_idle_cycles 213109834303.356140 # Number of idle cycles -system.cpu0.num_busy_cycles -212181309746.356140 # Number of busy cycles -system.cpu0.not_idle_fraction -228.514484 # Percentage of non-idle cycles -system.cpu0.idle_fraction 229.514484 # Percentage of idle cycles +system.cpu0.committedInsts 32518253 # Number of instructions committed +system.cpu0.committedOps 32518253 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 30397519 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 168035 # Number of float alu accesses +system.cpu0.num_func_calls 808172 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4307008 # number of instructions that are conditional controls +system.cpu0.num_int_insts 30397519 # number of integer instructions +system.cpu0.num_fp_insts 168035 # number of float instructions +system.cpu0.num_int_register_reads 42396693 # number of times the integer registers were read +system.cpu0.num_int_register_writes 22221610 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 86774 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 88345 # number of times the floating registers were written +system.cpu0.num_mem_refs 8404498 # number of memory refs +system.cpu0.num_load_insts 4895120 # Number of load instructions +system.cpu0.num_store_insts 3509378 # Number of store instructions +system.cpu0.num_idle_cycles 214025441196.436279 # Number of idle cycles +system.cpu0.num_busy_cycles -213096901471.436279 # Number of busy cycles +system.cpu0.not_idle_fraction -229.496806 # Percentage of non-idle cycles +system.cpu0.idle_fraction 230.496806 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211363 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74796 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6423 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211357 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105684 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182561 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73429 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 105682 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182557 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73429 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148939 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818585888500 98.75% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39023500 0.00% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 363355500 0.02% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22696621500 1.23% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841684889000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1818586321500 98.75% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38755000 0.00% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 363405500 0.02% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22696319000 1.23% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841684801000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694798 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815831 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694792 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815827 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -720,10 +709,10 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175304 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175300 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -732,21 +721,21 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192218 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu0.kern.callpal::total 192213 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches system.cpu0.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1908 -system.cpu0.kern.mode_good::user 1738 +system.cpu0.kern.mode_good::kernel 1909 +system.cpu0.kern.mode_good::user 1739 system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322134 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.322357 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29741940500 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2557110500 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809385834500 98.25% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4178 # number of times the context was actually changed +system.cpu0.kern.mode_switch_good::total 0.391349 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29734416500 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2561211500 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809389169500 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -778,356 +767,372 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 952688 # number of replacements -system.cpu0.icache.tagsinuse 511.197182 # Cycle average of tags in use -system.cpu0.icache.total_refs 41854962 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 953199 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 43.909994 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 10248069000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 255.807414 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 79.618511 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 175.771257 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.499624 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.155505 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.343303 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998432 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 31831928 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7734855 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2288179 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 41854962 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31831928 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7734855 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2288179 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 41854962 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31831928 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7734855 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2288179 # number of overall hits -system.cpu0.icache.overall_hits::total 41854962 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 521348 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 128929 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 320072 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 970349 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 521348 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 128929 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 320072 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 970349 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 521348 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 128929 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 320072 # number of overall misses -system.cpu0.icache.overall_misses::total 970349 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1813964500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4473861486 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6287825986 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1813964500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4473861486 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6287825986 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1813964500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4473861486 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6287825986 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32353276 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7863784 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2608251 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 42825311 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32353276 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7863784 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2608251 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 42825311 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32353276 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7863784 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2608251 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 42825311 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016114 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016395 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122715 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.022658 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016114 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016395 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122715 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.022658 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016114 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016395 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122715 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.022658 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14069.483980 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13977.672168 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6479.963380 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14069.483980 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13977.672168 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6479.963380 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14069.483980 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13977.672168 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6479.963380 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5140 # number of cycles access was blocked +system.cpu0.icache.replacements 953667 # number of replacements +system.cpu0.icache.tagsinuse 511.197543 # Cycle average of tags in use +system.cpu0.icache.total_refs 42031546 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 954178 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 44.050005 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 10246755000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 255.638706 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 78.351576 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 177.207261 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.499294 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.153030 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.346108 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998433 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 32003051 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7743805 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2284690 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 42031546 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 32003051 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7743805 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2284690 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 42031546 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 32003051 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7743805 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2284690 # number of overall hits +system.cpu0.icache.overall_hits::total 42031546 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 522052 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 129070 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 320206 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 971328 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 522052 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 129070 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 320206 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 971328 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 522052 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 129070 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 320206 # number of overall misses +system.cpu0.icache.overall_misses::total 971328 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1813664500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4475771482 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6289435982 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1813664500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4475771482 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6289435982 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1813664500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4475771482 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6289435982 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32525103 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 7872875 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 2604896 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 43002874 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 32525103 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 7872875 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 2604896 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 43002874 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32525103 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7872875 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2604896 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 43002874 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016051 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016394 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122925 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.022588 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016051 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016394 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122925 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.022588 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016051 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016394 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122925 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.022588 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14051.789727 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13977.787680 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6475.089755 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14051.789727 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13977.787680 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6475.089755 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14051.789727 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13977.787680 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6475.089755 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4631 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 170 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 184 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.235294 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.168478 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16975 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 16975 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 16975 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 16975 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 16975 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 16975 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 128929 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 303097 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 432026 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 128929 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 303097 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 432026 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 128929 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 303097 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 432026 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1556106500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3684207988 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5240314488 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1556106500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3684207988 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5240314488 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1556106500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3684207988 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5240314488 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016395 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116207 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010088 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016395 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116207 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010088 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016395 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116207 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010088 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12069.483980 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12155.210998 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12129.627587 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12069.483980 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12155.210998 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12129.627587 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12069.483980 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12155.210998 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12129.627587 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16976 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16976 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16976 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16976 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16976 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16976 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 129070 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 303230 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 432300 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 129070 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 303230 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 432300 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 129070 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 303230 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 432300 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1555524500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3682492984 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5238017484 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1555524500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3682492984 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5238017484 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1555524500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3682492984 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5238017484 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016394 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116408 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010053 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016394 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116408 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010053 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016394 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116408 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010053 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12051.789727 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12144.223804 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12116.626149 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12051.789727 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12144.223804 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12116.626149 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12051.789727 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12144.223804 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12116.626149 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1392453 # number of replacements +system.cpu0.dcache.replacements 1392556 # number of replacements system.cpu0.dcache.tagsinuse 511.997817 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13322507 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1392965 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.564136 # Average number of references to valid blocks. +system.cpu0.dcache.total_refs 13323345 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1393068 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.564031 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 248.356869 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 87.947367 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu2.data 175.693580 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.485072 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.171772 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu2.data 0.343152 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 246.086905 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 89.137504 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu2.data 176.773408 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.480638 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.174097 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu2.data 0.345261 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 4047369 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1097591 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2422191 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7567151 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3200230 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 858461 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1312963 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5371654 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116449 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19275 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 48623 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184347 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 125392 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21336 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 52561 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199289 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7247599 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1956052 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3735154 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12938805 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7247599 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1956052 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3735154 # number of overall hits -system.cpu0.dcache.overall_hits::total 12938805 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 707756 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 103680 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 547661 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1359097 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 169218 # number of WriteReq misses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4052041 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1098209 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2416271 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7566521 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3204724 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 859151 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1309317 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5373192 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116570 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19297 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 48424 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184291 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 125555 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21359 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 52366 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199280 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7256765 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1957360 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3725588 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12939713 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7256765 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1957360 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3725588 # number of overall hits +system.cpu0.dcache.overall_hits::total 12939713 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 706812 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 104504 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 547702 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1359018 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 169385 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::cpu1.data 48063 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 563002 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 780283 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9501 # number of LoadLockedReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 561193 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 778641 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9545 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2193 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7002 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18696 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 876974 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 151743 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1110663 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2139380 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 876974 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 151743 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1110663 # number of overall misses -system.cpu0.dcache.overall_misses::total 2139380 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2172880000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9444239000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11617119000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1393921500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 14767149219 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 16161070719 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28928500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 105213000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 134141500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 3566801500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 24211388219 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 27778189719 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 3566801500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 24211388219 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 27778189719 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4755125 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1201271 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 2969852 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8926248 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3369448 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 906524 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1875965 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6151937 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125950 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21468 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 55625 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203043 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125392 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21336 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 52561 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199289 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8124573 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2107795 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 4845817 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15078185 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8124573 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2107795 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 4845817 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15078185 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.148841 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.086309 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.184407 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.152258 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050221 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.053019 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.300113 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.126835 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075435 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.102152 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.125879 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092079 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.107941 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.071991 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.229200 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.141886 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.107941 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.071991 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.229200 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.141886 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 20957.561728 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17244.680560 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8547.674669 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29001.966169 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 26229.301528 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20711.806766 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13191.290470 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15026.135390 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7174.876979 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23505.542266 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 21799.040950 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 12984.224270 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23505.542266 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21799.040950 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12984.224270 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 420237 # number of cycles access was blocked +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7060 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 18798 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 1 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 876197 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 152567 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1108895 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2137659 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 876197 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 152567 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1108895 # number of overall misses +system.cpu0.dcache.overall_misses::total 2137659 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2184733000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9442098000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11626831000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1395266000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 14749790240 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 16145056240 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 29363000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 105564500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 134927500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 13000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 3579999000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 24191888240 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 27771887240 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 3579999000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 24191888240 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 27771887240 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 4758853 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1202713 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 2963973 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8925539 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3374109 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 907214 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 1870510 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6151833 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126115 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21490 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 55484 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 203089 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125555 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21359 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 52367 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 8132962 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 2109927 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 4834483 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 15077372 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8132962 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 2109927 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 4834483 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 15077372 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.148526 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.086890 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.184786 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.152262 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050201 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.052979 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.300021 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.126571 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075685 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.102047 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.127244 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092560 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000019 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.107734 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.072309 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.229372 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.141779 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.107734 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.072309 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.229372 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.141779 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 20905.735666 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17239.480593 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 8555.317884 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29029.939871 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 26282.919138 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20734.916656 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13389.420885 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14952.478754 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7177.758272 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23465.094024 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 21816.211851 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 12991.729382 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23465.094024 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21816.211851 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12991.729382 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 421766 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 580 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 16818 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 16882 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 24.987335 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 24.983177 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 82.857143 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 836144 # number of writebacks -system.cpu0.dcache.writebacks::total 836144 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 285747 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 285747 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 477794 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 477794 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1510 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1510 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 763541 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 763541 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 763541 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 763541 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 103680 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 261914 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 365594 # number of ReadReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 836280 # number of writebacks +system.cpu0.dcache.writebacks::total 836280 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 285653 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 285653 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 476174 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 476174 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1502 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1502 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 761827 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 761827 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 761827 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 761827 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 104504 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 262049 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 366553 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 48063 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 85208 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 133271 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 85019 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 133082 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2193 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5492 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7685 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 151743 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 347122 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 498865 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 151743 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 347122 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 498865 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1965520000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4314579500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6280099500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1297795500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2151055620 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3448851120 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24542500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69880000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94422500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3263315500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6465635120 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9728950620 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3263315500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6465635120 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9728950620 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287578500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342020000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 629598500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 357171000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 418642000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 775813000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 644749500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 760662000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1405411500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086309 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088191 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040957 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053019 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045421 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021663 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.102152 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.098733 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037849 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.071991 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071633 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033085 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.071991 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071633 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033085 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18957.561728 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16473.267943 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17177.796955 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27001.966169 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25244.761290 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25878.481590 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11191.290470 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12723.962127 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12286.597267 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21505.542266 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18626.405471 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19502.171169 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21505.542266 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18626.405471 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19502.171169 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5558 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7751 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 1 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 152567 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 347068 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 499635 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 152567 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 347068 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 499635 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1975725000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4306208500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6281933500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1299140000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2144349624 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3443489624 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24977000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 70824000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95801000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 11000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3274865000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6450558124 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9725423124 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3274865000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6450558124 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9725423124 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287731500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 345150500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 632882000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 357324500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 421745500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 779070000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 645056000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 766896000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1411952000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086890 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088411 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041068 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.052979 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045452 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021633 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.102047 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.100173 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.038166 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072309 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071790 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033138 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072309 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071790 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033138 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18905.735666 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16432.836989 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17137.858645 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27029.939871 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25222.004775 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25874.946454 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11389.420885 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12742.713206 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12359.824539 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21465.094024 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18585.862494 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19465.055739 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21465.094024 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18585.862494 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19465.055739 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1142,22 +1147,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1220324 # DTB read hits -system.cpu1.dtb.read_misses 1556 # DTB read misses -system.cpu1.dtb.read_acv 46 # DTB read access violations -system.cpu1.dtb.read_accesses 144016 # DTB read accesses -system.cpu1.dtb.write_hits 928239 # DTB write hits -system.cpu1.dtb.write_misses 207 # DTB write misses +system.cpu1.dtb.read_hits 1221793 # DTB read hits +system.cpu1.dtb.read_misses 1550 # DTB read misses +system.cpu1.dtb.read_acv 45 # DTB read access violations +system.cpu1.dtb.read_accesses 143987 # DTB read accesses +system.cpu1.dtb.write_hits 928954 # DTB write hits +system.cpu1.dtb.write_misses 206 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations -system.cpu1.dtb.write_accesses 60107 # DTB write accesses -system.cpu1.dtb.data_hits 2148563 # DTB hits -system.cpu1.dtb.data_misses 1763 # DTB misses -system.cpu1.dtb.data_acv 70 # DTB access violations -system.cpu1.dtb.data_accesses 204123 # DTB accesses -system.cpu1.itb.fetch_hits 875123 # ITB hits -system.cpu1.itb.fetch_misses 774 # ITB misses +system.cpu1.dtb.write_accesses 60098 # DTB write accesses +system.cpu1.dtb.data_hits 2150747 # DTB hits +system.cpu1.dtb.data_misses 1756 # DTB misses +system.cpu1.dtb.data_acv 69 # DTB access violations +system.cpu1.dtb.data_accesses 204085 # DTB accesses +system.cpu1.itb.fetch_hits 875028 # ITB hits +system.cpu1.itb.fetch_misses 772 # ITB misses system.cpu1.itb.fetch_acv 46 # ITB acv -system.cpu1.itb.fetch_accesses 875897 # ITB accesses +system.cpu1.itb.fetch_accesses 875800 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1170,28 +1175,28 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953544041 # number of cpu cycles simulated +system.cpu1.numCycles 953543873 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7861950 # Number of instructions committed -system.cpu1.committedOps 7861950 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7314131 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45433 # Number of float alu accesses -system.cpu1.num_func_calls 212083 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 960162 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7314131 # number of integer instructions -system.cpu1.num_fp_insts 45433 # number of float instructions -system.cpu1.num_int_register_reads 10166174 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5323213 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24545 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24803 # number of times the floating registers were written -system.cpu1.num_mem_refs 2156447 # number of memory refs -system.cpu1.num_load_insts 1225739 # Number of load instructions -system.cpu1.num_store_insts 930708 # Number of store instructions -system.cpu1.num_idle_cycles 195910527.476772 # Number of idle cycles -system.cpu1.num_busy_cycles 757633513.523228 # Number of busy cycles -system.cpu1.not_idle_fraction 0.794545 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.205455 # Percentage of idle cycles +system.cpu1.committedInsts 7871049 # Number of instructions committed +system.cpu1.committedOps 7871049 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7322486 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45486 # Number of float alu accesses +system.cpu1.num_func_calls 212361 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 961543 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7322486 # number of integer instructions +system.cpu1.num_fp_insts 45486 # number of float instructions +system.cpu1.num_int_register_reads 10177666 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5328829 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24537 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24857 # number of times the floating registers were written +system.cpu1.num_mem_refs 2158619 # number of memory refs +system.cpu1.num_load_insts 1227197 # Number of load instructions +system.cpu1.num_store_insts 931422 # Number of store instructions +system.cpu1.num_idle_cycles -1678612352.135852 # Number of idle cycles +system.cpu1.num_busy_cycles 2632156225.135852 # Number of busy cycles +system.cpu1.not_idle_fraction 2.760393 # Percentage of non-idle cycles +system.cpu1.idle_fraction -1.760393 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1209,35 +1214,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 8412639 # Number of BP lookups -system.cpu2.branchPred.condPredicted 7718594 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 129283 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 6816710 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 5762097 # Number of BTB hits +system.cpu2.branchPred.lookups 8388883 # Number of BP lookups +system.cpu2.branchPred.condPredicted 7698653 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 129790 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 6809522 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 5746337 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 84.529003 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 288281 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 15520 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 84.386790 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 285994 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 15305 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3230838 # DTB read hits -system.cpu2.dtb.read_misses 11458 # DTB read misses -system.cpu2.dtb.read_acv 112 # DTB read access violations -system.cpu2.dtb.read_accesses 217040 # DTB read accesses -system.cpu2.dtb.write_hits 2001661 # DTB write hits -system.cpu2.dtb.write_misses 2605 # DTB write misses -system.cpu2.dtb.write_acv 143 # DTB write access violations -system.cpu2.dtb.write_accesses 81606 # DTB write accesses -system.cpu2.dtb.data_hits 5232499 # DTB hits -system.cpu2.dtb.data_misses 14063 # DTB misses -system.cpu2.dtb.data_acv 255 # DTB access violations -system.cpu2.dtb.data_accesses 298646 # DTB accesses -system.cpu2.itb.fetch_hits 371716 # ITB hits -system.cpu2.itb.fetch_misses 5691 # ITB misses -system.cpu2.itb.fetch_acv 245 # ITB acv -system.cpu2.itb.fetch_accesses 377407 # ITB accesses +system.cpu2.dtb.read_hits 3222753 # DTB read hits +system.cpu2.dtb.read_misses 11767 # DTB read misses +system.cpu2.dtb.read_acv 114 # DTB read access violations +system.cpu2.dtb.read_accesses 216394 # DTB read accesses +system.cpu2.dtb.write_hits 1997746 # DTB write hits +system.cpu2.dtb.write_misses 2597 # DTB write misses +system.cpu2.dtb.write_acv 133 # DTB write access violations +system.cpu2.dtb.write_accesses 81219 # DTB write accesses +system.cpu2.dtb.data_hits 5220499 # DTB hits +system.cpu2.dtb.data_misses 14364 # DTB misses +system.cpu2.dtb.data_acv 247 # DTB access violations +system.cpu2.dtb.data_accesses 297613 # DTB accesses +system.cpu2.itb.fetch_hits 371919 # ITB hits +system.cpu2.itb.fetch_misses 5650 # ITB misses +system.cpu2.itb.fetch_acv 270 # ITB acv +system.cpu2.itb.fetch_accesses 377569 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1250,141 +1255,141 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30535693 # number of cpu cycles simulated +system.cpu2.numCycles 30487191 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8533990 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 34964700 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 8412639 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6050378 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8133501 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 621341 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9684407 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 10316 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1948 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 62496 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 78611 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2608255 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 90277 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 26910349 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.299303 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.309788 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8524791 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 34873991 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 8388883 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6032331 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8111828 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 622665 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9676306 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 10691 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1940 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 62420 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 80561 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 496 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2604903 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 90729 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 26874751 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.297649 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.309099 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18776848 69.78% 69.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 272793 1.01% 70.79% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 440434 1.64% 72.43% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4254202 15.81% 88.23% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 737771 2.74% 90.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 167398 0.62% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 196636 0.73% 92.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 433593 1.61% 93.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1630674 6.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18762923 69.82% 69.82% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 273694 1.02% 70.83% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 440641 1.64% 72.47% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4237897 15.77% 88.24% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 736346 2.74% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 166761 0.62% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 196079 0.73% 92.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 433619 1.61% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1626791 6.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 26910349 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.275502 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.145044 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8661368 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9779389 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7537152 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 294171 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 392385 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 168928 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12969 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34563096 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 40760 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 392385 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 9017327 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2819479 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5795758 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7393745 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1245780 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33400490 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2356 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 234346 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 410986 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 22419818 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 41624592 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41459015 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 165577 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 20587002 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1832816 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 505460 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 60216 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3692921 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3393863 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2097986 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 374319 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 252386 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 30873003 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 630971 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 30415505 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 38395 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2194500 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1105040 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 445283 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 26910349 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.130253 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.565605 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 26874751 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.275161 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.143890 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8657787 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9768162 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7515953 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 293497 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 393434 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 168963 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12933 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 34472576 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 40526 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 393434 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 9012684 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2836795 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5769605 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7372565 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1243759 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 33316352 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2373 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 234595 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 408588 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 22366948 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 41510379 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 41345500 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 164879 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 20534540 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1832408 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 504738 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 60071 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3686935 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3385510 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2088081 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 373278 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 254690 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 30792200 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 629969 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 30337437 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 32004 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2187587 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1093629 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 444846 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 26874751 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.128845 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.565283 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15319532 56.93% 56.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3107477 11.55% 68.48% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1555924 5.78% 74.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5075651 18.86% 93.12% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 913363 3.39% 96.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 492005 1.83% 98.34% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 286833 1.07% 99.41% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 141760 0.53% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 17804 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15311841 56.97% 56.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3103500 11.55% 68.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1551808 5.77% 74.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5059769 18.83% 93.12% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 912287 3.39% 96.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 489619 1.82% 98.34% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 286015 1.06% 99.40% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 141615 0.53% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18297 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 26910349 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 26874751 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 34989 13.90% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 113310 45.00% 58.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 103504 41.11% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 34821 13.89% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 112497 44.88% 58.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 103352 41.23% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2444 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 24705611 81.23% 81.24% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20302 0.07% 81.30% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2448 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 24640378 81.22% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20252 0.07% 81.30% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8486 0.03% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1222 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8482 0.03% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.33% # Type of FU issued @@ -1406,114 +1411,114 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.33% # Ty system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3362290 11.05% 92.39% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2024696 6.66% 99.05% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 290454 0.95% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3354206 11.06% 92.38% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2020424 6.66% 99.04% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 290023 0.96% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 30415505 # Type of FU issued -system.cpu2.iq.rate 0.996064 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 251803 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.008279 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 87793654 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 33586184 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 30009842 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 237903 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 116334 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 112629 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 30540947 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 123917 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 191281 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 30337437 # Type of FU issued +system.cpu2.iq.rate 0.995088 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 250670 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.008263 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 87595744 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 33498169 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 29934734 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 236555 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 115613 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 112132 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 30462481 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 123178 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 189585 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 420180 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 991 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4150 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 166079 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 417411 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 964 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4105 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 161809 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4737 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 23355 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4731 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 22958 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 392385 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2039220 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 211536 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32790350 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 224390 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3393863 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2097986 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 560382 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 149727 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2248 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4150 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 66680 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 129831 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 196511 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 30250749 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3250588 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 164756 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 393434 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2055085 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 212014 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32707784 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 224122 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3385510 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2088081 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 559310 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 150319 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2295 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4105 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 66873 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 130024 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 196897 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 30173481 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3242841 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 163956 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1286376 # number of nop insts executed -system.cpu2.iew.exec_refs 5259365 # number of memory reference insts executed -system.cpu2.iew.exec_branches 6817857 # Number of branches executed -system.cpu2.iew.exec_stores 2008777 # Number of stores executed -system.cpu2.iew.exec_rate 0.990668 # Inst execution rate -system.cpu2.iew.wb_sent 30155480 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 30122471 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17393530 # num instructions producing a value -system.cpu2.iew.wb_consumers 20640200 # num instructions consuming a value +system.cpu2.iew.exec_nop 1285615 # number of nop insts executed +system.cpu2.iew.exec_refs 5247672 # number of memory reference insts executed +system.cpu2.iew.exec_branches 6797242 # Number of branches executed +system.cpu2.iew.exec_stores 2004831 # Number of stores executed +system.cpu2.iew.exec_rate 0.989710 # Inst execution rate +system.cpu2.iew.wb_sent 30079535 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 30046866 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17352028 # num instructions producing a value +system.cpu2.iew.wb_consumers 20589621 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.986468 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.842702 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.985557 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.842756 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2374784 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 185688 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 182289 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26517964 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.145283 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.851177 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2372790 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 185123 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 182681 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26481317 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.143824 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.850690 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16375646 61.75% 61.75% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2329504 8.78% 70.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1218959 4.60% 75.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 4807373 18.13% 93.26% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 502647 1.90% 95.16% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 186921 0.70% 95.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 179411 0.68% 96.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 180660 0.68% 97.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 736843 2.78% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16366667 61.80% 61.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2324205 8.78% 70.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1216165 4.59% 75.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 4790733 18.09% 93.26% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 501931 1.90% 95.16% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 186373 0.70% 95.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 179761 0.68% 96.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 180772 0.68% 97.23% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 734710 2.77% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26517964 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 30370564 # Number of instructions committed -system.cpu2.commit.committedOps 30370564 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26481317 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 30289973 # Number of instructions committed +system.cpu2.commit.committedOps 30289973 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4905590 # Number of memory references committed -system.cpu2.commit.loads 2973683 # Number of loads committed -system.cpu2.commit.membars 65235 # Number of memory barriers committed -system.cpu2.commit.branches 6667985 # Number of branches committed -system.cpu2.commit.fp_insts 111312 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 28908366 # Number of committed integer instructions. -system.cpu2.commit.function_calls 232233 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 736843 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4894371 # Number of memory references committed +system.cpu2.commit.loads 2968099 # Number of loads committed +system.cpu2.commit.membars 65019 # Number of memory barriers committed +system.cpu2.commit.branches 6647353 # Number of branches committed +system.cpu2.commit.fp_insts 110870 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 28830509 # Number of committed integer instructions. +system.cpu2.commit.function_calls 231619 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 734710 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 58454819 # The number of ROB reads -system.cpu2.rob.rob_writes 65882909 # The number of ROB writes -system.cpu2.timesIdled 242872 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3625344 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1745288097 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 29192895 # Number of Instructions Simulated -system.cpu2.committedOps 29192895 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 29192895 # Number of Instructions Simulated -system.cpu2.cpi 1.045997 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.045997 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.956025 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.956025 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 39779596 # number of integer regfile reads -system.cpu2.int_regfile_writes 21289109 # number of integer regfile writes -system.cpu2.fp_regfile_reads 68643 # number of floating regfile reads -system.cpu2.fp_regfile_writes 68941 # number of floating regfile writes -system.cpu2.misc_regfile_reads 4607989 # number of misc regfile reads -system.cpu2.misc_regfile_writes 260558 # number of misc regfile writes +system.cpu2.rob.rob_reads 58337288 # The number of ROB reads +system.cpu2.rob.rob_writes 65718838 # The number of ROB writes +system.cpu2.timesIdled 243105 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3612440 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1745337726 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 29114232 # Number of Instructions Simulated +system.cpu2.committedOps 29114232 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 29114232 # Number of Instructions Simulated +system.cpu2.cpi 1.047158 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.047158 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.954966 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.954966 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 39679960 # number of integer regfile reads +system.cpu2.int_regfile_writes 21237504 # number of integer regfile writes +system.cpu2.fp_regfile_reads 68414 # number of floating regfile reads +system.cpu2.fp_regfile_writes 68689 # number of floating regfile writes +system.cpu2.misc_regfile_reads 4591435 # number of misc regfile reads +system.cpu2.misc_regfile_writes 259923 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 9c75c4e0e..b54fd326b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,153 +1,128 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.533148 # Number of seconds simulated -sim_ticks 2533147650000 # Number of ticks simulated -final_tick 2533147650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.533144 # Number of seconds simulated +sim_ticks 2533143504000 # Number of ticks simulated +final_tick 2533143504000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55856 # Simulator instruction rate (inst/s) -host_op_rate 71871 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2346171672 # Simulator tick rate (ticks/s) -host_mem_usage 407620 # Number of bytes of host memory used -host_seconds 1079.69 # Real time elapsed on the host -sim_insts 60307315 # Number of instructions simulated -sim_ops 77598799 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 65433 # Simulator instruction rate (inst/s) +host_op_rate 84194 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2748425484 # Simulator tick rate (ticks/s) +host_mem_usage 408856 # Number of bytes of host memory used +host_seconds 921.67 # Real time elapsed on the host +sim_insts 60307579 # Number of instructions simulated +sim_ops 77599125 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 795840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093648 # Number of bytes read from this memory -system.physmem.bytes_read::total 129429904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 795840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 795840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3782016 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093520 # Number of bytes read from this memory +system.physmem.bytes_read::total 129430672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3782592 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6798088 # Number of bytes written to this memory +system.physmem.bytes_written::total 6798664 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12435 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096808 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59094 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12449 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142120 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096820 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59103 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813112 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47189379 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813121 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47189456 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589861 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51094497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493010 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683652 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47189379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51094883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314525 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314525 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493240 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190644 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683884 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47189456 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096808 # Total number of read requests seen -system.physmem.writeReqs 813112 # Total number of write requests seen -system.physmem.cpureqs 218335 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966195712 # Total number of bytes read from memory -system.physmem.bytesWritten 52039168 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129429904 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6798088 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 295 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4677 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943938 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943447 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943391 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943143 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943273 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943781 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943299 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943231 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943694 # Track reads on a per bank basis +system.physmem.bw_total::cpu.inst 314525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53778768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096820 # Total number of read requests seen +system.physmem.writeReqs 813121 # Total number of write requests seen +system.physmem.cpureqs 218357 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966196480 # Total number of bytes read from memory +system.physmem.bytesWritten 52039744 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129430672 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6798664 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 227 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4678 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943951 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943388 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944196 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943983 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943145 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943274 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943869 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943805 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943304 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943616 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943708 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 943087 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 942964 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943610 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50827 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50416 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50443 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50907 # Track writes on a per bank basis +system.physmem.perBankRdReqs::14 942997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943623 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50838 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50409 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50910 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 50180 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50280 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51358 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51187 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51246 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50619 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51228 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50279 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51367 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50902 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50800 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51241 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50709 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50623 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2236976 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533146526000 # Total gap between requests +system.physmem.numWrRetry 2238337 # Number of times wr buffer was full causing retry +system.physmem.totGap 2533142364000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154564 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 2990994 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59094 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4677 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1039969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 980923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2688258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649649 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108720 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16731 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 21899 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 10876 # What read queue length does an incoming req see +system.physmem.readPktSize::6 154576 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 754018 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 59103 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1040115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2676376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2687982 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649582 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157630 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16713 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16586 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 21915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 10858 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see @@ -164,15 +139,14 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2815 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 2832 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see @@ -181,31 +155,30 @@ system.physmem.wrQLenPdf::12 35353 # Wh system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32538 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 32521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 393223278963 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485615648963 # Sum of mem lat for all requests -system.physmem.totBusLat 75482565000 # Total cycles spent in databus access -system.physmem.totBankLat 16909805000 # Total cycles spent in bank access -system.physmem.avgQLat 26047.29 # Average queueing delay per request -system.physmem.avgBankLat 1120.11 # Average bank access latency per request +system.physmem.totQLat 393245939250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485641693000 # Sum of mem lat for all requests +system.physmem.totBusLat 75482965000 # Total cycles spent in databus access +system.physmem.totBankLat 16912788750 # Total cycles spent in bank access +system.physmem.avgQLat 26048.65 # Average queueing delay per request +system.physmem.avgBankLat 1120.31 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32167.41 # Average memory access latency +system.physmem.avgMemAccLat 32168.96 # Average memory access latency system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s @@ -213,32 +186,44 @@ system.physmem.avgConsumedWrBW 2.68 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 11.48 # Average write queue length over time -system.physmem.readRowHits 15020221 # Number of row buffer hits during reads -system.physmem.writeRowHits 793131 # Number of row buffer hits during writes +system.physmem.avgWrQLen 9.55 # Average write queue length over time +system.physmem.readRowHits 15020273 # Number of row buffer hits during reads +system.physmem.writeRowHits 793117 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.54 # Row buffer hit rate for writes -system.physmem.avgGap 159218.06 # Average gap between requests +system.physmem.avgGap 159217.58 # Average gap between requests +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14676489 # Number of BP lookups -system.cpu.branchPred.condPredicted 11762878 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704619 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9800840 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7950249 # Number of BTB hits +system.cpu.branchPred.lookups 14678084 # Number of BP lookups +system.cpu.branchPred.condPredicted 11764424 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705314 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9806272 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7951789 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.118037 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1398960 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72172 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.088807 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1399019 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72620 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14987326 # DTB read hits +system.cpu.checker.dtb.read_hits 14987411 # DTB read hits system.cpu.checker.dtb.read_misses 7302 # DTB read misses -system.cpu.checker.dtb.write_hits 11227680 # DTB write hits +system.cpu.checker.dtb.write_hits 11227746 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -249,13 +234,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994628 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229869 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994713 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229935 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26215006 # DTB hits +system.cpu.checker.dtb.hits 26215157 # DTB hits system.cpu.checker.dtb.misses 9491 # DTB misses -system.cpu.checker.dtb.accesses 26224497 # DTB accesses -system.cpu.checker.itb.inst_hits 61481313 # ITB inst hits +system.cpu.checker.dtb.accesses 26224648 # DTB accesses +system.cpu.checker.itb.inst_hits 61481576 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -272,36 +257,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61485784 # ITB inst accesses -system.cpu.checker.itb.hits 61481313 # DTB hits +system.cpu.checker.itb.inst_accesses 61486047 # ITB inst accesses +system.cpu.checker.itb.hits 61481576 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61485784 # DTB accesses -system.cpu.checker.numCycles 77884604 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61486047 # DTB accesses +system.cpu.checker.numCycles 77884929 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51394402 # DTB read hits -system.cpu.dtb.read_misses 64202 # DTB read misses -system.cpu.dtb.write_hits 11700782 # DTB write hits -system.cpu.dtb.write_misses 15842 # DTB write misses +system.cpu.dtb.read_hits 51401633 # DTB read hits +system.cpu.dtb.read_misses 64365 # DTB read misses +system.cpu.dtb.write_hits 11702282 # DTB write hits +system.cpu.dtb.write_misses 15903 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6555 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2475 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6544 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2575 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 399 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1357 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51458604 # DTB read accesses -system.cpu.dtb.write_accesses 11716624 # DTB write accesses +system.cpu.dtb.perms_faults 1330 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51465998 # DTB read accesses +system.cpu.dtb.write_accesses 11718185 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63095184 # DTB hits -system.cpu.dtb.misses 80044 # DTB misses -system.cpu.dtb.accesses 63175228 # DTB accesses -system.cpu.itb.inst_hits 12330326 # ITB inst hits -system.cpu.itb.inst_misses 11351 # ITB inst misses +system.cpu.dtb.hits 63103915 # DTB hits +system.cpu.dtb.misses 80268 # DTB misses +system.cpu.dtb.accesses 63184183 # DTB accesses +system.cpu.itb.inst_hits 12333169 # ITB inst hits +system.cpu.itb.inst_misses 11311 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -310,114 +295,114 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4952 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4950 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2994 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2979 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12341677 # ITB inst accesses -system.cpu.itb.hits 12330326 # DTB hits -system.cpu.itb.misses 11351 # DTB misses -system.cpu.itb.accesses 12341677 # DTB accesses -system.cpu.numCycles 471833351 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12344480 # ITB inst accesses +system.cpu.itb.hits 12333169 # DTB hits +system.cpu.itb.misses 11311 # DTB misses +system.cpu.itb.accesses 12344480 # DTB accesses +system.cpu.numCycles 471839315 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30572359 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96029601 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14676489 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9349209 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21156129 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5298120 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 120373 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95586316 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2531 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87050 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195749 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 271 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12326631 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 900507 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5718 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151357354 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.785025 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.150266 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30570275 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96049459 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14678084 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9350808 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21162167 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5300670 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 119262 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95593563 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2640 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87521 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195771 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 307 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12329483 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 900673 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5698 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151369698 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.785111 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.150333 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130216652 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1302204 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1711626 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2495193 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2215033 1.46% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1107976 0.73% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2757688 1.82% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745754 0.49% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8805228 5.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130222829 86.03% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1303268 0.86% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1713149 1.13% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2496945 1.65% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2215858 1.46% 91.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107759 0.73% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2757122 1.82% 93.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745476 0.49% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8807292 5.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151357354 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031105 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203524 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32536934 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95207461 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19182239 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 963280 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3467440 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1956290 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171623 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112620131 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 567256 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3467440 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34479585 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36699027 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52520178 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18147266 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6043858 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106106757 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20523 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1005521 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4063485 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 592 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110532069 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485468581 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485377824 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90757 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78389582 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32142486 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830463 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737014 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12171984 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20324763 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13518088 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1981188 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2478536 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97936678 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983499 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124321529 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167156 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21750573 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 57066044 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501117 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151357354 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821378 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.534899 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151369698 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031108 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.203564 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32533087 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95216874 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19187667 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 962846 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3469224 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1957624 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171486 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112641564 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 566291 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3469224 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34475717 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36705773 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52523534 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18152425 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6043025 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106121315 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20520 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004083 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4063852 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 628 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110544866 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485535846 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485445234 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90612 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78389874 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32154991 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830680 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 737251 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12167564 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20329502 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13519419 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1975005 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2483431 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97943833 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983956 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124335595 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167777 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21753420 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 57059209 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501571 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151369698 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.821403 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.534931 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107117235 70.77% 70.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13550856 8.95% 79.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7067177 4.67% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5940673 3.92% 88.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12604400 8.33% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2784028 1.84% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1701066 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 465188 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126731 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107127102 70.77% 70.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13547292 8.95% 79.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7070046 4.67% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5943115 3.93% 88.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12603566 8.33% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2786171 1.84% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1700250 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 465001 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127155 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151357354 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151369698 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61039 0.69% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 60916 0.69% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available @@ -445,13 +430,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8364044 94.63% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413790 4.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365801 94.64% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413031 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58631158 47.16% 47.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93232 0.07% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58634354 47.16% 47.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93273 0.08% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.53% # Type of FU issued @@ -464,11 +449,11 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.53% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.53% # Type of FU issued @@ -477,351 +462,351 @@ system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.53% # Ty system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 18 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52911235 42.56% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12320074 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52919784 42.56% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12322346 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124321529 # Type of FU issued -system.cpu.iq.rate 0.263486 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8838876 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071097 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409062941 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121687155 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85967434 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23205 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12488 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10289 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132784424 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12315 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 622437 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124335595 # Type of FU issued +system.cpu.iq.rate 0.263513 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839750 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071096 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409105295 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121697619 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85975011 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23030 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12486 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10280 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132799466 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12213 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624029 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4670323 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6258 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30023 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1786078 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4674977 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6508 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30066 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1787339 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107730 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 893047 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107736 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 893802 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3467440 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27945377 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 433355 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100140842 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 200439 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20324763 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13518088 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1411116 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 112674 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3579 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30023 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350481 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268612 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619093 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121545908 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52081707 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2775621 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3469224 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27949054 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 432986 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100148718 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 201036 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20329502 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13519419 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1411238 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 112362 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3588 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30066 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350846 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269150 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619996 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121555637 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52088672 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2779958 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 220665 # number of nop insts executed -system.cpu.iew.exec_refs 64294282 # number of memory reference insts executed -system.cpu.iew.exec_branches 11561887 # Number of branches executed -system.cpu.iew.exec_stores 12212575 # Number of stores executed -system.cpu.iew.exec_rate 0.257603 # Inst execution rate -system.cpu.iew.wb_sent 120387103 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85977723 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47219839 # num instructions producing a value -system.cpu.iew.wb_consumers 88163371 # num instructions consuming a value +system.cpu.iew.exec_nop 220929 # number of nop insts executed +system.cpu.iew.exec_refs 64302587 # number of memory reference insts executed +system.cpu.iew.exec_branches 11562998 # Number of branches executed +system.cpu.iew.exec_stores 12213915 # Number of stores executed +system.cpu.iew.exec_rate 0.257621 # Inst execution rate +system.cpu.iew.wb_sent 120394624 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85985291 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47225460 # num instructions producing a value +system.cpu.iew.wb_consumers 88174567 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182221 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535595 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182234 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535590 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21484846 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482382 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535483 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147889914 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525723 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.514974 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21490031 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482385 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 536346 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147900474 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.525688 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.515007 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120439692 81.44% 81.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13316642 9.00% 90.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3906186 2.64% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2120970 1.43% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1946250 1.32% 95.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 970441 0.66% 96.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1598227 1.08% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 701359 0.47% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2890147 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120451739 81.44% 81.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13317188 9.00% 90.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3905098 2.64% 93.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2119368 1.43% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1946193 1.32% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 968094 0.65% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1600636 1.08% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 702304 0.47% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2889854 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147889914 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60457696 # Number of instructions committed -system.cpu.commit.committedOps 77749180 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147900474 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60457960 # Number of instructions committed +system.cpu.commit.committedOps 77749506 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386450 # Number of memory references committed -system.cpu.commit.loads 15654440 # Number of loads committed -system.cpu.commit.membars 403595 # Number of memory barriers committed -system.cpu.commit.branches 9961299 # Number of branches committed +system.cpu.commit.refs 27386605 # Number of memory references committed +system.cpu.commit.loads 15654525 # Number of loads committed +system.cpu.commit.membars 403599 # Number of memory barriers committed +system.cpu.commit.branches 9961316 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68854449 # Number of committed integer instructions. -system.cpu.commit.function_calls 991256 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2890147 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68854760 # Number of committed integer instructions. +system.cpu.commit.function_calls 991257 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2889854 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242385214 # The number of ROB reads -system.cpu.rob.rob_writes 202032533 # The number of ROB writes -system.cpu.timesIdled 1770643 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320475997 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4594378908 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307315 # Number of Instructions Simulated -system.cpu.committedOps 77598799 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307315 # Number of Instructions Simulated -system.cpu.cpi 7.823816 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823816 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127815 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127815 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550300284 # number of integer regfile reads -system.cpu.int_regfile_writes 88460224 # number of integer regfile writes -system.cpu.fp_regfile_reads 8330 # number of floating regfile reads -system.cpu.fp_regfile_writes 2914 # number of floating regfile writes -system.cpu.misc_regfile_reads 30137587 # number of misc regfile reads -system.cpu.misc_regfile_writes 831885 # number of misc regfile writes -system.cpu.icache.replacements 979919 # number of replacements -system.cpu.icache.tagsinuse 511.615669 # Cycle average of tags in use -system.cpu.icache.total_refs 11266751 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980431 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.491631 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 242401590 # The number of ROB reads +system.cpu.rob.rob_writes 202045449 # The number of ROB writes +system.cpu.timesIdled 1769758 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320469617 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4594364653 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60307579 # Number of Instructions Simulated +system.cpu.committedOps 77599125 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60307579 # Number of Instructions Simulated +system.cpu.cpi 7.823881 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.823881 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127814 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127814 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550352195 # number of integer regfile reads +system.cpu.int_regfile_writes 88467764 # number of integer regfile writes +system.cpu.fp_regfile_reads 8269 # number of floating regfile reads +system.cpu.fp_regfile_writes 2928 # number of floating regfile writes +system.cpu.misc_regfile_reads 30128398 # number of misc regfile reads +system.cpu.misc_regfile_writes 831890 # number of misc regfile writes +system.cpu.icache.replacements 979593 # number of replacements +system.cpu.icache.tagsinuse 511.615707 # Cycle average of tags in use +system.cpu.icache.total_refs 11270072 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980105 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.498841 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.615669 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 511.615707 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11266751 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11266751 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11266751 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11266751 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11266751 # number of overall hits -system.cpu.icache.overall_hits::total 11266751 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059755 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059755 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059755 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059755 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059755 # number of overall misses -system.cpu.icache.overall_misses::total 1059755 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13997065496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13997065496 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13997065496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13997065496 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13997065496 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13997065496 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12326506 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12326506 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12326506 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12326506 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12326506 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12326506 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085974 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.085974 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.085974 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.085974 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.085974 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.085974 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.831523 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13207.831523 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.831523 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13207.831523 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.831523 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13207.831523 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4420 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 11270072 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11270072 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11270072 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11270072 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11270072 # number of overall hits +system.cpu.icache.overall_hits::total 11270072 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1059286 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1059286 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1059286 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1059286 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1059286 # number of overall misses +system.cpu.icache.overall_misses::total 1059286 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13991116996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13991116996 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13991116996 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13991116996 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13991116996 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13991116996 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12329358 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12329358 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12329358 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12329358 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12329358 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12329358 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085916 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.085916 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.085916 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.085916 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.085916 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.085916 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13208.063730 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13208.063730 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13208.063730 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13208.063730 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13208.063730 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13208.063730 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4509 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 308 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 15.136986 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 14.639610 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79294 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79294 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79294 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79294 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79294 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79294 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980461 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980461 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980461 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980461 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980461 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980461 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11381703997 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11381703997 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11381703997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11381703997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11381703997 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11381703997 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79147 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79147 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79147 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79147 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79147 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79147 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980139 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 980139 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 980139 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 980139 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 980139 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 980139 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11380145996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11380145996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11380145996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11380145996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11380145996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11380145996 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7553500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7553500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7553500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7553500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079541 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079541 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079541 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.079541 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079541 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.079541 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11608.522926 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11608.522926 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11608.522926 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11608.522926 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11608.522926 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11608.522926 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079496 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079496 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079496 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.079496 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079496 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.079496 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11610.747043 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11610.747043 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11610.747043 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11610.747043 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11610.747043 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11610.747043 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64335 # number of replacements -system.cpu.l2cache.tagsinuse 51343.588717 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1886166 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129730 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.539166 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2498200830000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36928.997165 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 25.134248 # Average occupied blocks per requestor +system.cpu.l2cache.replacements 64347 # number of replacements +system.cpu.l2cache.tagsinuse 51347.741462 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1885858 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129741 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.535559 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2498197510500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36929.511487 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.548284 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8156.882895 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6232.574061 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563492 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000384 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 8159.884348 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6231.796994 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.563500 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000405 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.124464 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.095102 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783441 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53181 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10674 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 967006 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387028 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1417889 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607515 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607515 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 7 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112907 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112907 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 53181 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10674 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 967006 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 499935 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1530796 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 53181 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10674 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 967006 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 499935 # number of overall hits -system.cpu.l2cache.overall_hits::total 1530796 # number of overall hits +system.cpu.l2cache.occ_percent::cpu.inst 0.124510 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.095090 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.783504 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52622 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10526 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 966687 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387256 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1417091 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607840 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607840 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 40 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 40 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 11 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 112895 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112895 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 52622 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10526 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 966687 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 500151 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1529986 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 52622 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10526 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 966687 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 500151 # number of overall hits +system.cpu.l2cache.overall_hits::total 1529986 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12329 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10702 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23074 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2920 # number of UpgradeReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12342 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10709 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23094 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2921 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2921 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133200 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133200 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133191 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133191 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12329 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143902 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156274 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12342 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143900 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156285 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12329 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143902 # number of overall misses -system.cpu.l2cache.overall_misses::total 156274 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2844500 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 12342 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143900 # number of overall misses +system.cpu.l2cache.overall_misses::total 156285 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2975000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 695710500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 632225999 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1330898999 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 476500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 476500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6732832500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6732832500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2844500 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 697957500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 634176999 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1335227499 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 522000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 522000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6733037500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6733037500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2975000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 695710500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7365058499 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8063731499 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2844500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 697957500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7367214499 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8068264999 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2975000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 695710500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7365058499 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8063731499 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53222 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10676 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 979335 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 397730 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1440963 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607515 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607515 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2963 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2963 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 10 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246107 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246107 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53222 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10676 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 979335 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 643837 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1687070 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53222 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10676 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 979335 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 643837 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1687070 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000770 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000187 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012589 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026908 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016013 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985488 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985488 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.300000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.300000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541228 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541228 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000770 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000187 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012589 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223507 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092630 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000770 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000187 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012589 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223507 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092630 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 69378.048780 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_latency::cpu.inst 697957500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7367214499 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8068264999 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52663 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10528 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 979029 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 397965 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1440185 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607840 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607840 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2961 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2961 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 14 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 14 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246086 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246086 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52663 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10528 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 979029 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 644051 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1686271 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52663 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10528 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 979029 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 644051 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1686271 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000779 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000190 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012606 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026909 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016035 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986491 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986491 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541238 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541238 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000779 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000190 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012606 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223430 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.092681 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000779 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000190 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012606 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223430 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.092681 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 72560.975610 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56428.785790 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59075.499813 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 57679.596039 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.184932 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.184932 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50546.790541 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50546.790541 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 69378.048780 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56551.409820 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59219.067980 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 57817.073655 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 178.705923 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 178.705923 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50551.745238 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50551.745238 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 72560.975610 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56428.785790 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51181.071139 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51599.955840 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 69378.048780 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56551.409820 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51196.765108 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51625.331919 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 72560.975610 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56428.785790 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51181.071139 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51599.955840 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56551.409820 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51196.765108 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51625.331919 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -830,109 +815,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59094 # number of writebacks -system.cpu.l2cache.writebacks::total 59094 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 59103 # number of writebacks +system.cpu.l2cache.writebacks::total 59103 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12316 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10640 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 22999 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12330 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10647 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23020 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2921 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2921 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133200 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133200 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133191 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133191 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12316 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143840 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156199 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12330 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143838 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156211 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12316 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143840 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156199 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2335079 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93252 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 541798119 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 497025991 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1041252441 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29202920 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29202920 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12330 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143838 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156211 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2463540 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93251 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 543887277 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 499142740 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1045586808 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29212921 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29212921 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5072736540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5072736540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2335079 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93252 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 541798119 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5569762531 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6113988981 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2335079 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93252 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 541798119 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5569762531 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6113988981 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5079407 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002423276 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007502683 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26890048041 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26890048041 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5079407 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193892471317 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193897550724 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000770 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000187 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026752 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015961 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985488 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985488 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.300000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.300000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541228 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541228 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000770 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000187 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223411 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092586 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000770 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000187 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223411 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092586 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56953.146341 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46626 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43991.402972 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46712.969079 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45273.813688 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5073016629 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5073016629 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2463540 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93251 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 543887277 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5572159369 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6118603437 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2463540 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93251 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 543887277 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5572159369 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6118603437 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5079330 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002492267 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007571597 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26903234989 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26903234989 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5079330 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193905727256 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193910806586 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026754 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015984 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986491 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986491 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541238 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541238 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223333 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092637 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223333 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092637 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44110.890268 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46881.068846 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45420.799652 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38083.607658 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38083.607658 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56953.146341 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46626 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43991.402972 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38721.930833 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39142.305527 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56953.146341 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46626 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43991.402972 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38721.930833 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39142.305527 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38088.283961 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38088.283961 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44110.890268 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38739.132698 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39168.838539 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44110.890268 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38739.132698 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39168.838539 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -942,161 +927,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643325 # number of replacements +system.cpu.dcache.replacements 643539 # number of replacements system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use -system.cpu.dcache.total_refs 21505081 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 643837 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.401437 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 21509590 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644051 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.397340 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 42249000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13751349 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13751349 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259815 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259815 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 243177 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 243177 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247604 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247604 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21011164 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21011164 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21011164 # number of overall hits -system.cpu.dcache.overall_hits::total 21011164 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737485 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737485 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2962473 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2962473 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13509 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13509 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 10 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3699958 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3699958 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3699958 # number of overall misses -system.cpu.dcache.overall_misses::total 3699958 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9781666500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9781666500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104377974730 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104377974730 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180159500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 180159500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 166000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 166000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114159641230 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114159641230 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114159641230 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114159641230 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14488834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14488834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222288 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222288 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256686 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256686 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247614 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247614 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24711122 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24711122 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24711122 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24711122 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050900 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050900 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289805 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289805 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052629 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052629 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000040 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000040 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149728 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149728 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149728 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13263.546377 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13263.546377 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35233.392753 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35233.392753 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13336.257310 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13336.257310 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16600 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16600 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30854.307327 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30854.307327 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30854.307327 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30854.307327 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29793 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 16864 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2613 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 251 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.401837 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 67.187251 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13756144 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13756144 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7259539 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7259539 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 243175 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 243175 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247602 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21015683 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21015683 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21015683 # number of overall hits +system.cpu.dcache.overall_hits::total 21015683 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737609 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737609 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2962812 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2962812 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13513 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13513 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3700421 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3700421 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3700421 # number of overall misses +system.cpu.dcache.overall_misses::total 3700421 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9797923500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9797923500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104330736229 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104330736229 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180578000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 180578000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 218000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 218000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 114128659729 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 114128659729 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 114128659729 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 114128659729 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14493753 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14493753 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222351 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222351 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256688 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256688 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247616 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247616 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24716104 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24716104 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24716104 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24716104 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050892 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050892 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289837 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289837 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052644 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052644 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000057 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149717 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149717 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149717 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149717 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13283.356765 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13283.356765 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35213.417601 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35213.417601 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13363.279805 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13363.279805 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15571.428571 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15571.428571 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30842.074383 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30842.074383 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30842.074383 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30842.074383 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29695 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 17222 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2648 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 252 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.214124 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 68.341270 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607515 # number of writebacks -system.cpu.dcache.writebacks::total 607515 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351842 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351842 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713489 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713489 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1336 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1336 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3065331 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3065331 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3065331 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3065331 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385643 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385643 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248984 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248984 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12173 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12173 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 10 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634627 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634627 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634627 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634627 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4807486000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4807486000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8182883413 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8182883413 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140770000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140770000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12990369413 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12990369413 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12990369413 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12990369413 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395639500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395639500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36729406082 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36729406082 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219125045582 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 219125045582 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026617 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026617 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047424 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047424 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12466.156523 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12466.156523 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32865.097408 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32865.097408 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11564.117309 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11564.117309 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14600 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14600 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20469.298364 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20469.298364 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20469.298364 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20469.298364 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607840 # number of writebacks +system.cpu.dcache.writebacks::total 607840 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351729 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351729 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713855 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2713855 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1338 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1338 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065584 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065584 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065584 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065584 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385880 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385880 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248957 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248957 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12175 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12175 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634837 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634837 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634837 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634837 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4811592500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4811592500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8182885914 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8182885914 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141167000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141167000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 190000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 190000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12994478414 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12994478414 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12994478414 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12994478414 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395775000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395775000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36742499011 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36742499011 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219138274011 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 219138274011 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026624 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026624 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024354 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024354 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047431 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047431 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025685 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025685 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025685 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025685 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12469.141961 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12469.141961 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32868.671755 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32868.671755 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11594.825462 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11594.825462 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13571.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13571.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20468.999781 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20468.999781 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20468.999781 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20468.999781 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1118,16 +1103,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229589046447 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229589046447 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229610747140 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229610747140 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83042 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83041 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 93139ea5d..434326c81 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,180 +1,153 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.102937 # Number of seconds simulated -sim_ticks 1102937390000 # Number of ticks simulated -final_tick 1102937390000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.102950 # Number of seconds simulated +sim_ticks 1102950399000 # Number of ticks simulated +final_tick 1102950399000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 67484 # Simulator instruction rate (inst/s) -host_op_rate 86868 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1208579190 # Simulator tick rate (ticks/s) -host_mem_usage 412736 # Number of bytes of host memory used -host_seconds 912.59 # Real time elapsed on the host -sim_insts 61585042 # Number of instructions simulated -sim_ops 79274675 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 57810 # Simulator instruction rate (inst/s) +host_op_rate 74418 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1035290197 # Simulator tick rate (ticks/s) +host_mem_usage 414988 # Number of bytes of host memory used +host_seconds 1065.35 # Real time elapsed on the host +sim_insts 61588287 # Number of instructions simulated +sim_ops 79281553 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 408896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4378804 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 405888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5226160 # Number of bytes read from this memory -system.physmem.bytes_read::total 59180644 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 408896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 405888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 814784 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4259456 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 409024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4368244 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 405632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5247408 # Number of bytes read from this memory +system.physmem.bytes_read::total 59191204 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 409024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 405632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 814656 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4268864 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7286800 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296208 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6389 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68491 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6342 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81685 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257788 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66554 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6391 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68326 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82017 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257953 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66701 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823390 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44208116 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823537 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44207595 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 370734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3970129 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 368006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4738401 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53657301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 370734 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 368006 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 738740 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3861920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 370845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3960508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 367770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4757610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53666243 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 370845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 367770 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 738615 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3870404 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2729388 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6606721 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3861920 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44208116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2729356 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6615173 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3870404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44207595 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 370734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3985543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 368006 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7467789 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60264023 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257788 # Total number of read requests seen -system.physmem.writeReqs 823390 # Total number of write requests seen -system.physmem.cpureqs 281560 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 400498432 # Total number of bytes read from memory -system.physmem.bytesWritten 52696960 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59180644 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7286800 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 80 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 12623 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391400 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391208 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 390865 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 391604 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391517 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 390867 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 390930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 391637 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391401 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 390707 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 390849 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 391231 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 391237 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 390522 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 390468 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 391265 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51411 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51226 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51010 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51681 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51542 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50958 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51664 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52039 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51352 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51491 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51878 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.itb.walker 232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 370845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3975921 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 367770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7486966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60281416 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257953 # Total number of read requests seen +system.physmem.writeReqs 823537 # Total number of write requests seen +system.physmem.cpureqs 242283 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 400508992 # Total number of bytes read from memory +system.physmem.bytesWritten 52706368 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59191204 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7296208 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 121 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 12582 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391384 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 391213 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 390896 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 391625 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391537 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 390907 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 390959 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 391661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391406 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 390708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 390852 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 391232 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 391228 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 390507 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 390457 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 391260 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51392 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51231 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51042 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51697 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51560 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50996 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51009 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51679 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52043 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51353 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51501 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51879 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 51845 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51250 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51172 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51894 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51248 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51167 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51895 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2242937 # Number of times wr buffer was full causing retry -system.physmem.totGap 1102936257500 # Total gap between requests +system.physmem.numWrRetry 2243059 # Number of times wr buffer was full causing retry +system.physmem.totGap 1102949217500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 162835 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 2999773 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 66554 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 12623 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 493621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 430392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 391768 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1441431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1086063 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1098338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1064335 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 26976 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 44565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 63872 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 44300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12061 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 11818 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 138 # What read queue length does an incoming req see +system.physmem.readPktSize::6 163000 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 756836 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 66701 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 493596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 430243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 391400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1441381 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1086282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1098776 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1064567 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 26922 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 44531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 63867 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 44258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12048 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 11790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 152 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -187,292 +160,322 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 199170690855 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 238991050855 # Sum of mem lat for all requests -system.physmem.totBusLat 31288540000 # Total cycles spent in databus access -system.physmem.totBankLat 8531820000 # Total cycles spent in bank access -system.physmem.avgQLat 31828.06 # Average queueing delay per request -system.physmem.avgBankLat 1363.41 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32635 # What write queue length does an incoming req see +system.physmem.totQLat 199191841750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 239011336750 # Sum of mem lat for all requests +system.physmem.totBusLat 31289160000 # Total cycles spent in databus access +system.physmem.totBankLat 8530335000 # Total cycles spent in bank access +system.physmem.avgQLat 31830.81 # Average queueing delay per request +system.physmem.avgBankLat 1363.15 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38191.47 # Average memory access latency -system.physmem.avgRdBW 363.12 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 47.78 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 53.66 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 38193.95 # Average memory access latency +system.physmem.avgRdBW 363.13 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 47.79 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 53.67 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.62 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.21 # Data bus utilization in percentage system.physmem.avgRdQLen 0.22 # Average read queue length over time -system.physmem.avgWrQLen 10.24 # Average write queue length over time -system.physmem.readRowHits 6213872 # Number of row buffer hits during reads -system.physmem.writeRowHits 799892 # Number of row buffer hits during writes +system.physmem.avgWrQLen 11.98 # Average write queue length over time +system.physmem.readRowHits 6213974 # Number of row buffer hits during reads +system.physmem.writeRowHits 800028 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.15 # Row buffer hit rate for writes -system.physmem.avgGap 155756.04 # Average gap between requests -system.l2c.replacements 72539 # number of replacements -system.l2c.tagsinuse 53752.248637 # Cycle average of tags in use -system.l2c.total_refs 1841179 # Total number of references to valid blocks. -system.l2c.sampled_refs 137732 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.367838 # Average number of references to valid blocks. +system.physmem.avgGap 155751.01 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 72704 # number of replacements +system.l2c.tagsinuse 53743.106475 # Cycle average of tags in use +system.l2c.total_refs 1840692 # Total number of references to valid blocks. +system.l2c.sampled_refs 137860 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.351893 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39388.476412 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 3.826353 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000803 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4008.993875 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2816.909683 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 12.612753 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3717.226162 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3804.202595 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.601020 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 39373.484726 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 3.828040 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 1.177687 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4008.510797 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2822.170311 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 11.062329 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.921455 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3716.471787 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3805.479341 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.600792 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000058 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.061172 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.042983 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.056720 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.058048 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.820194 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 21699 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4247 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 385844 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166771 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30512 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5160 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 591639 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 198020 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1403892 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 581178 # number of Writeback hits -system.l2c.Writeback_hits::total 581178 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1163 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 739 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1902 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 201 # number of SCUpgradeReq hits +system.l2c.occ_percent::cpu0.itb.walker 0.000018 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.061165 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.043063 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000169 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.056709 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.058067 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.820055 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 21930 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4443 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 386616 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166642 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30274 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5231 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 590416 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 197851 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1403403 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 581067 # number of Writeback hits +system.l2c.Writeback_hits::total 581067 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1230 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 737 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1967 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 199 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 143 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 344 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48042 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58985 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107027 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 21699 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4247 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 385844 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214813 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30512 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5160 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 591639 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 257005 # number of demand (read+write) hits -system.l2c.demand_hits::total 1510919 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 21699 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4247 # number of overall hits -system.l2c.overall_hits::cpu0.inst 385844 # number of overall hits -system.l2c.overall_hits::cpu0.data 214813 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30512 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5160 # number of overall hits -system.l2c.overall_hits::cpu1.inst 591639 # number of overall hits -system.l2c.overall_hits::cpu1.data 257005 # number of overall hits -system.l2c.overall_hits::total 1510919 # number of overall hits +system.l2c.SCUpgradeReq_hits::total 342 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48406 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58608 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 107014 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 21930 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4443 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 386616 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 215048 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30274 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5231 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 590416 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 256459 # number of demand (read+write) hits +system.l2c.demand_hits::total 1510417 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 21930 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4443 # number of overall hits +system.l2c.overall_hits::cpu0.inst 386616 # number of overall hits +system.l2c.overall_hits::cpu0.data 215048 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30274 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5231 # number of overall hits +system.l2c.overall_hits::cpu1.inst 590416 # number of overall hits +system.l2c.overall_hits::cpu1.data 256459 # number of overall hits +system.l2c.overall_hits::total 1510417 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6268 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6367 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 20 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6307 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6294 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25269 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5150 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3804 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8954 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 644 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 418 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1062 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63486 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 76591 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140077 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6270 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6414 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 17 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 6302 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 6301 # number of ReadReq misses +system.l2c.ReadReq_misses::total 25320 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5137 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3774 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8911 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 641 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 414 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1055 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63277 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 76923 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140200 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 11 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6268 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69853 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6307 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 82885 # number of demand (read+write) misses -system.l2c.demand_misses::total 165346 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6270 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69691 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 17 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6302 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 83224 # number of demand (read+write) misses +system.l2c.demand_misses::total 165520 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 11 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6268 # number of overall misses -system.l2c.overall_misses::cpu0.data 69853 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 20 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6307 # number of overall misses -system.l2c.overall_misses::cpu1.data 82885 # number of overall misses -system.l2c.overall_misses::total 165346 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 727500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 118000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 346856000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 362407499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1360500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 380856500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 395446999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1487772998 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 8791989 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 11737000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 20528989 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 591000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2890499 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3481499 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3145264486 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4121590993 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7266855479 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 727500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 118000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 346856000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3507671985 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1360500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 380856500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4517037992 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8754628477 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 727500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 118000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 346856000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3507671985 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1360500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 380856500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4517037992 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8754628477 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 21710 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 4249 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 392112 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 173138 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 30532 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 5160 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 597946 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 204314 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1429161 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 581178 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 581178 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6313 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4543 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10856 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 845 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 561 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1406 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111528 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 135576 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247104 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 21710 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 4249 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 392112 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 284666 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 30532 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 5160 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 597946 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 339890 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1676265 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 21710 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 4249 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 392112 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 284666 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 30532 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5160 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 597946 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 339890 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1676265 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000507 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000471 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015985 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036774 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000655 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010548 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.030806 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.017681 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.815777 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.837332 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.824797 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.762130 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.745098 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.755334 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.569238 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.564930 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.566875 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000507 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000471 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015985 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.245386 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000655 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010548 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.243858 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.098640 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000507 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000471 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015985 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.245386 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000655 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010548 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.243858 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.098640 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66136.363636 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 59000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55337.587747 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 56919.663735 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 68025 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 60386.316791 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 62829.202256 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 58877.399106 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1707.182330 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3085.436383 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2292.717110 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 917.701863 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6915.069378 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3278.247646 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49542.646977 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53812.993602 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 51877.577896 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66136.363636 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 55337.587747 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 50215.051394 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 68025 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 60386.316791 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 54497.653279 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52947.325469 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66136.363636 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 55337.587747 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 50215.051394 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 68025 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 60386.316791 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 54497.653279 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52947.325469 # average overall miss latency +system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6270 # number of overall misses +system.l2c.overall_misses::cpu0.data 69691 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 17 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 6302 # number of overall misses +system.l2c.overall_misses::cpu1.data 83224 # number of overall misses +system.l2c.overall_misses::total 165520 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 728500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 255500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 345548000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 371089999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1384000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 68500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 378000500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 393265500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1490340499 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 8952484 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 11872000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 20824484 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 614000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2820500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 3434500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3142895481 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4127198996 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7270094477 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 728500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 255500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 345548000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3513985480 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1384000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 68500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 378000500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4520464496 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8760434976 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 728500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 255500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 345548000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3513985480 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1384000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 68500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 378000500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4520464496 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8760434976 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 21941 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 4447 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 392886 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 173056 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 30291 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 5232 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 596718 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 204152 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1428723 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 581067 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 581067 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6367 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4511 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10878 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 840 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 557 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1397 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111683 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 135531 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247214 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 21941 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 4447 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 392886 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 284739 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 30291 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5232 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 596718 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 339683 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1675937 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 21941 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 4447 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 392886 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 284739 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 30291 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5232 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 596718 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 339683 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1675937 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000501 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000899 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015959 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.037063 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000561 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000191 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010561 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.030864 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.017722 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.806816 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836622 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.819176 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.763095 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.743268 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.755190 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.566577 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.567568 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.567120 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000501 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000899 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015959 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.244754 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000561 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000191 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010561 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.245005 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.098763 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000501 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000899 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015959 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.244754 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000561 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000191 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010561 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.245005 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.098763 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66227.272727 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 63875 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55111.323764 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 57856.251793 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 81411.764706 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 68500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 59981.037766 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 62413.188383 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 58860.209281 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1742.745571 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3145.733969 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2336.941308 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 957.878315 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6812.801932 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3255.450237 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49668.844620 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53653.640602 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 51855.167454 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66227.272727 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 63875 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 55111.323764 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 50422.371325 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 81411.764706 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 68500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 59981.037766 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 54316.837643 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52926.745868 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66227.272727 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 63875 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 55111.323764 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 50422.371325 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 81411.764706 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 68500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 59981.037766 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 54316.837643 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52926.745868 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,168 +484,180 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 66554 # number of writebacks -system.l2c.writebacks::total 66554 # number of writebacks +system.l2c.writebacks::writebacks 66701 # number of writebacks +system.l2c.writebacks::total 66701 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 36 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 37 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 36 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 37 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 36 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 37 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 72 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 11 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6264 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6331 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 20 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6299 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 6270 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25197 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 5150 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3804 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8954 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 644 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 418 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1062 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 63486 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 76591 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140077 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 4 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6266 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6377 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 17 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6295 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 6277 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25248 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 5137 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3774 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8911 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 641 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 414 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1055 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 63277 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 76923 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140200 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 11 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6264 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 69817 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 20 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6299 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 82861 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 165274 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6266 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 69654 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 17 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6295 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 83200 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 165448 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 11 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6264 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 69817 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 20 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6299 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 82861 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 165274 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 591272 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93252 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 268680120 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 282241162 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1109289 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 302073229 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 316163964 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1170952288 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51809007 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38459231 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 90268238 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6463131 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4201410 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 10664541 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2358483918 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3163514299 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5521998217 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 591272 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93252 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 268680120 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2640725080 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1109289 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 302073229 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3479678263 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6692950505 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 591272 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93252 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 268680120 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2640725080 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1109289 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 302073229 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3479678263 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6692950505 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5299167 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12406738561 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2100314 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667521253 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167081659295 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050184240 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25918449225 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 26968633465 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5299167 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13456922801 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2100314 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180585970478 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 194050292760 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000507 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000471 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015975 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036566 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000655 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010534 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030688 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017631 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.815777 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.837332 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.824797 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.762130 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.745098 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.755334 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569238 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564930 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.566875 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000507 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000471 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015975 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.245259 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000655 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010534 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.243788 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.098597 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000507 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000471 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015975 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.245259 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000655 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010534 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.243788 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.098597 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 53752 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42892.739464 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44580.818512 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 55464.450000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47955.743610 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 50424.874641 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 46471.893003 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10060.001359 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10110.207939 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10081.331025 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.917702 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10051.220096 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10041.940678 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37149.669502 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41303.995234 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 39421.162768 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 53752 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42892.739464 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37823.525502 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 55464.450000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47955.743610 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41994.162067 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40496.088344 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53752 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42892.739464 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37823.525502 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55464.450000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47955.743610 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41994.162067 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40496.088344 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 6266 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 69654 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 17 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 6295 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 83200 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 165448 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 591261 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 205753 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 267326853 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 290309543 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1171267 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 56251 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 299283802 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 313561196 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1172505926 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51651498 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38386206 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 90037704 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6474116 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4151410 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10625526 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2358673626 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3165005465 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5523679091 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 591261 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 205753 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 267326853 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2648983169 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1171267 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 56251 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 299283802 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3478566661 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6696185017 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 591261 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 205753 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 267326853 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2648983169 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1171267 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 56251 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 299283802 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3478566661 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6696185017 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5299085 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12408173048 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2100282 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667335749 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167082908164 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050136738 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25922783304 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 26972920042 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5299085 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13458309786 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2100282 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180590119053 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 194055828206 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000501 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000899 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015949 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036849 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000561 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010549 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030747 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017672 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.806816 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836622 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.819176 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.763095 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.743268 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.755190 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566577 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567568 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567120 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000501 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000899 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015949 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244624 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000561 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010549 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244934 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098720 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000501 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000899 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015949 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244624 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000561 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010549 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244934 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098720 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45524.469657 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49953.990123 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 46439.556638 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10054.798131 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10171.225755 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10104.107732 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10100.024961 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.560386 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10071.588626 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37275.370609 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41145.112190 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39398.566983 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38030.596506 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41809.695445 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40473.049037 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38030.596506 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41809.695445 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40473.049037 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -663,38 +678,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 5998436 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4575399 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 294209 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3753379 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2912017 # Number of BTB hits +system.cpu0.branchPred.lookups 6001263 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4576664 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 295188 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3775279 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2913941 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.583878 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 673016 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28669 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.184786 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 673658 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28611 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8902974 # DTB read hits -system.cpu0.dtb.read_misses 28685 # DTB read misses -system.cpu0.dtb.write_hits 5134917 # DTB write hits -system.cpu0.dtb.write_misses 5599 # DTB write misses +system.cpu0.dtb.read_hits 8907872 # DTB read hits +system.cpu0.dtb.read_misses 28815 # DTB read misses +system.cpu0.dtb.write_hits 5138143 # DTB write hits +system.cpu0.dtb.write_misses 5606 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 1816 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1018 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 297 # Number of TLB faults due to prefetch +system.cpu0.dtb.align_faults 1053 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8931659 # DTB read accesses -system.cpu0.dtb.write_accesses 5140516 # DTB write accesses +system.cpu0.dtb.perms_faults 532 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8936687 # DTB read accesses +system.cpu0.dtb.write_accesses 5143749 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14037891 # DTB hits -system.cpu0.dtb.misses 34284 # DTB misses -system.cpu0.dtb.accesses 14072175 # DTB accesses -system.cpu0.itb.inst_hits 4215172 # ITB inst hits -system.cpu0.itb.inst_misses 5141 # ITB inst misses +system.cpu0.dtb.hits 14046015 # DTB hits +system.cpu0.dtb.misses 34421 # DTB misses +system.cpu0.dtb.accesses 14080436 # DTB accesses +system.cpu0.itb.inst_hits 4220167 # ITB inst hits +system.cpu0.itb.inst_misses 5223 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -703,148 +718,148 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1342 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1350 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1479 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1535 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4220313 # ITB inst accesses -system.cpu0.itb.hits 4215172 # DTB hits -system.cpu0.itb.misses 5141 # DTB misses -system.cpu0.itb.accesses 4220313 # DTB accesses -system.cpu0.numCycles 67779631 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4225390 # ITB inst accesses +system.cpu0.itb.hits 4220167 # DTB hits +system.cpu0.itb.misses 5223 # DTB misses +system.cpu0.itb.accesses 4225390 # DTB accesses +system.cpu0.numCycles 67827032 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11746060 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 31992288 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 5998436 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3585033 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7509031 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1449341 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 60597 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20626968 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4901 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 47542 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 85433 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 195 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4213506 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157466 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2283 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41121561 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.005038 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.385329 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11757994 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32012326 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6001263 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3587599 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7516289 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1452567 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 61154 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20647681 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4894 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 47403 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 85456 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4218433 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 158199 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2369 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41163993 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.004932 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.385225 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33620027 81.76% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 564307 1.37% 83.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 815894 1.98% 85.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 676094 1.64% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 772709 1.88% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 559273 1.36% 90.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 668674 1.63% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 351557 0.85% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3093026 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33655210 81.76% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 565659 1.37% 83.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 816805 1.98% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 675504 1.64% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 773580 1.88% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 559421 1.36% 90.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 670235 1.63% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 352235 0.86% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3095344 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41121561 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088499 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.472004 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12250531 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20568387 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6812697 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 512769 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 977177 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 933938 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64793 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 39972827 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213127 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 977177 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12817507 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5739937 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12718334 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6708425 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2160181 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38878118 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1834 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 434730 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1233458 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 20 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39234243 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175587138 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175552572 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34566 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30916046 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8318196 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 410984 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370136 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5348015 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7641998 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5680264 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1129998 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1207028 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36802265 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895658 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37215076 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 80061 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6274404 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13150521 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 257091 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41121561 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.905002 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.512830 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41163993 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088479 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.471970 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12263422 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20589298 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6819290 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 512710 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 979273 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 935723 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64727 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40009195 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 212284 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 979273 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12830808 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5739819 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12737837 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6714966 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2161290 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38908996 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1807 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 435519 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1234283 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 23 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39260907 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175730932 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175696732 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34200 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30930361 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8330545 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411120 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370260 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5349265 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7648868 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5685535 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1126587 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1232322 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36830553 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895643 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37237747 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80326 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6284476 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13189556 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256860 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41163993 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.904619 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.512118 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 25997548 63.22% 63.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5725018 13.92% 77.14% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3161670 7.69% 84.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2471559 6.01% 90.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2093564 5.09% 95.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 947248 2.30% 98.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 486513 1.18% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 185061 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53380 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26023978 63.22% 63.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5734172 13.93% 77.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3165060 7.69% 84.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2475453 6.01% 90.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2094791 5.09% 95.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 945417 2.30% 98.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 488035 1.19% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 184059 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53028 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41121561 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41163993 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 25811 2.41% 2.41% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 454 0.04% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 841861 78.66% 81.12% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 202059 18.88% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 25953 2.43% 2.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 456 0.04% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 841491 78.81% 81.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 199811 18.71% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22315653 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46928 0.13% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22327853 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46961 0.13% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued @@ -872,361 +887,361 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9358800 25.15% 85.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5440823 14.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9364731 25.15% 85.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5445265 14.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37215076 # Type of FU issued -system.cpu0.iq.rate 0.549060 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1070185 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028757 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 116727564 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 43980171 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34315180 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8451 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4750 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3900 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38228693 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4419 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 306291 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37237747 # Type of FU issued +system.cpu0.iq.rate 0.549010 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1067711 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028673 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 116813355 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44018555 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34334136 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8379 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3876 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38248858 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4386 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 306561 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1370106 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2445 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13123 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 533688 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1372448 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2379 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13100 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 535058 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192694 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5412 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192712 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5628 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 977177 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4122288 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 97984 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37816345 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 85218 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7641998 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5680264 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571541 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39816 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2781 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13123 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 149547 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 116915 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 266462 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36841770 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9218382 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 373306 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 979273 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4122692 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 98715 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37844885 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 85302 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7648868 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5685535 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571530 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40279 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2826 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13100 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150418 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117037 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 267455 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36861439 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9223512 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 376308 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118422 # number of nop insts executed -system.cpu0.iew.exec_refs 14612857 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4852888 # Number of branches executed -system.cpu0.iew.exec_stores 5394475 # Number of stores executed -system.cpu0.iew.exec_rate 0.543552 # Inst execution rate -system.cpu0.iew.wb_sent 36648414 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34319080 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18273947 # num instructions producing a value -system.cpu0.iew.wb_consumers 35157700 # num instructions consuming a value +system.cpu0.iew.exec_nop 118689 # number of nop insts executed +system.cpu0.iew.exec_refs 14621351 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4854206 # Number of branches executed +system.cpu0.iew.exec_stores 5397839 # Number of stores executed +system.cpu0.iew.exec_rate 0.543462 # Inst execution rate +system.cpu0.iew.wb_sent 36666981 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34338012 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18281082 # num instructions producing a value +system.cpu0.iew.wb_consumers 35173096 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.506333 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.519771 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.506259 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.519746 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6086541 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638567 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 230552 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40144384 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.778927 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.740713 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6098128 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638783 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 231564 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40184720 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.778562 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.740417 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28480985 70.95% 70.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5711149 14.23% 85.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1913332 4.77% 89.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 974787 2.43% 92.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 784907 1.96% 94.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 524754 1.31% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 386537 0.96% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 218696 0.54% 97.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1149237 2.86% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28508400 70.94% 70.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5724488 14.25% 85.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1913763 4.76% 89.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 974414 2.42% 92.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 785086 1.95% 94.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 523080 1.30% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 385100 0.96% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 218421 0.54% 97.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1151968 2.87% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40144384 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23670531 # Number of instructions committed -system.cpu0.commit.committedOps 31269562 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40184720 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23679748 # Number of instructions committed +system.cpu0.commit.committedOps 31286291 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11418468 # Number of memory references committed -system.cpu0.commit.loads 6271892 # Number of loads committed -system.cpu0.commit.membars 229609 # Number of memory barriers committed -system.cpu0.commit.branches 4243643 # Number of branches committed +system.cpu0.commit.refs 11426897 # Number of memory references committed +system.cpu0.commit.loads 6276420 # Number of loads committed +system.cpu0.commit.membars 229667 # Number of memory barriers committed +system.cpu0.commit.branches 4245051 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27627358 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489165 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1149237 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27642937 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489354 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1151968 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75500320 # The number of ROB reads -system.cpu0.rob.rob_writes 75691570 # The number of ROB writes -system.cpu0.timesIdled 360084 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26658070 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2138053443 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23589789 # Number of Instructions Simulated -system.cpu0.committedOps 31188820 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23589789 # Number of Instructions Simulated -system.cpu0.cpi 2.873261 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.873261 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.348037 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.348037 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171728285 # number of integer regfile reads -system.cpu0.int_regfile_writes 34072180 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3295 # number of floating regfile reads +system.cpu0.rob.rob_reads 75566033 # The number of ROB reads +system.cpu0.rob.rob_writes 75750322 # The number of ROB writes +system.cpu0.timesIdled 360462 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26663039 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2138032042 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23599006 # Number of Instructions Simulated +system.cpu0.committedOps 31205549 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23599006 # Number of Instructions Simulated +system.cpu0.cpi 2.874148 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.874148 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.347929 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.347929 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171822030 # number of integer regfile reads +system.cpu0.int_regfile_writes 34087122 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3256 # number of floating regfile reads system.cpu0.fp_regfile_writes 900 # number of floating regfile writes -system.cpu0.misc_regfile_reads 12998314 # number of misc regfile reads -system.cpu0.misc_regfile_writes 450987 # number of misc regfile writes -system.cpu0.icache.replacements 392135 # number of replacements -system.cpu0.icache.tagsinuse 511.076170 # Cycle average of tags in use -system.cpu0.icache.total_refs 3790159 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 392647 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.652841 # Average number of references to valid blocks. +system.cpu0.misc_regfile_reads 13007989 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451063 # number of misc regfile writes +system.cpu0.icache.replacements 392871 # number of replacements +system.cpu0.icache.tagsinuse 511.076375 # Cycle average of tags in use +system.cpu0.icache.total_refs 3794104 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 393383 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.644809 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6563458000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.076170 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 511.076375 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.998196 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.998196 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3790159 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3790159 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3790159 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3790159 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3790159 # number of overall hits -system.cpu0.icache.overall_hits::total 3790159 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 423214 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 423214 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 423214 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 423214 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 423214 # number of overall misses -system.cpu0.icache.overall_misses::total 423214 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5793685997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5793685997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5793685997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5793685997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5793685997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5793685997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4213373 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4213373 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4213373 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4213373 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4213373 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4213373 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100445 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100445 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100445 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100445 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100445 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100445 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13689.731429 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13689.731429 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13689.731429 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13689.731429 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13689.731429 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13689.731429 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2401 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 3794104 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3794104 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3794104 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3794104 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3794104 # number of overall hits +system.cpu0.icache.overall_hits::total 3794104 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 424196 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 424196 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 424196 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 424196 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 424196 # number of overall misses +system.cpu0.icache.overall_misses::total 424196 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5806369997 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5806369997 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5806369997 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5806369997 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5806369997 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5806369997 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4218300 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4218300 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4218300 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4218300 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4218300 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4218300 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100561 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100561 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100561 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100561 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100561 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100561 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13687.941416 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13687.941416 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13687.941416 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13687.941416 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13687.941416 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13687.941416 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2612 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 146 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.445205 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.071895 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30547 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30547 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30547 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30547 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30547 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30547 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 392667 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 392667 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 392667 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 392667 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 392667 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 392667 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4739152997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4739152997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4739152997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4739152997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4739152997 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4739152997 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30799 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30799 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30799 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30799 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30799 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30799 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393397 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 393397 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 393397 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 393397 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 393397 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 393397 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4747932997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4747932997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4747932997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4747932997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4747932997 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4747932997 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7900500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7900500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7900500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7900500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093195 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093195 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093195 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093195 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093195 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093195 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12069.140002 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12069.140002 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12069.140002 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12069.140002 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12069.140002 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12069.140002 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093260 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093260 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093260 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12069.062542 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12069.062542 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12069.062542 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 276137 # number of replacements -system.cpu0.dcache.tagsinuse 461.136878 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9254727 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276649 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.452957 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 43495000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 461.136878 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.900658 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.900658 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5777010 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5777010 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3157960 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3157960 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139054 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139054 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137010 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137010 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8934970 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8934970 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8934970 # number of overall hits -system.cpu0.dcache.overall_hits::total 8934970 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 392909 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 392909 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1581686 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1581686 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8773 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8773 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7509 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7509 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1974595 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1974595 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1974595 # number of overall misses -system.cpu0.dcache.overall_misses::total 1974595 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5473319500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5473319500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60618366371 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 60618366371 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87499000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 87499000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46786000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 46786000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 66091685871 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 66091685871 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 66091685871 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 66091685871 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6169919 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6169919 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4739646 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4739646 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147827 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 147827 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144519 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144519 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10909565 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10909565 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10909565 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10909565 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063681 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063681 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333714 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.333714 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059346 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059346 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051959 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051959 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180997 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.180997 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180997 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.180997 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13930.247207 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13930.247207 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38325.158325 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38325.158325 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9973.669212 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9973.669212 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6230.656545 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6230.656545 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33471.008420 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33471.008420 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33471.008420 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33471.008420 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9022 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2690 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 641 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 80 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.074883 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 33.625000 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 276008 # number of replacements +system.cpu0.dcache.tagsinuse 460.701040 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9261257 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276520 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.492178 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 43509000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 460.701040 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.899807 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.899807 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5781540 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5781540 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3159285 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3159285 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139162 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139162 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137068 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137068 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8940825 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8940825 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8940825 # number of overall hits +system.cpu0.dcache.overall_hits::total 8940825 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 392645 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 392645 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1583929 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1583929 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8775 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8775 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7462 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7462 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1976574 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1976574 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1976574 # number of overall misses +system.cpu0.dcache.overall_misses::total 1976574 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5479209500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5479209500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60675943869 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60675943869 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88042500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88042500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46456500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 46456500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 66155153369 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 66155153369 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 66155153369 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 66155153369 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6174185 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6174185 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4743214 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4743214 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147937 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 147937 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144530 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144530 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10917399 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10917399 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10917399 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10917399 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063595 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063595 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333936 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333936 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059316 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059316 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051629 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051629 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181048 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.181048 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181048 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.181048 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13954.614219 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13954.614219 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38307.237174 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38307.237174 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10033.333333 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10033.333333 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6225.743768 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6225.743768 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33469.606182 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33469.606182 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33469.606182 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33469.606182 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8661 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 5567 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 621 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 82 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.946860 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 67.890244 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256527 # number of writebacks -system.cpu0.dcache.writebacks::total 256527 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204116 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 204116 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451395 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1451395 # number of WriteReq MSHR hits +system.cpu0.dcache.writebacks::writebacks 256612 # number of writebacks +system.cpu0.dcache.writebacks::total 256612 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204222 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 204222 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1453551 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1453551 # number of WriteReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 471 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 471 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1655511 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1655511 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1655511 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1655511 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188793 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188793 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130291 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130291 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8302 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8302 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7505 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7505 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319084 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319084 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319084 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319084 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2371443000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2371443000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4036122491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4036122491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 65692500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 65692500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31776000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31776000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6407565491 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6407565491 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6407565491 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6407565491 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13513513000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13513513000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180350378 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180350378 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14693863378 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14693863378 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030599 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030599 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027490 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027490 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056160 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056160 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051931 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051931 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029248 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029248 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029248 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029248 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12561.074828 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12561.074828 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30977.753575 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30977.753575 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7912.852325 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7912.852325 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4233.977348 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4233.977348 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20081.124378 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20081.124378 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20081.124378 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20081.124378 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657773 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1657773 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657773 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1657773 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188423 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188423 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130378 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130378 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8304 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8304 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7462 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7462 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 318801 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 318801 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 318801 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 318801 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2378188000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2378188000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4038291991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4038291991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66252500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66252500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31532500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31532500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6416479991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6416479991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6416479991 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6416479991 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514893000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514893000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180267878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180267878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695160878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695160878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030518 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030518 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027487 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027487 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056132 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056132 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051629 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051629 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029201 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029201 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029201 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029201 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12621.537710 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12621.537710 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30973.722492 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30973.722492 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7978.383911 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7978.383911 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4225.743768 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4225.743768 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20126.912999 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20126.912999 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20126.912999 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20126.912999 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1234,38 +1249,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9086614 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7469023 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 411441 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6087298 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5252816 # Number of BTB hits +system.cpu1.branchPred.lookups 9071093 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7457126 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 408382 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6063336 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5242542 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 86.291422 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 771111 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 43004 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 86.462997 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 772870 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42976 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42908069 # DTB read hits -system.cpu1.dtb.read_misses 37093 # DTB read misses -system.cpu1.dtb.write_hits 6828111 # DTB write hits -system.cpu1.dtb.write_misses 10566 # DTB write misses +system.cpu1.dtb.read_hits 42899284 # DTB read hits +system.cpu1.dtb.read_misses 36667 # DTB read misses +system.cpu1.dtb.write_hits 6823776 # DTB write hits +system.cpu1.dtb.write_misses 10740 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2002 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2479 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 308 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2487 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 658 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42945162 # DTB read accesses -system.cpu1.dtb.write_accesses 6838677 # DTB write accesses +system.cpu1.dtb.perms_faults 676 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42935951 # DTB read accesses +system.cpu1.dtb.write_accesses 6834516 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49736180 # DTB hits -system.cpu1.dtb.misses 47659 # DTB misses -system.cpu1.dtb.accesses 49783839 # DTB accesses -system.cpu1.itb.inst_hits 8400139 # ITB inst hits -system.cpu1.itb.inst_misses 5511 # ITB inst misses +system.cpu1.dtb.hits 49723060 # DTB hits +system.cpu1.dtb.misses 47407 # DTB misses +system.cpu1.dtb.accesses 49770467 # DTB accesses +system.cpu1.itb.inst_hits 8396614 # ITB inst hits +system.cpu1.itb.inst_misses 5496 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1274,114 +1289,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1535 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1516 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1557 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8405650 # ITB inst accesses -system.cpu1.itb.hits 8400139 # DTB hits -system.cpu1.itb.misses 5511 # DTB misses -system.cpu1.itb.accesses 8405650 # DTB accesses -system.cpu1.numCycles 408778710 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8402110 # ITB inst accesses +system.cpu1.itb.hits 8396614 # DTB hits +system.cpu1.itb.misses 5496 # DTB misses +system.cpu1.itb.accesses 8402110 # DTB accesses +system.cpu1.numCycles 408759365 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19802343 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 66108771 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9086614 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6023927 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14149480 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3968467 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 63429 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77260462 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4652 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42943 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 130023 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 107 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8398224 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 741385 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2977 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114156752 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.701240 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.046062 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 19792479 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 66053661 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9071093 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6015412 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14141488 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3960570 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 63871 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77254295 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4578 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 41467 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 129632 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8394649 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 740550 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3020 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114126730 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.700802 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.045190 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 100014473 87.61% 87.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796994 0.70% 88.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 939704 0.82% 89.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1889255 1.65% 90.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1506031 1.32% 92.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 574931 0.50% 92.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2131854 1.87% 94.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410857 0.36% 94.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5892653 5.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 99992423 87.62% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 796833 0.70% 88.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 937270 0.82% 89.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1888150 1.65% 90.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1516879 1.33% 92.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 570874 0.50% 92.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2130694 1.87% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410492 0.36% 94.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5883115 5.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114156752 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022229 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.161723 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21320888 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 76914540 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12790943 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 524179 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2606202 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1106995 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98605 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 75226388 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 330391 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2606202 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22704982 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 31945118 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40735326 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11835422 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4329702 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 69763643 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18779 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 668299 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3087296 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 338 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 73772994 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 321197839 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 321138769 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59070 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49056932 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 24716062 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 445445 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 388435 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7877150 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13206045 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8148691 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1035919 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1598177 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 63545873 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1154873 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89160933 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94911 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16250476 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 45782181 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 274059 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114156752 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.781040 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.519067 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114126730 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022192 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.161595 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21309229 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 76907002 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12785223 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 523232 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2602044 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1105609 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98242 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 75190345 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 327184 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2602044 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22692364 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 31945147 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40728563 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11830258 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4328354 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 69732759 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18777 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 668377 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3086520 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 411 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 73724172 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 321062566 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 321003544 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59022 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49048322 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24675850 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444626 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 387642 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7869295 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13203135 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8142815 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1033166 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1534389 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 63494746 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1157882 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89124827 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94932 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16221194 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 45699544 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 277241 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114126730 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.780929 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.519205 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83738528 73.35% 73.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8425243 7.38% 80.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4289902 3.76% 84.49% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3781770 3.31% 87.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10587758 9.27% 97.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1962324 1.72% 98.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1024618 0.90% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 272656 0.24% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 73953 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83735089 73.37% 73.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8399712 7.36% 80.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4300489 3.77% 84.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3770900 3.30% 87.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10582685 9.27% 97.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1966579 1.72% 98.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1024954 0.90% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 272498 0.24% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 73824 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114156752 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114126730 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29608 0.38% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 998 0.01% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29743 0.38% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 996 0.01% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available @@ -1409,399 +1424,395 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7547947 95.93% 96.32% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 289296 3.68% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7545200 95.88% 96.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 293621 3.73% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 313997 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37637940 42.21% 42.57% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59271 0.07% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43972305 49.32% 91.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7175883 8.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37614506 42.20% 42.56% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59141 0.07% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43964242 49.33% 91.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7171411 8.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89160933 # Type of FU issued -system.cpu1.iq.rate 0.218115 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7867849 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088243 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 300473883 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 80959646 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53671142 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14975 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8034 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6858 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96706888 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7897 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 342362 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89124827 # Type of FU issued +system.cpu1.iq.rate 0.218037 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7869560 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088298 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300373215 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 80882348 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53634324 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14862 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8064 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6807 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96672574 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7816 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 343282 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3450901 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3895 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17010 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1308558 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3450539 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3807 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17140 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1304937 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31911884 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 888923 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31906056 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 888018 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2606202 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24177339 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 360038 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 64805263 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 113338 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13206045 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8148691 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 865764 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 64951 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3491 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17010 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 203575 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 156879 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 360454 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 86736990 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43278008 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2423943 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2602044 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24184461 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 360387 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 64757250 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 110652 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13203135 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8142815 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869312 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 65433 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3547 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17140 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 201642 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 155418 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 357060 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 86694604 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43269055 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2430223 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104517 # number of nop insts executed -system.cpu1.iew.exec_refs 50391999 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7007502 # Number of branches executed -system.cpu1.iew.exec_stores 7113991 # Number of stores executed -system.cpu1.iew.exec_rate 0.212186 # Inst execution rate -system.cpu1.iew.wb_sent 85759457 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53678000 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29917161 # num instructions producing a value -system.cpu1.iew.wb_consumers 53364078 # num instructions consuming a value +system.cpu1.iew.exec_nop 104622 # number of nop insts executed +system.cpu1.iew.exec_refs 50378581 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7000416 # Number of branches executed +system.cpu1.iew.exec_stores 7109526 # Number of stores executed +system.cpu1.iew.exec_rate 0.212092 # Inst execution rate +system.cpu1.iew.wb_sent 85717179 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53641131 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29911901 # num instructions producing a value +system.cpu1.iew.wb_consumers 53368558 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131313 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560624 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131229 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560478 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 16174786 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880814 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 314330 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111550550 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.431692 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.400024 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 16124623 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880641 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 311654 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111524686 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.431704 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.400261 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94808427 84.99% 84.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8234297 7.38% 92.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2114478 1.90% 94.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1250833 1.12% 95.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1245005 1.12% 96.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 571421 0.51% 97.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1000699 0.90% 97.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 504697 0.45% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1820693 1.63% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94788278 84.99% 84.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8230770 7.38% 92.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2113389 1.89% 94.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1254382 1.12% 95.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1243785 1.12% 96.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 567669 0.51% 97.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 997860 0.89% 97.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 504120 0.45% 98.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1824433 1.64% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111550550 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38064892 # Number of instructions committed -system.cpu1.commit.committedOps 48155494 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111524686 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38058920 # Number of instructions committed +system.cpu1.commit.committedOps 48145643 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16595277 # Number of memory references committed -system.cpu1.commit.loads 9755144 # Number of loads committed -system.cpu1.commit.membars 190149 # Number of memory barriers committed -system.cpu1.commit.branches 5967637 # Number of branches committed -system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42690457 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534638 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1820693 # number cycles where commit BW limit reached +system.cpu1.commit.refs 16590474 # Number of memory references committed +system.cpu1.commit.loads 9752596 # Number of loads committed +system.cpu1.commit.membars 190088 # Number of memory barriers committed +system.cpu1.commit.branches 5966646 # Number of branches committed +system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 42681359 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534484 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1824433 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 173015978 # The number of ROB reads -system.cpu1.rob.rob_writes 131360292 # The number of ROB writes -system.cpu1.timesIdled 1408221 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 294621958 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1796461003 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37995253 # Number of Instructions Simulated -system.cpu1.committedOps 48085855 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37995253 # Number of Instructions Simulated -system.cpu1.cpi 10.758678 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.758678 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092948 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092948 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 388090475 # number of integer regfile reads -system.cpu1.int_regfile_writes 56232580 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4956 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18472941 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405527 # number of misc regfile writes -system.cpu1.icache.replacements 597992 # number of replacements -system.cpu1.icache.tagsinuse 480.750463 # Cycle average of tags in use -system.cpu1.icache.total_refs 7754983 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 598504 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 12.957278 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74232640500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 480.750463 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.938966 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.938966 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7754983 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7754983 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7754983 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7754983 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7754983 # number of overall hits -system.cpu1.icache.overall_hits::total 7754983 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 643188 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 643188 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 643188 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 643188 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 643188 # number of overall misses -system.cpu1.icache.overall_misses::total 643188 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8662129496 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8662129496 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8662129496 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8662129496 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8662129496 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8662129496 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8398171 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8398171 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8398171 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8398171 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8398171 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8398171 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076587 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.076587 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076587 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.076587 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076587 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.076587 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13467.492391 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13467.492391 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13467.492391 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13467.492391 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13467.492391 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13467.492391 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2692 # number of cycles access was blocked +system.cpu1.rob.rob_reads 172926580 # The number of ROB reads +system.cpu1.rob.rob_writes 131236338 # The number of ROB writes +system.cpu1.timesIdled 1408486 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 294632635 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1796502635 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37989281 # Number of Instructions Simulated +system.cpu1.committedOps 48076004 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37989281 # Number of Instructions Simulated +system.cpu1.cpi 10.759861 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.759861 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092938 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092938 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 387915275 # number of integer regfile reads +system.cpu1.int_regfile_writes 56205449 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4899 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2328 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18464839 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405417 # number of misc regfile writes +system.cpu1.icache.replacements 596801 # number of replacements +system.cpu1.icache.tagsinuse 480.742161 # Cycle average of tags in use +system.cpu1.icache.total_refs 7752714 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 597313 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 12.979316 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74225092500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 480.742161 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.938950 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.938950 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7752714 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7752714 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7752714 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7752714 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7752714 # number of overall hits +system.cpu1.icache.overall_hits::total 7752714 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 641884 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 641884 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 641884 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 641884 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 641884 # number of overall misses +system.cpu1.icache.overall_misses::total 641884 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8651274491 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8651274491 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8651274491 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8651274491 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8651274491 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8651274491 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8394598 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8394598 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8394598 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8394598 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8394598 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8394598 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076464 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.076464 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076464 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.076464 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076464 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.076464 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13477.940704 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13477.940704 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13477.940704 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13477.940704 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13477.940704 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13477.940704 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2229 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 184 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 165 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.630435 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.509091 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44654 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44654 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44654 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44654 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44654 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44654 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 598534 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 598534 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 598534 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 598534 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 598534 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 598534 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7093435997 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7093435997 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7093435997 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7093435997 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7093435997 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7093435997 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44542 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44542 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44542 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44542 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44542 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44542 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597342 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 597342 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 597342 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 597342 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 597342 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 597342 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7075238492 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7075238492 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7075238492 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7075238492 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7075238492 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7075238492 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3098500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3098500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3098500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 3098500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071270 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071270 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071270 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071270 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071270 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071270 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11851.350127 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11851.350127 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11851.350127 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11851.350127 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11851.350127 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11851.350127 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071158 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.071158 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071158 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11844.535445 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11844.535445 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11844.535445 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 360685 # number of replacements -system.cpu1.dcache.tagsinuse 474.635478 # Cycle average of tags in use -system.cpu1.dcache.total_refs 12674649 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 361036 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 35.106330 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 70356699000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 474.635478 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.927022 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.927022 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8306809 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8306809 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4139176 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4139176 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97757 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 97757 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94875 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 94875 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12445985 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12445985 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12445985 # number of overall hits -system.cpu1.dcache.overall_hits::total 12445985 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 399972 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 399972 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1557467 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1557467 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14022 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14022 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10623 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10623 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1957439 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1957439 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1957439 # number of overall misses -system.cpu1.dcache.overall_misses::total 1957439 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6115655000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6115655000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61487432499 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 61487432499 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129927000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 129927000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53882500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 53882500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 67603087499 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 67603087499 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 67603087499 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 67603087499 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8706781 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8706781 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5696643 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5696643 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111779 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 111779 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105498 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 105498 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14403424 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14403424 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14403424 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14403424 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045938 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045938 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273401 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.273401 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125444 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125444 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100694 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100694 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135901 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135901 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135901 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135901 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15290.207815 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15290.207815 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39479.123795 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 39479.123795 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9265.939238 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9265.939238 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5072.248894 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5072.248894 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34536.497689 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 34536.497689 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34536.497689 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 34536.497689 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 30853 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 12637 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3329 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 157 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.267948 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 80.490446 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 360372 # number of replacements +system.cpu1.dcache.tagsinuse 474.682760 # Cycle average of tags in use +system.cpu1.dcache.total_refs 12670584 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 360741 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.123770 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 70354132000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 474.682760 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.927115 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.927115 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8303637 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8303637 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4137955 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4137955 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97570 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 97570 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94868 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 94868 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12441592 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12441592 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12441592 # number of overall hits +system.cpu1.dcache.overall_hits::total 12441592 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 400129 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 400129 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1556605 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1556605 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13952 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13952 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10604 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10604 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1956734 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1956734 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1956734 # number of overall misses +system.cpu1.dcache.overall_misses::total 1956734 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6110776000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6110776000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61798994997 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 61798994997 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 128780500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 128780500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53871000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 53871000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 67909770997 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 67909770997 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 67909770997 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 67909770997 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8703766 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8703766 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5694560 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5694560 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111522 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111522 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105472 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105472 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14398326 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14398326 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14398326 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14398326 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045972 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045972 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273349 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273349 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125105 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125105 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100539 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100539 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135900 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135900 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135900 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135900 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15272.014775 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15272.014775 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39701.141264 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39701.141264 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9230.253727 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9230.253727 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5080.252735 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5080.252735 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34705.673330 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 34705.673330 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34705.673330 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 34705.673330 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 24403 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 13534 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3330 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 160 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.328228 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 84.587500 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324651 # number of writebacks -system.cpu1.dcache.writebacks::total 324651 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171732 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 171732 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395801 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1395801 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1444 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1444 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1567533 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1567533 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1567533 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1567533 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228240 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 228240 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161666 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161666 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12578 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12578 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10618 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10618 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389906 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389906 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389906 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389906 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2856522500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2856522500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5131083207 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5131083207 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89046000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89046000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32648500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32648500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7987605707 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7987605707 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7987605707 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7987605707 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168990252000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168990252000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35686741676 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35686741676 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204676993676 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204676993676 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026214 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026214 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028379 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028379 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112526 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112526 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100646 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100646 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027070 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027070 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027070 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027070 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12515.433316 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12515.433316 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31738.789894 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31738.789894 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7079.503896 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7079.503896 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3074.825768 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3074.825768 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20485.977920 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20485.977920 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20485.977920 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20485.977920 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324455 # number of writebacks +system.cpu1.dcache.writebacks::total 324455 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172117 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 172117 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395143 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1395143 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1446 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1446 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1567260 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1567260 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1567260 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1567260 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228012 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228012 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161462 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161462 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12506 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12506 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10600 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10600 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389474 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389474 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389474 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389474 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2852988500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2852988500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5131820706 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5131820706 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87942500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87942500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32671000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32671000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7984809206 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7984809206 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7984809206 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7984809206 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989984000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989984000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35691030962 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35691030962 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204681014962 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204681014962 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026197 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026197 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028354 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028354 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112139 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112139 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100501 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100501 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027050 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027050 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.448906 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.448906 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31783.458064 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31783.458064 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7032.024628 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7032.024628 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3082.169811 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3082.169811 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20501.520528 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20501.520528 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20501.520528 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20501.520528 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1823,18 +1834,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540120016505 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 540120016505 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540120016505 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 540120016505 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540140520228 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 540140520228 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540140520228 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 540140520228 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41707 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41725 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48866 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48857 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 5e631440d..21b68a213 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,153 +1,128 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.533148 # Number of seconds simulated -sim_ticks 2533147650000 # Number of ticks simulated -final_tick 2533147650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.533144 # Number of seconds simulated +sim_ticks 2533143504000 # Number of ticks simulated +final_tick 2533143504000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66149 # Simulator instruction rate (inst/s) -host_op_rate 85115 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2778505291 # Simulator tick rate (ticks/s) -host_mem_usage 406592 # Number of bytes of host memory used -host_seconds 911.69 # Real time elapsed on the host -sim_insts 60307315 # Number of instructions simulated -sim_ops 77598799 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 80573 # Simulator instruction rate (inst/s) +host_op_rate 103675 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3384348477 # Simulator tick rate (ticks/s) +host_mem_usage 408856 # Number of bytes of host memory used +host_seconds 748.49 # Real time elapsed on the host +sim_insts 60307579 # Number of instructions simulated +sim_ops 77599125 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 795840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093648 # Number of bytes read from this memory -system.physmem.bytes_read::total 129429904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 795840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 795840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3782016 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093520 # Number of bytes read from this memory +system.physmem.bytes_read::total 129430672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3782592 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6798088 # Number of bytes written to this memory +system.physmem.bytes_written::total 6798664 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12435 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096808 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59094 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12449 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142120 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096820 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59103 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813112 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47189379 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813121 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47189456 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589861 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51094497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493010 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683652 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47189379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51094883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314525 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314525 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493240 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190644 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683884 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47189456 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096808 # Total number of read requests seen -system.physmem.writeReqs 813112 # Total number of write requests seen -system.physmem.cpureqs 218335 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966195712 # Total number of bytes read from memory -system.physmem.bytesWritten 52039168 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129429904 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6798088 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 295 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4677 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943938 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943447 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943391 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943143 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943273 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943781 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943299 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943231 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943694 # Track reads on a per bank basis +system.physmem.bw_total::cpu.inst 314525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53778768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096820 # Total number of read requests seen +system.physmem.writeReqs 813121 # Total number of write requests seen +system.physmem.cpureqs 218357 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966196480 # Total number of bytes read from memory +system.physmem.bytesWritten 52039744 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129430672 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6798664 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 227 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4678 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943951 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943388 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944196 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943983 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943145 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943274 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943869 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943805 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943304 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943616 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943708 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 943087 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 942964 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943610 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50827 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50416 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50443 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50907 # Track writes on a per bank basis +system.physmem.perBankRdReqs::14 942997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943623 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50838 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50409 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50910 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 50180 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50280 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51358 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51187 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51246 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50619 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51228 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50279 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51367 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50902 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50800 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51241 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50709 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50623 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2236976 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533146526000 # Total gap between requests +system.physmem.numWrRetry 2238337 # Number of times wr buffer was full causing retry +system.physmem.totGap 2533142364000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154564 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 2990994 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59094 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4677 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1039969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 980923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2688258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649649 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108720 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16731 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 21899 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 10876 # What read queue length does an incoming req see +system.physmem.readPktSize::6 154576 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 754018 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 59103 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1040115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2676376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2687982 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649582 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157630 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16713 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16586 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 21915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 10858 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see @@ -164,15 +139,14 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2815 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 2832 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see @@ -181,31 +155,30 @@ system.physmem.wrQLenPdf::12 35353 # Wh system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32538 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 32521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 393223278963 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485615648963 # Sum of mem lat for all requests -system.physmem.totBusLat 75482565000 # Total cycles spent in databus access -system.physmem.totBankLat 16909805000 # Total cycles spent in bank access -system.physmem.avgQLat 26047.29 # Average queueing delay per request -system.physmem.avgBankLat 1120.11 # Average bank access latency per request +system.physmem.totQLat 393245939250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485641693000 # Sum of mem lat for all requests +system.physmem.totBusLat 75482965000 # Total cycles spent in databus access +system.physmem.totBankLat 16912788750 # Total cycles spent in bank access +system.physmem.avgQLat 26048.65 # Average queueing delay per request +system.physmem.avgBankLat 1120.31 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32167.41 # Average memory access latency +system.physmem.avgMemAccLat 32168.96 # Average memory access latency system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s @@ -213,50 +186,62 @@ system.physmem.avgConsumedWrBW 2.68 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 11.48 # Average write queue length over time -system.physmem.readRowHits 15020221 # Number of row buffer hits during reads -system.physmem.writeRowHits 793131 # Number of row buffer hits during writes +system.physmem.avgWrQLen 9.55 # Average write queue length over time +system.physmem.readRowHits 15020273 # Number of row buffer hits during reads +system.physmem.writeRowHits 793117 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.54 # Row buffer hit rate for writes -system.physmem.avgGap 159218.06 # Average gap between requests +system.physmem.avgGap 159217.58 # Average gap between requests +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14676489 # Number of BP lookups -system.cpu.branchPred.condPredicted 11762878 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704619 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9800840 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7950249 # Number of BTB hits +system.cpu.branchPred.lookups 14678084 # Number of BP lookups +system.cpu.branchPred.condPredicted 11764424 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705314 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9806272 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7951789 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.118037 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1398960 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72172 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.088807 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1399019 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72620 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51394402 # DTB read hits -system.cpu.dtb.read_misses 64202 # DTB read misses -system.cpu.dtb.write_hits 11700782 # DTB write hits -system.cpu.dtb.write_misses 15842 # DTB write misses +system.cpu.dtb.read_hits 51401633 # DTB read hits +system.cpu.dtb.read_misses 64365 # DTB read misses +system.cpu.dtb.write_hits 11702282 # DTB write hits +system.cpu.dtb.write_misses 15903 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3565 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2475 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3559 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2575 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 399 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1357 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51458604 # DTB read accesses -system.cpu.dtb.write_accesses 11716624 # DTB write accesses +system.cpu.dtb.perms_faults 1330 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51465998 # DTB read accesses +system.cpu.dtb.write_accesses 11718185 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63095184 # DTB hits -system.cpu.dtb.misses 80044 # DTB misses -system.cpu.dtb.accesses 63175228 # DTB accesses -system.cpu.itb.inst_hits 12330326 # ITB inst hits -system.cpu.itb.inst_misses 11351 # ITB inst misses +system.cpu.dtb.hits 63103915 # DTB hits +system.cpu.dtb.misses 80268 # DTB misses +system.cpu.dtb.accesses 63184183 # DTB accesses +system.cpu.itb.inst_hits 12333169 # ITB inst hits +system.cpu.itb.inst_misses 11311 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -265,114 +250,114 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2478 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2477 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2994 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2979 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12341677 # ITB inst accesses -system.cpu.itb.hits 12330326 # DTB hits -system.cpu.itb.misses 11351 # DTB misses -system.cpu.itb.accesses 12341677 # DTB accesses -system.cpu.numCycles 471833351 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12344480 # ITB inst accesses +system.cpu.itb.hits 12333169 # DTB hits +system.cpu.itb.misses 11311 # DTB misses +system.cpu.itb.accesses 12344480 # DTB accesses +system.cpu.numCycles 471839315 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30572359 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96029601 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14676489 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9349209 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21156129 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5298120 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 120373 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95586316 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2531 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87050 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195749 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 271 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12326631 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 900507 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5718 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151357354 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.785025 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.150266 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30570275 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96049459 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14678084 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9350808 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21162167 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5300670 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 119262 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95593563 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2640 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87521 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195771 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 307 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12329483 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 900673 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5698 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151369698 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.785111 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.150333 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130216652 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1302204 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1711626 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2495193 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2215033 1.46% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1107976 0.73% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2757688 1.82% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745754 0.49% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8805228 5.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130222829 86.03% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1303268 0.86% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1713149 1.13% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2496945 1.65% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2215858 1.46% 91.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107759 0.73% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2757122 1.82% 93.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745476 0.49% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8807292 5.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151357354 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031105 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203524 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32536934 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95207461 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19182239 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 963280 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3467440 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1956290 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171623 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112620131 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 567256 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3467440 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34479585 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36699027 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52520178 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18147266 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6043858 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106106757 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20523 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1005521 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4063485 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 592 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110532069 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485468581 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485377824 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90757 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78389582 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32142486 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830463 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737014 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12171984 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20324763 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13518088 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1981188 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2478536 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97936678 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983499 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124321529 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167156 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21750573 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 57066044 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501117 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151357354 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821378 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.534899 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151369698 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031108 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.203564 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32533087 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95216874 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19187667 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 962846 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3469224 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1957624 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171486 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112641564 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 566291 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3469224 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34475717 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36705773 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52523534 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18152425 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6043025 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106121315 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20520 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004083 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4063852 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 628 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110544866 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485535846 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485445234 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90612 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78389874 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32154991 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830680 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 737251 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12167564 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20329502 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13519419 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1975005 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2483431 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97943833 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983956 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124335595 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167777 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21753420 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 57059209 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501571 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151369698 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.821403 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.534931 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107117235 70.77% 70.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13550856 8.95% 79.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7067177 4.67% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5940673 3.92% 88.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12604400 8.33% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2784028 1.84% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1701066 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 465188 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126731 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107127102 70.77% 70.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13547292 8.95% 79.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7070046 4.67% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5943115 3.93% 88.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12603566 8.33% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2786171 1.84% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1700250 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 465001 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127155 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151357354 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151369698 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61039 0.69% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 60916 0.69% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available @@ -400,13 +385,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8364044 94.63% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413790 4.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365801 94.64% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413031 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58631158 47.16% 47.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93232 0.07% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58634354 47.16% 47.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93273 0.08% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.53% # Type of FU issued @@ -419,11 +404,11 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.53% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.53% # Type of FU issued @@ -432,351 +417,351 @@ system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.53% # Ty system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 18 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52911235 42.56% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12320074 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52919784 42.56% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12322346 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124321529 # Type of FU issued -system.cpu.iq.rate 0.263486 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8838876 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071097 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409062941 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121687155 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85967434 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23205 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12488 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10289 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132784424 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12315 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 622437 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124335595 # Type of FU issued +system.cpu.iq.rate 0.263513 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839750 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071096 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409105295 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121697619 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85975011 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23030 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12486 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10280 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132799466 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12213 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624029 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4670323 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6258 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30023 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1786078 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4674977 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6508 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30066 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1787339 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107730 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 893047 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107736 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 893802 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3467440 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27945377 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 433355 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100140842 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 200439 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20324763 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13518088 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1411116 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 112674 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3579 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30023 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350481 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268612 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619093 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121545908 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52081707 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2775621 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3469224 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27949054 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 432986 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100148718 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 201036 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20329502 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13519419 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1411238 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 112362 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3588 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30066 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350846 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269150 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619996 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121555637 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52088672 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2779958 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 220665 # number of nop insts executed -system.cpu.iew.exec_refs 64294282 # number of memory reference insts executed -system.cpu.iew.exec_branches 11561887 # Number of branches executed -system.cpu.iew.exec_stores 12212575 # Number of stores executed -system.cpu.iew.exec_rate 0.257603 # Inst execution rate -system.cpu.iew.wb_sent 120387103 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85977723 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47219839 # num instructions producing a value -system.cpu.iew.wb_consumers 88163371 # num instructions consuming a value +system.cpu.iew.exec_nop 220929 # number of nop insts executed +system.cpu.iew.exec_refs 64302587 # number of memory reference insts executed +system.cpu.iew.exec_branches 11562998 # Number of branches executed +system.cpu.iew.exec_stores 12213915 # Number of stores executed +system.cpu.iew.exec_rate 0.257621 # Inst execution rate +system.cpu.iew.wb_sent 120394624 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85985291 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47225460 # num instructions producing a value +system.cpu.iew.wb_consumers 88174567 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182221 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535595 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182234 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535590 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21484846 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482382 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535483 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147889914 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525723 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.514974 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21490031 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482385 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 536346 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147900474 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.525688 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.515007 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120439692 81.44% 81.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13316642 9.00% 90.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3906186 2.64% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2120970 1.43% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1946250 1.32% 95.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 970441 0.66% 96.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1598227 1.08% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 701359 0.47% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2890147 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120451739 81.44% 81.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13317188 9.00% 90.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3905098 2.64% 93.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2119368 1.43% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1946193 1.32% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 968094 0.65% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1600636 1.08% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 702304 0.47% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2889854 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147889914 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60457696 # Number of instructions committed -system.cpu.commit.committedOps 77749180 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147900474 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60457960 # Number of instructions committed +system.cpu.commit.committedOps 77749506 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386450 # Number of memory references committed -system.cpu.commit.loads 15654440 # Number of loads committed -system.cpu.commit.membars 403595 # Number of memory barriers committed -system.cpu.commit.branches 9961299 # Number of branches committed +system.cpu.commit.refs 27386605 # Number of memory references committed +system.cpu.commit.loads 15654525 # Number of loads committed +system.cpu.commit.membars 403599 # Number of memory barriers committed +system.cpu.commit.branches 9961316 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68854449 # Number of committed integer instructions. -system.cpu.commit.function_calls 991256 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2890147 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68854760 # Number of committed integer instructions. +system.cpu.commit.function_calls 991257 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2889854 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242385214 # The number of ROB reads -system.cpu.rob.rob_writes 202032533 # The number of ROB writes -system.cpu.timesIdled 1770643 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320475997 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4594378908 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307315 # Number of Instructions Simulated -system.cpu.committedOps 77598799 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307315 # Number of Instructions Simulated -system.cpu.cpi 7.823816 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823816 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127815 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127815 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550300281 # number of integer regfile reads -system.cpu.int_regfile_writes 88460223 # number of integer regfile writes -system.cpu.fp_regfile_reads 8330 # number of floating regfile reads -system.cpu.fp_regfile_writes 2914 # number of floating regfile writes -system.cpu.misc_regfile_reads 30137587 # number of misc regfile reads -system.cpu.misc_regfile_writes 831885 # number of misc regfile writes -system.cpu.icache.replacements 979919 # number of replacements -system.cpu.icache.tagsinuse 511.615669 # Cycle average of tags in use -system.cpu.icache.total_refs 11266751 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980431 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.491631 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 242401590 # The number of ROB reads +system.cpu.rob.rob_writes 202045449 # The number of ROB writes +system.cpu.timesIdled 1769758 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320469617 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4594364653 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60307579 # Number of Instructions Simulated +system.cpu.committedOps 77599125 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60307579 # Number of Instructions Simulated +system.cpu.cpi 7.823881 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.823881 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127814 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127814 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550352189 # number of integer regfile reads +system.cpu.int_regfile_writes 88467762 # number of integer regfile writes +system.cpu.fp_regfile_reads 8269 # number of floating regfile reads +system.cpu.fp_regfile_writes 2928 # number of floating regfile writes +system.cpu.misc_regfile_reads 30128398 # number of misc regfile reads +system.cpu.misc_regfile_writes 831890 # number of misc regfile writes +system.cpu.icache.replacements 979593 # number of replacements +system.cpu.icache.tagsinuse 511.615707 # Cycle average of tags in use +system.cpu.icache.total_refs 11270072 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980105 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.498841 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.615669 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 511.615707 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11266751 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11266751 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11266751 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11266751 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11266751 # number of overall hits -system.cpu.icache.overall_hits::total 11266751 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059755 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059755 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059755 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059755 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059755 # number of overall misses -system.cpu.icache.overall_misses::total 1059755 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13997065496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13997065496 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13997065496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13997065496 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13997065496 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13997065496 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12326506 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12326506 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12326506 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12326506 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12326506 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12326506 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085974 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.085974 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.085974 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.085974 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.085974 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.085974 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.831523 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13207.831523 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.831523 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13207.831523 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.831523 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13207.831523 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4420 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 11270072 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11270072 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11270072 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11270072 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11270072 # number of overall hits +system.cpu.icache.overall_hits::total 11270072 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1059286 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1059286 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1059286 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1059286 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1059286 # number of overall misses +system.cpu.icache.overall_misses::total 1059286 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13991116996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13991116996 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13991116996 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13991116996 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13991116996 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13991116996 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12329358 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12329358 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12329358 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12329358 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12329358 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12329358 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085916 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.085916 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.085916 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.085916 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.085916 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.085916 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13208.063730 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13208.063730 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13208.063730 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13208.063730 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13208.063730 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13208.063730 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4509 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 308 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 15.136986 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 14.639610 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79294 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79294 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79294 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79294 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79294 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79294 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980461 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980461 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980461 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980461 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980461 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980461 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11381703997 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11381703997 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11381703997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11381703997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11381703997 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11381703997 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79147 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79147 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79147 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79147 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79147 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79147 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980139 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 980139 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 980139 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 980139 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 980139 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 980139 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11380145996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11380145996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11380145996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11380145996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11380145996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11380145996 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7553500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7553500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7553500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7553500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079541 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079541 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079541 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.079541 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079541 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.079541 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11608.522926 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11608.522926 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11608.522926 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11608.522926 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11608.522926 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11608.522926 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079496 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079496 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079496 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.079496 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079496 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.079496 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11610.747043 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11610.747043 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11610.747043 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11610.747043 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11610.747043 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11610.747043 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64335 # number of replacements -system.cpu.l2cache.tagsinuse 51343.588717 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1886166 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129730 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.539166 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2498200830000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36928.997165 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 25.134248 # Average occupied blocks per requestor +system.cpu.l2cache.replacements 64347 # number of replacements +system.cpu.l2cache.tagsinuse 51347.741462 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1885858 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129741 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.535559 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2498197510500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36929.511487 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.548284 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8156.882895 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6232.574061 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563492 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000384 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 8159.884348 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6231.796994 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.563500 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000405 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.124464 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.095102 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783441 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53181 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10674 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 967006 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387028 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1417889 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607515 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607515 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 7 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112907 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112907 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 53181 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10674 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 967006 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 499935 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1530796 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 53181 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10674 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 967006 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 499935 # number of overall hits -system.cpu.l2cache.overall_hits::total 1530796 # number of overall hits +system.cpu.l2cache.occ_percent::cpu.inst 0.124510 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.095090 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.783504 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52622 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10526 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 966687 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387256 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1417091 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607840 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607840 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 40 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 40 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 11 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 112895 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112895 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 52622 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10526 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 966687 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 500151 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1529986 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 52622 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10526 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 966687 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 500151 # number of overall hits +system.cpu.l2cache.overall_hits::total 1529986 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12329 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10702 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23074 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2920 # number of UpgradeReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12342 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10709 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23094 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2921 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2921 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133200 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133200 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133191 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133191 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12329 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143902 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156274 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12342 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143900 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156285 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12329 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143902 # number of overall misses -system.cpu.l2cache.overall_misses::total 156274 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2844500 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 12342 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143900 # number of overall misses +system.cpu.l2cache.overall_misses::total 156285 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2975000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 695710500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 632225999 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1330898999 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 476500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 476500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6732832500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6732832500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2844500 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 697957500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 634176999 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1335227499 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 522000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 522000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6733037500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6733037500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2975000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 695710500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7365058499 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8063731499 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2844500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 697957500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7367214499 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8068264999 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2975000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 695710500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7365058499 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8063731499 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53222 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10676 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 979335 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 397730 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1440963 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607515 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607515 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2963 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2963 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 10 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246107 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246107 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53222 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10676 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 979335 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 643837 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1687070 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53222 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10676 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 979335 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 643837 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1687070 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000770 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000187 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012589 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026908 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016013 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985488 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985488 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.300000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.300000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541228 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541228 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000770 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000187 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012589 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223507 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092630 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000770 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000187 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012589 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223507 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092630 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 69378.048780 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_latency::cpu.inst 697957500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7367214499 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8068264999 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52663 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10528 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 979029 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 397965 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1440185 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607840 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607840 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2961 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2961 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 14 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 14 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246086 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246086 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52663 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10528 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 979029 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 644051 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1686271 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52663 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10528 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 979029 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 644051 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1686271 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000779 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000190 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012606 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026909 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016035 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986491 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986491 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541238 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541238 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000779 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000190 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012606 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223430 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.092681 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000779 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000190 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012606 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223430 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.092681 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 72560.975610 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56428.785790 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59075.499813 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 57679.596039 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.184932 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.184932 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50546.790541 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50546.790541 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 69378.048780 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56551.409820 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59219.067980 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 57817.073655 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 178.705923 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 178.705923 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50551.745238 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50551.745238 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 72560.975610 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56428.785790 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51181.071139 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51599.955840 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 69378.048780 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56551.409820 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51196.765108 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51625.331919 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 72560.975610 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56428.785790 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51181.071139 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51599.955840 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56551.409820 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51196.765108 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51625.331919 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -785,109 +770,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59094 # number of writebacks -system.cpu.l2cache.writebacks::total 59094 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 59103 # number of writebacks +system.cpu.l2cache.writebacks::total 59103 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12316 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10640 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 22999 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12330 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10647 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23020 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2921 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2921 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133200 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133200 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133191 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133191 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12316 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143840 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156199 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12330 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143838 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156211 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12316 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143840 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156199 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2335079 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93252 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 541798119 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 497025991 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1041252441 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29202920 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29202920 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12330 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143838 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156211 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2463540 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93251 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 543887277 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 499142740 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1045586808 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29212921 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29212921 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5072736540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5072736540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2335079 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93252 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 541798119 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5569762531 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6113988981 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2335079 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93252 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 541798119 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5569762531 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6113988981 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5079407 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002423276 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007502683 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26890048041 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26890048041 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5079407 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193892471317 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193897550724 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000770 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000187 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026752 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015961 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985488 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985488 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.300000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.300000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541228 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541228 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000770 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000187 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223411 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092586 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000770 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000187 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223411 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092586 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56953.146341 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46626 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43991.402972 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46712.969079 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45273.813688 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5073016629 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5073016629 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2463540 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93251 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 543887277 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5572159369 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6118603437 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2463540 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93251 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 543887277 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5572159369 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6118603437 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5079330 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002492267 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007571597 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26903234989 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26903234989 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5079330 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193905727256 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193910806586 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026754 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015984 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986491 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986491 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541238 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541238 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223333 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092637 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223333 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092637 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44110.890268 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46881.068846 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45420.799652 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38083.607658 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38083.607658 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56953.146341 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46626 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43991.402972 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38721.930833 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39142.305527 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56953.146341 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46626 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43991.402972 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38721.930833 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39142.305527 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38088.283961 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38088.283961 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44110.890268 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38739.132698 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39168.838539 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44110.890268 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38739.132698 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39168.838539 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -897,161 +882,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643325 # number of replacements +system.cpu.dcache.replacements 643539 # number of replacements system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use -system.cpu.dcache.total_refs 21505081 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 643837 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.401437 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 21509590 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644051 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.397340 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 42249000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13751349 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13751349 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259815 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259815 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 243177 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 243177 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247604 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247604 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21011164 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21011164 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21011164 # number of overall hits -system.cpu.dcache.overall_hits::total 21011164 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737485 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737485 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2962473 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2962473 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13509 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13509 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 10 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3699958 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3699958 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3699958 # number of overall misses -system.cpu.dcache.overall_misses::total 3699958 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9781666500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9781666500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104377974730 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104377974730 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180159500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 180159500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 166000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 166000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114159641230 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114159641230 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114159641230 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114159641230 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14488834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14488834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222288 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222288 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256686 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256686 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247614 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247614 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24711122 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24711122 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24711122 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24711122 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050900 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050900 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289805 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289805 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052629 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052629 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000040 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000040 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149728 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149728 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149728 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13263.546377 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13263.546377 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35233.392753 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35233.392753 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13336.257310 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13336.257310 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16600 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16600 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30854.307327 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30854.307327 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30854.307327 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30854.307327 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29793 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 16864 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2613 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 251 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.401837 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 67.187251 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13756144 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13756144 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7259539 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7259539 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 243175 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 243175 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247602 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21015683 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21015683 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21015683 # number of overall hits +system.cpu.dcache.overall_hits::total 21015683 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737609 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737609 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2962812 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2962812 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13513 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13513 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3700421 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3700421 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3700421 # number of overall misses +system.cpu.dcache.overall_misses::total 3700421 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9797923500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9797923500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104330736229 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104330736229 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180578000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 180578000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 218000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 218000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 114128659729 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 114128659729 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 114128659729 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 114128659729 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14493753 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14493753 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222351 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222351 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256688 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256688 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247616 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247616 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24716104 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24716104 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24716104 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24716104 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050892 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050892 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289837 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289837 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052644 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052644 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000057 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149717 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149717 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149717 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149717 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13283.356765 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13283.356765 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35213.417601 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35213.417601 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13363.279805 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13363.279805 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15571.428571 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15571.428571 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30842.074383 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30842.074383 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30842.074383 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30842.074383 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29695 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 17222 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2648 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 252 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.214124 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 68.341270 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607515 # number of writebacks -system.cpu.dcache.writebacks::total 607515 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351842 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351842 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713489 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713489 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1336 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1336 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3065331 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3065331 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3065331 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3065331 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385643 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385643 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248984 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248984 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12173 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12173 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 10 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634627 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634627 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634627 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634627 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4807486000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4807486000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8182883413 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8182883413 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140770000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140770000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12990369413 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12990369413 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12990369413 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12990369413 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395639500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395639500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36729406082 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36729406082 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219125045582 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 219125045582 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026617 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026617 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047424 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047424 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12466.156523 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12466.156523 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32865.097408 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32865.097408 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11564.117309 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11564.117309 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14600 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14600 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20469.298364 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20469.298364 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20469.298364 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20469.298364 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607840 # number of writebacks +system.cpu.dcache.writebacks::total 607840 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351729 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351729 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713855 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2713855 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1338 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1338 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065584 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065584 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065584 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065584 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385880 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385880 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248957 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248957 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12175 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12175 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634837 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634837 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634837 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634837 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4811592500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4811592500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8182885914 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8182885914 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141167000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141167000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 190000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 190000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12994478414 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12994478414 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12994478414 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12994478414 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395775000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395775000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36742499011 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36742499011 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219138274011 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 219138274011 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026624 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026624 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024354 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024354 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047431 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047431 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025685 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025685 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025685 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025685 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12469.141961 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12469.141961 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32868.671755 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32868.671755 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11594.825462 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11594.825462 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13571.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13571.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20468.999781 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20468.999781 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20468.999781 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20468.999781 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1073,16 +1058,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229589046447 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229589046447 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229610747140 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229610747140 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83042 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83041 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index e69de29bb..cb0094499 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -0,0 +1,1539 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 2.401342 # Number of seconds simulated +sim_ticks 2401342466000 # Number of ticks simulated +final_tick 2401342466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 244723 # Simulator instruction rate (inst/s) +host_op_rate 314293 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9740625246 # Simulator tick rate (ticks/s) +host_mem_usage 401684 # Number of bytes of host memory used +host_seconds 246.53 # Real time elapsed on the host +sim_insts 60331304 # Number of instructions simulated +sim_ops 77482270 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 501920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7085968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 85312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 678144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 178368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1313020 # Number of bytes read from this memory +system.physmem.bytes_read::total 124662764 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 501920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 85312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 178368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 765600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3747328 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1490908 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 199452 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1325456 # Number of bytes written to this memory +system.physmem.bytes_written::total 6763144 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14045 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110752 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1333 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10596 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2787 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20530 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512442 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58552 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 372727 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 49863 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 331364 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47814534 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 209016 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2950836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 282402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 74278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 546786 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51913780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 209016 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35527 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 74278 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318822 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1560514 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 620864 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 83059 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 551965 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2816401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1560514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47814534 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 209016 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3571700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 35527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 365461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 267 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 74278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1098750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54730181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12618170 # Total number of read requests seen +system.physmem.writeReqs 398699 # Total number of write requests seen +system.physmem.cpureqs 55066 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 807562880 # Total number of bytes read from memory +system.physmem.bytesWritten 25516736 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 102918908 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2643116 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 2351 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 789127 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 788778 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 788875 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 789205 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 789031 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 788756 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 788906 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 788958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 788649 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 788041 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 788042 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 788299 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 788288 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 788136 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 788329 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 788749 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 24964 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 24827 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 24766 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 25058 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 24835 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 24655 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 24742 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 25296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 25174 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 24837 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 24777 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 24716 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 24968 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 24890 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 24969 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 25225 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 780903 # Number of times wr buffer was full causing retry +system.physmem.totGap 2400307249500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 15 # Categorize read packet sizes +system.physmem.readPktSize::3 12582912 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 35243 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 381227 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 17472 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 816053 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 792099 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 797750 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2998172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2260822 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2261142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2249570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 49283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 49193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 91349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 133522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 91347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 6979 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6956 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 2982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 17344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 17336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 17332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 17328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 17322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 17319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 17313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 17309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 14407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 14392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 14382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 14355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 14353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 14351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14347 # What write queue length does an incoming req see +system.physmem.totQLat 277225501500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 353051170250 # Sum of mem lat for all requests +system.physmem.totBusLat 63090845000 # Total cycles spent in databus access +system.physmem.totBankLat 12734823750 # Total cycles spent in bank access +system.physmem.avgQLat 21970.34 # Average queueing delay per request +system.physmem.avgBankLat 1009.24 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 27979.59 # Average memory access latency +system.physmem.avgRdBW 336.30 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 10.63 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 42.86 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 2.71 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 0.39 # Average write queue length over time +system.physmem.readRowHits 12563520 # Number of row buffer hits during reads +system.physmem.writeRowHits 392353 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.41 # Row buffer hit rate for writes +system.physmem.avgGap 184399.74 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 63278 # number of replacements +system.l2c.tagsinuse 50361.338948 # Cycle average of tags in use +system.l2c.total_refs 1750374 # Total number of references to valid blocks. +system.l2c.sampled_refs 128673 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.603273 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2374434052500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36832.479753 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5142.503015 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3774.307963 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 800.237683 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 747.699491 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.dtb.walker 9.796874 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.itb.walker 0.004225 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1464.578885 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 1588.737598 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.562019 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.078468 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.057591 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.012211 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.011409 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.dtb.walker 0.000149 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.022348 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.024242 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.768453 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 9023 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3354 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 461813 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 169129 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2581 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1136 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 133321 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 66093 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18237 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4298 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 284840 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 138220 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1292045 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597703 # number of Writeback hits +system.l2c.Writeback_hits::total 597703 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 14 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 60564 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 19513 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 33544 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113621 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 9023 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3354 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 461813 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 229693 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 2581 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1136 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 133321 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 85606 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 18237 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 4298 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 284840 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 171764 # number of demand (read+write) hits +system.l2c.demand_hits::total 1405666 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 9023 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3354 # number of overall hits +system.l2c.overall_hits::cpu0.inst 461813 # number of overall hits +system.l2c.overall_hits::cpu0.data 229693 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 2581 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1136 # number of overall hits +system.l2c.overall_hits::cpu1.inst 133321 # number of overall hits +system.l2c.overall_hits::cpu1.data 85606 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 18237 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 4298 # number of overall hits +system.l2c.overall_hits::cpu2.inst 284840 # number of overall hits +system.l2c.overall_hits::cpu2.data 171764 # number of overall hits +system.l2c.overall_hits::total 1405666 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7429 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6366 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1333 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1201 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 10 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 2787 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 2568 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21699 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1417 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 511 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 974 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2902 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 105147 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9666 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 18550 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133363 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7429 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 111513 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1333 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10867 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 10 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 2787 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 21118 # number of demand (read+write) misses +system.l2c.demand_misses::total 155062 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7429 # number of overall misses +system.l2c.overall_misses::cpu0.data 111513 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1333 # number of overall misses +system.l2c.overall_misses::cpu1.data 10867 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 10 # number of overall misses +system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu2.inst 2787 # number of overall misses +system.l2c.overall_misses::cpu2.data 21118 # number of overall misses +system.l2c.overall_misses::total 155062 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 69000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 75830000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 69208000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 884500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.itb.walker 68500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 178915500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 156399500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 481375000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 137000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 92000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 229000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 434051500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 982435000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1416486500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 69000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 75830000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 503259500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 884500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.itb.walker 68500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 178915500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1138834500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 1897861500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 69000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 75830000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 503259500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 884500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.itb.walker 68500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 178915500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1138834500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 1897861500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 9024 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3356 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 469242 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 175495 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 2582 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1136 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 134654 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 67294 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 18247 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 4299 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 287627 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 140788 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1313744 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 597703 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 597703 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1430 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 515 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 988 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2933 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu2.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 165711 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 29179 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 52094 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246984 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 9024 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3356 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 469242 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 341206 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 2582 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1136 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 134654 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 96473 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 18247 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 4299 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 287627 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 192882 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1560728 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 9024 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3356 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 469242 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 341206 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 2582 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1136 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 134654 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 96473 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 18247 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 4299 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 287627 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 192882 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1560728 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000111 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000596 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015832 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036275 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000387 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009899 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.017847 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000548 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000233 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.009690 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.018240 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016517 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990909 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992233 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.985830 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.989431 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.634520 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.331266 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.356087 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.539966 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000111 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000596 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015832 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.326820 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000387 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009899 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.112643 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000548 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.itb.walker 0.000233 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.009690 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.109487 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.099352 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000111 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000596 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015832 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.326820 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000387 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009899 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.112643 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000548 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.itb.walker 0.000233 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.009690 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.109487 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.099352 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 69000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 56886.721680 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 57625.312240 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 88450 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 68500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 64196.447793 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 60903.232087 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 22184.202037 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 268.101761 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 94.455852 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 78.911096 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 44904.976205 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52961.455526 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 10621.285514 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 56886.721680 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 46310.803350 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 88450 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.itb.walker 68500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 64196.447793 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 53927.194810 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 12239.371993 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 56886.721680 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 46310.803350 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 88450 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.itb.walker 68500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 64196.447793 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 53927.194810 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 12239.371993 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 58552 # number of writebacks +system.l2c.writebacks::total 58552 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu2.data 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu2.data 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu2.data 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 8 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1333 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1201 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 10 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 2787 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 2560 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 7893 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 511 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 974 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 1485 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 9666 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 18550 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 28216 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1333 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 10867 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 10 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 2787 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 21110 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 36109 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1333 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 10867 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 10 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 2787 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 21110 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 36109 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 56251 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 59113583 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 54211451 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 759510 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 56251 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 144190451 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 124139149 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 382526646 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5151985 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9740974 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 14892959 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 313700656 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 751148342 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1064848998 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 59113583 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 367912107 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 759510 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 56251 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 144190451 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 875287491 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1447375644 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 56251 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 59113583 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 367912107 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 759510 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 56251 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 144190451 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 875287491 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1447375644 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25246497500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26552444012 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 51798941512 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 646821363 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9787797859 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 10434619222 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25893318863 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 36340241871 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 62233560734 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009899 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017847 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000548 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000233 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009690 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018183 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.006008 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992233 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.985830 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.506308 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.331266 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.356087 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.114242 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009899 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.112643 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000548 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000233 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009690 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.109445 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.023136 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009899 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.112643 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000548 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000233 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009690 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.109445 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.023136 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 44346.273818 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45138.593672 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 75951 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 51736.796197 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 48491.855078 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 48464.037248 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10082.162427 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10028.928620 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32454.030209 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40493.172075 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 37739.190459 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44346.273818 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33855.903837 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 75951 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 56251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 51736.796197 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41463.168688 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40083.515024 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44346.273818 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33855.903837 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75951 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 56251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 51736.796197 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41463.168688 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40083.515024 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.cpu0.dtb.inst_hits 0 # ITB inst hits +system.cpu0.dtb.inst_misses 0 # ITB inst misses +system.cpu0.dtb.read_hits 8066281 # DTB read hits +system.cpu0.dtb.read_misses 6214 # DTB read misses +system.cpu0.dtb.write_hits 6622863 # DTB write hits +system.cpu0.dtb.write_misses 2042 # DTB write misses +system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5688 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 124 # Number of TLB faults due to prefetch +system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8072495 # DTB read accesses +system.cpu0.dtb.write_accesses 6624905 # DTB write accesses +system.cpu0.dtb.inst_accesses 0 # ITB inst accesses +system.cpu0.dtb.hits 14689144 # DTB hits +system.cpu0.dtb.misses 8256 # DTB misses +system.cpu0.dtb.accesses 14697400 # DTB accesses +system.cpu0.itb.inst_hits 32699803 # ITB inst hits +system.cpu0.itb.inst_misses 3478 # ITB inst misses +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2588 # Number of entries that have been flushed from TLB +system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.inst_accesses 32703281 # ITB inst accesses +system.cpu0.itb.hits 32699803 # DTB hits +system.cpu0.itb.misses 3478 # DTB misses +system.cpu0.itb.accesses 32703281 # DTB accesses +system.cpu0.numCycles 113984620 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 32203473 # Number of instructions committed +system.cpu0.committedOps 42387015 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37536520 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5136 # Number of float alu accesses +system.cpu0.num_func_calls 1187911 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4237941 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37536520 # number of integer instructions +system.cpu0.num_fp_insts 5136 # number of float instructions +system.cpu0.num_int_register_reads 191230728 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39632670 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3646 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1492 # number of times the floating registers were written +system.cpu0.num_mem_refs 15352482 # number of memory refs +system.cpu0.num_load_insts 8433499 # Number of load instructions +system.cpu0.num_store_insts 6918983 # Number of store instructions +system.cpu0.num_idle_cycles 13416591638.099268 # Number of idle cycles +system.cpu0.num_busy_cycles -13302607018.099268 # Number of busy cycles +system.cpu0.not_idle_fraction -116.705280 # Percentage of non-idle cycles +system.cpu0.idle_fraction 117.705280 # Percentage of idle cycles +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 82893 # number of quiesce instructions executed +system.cpu0.icache.replacements 892430 # number of replacements +system.cpu0.icache.tagsinuse 511.604238 # Cycle average of tags in use +system.cpu0.icache.total_refs 44287726 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 892942 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 49.597539 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 8108819000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 477.620118 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 17.749624 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 16.234496 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.932852 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.034667 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.031708 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999227 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 32232511 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 8306544 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3748671 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 44287726 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 32232511 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 8306544 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3748671 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 44287726 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 32232511 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 8306544 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3748671 # number of overall hits +system.cpu0.icache.overall_hits::total 44287726 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 469964 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 134928 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 311926 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 916818 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 469964 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 134928 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 311926 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 916818 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 469964 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 134928 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 311926 # number of overall misses +system.cpu0.icache.overall_misses::total 916818 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1820105000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4164885486 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5984990486 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1820105000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4164885486 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5984990486 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1820105000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4164885486 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5984990486 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32702475 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 8441472 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 4060597 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 45204544 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 32702475 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 8441472 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 4060597 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 45204544 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32702475 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 8441472 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 4060597 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 45204544 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014371 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015984 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076818 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.020282 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014371 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015984 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076818 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.020282 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014371 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015984 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076818 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.020282 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13489.453635 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13352.158800 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6528.002816 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13489.453635 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13352.158800 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6528.002816 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13489.453635 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13352.158800 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6528.002816 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3429 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 208 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.485577 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23868 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 23868 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 23868 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 23868 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 23868 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 23868 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 134928 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 288058 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 422986 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 134928 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 288058 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 422986 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 134928 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 288058 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 422986 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1550249000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3396275986 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4946524986 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1550249000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3396275986 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4946524986 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1550249000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3396275986 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4946524986 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015984 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070940 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009357 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015984 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070940 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009357 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015984 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070940 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009357 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11489.453635 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11790.250526 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11694.299542 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11489.453635 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11790.250526 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11694.299542 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11489.453635 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11790.250526 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11694.299542 # average overall mshr miss latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.replacements 630049 # number of replacements +system.cpu0.dcache.tagsinuse 511.997116 # Cycle average of tags in use +system.cpu0.dcache.total_refs 23214638 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 630561 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 36.815848 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 495.732545 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 9.762803 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu2.data 6.501768 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.968228 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.019068 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu2.data 0.012699 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6947999 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1896291 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4462491 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13306781 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5945013 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1350334 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2123860 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9419207 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131148 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 34213 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 72919 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 238280 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137519 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35934 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73941 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247394 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12893012 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 3246625 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6586351 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 22725988 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12893012 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 3246625 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6586351 # number of overall hits +system.cpu0.dcache.overall_hits::total 22725988 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 169124 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 65573 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 283564 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 518261 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 167141 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 29694 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 600320 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 797155 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6371 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1721 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3875 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11967 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 2 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 336265 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 95267 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 883884 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1315416 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 336265 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 95267 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 883884 # number of overall misses +system.cpu0.dcache.overall_misses::total 1315416 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 913976500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4087103500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5001080000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 729946000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18483212402 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 19213158402 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22529500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52387500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 74917000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 26000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 1643922500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 22570315902 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 24214238402 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 1643922500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 22570315902 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 24214238402 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7117123 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1961864 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4746055 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13825042 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6112154 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1380028 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2724180 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10216362 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137519 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35934 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 76794 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 250247 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137519 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35934 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73943 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247396 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13229277 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 3341892 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7470235 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24041404 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13229277 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 3341892 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7470235 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24041404 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023763 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033424 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059747 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037487 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027346 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021517 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.220367 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.078027 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046328 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.047893 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050460 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047821 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000027 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025418 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028507 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.118321 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.054715 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025418 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028507 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.118321 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.054715 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13938.305400 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14413.337024 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9649.732471 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 24582.272513 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30788.933239 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 24102.161314 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13090.935503 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13519.354839 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6260.299156 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17255.949069 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25535.382360 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 18408.046125 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17255.949069 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25535.382360 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18408.046125 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9020 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1069 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1100 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 51 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.200000 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 20.960784 # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 597703 # number of writebacks +system.cpu0.dcache.writebacks::total 597703 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 146204 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 146204 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 547277 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 547277 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 408 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 408 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 693481 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 693481 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 693481 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 693481 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65573 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 137360 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 202933 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29694 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53043 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 82737 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1721 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3467 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5188 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 95267 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 190403 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 285670 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 95267 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 190403 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 285670 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 782830500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1785427500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2568258000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 670558000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1431904990 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2102462990 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19087500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40642000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59729500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1453388500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3217332490 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 4670720990 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1453388500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3217332490 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4670720990 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27581235500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28989086000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56570321500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1280021500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14116548125 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15396569625 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28861257000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43105634125 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71966891125 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033424 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028942 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014679 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021517 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019471 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008098 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047893 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.045147 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020732 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028507 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025488 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011882 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028507 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025488 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011882 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11938.305400 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12998.161765 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12655.694244 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22582.272513 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26995.173538 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25411.399857 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.935503 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11722.526680 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11513.010794 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15255.949069 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16897.488432 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16350.057724 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15255.949069 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16897.488432 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16350.057724 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dtb.inst_hits 0 # ITB inst hits +system.cpu1.dtb.inst_misses 0 # ITB inst misses +system.cpu1.dtb.read_hits 2177390 # DTB read hits +system.cpu1.dtb.read_misses 2104 # DTB read misses +system.cpu1.dtb.write_hits 1466734 # DTB write hits +system.cpu1.dtb.write_misses 391 # DTB write misses +system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 40 # Number of TLB faults due to prefetch +system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dtb.perms_faults 80 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 2179494 # DTB read accesses +system.cpu1.dtb.write_accesses 1467125 # DTB write accesses +system.cpu1.dtb.inst_accesses 0 # ITB inst accesses +system.cpu1.dtb.hits 3644124 # DTB hits +system.cpu1.dtb.misses 2495 # DTB misses +system.cpu1.dtb.accesses 3646619 # DTB accesses +system.cpu1.itb.inst_hits 8441472 # ITB inst hits +system.cpu1.itb.inst_misses 1131 # ITB inst misses +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 829 # Number of entries that have been flushed from TLB +system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.inst_accesses 8442603 # ITB inst accesses +system.cpu1.itb.hits 8441472 # DTB hits +system.cpu1.itb.misses 1131 # DTB misses +system.cpu1.itb.accesses 8442603 # DTB accesses +system.cpu1.numCycles 574629535 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 8231527 # Number of instructions committed +system.cpu1.committedOps 10483049 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9384758 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1998 # Number of float alu accesses +system.cpu1.num_func_calls 317840 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1148947 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9384758 # number of integer instructions +system.cpu1.num_fp_insts 1998 # number of float instructions +system.cpu1.num_int_register_reads 54113079 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10168310 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1549 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written +system.cpu1.num_mem_refs 3817736 # number of memory refs +system.cpu1.num_load_insts 2273251 # Number of load instructions +system.cpu1.num_store_insts 1544485 # Number of store instructions +system.cpu1.num_idle_cycles 533738024.963358 # Number of idle cycles +system.cpu1.num_busy_cycles 40891510.036642 # Number of busy cycles +system.cpu1.not_idle_fraction 0.071162 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.928838 # Percentage of idle cycles +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu2.branchPred.lookups 4718167 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3836083 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 222496 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3137475 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2530778 # Number of BTB hits +system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu2.branchPred.BTBHitPct 80.662890 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 410861 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21436 # Number of incorrect RAS predictions. +system.cpu2.dtb.inst_hits 0 # ITB inst hits +system.cpu2.dtb.inst_misses 0 # ITB inst misses +system.cpu2.dtb.read_hits 10866526 # DTB read hits +system.cpu2.dtb.read_misses 22717 # DTB read misses +system.cpu2.dtb.write_hits 3271799 # DTB write hits +system.cpu2.dtb.write_misses 5746 # DTB write misses +system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed +system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu2.dtb.flush_tlb_mva_asid 504 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 2317 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 908 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 162 # Number of TLB faults due to prefetch +system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu2.dtb.perms_faults 438 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10889243 # DTB read accesses +system.cpu2.dtb.write_accesses 3277545 # DTB write accesses +system.cpu2.dtb.inst_accesses 0 # ITB inst accesses +system.cpu2.dtb.hits 14138325 # DTB hits +system.cpu2.dtb.misses 28463 # DTB misses +system.cpu2.dtb.accesses 14166788 # DTB accesses +system.cpu2.itb.inst_hits 4062010 # ITB inst hits +system.cpu2.itb.inst_misses 4544 # ITB inst misses +system.cpu2.itb.read_hits 0 # DTB read hits +system.cpu2.itb.read_misses 0 # DTB read misses +system.cpu2.itb.write_hits 0 # DTB write hits +system.cpu2.itb.write_misses 0 # DTB write misses +system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb_mva_asid 504 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 1576 # Number of entries that have been flushed from TLB +system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu2.itb.perms_faults 990 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.read_accesses 0 # DTB read accesses +system.cpu2.itb.write_accesses 0 # DTB write accesses +system.cpu2.itb.inst_accesses 4066554 # ITB inst accesses +system.cpu2.itb.hits 4062010 # DTB hits +system.cpu2.itb.misses 4544 # DTB misses +system.cpu2.itb.accesses 4066554 # DTB accesses +system.cpu2.numCycles 88259424 # number of cpu cycles simulated +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.fetch.icacheStallCycles 9446644 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32376030 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4718167 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2941639 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6823560 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1815993 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 51150 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19328654 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 980 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 33196 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 57154 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 380 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4060600 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 310025 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2087 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 36989038 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.050362 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.436921 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30170666 81.57% 81.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 382975 1.04% 82.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 509806 1.38% 83.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 812610 2.20% 86.18% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 650446 1.76% 87.94% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 344174 0.93% 88.87% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1009971 2.73% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 238143 0.64% 92.24% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2870247 7.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::total 36989038 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053458 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.366828 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10060365 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19264823 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6175765 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 293250 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1193736 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 611236 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 54016 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36687044 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 183513 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1193736 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10634106 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6560148 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11167231 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5875066 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1557700 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34442910 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2428 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 416233 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 878364 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 86 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 36942900 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 157448988 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 157420907 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 28081 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 25732227 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11210672 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 231165 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 207502 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3338949 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6517311 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3844285 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 533485 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 782358 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 31699556 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 512260 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34239526 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 54408 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7411685 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19905699 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 155950 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 36989038 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.925667 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.579936 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24424083 66.03% 66.03% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3914413 10.58% 76.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2344925 6.34% 82.95% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1979398 5.35% 88.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2782245 7.52% 95.83% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 897303 2.43% 98.25% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 479565 1.30% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 132664 0.36% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34442 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 36989038 # Number of insts issued each cycle +system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 16741 1.09% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1406719 91.75% 92.84% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 109821 7.16% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.FU_type_0::No_OpClass 61341 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19346638 56.50% 56.68% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 25970 0.08% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 8 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 8 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 382 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11366450 33.20% 89.96% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3438720 10.04% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::total 34239526 # Type of FU issued +system.cpu2.iq.rate 0.387942 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1533281 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044781 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 107077115 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39628603 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27373114 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7012 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3867 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3171 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 35707743 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3723 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 207144 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu2.iew.lsq.thread0.squashedLoads 1578939 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1781 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9287 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 581487 # Number of stores squashed +system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu2.iew.lsq.thread0.rescheduledLoads 5366547 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 352710 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu2.iew.iewSquashCycles 1193736 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4865575 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 91265 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32289220 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 60072 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6517311 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3844285 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 370110 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 31382 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2364 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9287 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 105801 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 88656 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 194457 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33253955 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11078248 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 985571 # Number of squashed instructions skipped in execute +system.cpu2.iew.exec_swp 0 # number of swp insts executed +system.cpu2.iew.exec_nop 77404 # number of nop insts executed +system.cpu2.iew.exec_refs 14484069 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3693959 # Number of branches executed +system.cpu2.iew.exec_stores 3405821 # Number of stores executed +system.cpu2.iew.exec_rate 0.376775 # Inst execution rate +system.cpu2.iew.wb_sent 32835376 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27376285 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15639881 # num instructions producing a value +system.cpu2.iew.wb_consumers 28443914 # num instructions consuming a value +system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu2.iew.wb_rate 0.310180 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.549850 # average fanout of values written-back +system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu2.commit.commitSquashedInsts 7353370 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356310 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 169242 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35795177 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.689030 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.716377 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27161144 75.88% 75.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4182796 11.69% 87.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1257934 3.51% 91.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 650072 1.82% 92.90% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 572405 1.60% 94.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 318145 0.89% 95.38% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 398611 1.11% 96.50% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 289517 0.81% 97.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 964553 2.69% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::total 35795177 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 19948032 # Number of instructions committed +system.cpu2.commit.committedOps 24663934 # Number of ops (including micro ops) committed +system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu2.commit.refs 8201170 # Number of memory references committed +system.cpu2.commit.loads 4938372 # Number of loads committed +system.cpu2.commit.membars 94284 # Number of memory barriers committed +system.cpu2.commit.branches 3159330 # Number of branches committed +system.cpu2.commit.fp_insts 3119 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 21896584 # Number of committed integer instructions. +system.cpu2.commit.function_calls 294432 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 964553 # number cycles where commit BW limit reached +system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu2.rob.rob_reads 66322359 # The number of ROB reads +system.cpu2.rob.rob_writes 65269716 # The number of ROB writes +system.cpu2.timesIdled 360610 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51270386 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3567282777 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 19896304 # Number of Instructions Simulated +system.cpu2.committedOps 24612206 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 19896304 # Number of Instructions Simulated +system.cpu2.cpi 4.435971 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.435971 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.225430 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.225430 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 153619479 # number of integer regfile reads +system.cpu2.int_regfile_writes 29201382 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22411 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20842 # number of floating regfile writes +system.cpu2.misc_regfile_reads 9012056 # number of misc regfile reads +system.cpu2.misc_regfile_writes 240747 # number of misc regfile writes +system.iocache.replacements 0 # number of replacements +system.iocache.tagsinuse 0 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.avg_refs nan # Average number of references to valid blocks. +system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981147786186 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 981147786186 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981147786186 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 981147786186 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.kern.inst.arm 0 # number of arm instructions executed +system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed + +---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 1af17ec8e..73a40b4c9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,162 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.542296 # Number of seconds simulated -sim_ticks 2542295570500 # Number of ticks simulated -final_tick 2542295570500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.541289 # Number of seconds simulated +sim_ticks 2541288973500 # Number of ticks simulated +final_tick 2541288973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70655 # Simulator instruction rate (inst/s) -host_op_rate 90914 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2978397497 # Simulator tick rate (ticks/s) -host_mem_usage 409668 # Number of bytes of host memory used -host_seconds 853.58 # Real time elapsed on the host -sim_insts 60309877 # Number of instructions simulated -sim_ops 77602149 # Number of ops (including micro ops) simulated +host_inst_rate 61532 # Simulator instruction rate (inst/s) +host_op_rate 79175 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2592785663 # Simulator tick rate (ticks/s) +host_mem_usage 411940 # Number of bytes of host memory used +host_seconds 980.14 # Real time elapsed on the host +sim_insts 60309889 # Number of instructions simulated +sim_ops 77602313 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 504448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4169680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 296128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4925148 # Number of bytes read from this memory -system.physmem.bytes_read::total 131008300 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 504448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 296128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3787072 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1346312 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1669800 # Number of bytes written to this memory -system.physmem.bytes_written::total 6803184 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 501184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4156432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 298496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4937244 # Number of bytes read from this memory +system.physmem.bytes_read::total 131006380 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 501184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 298496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784960 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1345340 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1670772 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801072 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7882 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 65185 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4627 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 76962 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293509 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59173 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 336578 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 417450 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813201 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47638256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 503 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7831 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 64978 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4664 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 77151 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293479 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59140 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 336335 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 417693 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813168 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47657126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 630 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 198422 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1640124 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 116481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1937284 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51531498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 198422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 116481 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314903 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489627 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 529565 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 656808 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2676000 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47638256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 197216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1635561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 302 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 117459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1942811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51551154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 197216 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 117459 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314675 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489386 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 529393 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 657451 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2676229 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47657126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 630 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 198422 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2169689 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 116481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2594092 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54207499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293509 # Total number of read requests seen -system.physmem.writeReqs 813201 # Total number of write requests seen -system.physmem.cpureqs 218507 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978784576 # Total number of bytes read from memory -system.physmem.bytesWritten 52044864 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131008300 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6803184 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956235 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955738 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955673 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956489 # Track reads on a per bank basis +system.physmem.bw_total::cpu0.inst 197216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2164953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 302 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 117459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2600262 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54227384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293479 # Total number of read requests seen +system.physmem.writeReqs 813168 # Total number of write requests seen +system.physmem.cpureqs 218447 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978782656 # Total number of bytes read from memory +system.physmem.bytesWritten 52042752 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131006380 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6801072 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 10 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956234 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955730 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956486 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 956267 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955445 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955564 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956162 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956093 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955524 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955440 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955563 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956167 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956088 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955610 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955526 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 955926 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956035 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955433 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 955318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955984 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50833 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50416 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50435 # Track writes on a per bank basis +system.physmem.perBankRdReqs::12 956037 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955427 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 955317 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955983 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50835 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50411 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50432 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 51159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50911 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50191 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50281 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51366 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50906 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50808 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51188 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51253 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50731 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50630 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50913 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50185 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50283 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50857 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51358 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50902 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50806 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51187 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51249 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50729 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50629 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 51233 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1856479 # Number of times wr buffer was full causing retry -system.physmem.totGap 2542294418500 # Total gap between requests +system.physmem.numWrRetry 1856346 # Number of times wr buffer was full causing retry +system.physmem.totGap 2541287786000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 43 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154650 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 2610507 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59173 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1054657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 991834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3604952 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2718225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2722186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2700242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60067 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59423 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 110017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 160496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 109935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 11014 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8845 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see +system.physmem.readPktSize::6 154620 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 754028 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 59140 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1054883 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 992061 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961934 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3604876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2718031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2722784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2698984 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 109990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 160408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 109908 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10058 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9982 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 11017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -169,61 +156,59 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2918 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35370 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35255 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35218 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 32761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 346840685210 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 440008538960 # Sum of mem lat for all requests -system.physmem.totBusLat 76467475000 # Total cycles spent in databus access -system.physmem.totBankLat 16700378750 # Total cycles spent in bank access -system.physmem.avgQLat 22678.97 # Average queueing delay per request -system.physmem.avgBankLat 1091.99 # Average bank access latency per request +system.physmem.wrQLenPdf::24 32641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32476 # What write queue length does an incoming req see +system.physmem.totQLat 346721486500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 439895947750 # Sum of mem lat for all requests +system.physmem.totBusLat 76467345000 # Total cycles spent in databus access +system.physmem.totBankLat 16707116250 # Total cycles spent in bank access +system.physmem.avgQLat 22671.21 # Average queueing delay per request +system.physmem.avgBankLat 1092.43 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28770.96 # Average memory access latency -system.physmem.avgRdBW 385.00 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.47 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.53 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 28763.65 # Average memory access latency +system.physmem.avgRdBW 385.15 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.48 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.55 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.17 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 1.14 # Average write queue length over time -system.physmem.readRowHits 15218397 # Number of row buffer hits during reads -system.physmem.writeRowHits 794710 # Number of row buffer hits during writes +system.physmem.avgWrQLen 1.13 # Average write queue length over time +system.physmem.readRowHits 15218362 # Number of row buffer hits during reads +system.physmem.writeRowHits 794635 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.73 # Row buffer hit rate for writes -system.physmem.avgGap 157840.70 # Average gap between requests +system.physmem.writeRowHitRate 97.72 # Row buffer hit rate for writes +system.physmem.avgGap 157778.82 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory @@ -236,225 +221,225 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64418 # number of replacements -system.l2c.tagsinuse 51401.261729 # Cycle average of tags in use -system.l2c.total_refs 1905310 # Total number of references to valid blocks. -system.l2c.sampled_refs 129810 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.677683 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2531415043500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36947.323889 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 9.916328 # Average occupied blocks per requestor +system.l2c.replacements 64388 # number of replacements +system.l2c.tagsinuse 51386.157207 # Cycle average of tags in use +system.l2c.total_refs 1906213 # Total number of references to valid blocks. +system.l2c.sampled_refs 129781 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.687920 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2505304860500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36943.345859 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 11.980136 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000349 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5145.662568 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3278.560293 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 13.240870 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3059.988680 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2946.568751 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563771 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000151 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.inst 5122.722111 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3272.415541 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 10.482410 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3080.689127 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2944.521672 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563711 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000183 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.078517 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.050027 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000202 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.046692 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.044961 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.784321 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 32362 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 7566 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 491236 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 213718 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30461 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6864 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 480165 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 173950 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1436322 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608473 # number of Writeback hits -system.l2c.Writeback_hits::total 608473 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 19 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 14 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 33 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 4 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57779 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 55086 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112865 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 32362 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 7566 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 491236 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 271497 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30461 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6864 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 480165 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 229036 # number of demand (read+write) hits -system.l2c.demand_hits::total 1549187 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 32362 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 7566 # number of overall hits -system.l2c.overall_hits::cpu0.inst 491236 # number of overall hits -system.l2c.overall_hits::cpu0.data 271497 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30461 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6864 # number of overall hits -system.l2c.overall_hits::cpu1.inst 480165 # number of overall hits -system.l2c.overall_hits::cpu1.data 229036 # number of overall hits -system.l2c.overall_hits::total 1549187 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 20 # number of ReadReq misses +system.l2c.occ_percent::cpu0.inst 0.078167 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.049933 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000160 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.047008 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.044930 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.784091 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 32856 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 7561 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 491369 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 213716 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30962 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 7078 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 479886 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 173939 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1437367 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608382 # number of Writeback hits +system.l2c.Writeback_hits::total 608382 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 20 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 18 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 4 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 57851 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 55061 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112912 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 32856 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 7561 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 491369 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 271567 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30962 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 7078 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 479886 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 229000 # number of demand (read+write) hits +system.l2c.demand_hits::total 1550279 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 32856 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 7561 # number of overall hits +system.l2c.overall_hits::cpu0.inst 491369 # number of overall hits +system.l2c.overall_hits::cpu0.data 271567 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30962 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 7078 # number of overall hits +system.l2c.overall_hits::cpu1.inst 479886 # number of overall hits +system.l2c.overall_hits::cpu1.data 229000 # number of overall hits +system.l2c.overall_hits::total 1550279 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 25 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7773 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6102 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4633 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4618 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23163 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1544 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1370 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2914 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 60061 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 73152 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133213 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 20 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 7722 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6085 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 12 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 4670 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4619 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23135 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1541 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1365 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2906 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 59871 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 73351 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133222 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 25 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7773 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 66163 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4633 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 77770 # number of demand (read+write) misses -system.l2c.demand_misses::total 156376 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 20 # number of overall misses +system.l2c.demand_misses::cpu0.inst 7722 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 65956 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 12 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 4670 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 77970 # number of demand (read+write) misses +system.l2c.demand_misses::total 156357 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 25 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7773 # number of overall misses -system.l2c.overall_misses::cpu0.data 66163 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4633 # number of overall misses -system.l2c.overall_misses::cpu1.data 77770 # number of overall misses -system.l2c.overall_misses::total 156376 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1354500 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu0.inst 7722 # number of overall misses +system.l2c.overall_misses::cpu0.data 65956 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 12 # number of overall misses +system.l2c.overall_misses::cpu1.inst 4670 # number of overall misses +system.l2c.overall_misses::cpu1.data 77970 # number of overall misses +system.l2c.overall_misses::total 156357 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1696500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 118000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 429697500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 347820500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 983000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 271281500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 271043000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1322298000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 251500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 204000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 455500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3137999000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3639162500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6777161500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 1354500 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 425410000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 344277000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 826500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 270381000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 269029500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1311738500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 205000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 205500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 410500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3130049500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3648768000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6778817500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 1696500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 118000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 429697500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3485819500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 983000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 271281500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3910205500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8099459500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 1354500 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 425410000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3474326500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 826500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 270381000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3917797500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8090556000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 1696500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 118000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 429697500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3485819500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 983000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 271281500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3910205500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8099459500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 32382 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 7568 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 499009 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 219820 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 30476 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6864 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 484798 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 178568 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1459485 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 608473 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 608473 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1563 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1384 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2947 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 4 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 6 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 117840 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 128238 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246078 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 32382 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 7568 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 499009 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 337660 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 30476 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6864 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 484798 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 306806 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1705563 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 32382 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7568 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 499009 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 337660 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 30476 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6864 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 484798 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 306806 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1705563 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000618 # miss rate for ReadReq accesses +system.l2c.overall_miss_latency::cpu0.inst 425410000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3474326500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 826500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 270381000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3917797500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8090556000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 32881 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 7563 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 499091 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 219801 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 30974 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 7078 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 484556 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 178558 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1460502 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 608382 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 608382 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1561 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1383 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 5 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 4 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 9 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 117722 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 128412 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246134 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 32881 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 7563 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 499091 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 337523 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 30974 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7078 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 484556 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 306970 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1706636 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 32881 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 7563 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 499091 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 337523 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 30974 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7078 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 484556 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 306970 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1706636 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000760 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000264 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015577 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.027759 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000492 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009557 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.025861 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015871 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.987844 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989884 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.988802 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.509683 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.570439 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541345 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000618 # miss rate for demand accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015472 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.027684 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000387 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009638 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.025868 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015840 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.987188 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.986985 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.987092 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.508580 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.571216 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541258 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000760 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000264 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015577 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.195946 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000492 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009557 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.253483 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.091686 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000618 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015472 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.195412 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000387 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009638 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.253999 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.091617 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000760 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000264 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015577 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.195946 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000492 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009557 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.253483 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.091686 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 67725 # average ReadReq miss latency +system.l2c.overall_miss_rate::cpu0.inst 0.015472 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.195412 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000387 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009638 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.253999 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.091617 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 67860 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 59000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55280.779622 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 57001.065225 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 65533.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 58554.176559 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 58692.724123 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 57086.646807 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 162.888601 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 148.905109 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 156.314345 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52246.865687 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 49747.956310 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 50874.625600 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 67725 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55090.650091 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 56577.978636 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 68875 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 57897.430407 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 58244.100455 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 56699.308407 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 133.030500 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 150.549451 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 141.259463 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52279.893438 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 49743.943505 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 50883.619072 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 67860 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 55280.779622 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52685.330169 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 65533.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 58554.176559 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 50279.098624 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 51794.773495 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 67725 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 55090.650091 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52676.428225 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 68875 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 57897.430407 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 50247.499038 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 51744.124024 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 67860 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 55280.779622 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52685.330169 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 65533.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 58554.176559 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 50279.098624 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 51794.773495 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 55090.650091 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52676.428225 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 68875 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 57897.430407 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 50247.499038 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 51744.124024 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -463,8 +448,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 59173 # number of writebacks -system.l2c.writebacks::total 59173 # number of writebacks +system.l2c.writebacks::writebacks 59140 # number of writebacks +system.l2c.writebacks::total 59140 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 10 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits @@ -480,141 +465,141 @@ system.l2c.overall_mshr_hits::cpu0.data 39 # nu system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 20 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 20 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 25 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 7763 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6063 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 15 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 4627 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4598 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23088 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1544 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1370 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2914 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 60061 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 73152 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133213 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 20 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 7712 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6046 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 12 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 4664 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4599 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23060 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1541 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1365 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2906 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 59871 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 73351 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133222 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 25 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 7763 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 66124 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 15 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 4627 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 77750 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 156301 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 20 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 7712 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 65917 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 12 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 4664 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 77950 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 156282 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 25 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 7763 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 66124 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 4627 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 77750 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 156301 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1106788 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93252 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 332555399 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 270417799 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 796028 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 213310327 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 212900467 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1031180060 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 15532986 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13701370 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 29234356 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2388927373 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2728057055 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5116984428 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1106788 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93252 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 332555399 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2659345172 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 796028 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 213310327 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2940957522 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6148164488 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1106788 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93252 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 332555399 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2659345172 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 796028 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 213310327 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2940957522 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6148164488 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5050907 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84173719776 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82789281508 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166968052191 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 10449638570 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 13171042406 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 23620680976 # number of WriteReq MSHR uncacheable cycles -system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76254 # number of LoadLockedReq MSHR uncacheable cycles -system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76254 # number of LoadLockedReq MSHR uncacheable cycles +system.l2c.overall_mshr_misses::cpu0.inst 7712 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 65917 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 12 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 4664 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 77950 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 156282 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1386024 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93251 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 329024705 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 267448944 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 675012 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 211941612 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 210372572 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1020942120 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 15411541 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13749804 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 29161345 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2383249825 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2735103931 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5118353756 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1386024 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93251 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 329024705 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2650698769 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 675012 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 211941612 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2945476503 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6139295876 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1386024 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93251 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 329024705 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2650698769 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 675012 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 211941612 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2945476503 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6139295876 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5050830 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84200622267 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82767168504 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166972841601 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 10453604329 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 13166783666 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 23620387995 # number of WriteReq MSHR uncacheable cycles +system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76253 # number of LoadLockedReq MSHR uncacheable cycles +system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76253 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 30003 # number of StoreCondReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::total 30003 # number of StoreCondReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5050907 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94623358346 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 95960323914 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 190588733167 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000618 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5050830 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94654226596 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 95933952170 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 190593229596 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000760 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000264 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015557 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027582 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000492 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009544 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025749 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015819 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987844 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989884 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.988802 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.509683 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.570439 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541345 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000618 # mshr miss rate for demand accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015452 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027507 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009625 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025756 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015789 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987188 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.986985 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.987092 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.508580 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.571216 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541258 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000760 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015557 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.195830 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000492 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009544 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.253417 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.091642 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000618 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015452 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.195296 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009625 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.253934 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091573 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000760 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015557 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.195830 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000492 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009544 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.253417 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091642 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55339.400000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42838.515909 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44601.319314 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 53068.533333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 46101.216123 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46302.841888 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 44663.031012 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10060.224093 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10032.380233 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39775.018281 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37292.993425 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 38412.050085 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55339.400000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42838.515909 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40217.548424 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 53068.533333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46101.216123 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37825.820219 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39335.413644 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55339.400000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42838.515909 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40217.548424 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 53068.533333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46101.216123 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37825.820219 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39335.413644 # average overall mshr miss latency +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015452 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.195296 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009625 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.253934 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091573 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55440.960000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42663.991831 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44235.683758 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45743.111981 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 44273.292281 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10073.116484 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10034.874398 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39806.414207 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37287.888795 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 38419.733648 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55440.960000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42663.991831 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40212.673043 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37786.741539 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39283.448356 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55440.960000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42663.991831 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40212.673043 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37786.741539 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39283.448356 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -637,38 +622,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 7620138 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6076880 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 380507 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4965064 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4053585 # Number of BTB hits +system.cpu0.branchPred.lookups 7614306 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6072650 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 380012 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4955572 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4051897 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.642150 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 731859 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39538 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.764466 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 730604 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39458 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 26058653 # DTB read hits -system.cpu0.dtb.read_misses 40101 # DTB read misses -system.cpu0.dtb.write_hits 5895373 # DTB write hits -system.cpu0.dtb.write_misses 9447 # DTB write misses +system.cpu0.dtb.read_hits 26054511 # DTB read hits +system.cpu0.dtb.read_misses 40169 # DTB read misses +system.cpu0.dtb.write_hits 5887052 # DTB write hits +system.cpu0.dtb.write_misses 9355 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5619 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1431 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 273 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5627 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1395 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 274 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 647 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 26098754 # DTB read accesses -system.cpu0.dtb.write_accesses 5904820 # DTB write accesses +system.cpu0.dtb.perms_faults 638 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 26094680 # DTB read accesses +system.cpu0.dtb.write_accesses 5896407 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31954026 # DTB hits -system.cpu0.dtb.misses 49548 # DTB misses -system.cpu0.dtb.accesses 32003574 # DTB accesses -system.cpu0.itb.inst_hits 6112115 # ITB inst hits -system.cpu0.itb.inst_misses 7637 # ITB inst misses +system.cpu0.dtb.hits 31941563 # DTB hits +system.cpu0.dtb.misses 49524 # DTB misses +system.cpu0.dtb.accesses 31991087 # DTB accesses +system.cpu0.itb.inst_hits 6108612 # ITB inst hits +system.cpu0.itb.inst_misses 7590 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -677,149 +662,149 @@ system.cpu0.itb.flush_tlb 257 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2623 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1579 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1574 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6119752 # ITB inst accesses -system.cpu0.itb.hits 6112115 # DTB hits -system.cpu0.itb.misses 7637 # DTB misses -system.cpu0.itb.accesses 6119752 # DTB accesses -system.cpu0.numCycles 239063312 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6116202 # ITB inst accesses +system.cpu0.itb.hits 6108612 # DTB hits +system.cpu0.itb.misses 7590 # DTB misses +system.cpu0.itb.accesses 6116202 # DTB accesses +system.cpu0.numCycles 239083473 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15490963 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 47835555 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7620138 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4785444 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10608217 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2561094 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 89115 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 49527666 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1654 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1892 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 49952 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 101088 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 226 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6110008 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 396628 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3581 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77642580 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.762278 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.119818 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15485568 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 47808985 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7614306 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4782501 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10601732 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2558486 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 88790 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 49524477 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1650 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 2036 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 49879 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 101149 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 238 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6106475 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 397023 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3536 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77625046 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.761902 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.119269 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67041875 86.35% 86.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 689016 0.89% 87.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 885560 1.14% 88.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1228014 1.58% 89.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1141359 1.47% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 577108 0.74% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1324549 1.71% 93.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 398041 0.51% 94.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4357058 5.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67030834 86.35% 86.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 688188 0.89% 87.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 885369 1.14% 88.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1227712 1.58% 89.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1142460 1.47% 91.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 576598 0.74% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1323002 1.70% 93.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 397300 0.51% 94.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4353583 5.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77642580 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031875 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.200096 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16540886 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49255967 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9607571 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 552371 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1683667 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1024811 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 90579 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56316085 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 302289 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1683667 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17475063 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 18984775 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27019953 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9154130 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3322955 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 53494037 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 13484 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 621738 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2157353 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 548 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 55660367 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 243519467 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 243471355 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 48112 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 40417937 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 15242430 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 429833 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 381699 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6758508 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10355148 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6782314 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1058612 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1316675 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 49644359 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1043369 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 63195717 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 96260 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10515144 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26542188 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 266673 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77642580 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.813931 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.519230 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77625046 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031848 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.199968 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16533020 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49254882 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9604301 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 549145 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1681530 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1023916 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 90477 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56278023 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 301850 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1681530 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17466172 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 18987810 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27019642 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9149380 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3318436 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 53462165 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 13485 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 622165 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2153440 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 547 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 55626962 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 243359254 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 243311426 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 47828 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 40393377 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 15233585 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 429285 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 381212 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6745205 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10341737 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6773194 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1063883 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1311451 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 49606690 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1043899 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 63171257 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 95885 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10502922 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 26495317 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 267486 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77625046 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.813800 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.519198 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54792876 70.57% 70.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7218069 9.30% 79.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3694351 4.76% 84.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3145323 4.05% 88.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6277418 8.09% 96.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1407401 1.81% 98.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 809465 1.04% 99.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 231906 0.30% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 65771 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54791410 70.58% 70.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7205110 9.28% 79.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3690427 4.75% 84.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3148985 4.06% 88.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6276259 8.09% 96.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1405987 1.81% 98.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 810578 1.04% 99.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 230421 0.30% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 65869 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77642580 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77625046 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 29563 0.66% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 4 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4229523 94.72% 95.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 206294 4.62% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 29841 0.67% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4229016 94.75% 95.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 204408 4.58% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 195578 0.31% 0.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29951554 47.39% 47.70% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46938 0.07% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 195533 0.31% 0.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29939610 47.39% 47.70% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46892 0.07% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued @@ -832,485 +817,485 @@ system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.78% # Ty system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1212 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1207 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26776565 42.37% 90.15% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6223855 9.85% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26772486 42.38% 90.16% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6215505 9.84% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 63195717 # Type of FU issued -system.cpu0.iq.rate 0.264347 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4465384 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.070660 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208632682 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61211746 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 44166006 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12339 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6563 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5520 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67458994 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6529 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 322005 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 63171257 # Type of FU issued +system.cpu0.iq.rate 0.264223 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4463267 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.070653 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208563844 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61162491 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 44139446 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12207 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6555 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5480 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 67432539 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6452 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 322060 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2276398 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3543 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16033 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 889328 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2267012 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3473 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16117 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 886206 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17163737 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 367898 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17168110 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 367587 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1683667 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14223209 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 234272 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50804503 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 105344 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10355148 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6782314 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 742198 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 56887 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3242 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16033 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 187141 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 147345 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 334486 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 62025172 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26418520 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1170545 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1681530 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14225625 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 233605 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50767973 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 106118 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10341737 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6773194 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 742853 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 56514 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3354 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16117 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 186814 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 146956 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 333770 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 62000418 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26414197 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1170839 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 116775 # number of nop insts executed -system.cpu0.iew.exec_refs 32585401 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6028949 # Number of branches executed -system.cpu0.iew.exec_stores 6166881 # Number of stores executed -system.cpu0.iew.exec_rate 0.259451 # Inst execution rate -system.cpu0.iew.wb_sent 61495183 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44171526 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24314220 # num instructions producing a value -system.cpu0.iew.wb_consumers 44686636 # num instructions consuming a value +system.cpu0.iew.exec_nop 117384 # number of nop insts executed +system.cpu0.iew.exec_refs 32572588 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6026978 # Number of branches executed +system.cpu0.iew.exec_stores 6158391 # Number of stores executed +system.cpu0.iew.exec_rate 0.259325 # Inst execution rate +system.cpu0.iew.wb_sent 61472286 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44144926 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24307807 # num instructions producing a value +system.cpu0.iew.wb_consumers 44674584 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.184769 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.544105 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.184642 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.544108 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10365934 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 776696 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 291216 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75958913 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.525792 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.508136 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10350620 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 776413 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 290797 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75943516 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.525572 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.508217 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61730922 81.27% 81.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6914068 9.10% 90.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2040925 2.69% 93.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1133695 1.49% 94.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1039727 1.37% 95.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 547660 0.72% 96.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 699909 0.92% 97.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 371161 0.49% 98.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1480846 1.95% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61731521 81.29% 81.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6903711 9.09% 90.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2039504 2.69% 93.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1132941 1.49% 94.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1032773 1.36% 95.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 549051 0.72% 96.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 702703 0.93% 97.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 370837 0.49% 98.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1480475 1.95% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75958913 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 31284581 # Number of instructions committed -system.cpu0.commit.committedOps 39938560 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75943516 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 31268406 # Number of instructions committed +system.cpu0.commit.committedOps 39913766 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13971736 # Number of memory references committed -system.cpu0.commit.loads 8078750 # Number of loads committed -system.cpu0.commit.membars 212403 # Number of memory barriers committed -system.cpu0.commit.branches 5205711 # Number of branches committed -system.cpu0.commit.fp_insts 5497 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 35286774 # Number of committed integer instructions. -system.cpu0.commit.function_calls 514203 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1480846 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13961713 # Number of memory references committed +system.cpu0.commit.loads 8074725 # Number of loads committed +system.cpu0.commit.membars 212370 # Number of memory barriers committed +system.cpu0.commit.branches 5203416 # Number of branches committed +system.cpu0.commit.fp_insts 5433 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 35263906 # Number of committed integer instructions. +system.cpu0.commit.function_calls 513958 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1480475 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123805555 # The number of ROB reads -system.cpu0.rob.rob_writes 102335061 # The number of ROB writes -system.cpu0.timesIdled 884089 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 161420732 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2289699870 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 31205252 # Number of Instructions Simulated -system.cpu0.committedOps 39859231 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 31205252 # Number of Instructions Simulated -system.cpu0.cpi 7.660996 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.660996 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.130531 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.130531 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 280760557 # number of integer regfile reads -system.cpu0.int_regfile_writes 45445732 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22770 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19806 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15502985 # number of misc regfile reads -system.cpu0.misc_regfile_writes 430013 # number of misc regfile writes -system.cpu0.icache.replacements 984427 # number of replacements -system.cpu0.icache.tagsinuse 510.429233 # Cycle average of tags in use -system.cpu0.icache.total_refs 11039860 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 984939 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 11.208674 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 123750130 # The number of ROB reads +system.cpu0.rob.rob_writes 102252787 # The number of ROB writes +system.cpu0.timesIdled 884124 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 161458427 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2289647904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 31189179 # Number of Instructions Simulated +system.cpu0.committedOps 39834539 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 31189179 # Number of Instructions Simulated +system.cpu0.cpi 7.665590 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 7.665590 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.130453 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.130453 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 280633966 # number of integer regfile reads +system.cpu0.int_regfile_writes 45420954 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22760 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19830 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15480243 # number of misc regfile reads +system.cpu0.misc_regfile_writes 429707 # number of misc regfile writes +system.cpu0.icache.replacements 984233 # number of replacements +system.cpu0.icache.tagsinuse 511.604349 # Cycle average of tags in use +system.cpu0.icache.total_refs 11036411 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 984745 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 11.207380 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6522889000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 356.685952 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 153.743281 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.696652 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.300280 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996932 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5569328 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5470532 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 11039860 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5569328 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5470532 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 11039860 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5569328 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5470532 # number of overall hits -system.cpu0.icache.overall_hits::total 11039860 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 540556 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 524651 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065207 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 540556 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 524651 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065207 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 540556 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 524651 # number of overall misses -system.cpu0.icache.overall_misses::total 1065207 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7319258495 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6971682996 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14290941491 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7319258495 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6971682996 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14290941491 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7319258495 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6971682996 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14290941491 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6109884 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5995183 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 12105067 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6109884 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5995183 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 12105067 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6109884 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5995183 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12105067 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088472 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087512 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.087997 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088472 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087512 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.087997 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088472 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087512 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.087997 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13540.240965 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13288.229692 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13416.116765 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13540.240965 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13288.229692 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13416.116765 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13540.240965 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13288.229692 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13416.116765 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4720 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 356.507188 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 155.097161 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.696303 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.302924 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999227 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5565457 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5470954 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 11036411 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5565457 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5470954 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 11036411 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5565457 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5470954 # number of overall hits +system.cpu0.icache.overall_hits::total 11036411 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 540893 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 524443 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1065336 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 540893 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 524443 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1065336 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 540893 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 524443 # number of overall misses +system.cpu0.icache.overall_misses::total 1065336 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7322738992 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6974356493 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14297095485 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7322738992 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6974356493 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14297095485 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7322738992 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6974356493 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14297095485 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6106350 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5995397 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 12101747 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6106350 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5995397 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 12101747 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6106350 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5995397 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 12101747 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088579 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087474 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.088032 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088579 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087474 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.088032 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088579 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087474 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.088032 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13538.239526 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13298.597737 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13420.268803 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13538.239526 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13298.597737 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13420.268803 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13538.239526 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13298.597737 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13420.268803 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4718 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 314 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 353 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.031847 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.365439 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 40959 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39286 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 80245 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 40959 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 39286 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 80245 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 40959 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 39286 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 80245 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 499597 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 485365 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 984962 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 499597 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 485365 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 984962 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 499597 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 485365 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 984962 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5974261995 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5687350997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11661612992 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5974261995 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5687350997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11661612992 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5974261995 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5687350997 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11661612992 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41212 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39352 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 80564 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 41212 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 39352 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 80564 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 41212 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 39352 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 80564 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 499681 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 485091 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 984772 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 499681 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 485091 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 984772 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 499681 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 485091 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 984772 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5972321992 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5682978994 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11655300986 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5972321992 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5682978994 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11655300986 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5972321992 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5682978994 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11655300986 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7526000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7526000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7526000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7526000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081769 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.080959 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081368 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081769 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.080959 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.081368 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081769 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.080959 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.081368 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11958.162269 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11717.678442 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11839.657765 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11958.162269 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11717.678442 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11839.657765 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11958.162269 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11717.678442 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11839.657765 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081830 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.080911 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081374 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081830 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.080911 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.081374 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081830 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.080911 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.081374 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11952.269532 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11715.284336 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11835.532475 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11952.269532 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11715.284336 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11835.532475 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11952.269532 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11715.284336 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11835.532475 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 643954 # number of replacements -system.cpu0.dcache.tagsinuse 511.992718 # Cycle average of tags in use -system.cpu0.dcache.total_refs 21537903 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 644466 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.419766 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 643981 # number of replacements +system.cpu0.dcache.tagsinuse 511.992715 # Cycle average of tags in use +system.cpu0.dcache.total_refs 21533340 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 644493 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.411286 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 43205000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 318.437002 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 193.555716 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.621947 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.378039 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 320.784691 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 191.208024 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.626533 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.373453 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7114821 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6667161 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13781982 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3771949 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3489739 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7261688 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125842 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117705 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243547 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127851 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 119764 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247615 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10886770 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10156900 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21043670 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10886770 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10156900 # number of overall hits -system.cpu0.dcache.overall_hits::total 21043670 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 435511 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 315516 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 751027 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1388695 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1572418 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2961113 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6824 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6787 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13611 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 6 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1824206 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1887934 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3712140 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1824206 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1887934 # number of overall misses -system.cpu0.dcache.overall_misses::total 3712140 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6465462500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 4867480500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11332943000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52611155364 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 61827357784 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 114438513148 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92173500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 95497500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 187671000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 52000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 78000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 130000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 59076617864 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 66694838284 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 125771456148 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 59076617864 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 66694838284 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 125771456148 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7550332 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6982677 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14533009 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5160644 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5062157 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10222801 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132666 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 124492 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 257158 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127855 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 119770 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247625 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12710976 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12044834 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24755810 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12710976 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12044834 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24755810 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.057681 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.045186 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051677 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.269093 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.310622 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289658 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051437 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054518 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052929 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000031 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000050 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000040 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.143514 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.156742 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149950 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.143514 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.156742 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149950 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14845.692761 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15427.048074 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15089.927526 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37885.320653 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39319.924972 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38647.128005 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13507.253810 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14070.649772 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13788.186026 # average LoadLockedReq miss latency +system.cpu0.dcache.ReadReq_hits::cpu0.data 7106515 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6670987 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13777502 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3768669 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3492995 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7261664 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125802 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117658 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243460 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127804 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 119816 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247620 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10875184 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10163982 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 21039166 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10875184 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10163982 # number of overall hits +system.cpu0.dcache.overall_hits::total 21039166 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 435450 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 315528 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 750978 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1386539 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1574618 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2961157 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6834 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6765 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13599 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 4 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1821989 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1890146 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3712135 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1821989 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1890146 # number of overall misses +system.cpu0.dcache.overall_misses::total 3712135 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6465601500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 4868577500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11334179000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52482898858 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 61975315789 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 114458214647 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92223500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 94082500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 186306000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 65000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 52000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 117000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 58948500358 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 66843893289 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 125792393647 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 58948500358 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 66843893289 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 125792393647 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7541965 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6986515 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 14528480 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5155208 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5067613 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10222821 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132636 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 124423 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 257059 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127809 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 119820 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247629 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12697173 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 12054128 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24751301 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12697173 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 12054128 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24751301 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.057737 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.045162 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.051690 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.268959 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.310722 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.289661 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051524 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054371 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052902 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000039 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000033 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000036 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.143496 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.156805 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.149977 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.143496 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.156805 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.149977 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14848.091629 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15429.938072 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15092.557971 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37851.729276 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39358.952958 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38653.207056 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13494.805385 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13907.243163 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13699.977940 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32384.839138 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35326.890815 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33881.118748 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32384.839138 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35326.890815 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33881.118748 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 35462 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 15651 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3547 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 261 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.997745 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 59.965517 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32353.927690 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35364.407453 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33886.804668 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32353.927690 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35364.407453 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33886.804668 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 35336 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 15995 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3561 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 266 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.923055 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 60.131579 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 608473 # number of writebacks -system.cpu0.dcache.writebacks::total 608473 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 221772 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 142997 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 364769 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1269356 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1442834 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2712190 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 679 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 700 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1379 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1491128 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1585831 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3076959 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1491128 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1585831 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3076959 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 213739 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 172519 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 386258 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119339 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 129584 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 248923 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6145 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6087 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12232 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 6 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 333078 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 302103 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 635181 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 333078 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 302103 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 635181 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2903093500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2321765000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5224858500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3977310493 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4483624933 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8460935426 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71679000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74936000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146615000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 44000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 66000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 110000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6880403993 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6805389933 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13685793926 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6880403993 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6805389933 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13685793926 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91929858500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90426612500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182356471000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14888104285 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18626460302 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33514564587 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.writebacks::writebacks 608382 # number of writebacks +system.cpu0.dcache.writebacks::total 608382 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 221746 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 143011 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 364757 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1267305 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1444859 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2712164 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 688 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 688 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1376 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1489051 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1587870 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3076921 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1489051 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1587870 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3076921 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 213704 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 172517 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 386221 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119234 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 129759 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 248993 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6146 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6077 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12223 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 4 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 332938 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 302276 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 635214 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 332938 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 302276 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 635214 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2899504500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2321074000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5220578500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3969032491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4493255436 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8462287927 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71687000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73644500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145331500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 55000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 99000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6868536991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6814329436 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13682866427 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6868536991 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6814329436 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13682866427 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91958825500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90402409000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182361234500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14888911816 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18625662995 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33514574811 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106817962785 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109053072802 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215871035587 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028309 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024707 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026578 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023125 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025599 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024350 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046319 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048895 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047566 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000031 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000050 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025082 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025658 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025082 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025658 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13582.422955 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13458.024913 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13526.861580 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33327.834932 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34600.143019 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33990.171362 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11664.605370 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12310.826351 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11986.183780 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106847737316 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109028071995 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215875809311 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028335 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024693 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026584 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023129 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025606 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046337 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048841 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047549 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000039 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000033 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000036 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026221 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025077 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025664 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026221 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025077 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025664 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13567.853199 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13454.175531 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13517.075716 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33287.757611 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34627.697778 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33986.047507 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11664.009112 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12118.561790 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11890.002454 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20657.035268 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22526.720797 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21546.289839 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20657.035268 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22526.720797 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21546.289839 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20630.078246 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22543.402175 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21540.561806 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20630.078246 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22543.402175 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21540.561806 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1325,38 +1310,38 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7047379 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5653088 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 345044 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4644809 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3819502 # Number of BTB hits +system.cpu1.branchPred.lookups 7038093 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5643597 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 344397 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4629014 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3810883 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 82.231627 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 672042 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34964 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 82.326020 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 671158 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34749 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25308350 # DTB read hits -system.cpu1.dtb.read_misses 36279 # DTB read misses -system.cpu1.dtb.write_hits 5820677 # DTB write hits -system.cpu1.dtb.write_misses 9386 # DTB write misses +system.cpu1.dtb.read_hits 25308103 # DTB read hits +system.cpu1.dtb.read_misses 36468 # DTB read misses +system.cpu1.dtb.write_hits 5825949 # DTB write hits +system.cpu1.dtb.write_misses 9352 # DTB write misses system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5518 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1305 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 250 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5514 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1257 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 236 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 636 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25344629 # DTB read accesses -system.cpu1.dtb.write_accesses 5830063 # DTB write accesses +system.cpu1.dtb.perms_faults 652 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25344571 # DTB read accesses +system.cpu1.dtb.write_accesses 5835301 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31129027 # DTB hits -system.cpu1.dtb.misses 45665 # DTB misses -system.cpu1.dtb.accesses 31174692 # DTB accesses -system.cpu1.itb.inst_hits 5997294 # ITB inst hits -system.cpu1.itb.inst_misses 6928 # ITB inst misses +system.cpu1.dtb.hits 31134052 # DTB hits +system.cpu1.dtb.misses 45820 # DTB misses +system.cpu1.dtb.accesses 31179872 # DTB accesses +system.cpu1.itb.inst_hits 5997509 # ITB inst hits +system.cpu1.itb.inst_misses 6989 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1365,284 +1350,284 @@ system.cpu1.itb.flush_tlb 254 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2607 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2597 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1462 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1435 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 6004222 # ITB inst accesses -system.cpu1.itb.hits 5997294 # DTB hits -system.cpu1.itb.misses 6928 # DTB misses -system.cpu1.itb.accesses 6004222 # DTB accesses -system.cpu1.numCycles 234192897 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 6004498 # ITB inst accesses +system.cpu1.itb.hits 5997509 # DTB hits +system.cpu1.itb.misses 6989 # DTB misses +system.cpu1.itb.accesses 6004498 # DTB accesses +system.cpu1.numCycles 234155519 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15145693 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46615728 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7047379 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4491544 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10277592 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2615595 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 81100 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 47506260 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 991 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2050 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 43629 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 94802 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 132 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5995185 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 443145 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3161 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 74942742 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.773391 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.139188 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15142136 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46597306 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7038093 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4482041 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10279188 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2613913 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 81086 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 47501023 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2061 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 42896 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 94668 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 141 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5995399 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 442650 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3270 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 74933804 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.773237 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.138568 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 64672921 86.30% 86.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 620255 0.83% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 831184 1.11% 88.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1205105 1.61% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1036791 1.38% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 535666 0.71% 91.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1369144 1.83% 93.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 351637 0.47% 94.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4320039 5.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 64662280 86.29% 86.29% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 620375 0.83% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 831799 1.11% 88.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1204715 1.61% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1045196 1.39% 91.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 534648 0.71% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1368616 1.83% 93.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 351624 0.47% 94.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4314551 5.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 74942742 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030092 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.199048 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 16159158 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 47296340 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9320957 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 457304 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1706877 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 946060 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 86144 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54858013 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 286862 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1706877 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17095317 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18544880 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 25731919 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8763106 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3098607 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51692102 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 7152 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 482288 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2118635 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 58 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53768769 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 237295359 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 237252975 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42384 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 37974901 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15793867 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 403461 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 357400 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6244351 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9843526 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6693253 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 891235 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1110531 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47673025 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 943085 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60813772 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 81704 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10584682 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 28040387 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 237278 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 74942742 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.811470 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.521589 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 74933804 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030057 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.199002 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 16155094 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 47289878 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9321974 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 458622 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1706108 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 946431 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 86032 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54867135 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 286067 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1706108 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17091509 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 18549403 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 25716073 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8765190 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3103459 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51703267 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 7138 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 482463 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2122538 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 91 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53752733 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 237374868 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 237332026 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42842 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 37999603 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15753129 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 403463 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 357307 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6254395 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9847442 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6700780 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 890369 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1126759 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47663057 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 942444 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60816475 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 81421 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10551432 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 27971257 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 236318 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 74933804 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.811603 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.521433 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53203952 70.99% 70.99% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6663470 8.89% 79.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3519082 4.70% 84.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2892768 3.86% 88.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6218608 8.30% 96.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1439258 1.92% 98.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 735883 0.98% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 209954 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 59767 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53188932 70.98% 70.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6663266 8.89% 79.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3530113 4.71% 84.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2889463 3.86% 88.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6218055 8.30% 96.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1440706 1.92% 98.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 733706 0.98% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 209896 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 59667 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 74942742 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 74933804 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 24319 0.56% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4142702 94.84% 95.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 201068 4.60% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 24001 0.55% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 1 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4142238 94.88% 95.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 199692 4.57% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 168088 0.28% 0.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28444166 46.77% 47.05% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46611 0.08% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 900 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26040619 42.82% 89.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6113365 10.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 168133 0.28% 0.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28440656 46.76% 47.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46730 0.08% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 904 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26040768 42.82% 89.94% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6119264 10.06% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60813772 # Type of FU issued -system.cpu1.iq.rate 0.259674 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4368089 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.071827 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 201054983 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 59209073 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41787342 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 10574 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5911 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4752 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65008196 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5577 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 302847 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60816475 # Type of FU issued +system.cpu1.iq.rate 0.259727 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4365932 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.071789 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 201049061 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 59165079 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41785793 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 10680 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5951 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4814 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65008639 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5635 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 303573 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2267035 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3168 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14674 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 853664 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2266828 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3041 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14605 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 855166 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16940133 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 457083 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16935844 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 457097 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1706877 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 13961840 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 229523 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48721689 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 98782 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9843526 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6693253 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 669936 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 49642 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3791 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14674 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 166878 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 133542 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 300420 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59454145 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25635874 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1359627 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1706108 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 13962333 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 229984 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48711452 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 98533 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9847442 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6700780 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 669329 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 49837 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3707 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14605 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 166001 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 133612 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 299613 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59448141 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25635797 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1368334 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 105579 # number of nop insts executed -system.cpu1.iew.exec_refs 31697240 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5530994 # Number of branches executed -system.cpu1.iew.exec_stores 6061366 # Number of stores executed -system.cpu1.iew.exec_rate 0.253868 # Inst execution rate -system.cpu1.iew.wb_sent 58875000 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41792094 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 22753184 # num instructions producing a value -system.cpu1.iew.wb_consumers 41716740 # num instructions consuming a value +system.cpu1.iew.exec_nop 105951 # number of nop insts executed +system.cpu1.iew.exec_refs 31702689 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5524822 # Number of branches executed +system.cpu1.iew.exec_stores 6066892 # Number of stores executed +system.cpu1.iew.exec_rate 0.253883 # Inst execution rate +system.cpu1.iew.wb_sent 58868959 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41790607 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 22765083 # num instructions producing a value +system.cpu1.iew.wb_consumers 41748877 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178452 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.545421 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.178474 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.545286 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 10509796 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 705807 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 260176 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 73235865 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.516331 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.496791 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 10475750 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 706126 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 259614 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 73227696 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.516730 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.497193 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 59723279 81.55% 81.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6657456 9.09% 90.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1906988 2.60% 93.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1010218 1.38% 94.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 959564 1.31% 95.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 524950 0.72% 96.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 702340 0.96% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 373722 0.51% 98.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1377348 1.88% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 59700930 81.53% 81.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6668134 9.11% 90.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1908648 2.61% 93.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1011673 1.38% 94.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 958934 1.31% 95.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 524760 0.72% 96.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 701730 0.96% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 374533 0.51% 98.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1378354 1.88% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 73235865 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 29175677 # Number of instructions committed -system.cpu1.commit.committedOps 37813970 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 73227696 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 29191864 # Number of instructions committed +system.cpu1.commit.committedOps 37838928 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13416080 # Number of memory references committed -system.cpu1.commit.loads 7576491 # Number of loads committed -system.cpu1.commit.membars 191234 # Number of memory barriers committed -system.cpu1.commit.branches 4755917 # Number of branches committed -system.cpu1.commit.fp_insts 4715 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33570741 # Number of committed integer instructions. -system.cpu1.commit.function_calls 477112 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1377348 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13426228 # Number of memory references committed +system.cpu1.commit.loads 7580614 # Number of loads committed +system.cpu1.commit.membars 191280 # Number of memory barriers committed +system.cpu1.commit.branches 4758264 # Number of branches committed +system.cpu1.commit.fp_insts 4779 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33593707 # Number of committed integer instructions. +system.cpu1.commit.function_calls 477362 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1378354 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 119309924 # The number of ROB reads -system.cpu1.rob.rob_writes 98406667 # The number of ROB writes -system.cpu1.timesIdled 873323 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159250155 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2285809379 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29104625 # Number of Instructions Simulated -system.cpu1.committedOps 37742918 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 29104625 # Number of Instructions Simulated -system.cpu1.cpi 8.046587 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.046587 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.124276 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.124276 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 269354983 # number of integer regfile reads -system.cpu1.int_regfile_writes 42881539 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22070 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19722 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14807942 # number of misc regfile reads -system.cpu1.misc_regfile_writes 402452 # number of misc regfile writes +system.cpu1.rob.rob_reads 119292034 # The number of ROB reads +system.cpu1.rob.rob_writes 98387822 # The number of ROB writes +system.cpu1.timesIdled 873010 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159221715 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2285865988 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29120710 # Number of Instructions Simulated +system.cpu1.committedOps 37767774 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 29120710 # Number of Instructions Simulated +system.cpu1.cpi 8.040859 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.040859 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.124365 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.124365 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 269346342 # number of integer regfile reads +system.cpu1.int_regfile_writes 42878504 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22102 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19714 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14810651 # number of misc regfile reads +system.cpu1.misc_regfile_writes 402789 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1657,17 +1642,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192818443837 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1192818443837 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192818443837 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1192818443837 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192717579972 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1192717579972 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192717579972 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1192717579972 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83054 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83049 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index cc1497460..e925b6c9c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -4,63 +4,63 @@ sim_seconds 2.608779 # Nu sim_ticks 2608778789000 # Number of ticks simulated final_tick 2608778789000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 458042 # Simulator instruction rate (inst/s) -host_op_rate 582855 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19847185908 # Simulator tick rate (ticks/s) -host_mem_usage 403628 # Number of bytes of host memory used -host_seconds 131.44 # Real time elapsed on the host +host_inst_rate 616577 # Simulator instruction rate (inst/s) +host_op_rate 784589 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26716567066 # Simulator tick rate (ticks/s) +host_mem_usage 403640 # Number of bytes of host memory used +host_seconds 97.65 # Real time elapsed on the host sim_insts 60206536 # Number of instructions simulated sim_ops 76612339 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 419296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4486284 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4486348 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 285888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4557412 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4557348 # Number of bytes read from this memory system.physmem.bytes_read::total 132432464 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 419296 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 285888 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 705184 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 3671168 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1520308 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1495832 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1520260 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1495880 # Number of bytes written to this memory system.physmem.bytes_written::total 6687308 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 12754 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 70131 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 70132 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 4467 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 71233 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 71232 # Number of read requests responded to by this memory system.physmem.num_reads::total 15494012 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 57362 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380077 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373958 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380065 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373970 # Number of write requests responded to by this memory system.physmem.num_writes::total 811397 # Number of write requests responded to by this memory system.physmem.bw_read::realview.clcd 47027135 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 160725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1719687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1719712 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 109587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1746952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1746928 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 50764160 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 160725 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 109587 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 270312 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1407236 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 582766 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 573384 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 582748 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 573402 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 2563386 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1407236 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.clcd 47027135 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 160725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2302454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2302460 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 109587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2320336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2320330 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 53327546 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15494012 # Total number of read requests seen system.physmem.writeReqs 811397 # Total number of write requests seen @@ -113,42 +113,29 @@ system.physmem.readPktSize::3 15335424 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 151912 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 754035 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 57362 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4515 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1116413 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 960010 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 974367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3651904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2754719 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2759720 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2733933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 61766 # What read queue length does an incoming req see +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 754035 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 57362 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1116374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 959978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 974289 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3651919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2754799 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2759743 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2734008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 61745 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 60421 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 111612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 162702 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 111491 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8813 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8742 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8677 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 111605 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 162677 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 111472 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8821 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8748 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8654 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 53 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -165,48 +152,46 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35286 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 35272 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 35257 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35243 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35141 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35124 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 338341857800 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 433208122800 # Sum of mem lat for all requests +system.physmem.wrQLenPdf::23 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see +system.physmem.totQLat 338360116500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 433225996500 # Sum of mem lat for all requests system.physmem.totBusLat 77469930000 # Total cycles spent in databus access -system.physmem.totBankLat 17396335000 # Total cycles spent in bank access -system.physmem.avgQLat 21836.98 # Average queueing delay per request -system.physmem.avgBankLat 1122.78 # Average bank access latency per request +system.physmem.totBankLat 17395950000 # Total cycles spent in bank access +system.physmem.avgQLat 21838.16 # Average queueing delay per request +system.physmem.avgBankLat 1122.75 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27959.76 # Average memory access latency +system.physmem.avgMemAccLat 27960.91 # Average memory access latency system.physmem.avgRdBW 380.11 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 19.91 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 50.76 # Average consumed read bandwidth in MB/s @@ -215,8 +200,8 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 3.13 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time system.physmem.avgWrQLen 1.24 # Average write queue length over time -system.physmem.readRowHits 15419486 # Number of row buffer hits during reads -system.physmem.writeRowHits 793977 # Number of row buffer hits during writes +system.physmem.readRowHits 15419485 # Number of row buffer hits during reads +system.physmem.writeRowHits 793971 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes system.physmem.avgGap 159994.42 # Average gap between requests @@ -233,67 +218,67 @@ system.realview.nvmem.bw_inst_read::total 8 # I system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 61800 # number of replacements -system.l2c.tagsinuse 50918.253702 # Cycle average of tags in use -system.l2c.total_refs 1698591 # Total number of references to valid blocks. +system.l2c.tagsinuse 50918.274770 # Cycle average of tags in use +system.l2c.total_refs 1698590 # Total number of references to valid blocks. system.l2c.sampled_refs 127185 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.355278 # Average number of references to valid blocks. +system.l2c.avg_refs 13.355270 # Average number of references to valid blocks. system.l2c.warmup_cycle 2557152484500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37907.717848 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 37907.739724 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000184 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000642 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4327.115126 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3096.490855 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2668.881351 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2918.047697 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4327.115083 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3097.452751 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2668.881349 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2917.085036 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.578426 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.066027 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.047249 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.047263 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.inst 0.040724 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.044526 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.044511 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.776951 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 10142 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.dtb.walker 10140 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3715 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 409497 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 188260 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 9560 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 409506 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 188271 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 9561 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 3405 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 434855 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 182318 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1241752 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 434846 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 182307 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1241751 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 596435 # number of Writeback hits system.l2c.Writeback_hits::total 596435 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 11 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57590 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 56979 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 57591 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 56978 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 114569 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 10142 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.dtb.walker 10140 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 3715 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 409497 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 245850 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9560 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 409506 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 245862 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 9561 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 3405 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 434855 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 239297 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356321 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 10142 # number of overall hits +system.l2c.demand_hits::cpu1.inst 434846 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 239285 # number of demand (read+write) hits +system.l2c.demand_hits::total 1356320 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 10140 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 3715 # number of overall hits -system.l2c.overall_hits::cpu0.inst 409497 # number of overall hits -system.l2c.overall_hits::cpu0.data 245850 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 9560 # number of overall hits +system.l2c.overall_hits::cpu0.inst 409506 # number of overall hits +system.l2c.overall_hits::cpu0.data 245862 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 9561 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 3405 # number of overall hits -system.l2c.overall_hits::cpu1.inst 434855 # number of overall hits -system.l2c.overall_hits::cpu1.data 239297 # number of overall hits -system.l2c.overall_hits::total 1356321 # number of overall hits +system.l2c.overall_hits::cpu1.inst 434846 # number of overall hits +system.l2c.overall_hits::cpu1.data 239285 # number of overall hits +system.l2c.overall_hits::total 1356320 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.inst 6138 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5512 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5513 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 4467 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4338 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4337 # number of ReadReq misses system.l2c.ReadReq_misses::total 20458 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 1394 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 1477 # number of UpgradeReq misses @@ -304,133 +289,133 @@ system.l2c.ReadExReq_misses::total 133098 # nu system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 6138 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 70913 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 70914 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 4467 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 72035 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 72034 # number of demand (read+write) misses system.l2c.demand_misses::total 153556 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses system.l2c.overall_misses::cpu0.inst 6138 # number of overall misses -system.l2c.overall_misses::cpu0.data 70913 # number of overall misses +system.l2c.overall_misses::cpu0.data 70914 # number of overall misses system.l2c.overall_misses::cpu1.inst 4467 # number of overall misses -system.l2c.overall_misses::cpu1.data 72035 # number of overall misses +system.l2c.overall_misses::cpu1.data 72034 # number of overall misses system.l2c.overall_misses::total 153556 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 69000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 318096500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 286803500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 246123500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 241819000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1092994000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 318133500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 286446000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 246251500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 242168000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1093150500 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu0.data 227000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 228000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 455000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 2952460500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3124906000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6077366500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 2952570500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3124407000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6076977500 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 69000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 82500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 318096500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3239264000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 246123500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3366725000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 7170360500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 318133500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3239016500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 246251500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3366575000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 7170128000 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 69000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 82500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 318096500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3239264000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 246123500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3366725000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 7170360500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 10143 # number of ReadReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu0.inst 318133500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3239016500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 246251500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3366575000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 7170128000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 10141 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 3717 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 415635 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 193772 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 9560 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 415644 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 193784 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 9561 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 3405 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 439322 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 186656 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1262210 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 439313 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 186644 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1262209 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 596435 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 596435 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1405 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1492 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2897 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 122991 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 124676 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 122992 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 124675 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 247667 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 10143 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.dtb.walker 10141 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 3717 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 415635 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 316763 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 9560 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 415644 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 316776 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 9561 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 3405 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 439322 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 311332 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1509877 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 10143 # number of overall (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 439313 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 311319 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1509876 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 10141 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 3717 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 415635 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 316763 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 9560 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 415644 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 316776 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 9561 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 3405 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 439322 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 311332 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1509877 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 439313 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 311319 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1509876 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000099 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000538 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014768 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.028446 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014767 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.028449 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.010168 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.023241 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.023237 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.016208 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992171 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989946 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.991025 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.531754 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.542983 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.531750 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.542988 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.537407 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000099 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000538 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014768 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.223868 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014767 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.223862 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.010168 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.231377 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.231383 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.101701 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000099 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000538 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014768 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.223868 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014767 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.223862 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.010168 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.231377 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.231383 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.101701 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 69000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 41250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 51824.128381 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52032.565312 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55098.164316 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 55744.352236 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 53426.239124 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 51830.156403 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 51958.280428 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55126.818894 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 55837.675813 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 53433.888943 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 162.840746 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 154.366960 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 158.481365 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 45143.965689 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 46160.184351 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 45660.840133 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 45145.647620 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 46152.813271 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 45657.917474 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 41250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 51824.128381 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 45679.409981 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 55098.164316 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 46737.349899 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 46695.410795 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 51830.156403 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 45675.275686 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 55126.818894 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 46735.916373 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 46693.896689 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 41250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 51824.128381 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 45679.409981 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 55098.164316 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 46737.349899 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 46695.410795 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 51830.156403 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 45675.275686 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 55126.818894 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 46735.916373 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 46693.896689 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -444,9 +429,9 @@ system.l2c.writebacks::total 57362 # nu system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.inst 6138 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 5512 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 5513 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.inst 4467 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4338 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4337 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 20458 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 1394 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1.data 1477 # number of UpgradeReq MSHR misses @@ -457,113 +442,113 @@ system.l2c.ReadExReq_mshr_misses::total 133098 # nu system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.inst 6138 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 70913 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 70914 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 4467 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 72035 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 72034 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 153556 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.inst 6138 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 70913 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 70914 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 4467 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 72035 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 72034 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 153556 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 56252 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 57504 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 241157706 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 218147951 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 190156606 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 187657351 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 837233370 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 56251 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 57502 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 241189638 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 217772763 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 190279467 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 188012087 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 837367708 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13941394 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14811949 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 28753343 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2130052049 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2272372420 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4402424469 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 56252 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 57504 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 241157706 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2348200000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 190156606 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2460029771 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 5239657839 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 56252 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 57504 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 241157706 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2348200000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 190156606 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2460029771 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 5239657839 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 209122550 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83655977314 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83046075777 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166911175641 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4790521424 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 4370138455 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 9160659879 # number of WriteReq MSHR uncacheable cycles -system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76254 # number of LoadLockedReq MSHR uncacheable cycles -system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76254 # number of LoadLockedReq MSHR uncacheable cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14803954 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 28745348 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2130102401 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2271808177 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4401910578 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 57502 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 241189638 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2347875164 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 190279467 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2459820264 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5239278286 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 56251 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 57502 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 241189638 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2347875164 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 190279467 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2459820264 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5239278286 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 209116116 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83656256785 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83045804272 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166911177173 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4790532841 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 4370266467 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 9160799308 # number of WriteReq MSHR uncacheable cycles +system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76253 # number of LoadLockedReq MSHR uncacheable cycles +system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76253 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 30003 # number of StoreCondReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::total 30003 # number of StoreCondReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 209122550 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 88446498738 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 87416214232 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 176071835520 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 209116116 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 88446789626 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 87416070739 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 176071976481 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000099 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000538 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014768 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028446 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014767 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028449 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010168 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.023241 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.023237 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.016208 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.992171 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989946 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.991025 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.531754 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.542983 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.531750 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.542988 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.537407 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000099 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000538 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014768 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.223868 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014767 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.223862 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010168 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.231377 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.231383 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.101701 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000099 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000538 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014768 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.223868 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014767 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.223862 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010168 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.231377 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.231383 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.101701 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28752 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39289.297165 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 39576.914187 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42569.197672 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 43258.955970 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40924.497507 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39294.499511 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 39501.680210 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42596.701813 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 43350.723311 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40931.064034 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.401490 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10015.096830 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32569.105197 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 33566.811232 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 33076.563652 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 28752 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39289.297165 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 33113.815520 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42569.197672 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 34150.479225 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 34122.130291 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 28752 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39289.297165 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33113.815520 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42569.197672 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 34150.479225 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 34122.130291 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10022.988490 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10012.312086 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32569.875094 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 33558.476402 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 33072.702655 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39294.499511 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 33108.767860 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42596.701813 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 34148.044868 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 34119.658535 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39294.499511 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33108.767860 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42596.701813 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 34148.044868 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 34119.658535 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -588,10 +573,10 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7507423 # DTB read hits +system.cpu0.dtb.read_hits 7507395 # DTB read hits system.cpu0.dtb.read_misses 6880 # DTB read misses -system.cpu0.dtb.write_hits 5552288 # DTB write hits -system.cpu0.dtb.write_misses 1844 # DTB write misses +system.cpu0.dtb.write_hits 5552217 # DTB write hits +system.cpu0.dtb.write_misses 1843 # DTB write misses system.cpu0.dtb.flush_tlb 1276 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 721 # Number of times TLB was flushed by MVA & ASID @@ -601,13 +586,13 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 127 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 245 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7514303 # DTB read accesses -system.cpu0.dtb.write_accesses 5554132 # DTB write accesses +system.cpu0.dtb.read_accesses 7514275 # DTB read accesses +system.cpu0.dtb.write_accesses 5554060 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13059711 # DTB hits -system.cpu0.dtb.misses 8724 # DTB misses -system.cpu0.dtb.accesses 13068435 # DTB accesses -system.cpu0.itb.inst_hits 30766737 # ITB inst hits +system.cpu0.dtb.hits 13059612 # DTB hits +system.cpu0.dtb.misses 8723 # DTB misses +system.cpu0.dtb.accesses 13068335 # DTB accesses +system.cpu0.itb.inst_hits 30766787 # ITB inst hits system.cpu0.itb.inst_misses 3610 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -624,30 +609,30 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30770347 # ITB inst accesses -system.cpu0.itb.hits 30766737 # DTB hits +system.cpu0.itb.inst_accesses 30770397 # ITB inst accesses +system.cpu0.itb.hits 30766787 # DTB hits system.cpu0.itb.misses 3610 # DTB misses -system.cpu0.itb.accesses 30770347 # DTB accesses -system.cpu0.numCycles 2552892042 # number of cpu cycles simulated +system.cpu0.itb.accesses 30770397 # DTB accesses +system.cpu0.numCycles 2552895768 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 30144083 # Number of instructions committed -system.cpu0.committedOps 38293118 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34424567 # Number of integer alu accesses +system.cpu0.committedInsts 30144155 # Number of instructions committed +system.cpu0.committedOps 38293148 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34424496 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5276 # Number of float alu accesses -system.cpu0.num_func_calls 1041312 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4017319 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34424567 # number of integer instructions +system.cpu0.num_func_calls 1041305 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4017298 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34424496 # number of integer instructions system.cpu0.num_fp_insts 5276 # number of float instructions -system.cpu0.num_int_register_reads 197342497 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37147622 # number of times the integer registers were written +system.cpu0.num_int_register_reads 197342644 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37147872 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3922 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1356 # number of times the floating registers were written -system.cpu0.num_mem_refs 13659512 # number of memory refs -system.cpu0.num_load_insts 7847120 # Number of load instructions -system.cpu0.num_store_insts 5812392 # Number of store instructions -system.cpu0.num_idle_cycles 3486759367.777020 # Number of idle cycles -system.cpu0.num_busy_cycles -933867325.777020 # Number of busy cycles +system.cpu0.num_mem_refs 13659420 # number of memory refs +system.cpu0.num_load_insts 7847088 # Number of load instructions +system.cpu0.num_store_insts 5812332 # Number of store instructions +system.cpu0.num_idle_cycles 3486764467.544441 # Number of idle cycles +system.cpu0.num_busy_cycles -933868699.544441 # Number of busy cycles system.cpu0.not_idle_fraction -0.365808 # Percentage of non-idle cycles system.cpu0.idle_fraction 1.365808 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed @@ -658,65 +643,65 @@ system.cpu0.icache.total_refs 60644038 # To system.cpu0.icache.sampled_refs 856594 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 70.796711 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 18804733000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 354.105005 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 156.872348 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.691611 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.306391 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 354.101290 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 156.876063 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.691604 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.306399 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.998003 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 30350365 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30293673 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu0.inst 30350406 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 30293632 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 60644038 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 30350365 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30293673 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu0.inst 30350406 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 30293632 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 60644038 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 30350365 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 30293673 # number of overall hits +system.cpu0.icache.overall_hits::cpu0.inst 30350406 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 30293632 # number of overall hits system.cpu0.icache.overall_hits::total 60644038 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 416372 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 440222 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu0.inst 416381 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 440213 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 856594 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 416372 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 440222 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu0.inst 416381 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 440213 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 856594 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 416372 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 440222 # number of overall misses +system.cpu0.icache.overall_misses::cpu0.inst 416381 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 440213 # number of overall misses system.cpu0.icache.overall_misses::total 856594 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5679878500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5933784000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11613662500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5679878500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 5933784000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11613662500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5679878500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 5933784000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11613662500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30766737 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 30733895 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5680035500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5933793500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11613829000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5680035500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 5933793500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11613829000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5680035500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 5933793500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11613829000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30766787 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 30733845 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 61500632 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30766737 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 30733895 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu0.inst 30766787 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 30733845 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 61500632 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30766737 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 30733895 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30766787 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 30733845 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 61500632 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013533 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014324 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014323 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.013928 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013533 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014324 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014323 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.013928 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013533 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014324 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014323 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013928 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13641.355567 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13479.071923 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13557.954527 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13641.355567 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13479.071923 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13557.954527 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13641.355567 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13479.071923 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13557.954527 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13641.437770 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13479.369078 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13558.148901 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13641.437770 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13479.369078 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13558.148901 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13641.437770 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13479.369078 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13558.148901 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -725,46 +710,46 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 416372 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 440222 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 416381 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 440213 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 856594 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 416372 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 440222 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 416381 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 440213 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 856594 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 416372 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 440222 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 416381 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 440213 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 856594 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4847134500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5053340000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9900474500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4847134500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5053340000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9900474500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4847134500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5053340000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9900474500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4847273500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5053367500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9900641000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4847273500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5053367500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9900641000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4847273500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5053367500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9900641000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 298856500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 298856500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 298856500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 298856500 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013533 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014324 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014323 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013928 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013533 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014324 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014323 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.013928 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013533 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014324 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014323 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.013928 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11641.355567 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11479.071923 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11557.954527 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11641.355567 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11479.071923 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11557.954527 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11641.355567 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11479.071923 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11557.954527 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11641.437770 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11479.369078 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11558.148901 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11641.437770 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11479.369078 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11558.148901 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11641.437770 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11479.369078 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11558.148901 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency @@ -776,107 +761,107 @@ system.cpu0.dcache.total_refs 23658997 # To system.cpu0.dcache.sampled_refs 628094 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 37.667924 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 472186000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 366.656660 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 145.256121 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.716126 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.283703 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 366.658408 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 145.254373 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.716130 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.283700 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999830 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6610551 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6586942 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu0.data 6610508 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6586985 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 13197493 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4931268 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 5043253 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4931207 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 5043314 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 9974521 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 109193 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 127143 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 109194 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 127142 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 236336 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 114800 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 132950 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 114801 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 132949 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 247750 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11541819 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 11630195 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 11541715 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 11630299 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 23172014 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11541819 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 11630195 # number of overall hits +system.cpu0.dcache.overall_hits::cpu0.data 11541715 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 11630299 # number of overall hits system.cpu0.dcache.overall_hits::total 23172014 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 188165 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 180848 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu0.data 188176 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 180837 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 369013 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 124396 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 126168 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 124397 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 126167 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 250564 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 5607 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5808 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 5608 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5807 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 11415 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 312561 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 307016 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu0.data 312573 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 307004 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 619577 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 312561 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 307016 # number of overall misses +system.cpu0.dcache.overall_misses::cpu0.data 312573 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 307004 # number of overall misses system.cpu0.dcache.overall_misses::total 619577 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2684596500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2560064500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5244661000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 3933387000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 4106921000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8040308000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 77883000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 77590000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 155473000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 6617983500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 6666985500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 13284969000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 6617983500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 6666985500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 13284969000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6798716 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6767790 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2684372000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2560293500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5244665500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 3933510000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 4106405000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8039915000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 77896000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 77564000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 155460000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 6617882000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 6666698500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 13284580500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 6617882000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 6666698500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 13284580500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6798684 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6767822 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 13566506 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5055664 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5169421 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5055604 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5169481 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 10225085 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 114800 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 132951 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 114802 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 132949 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 247751 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 114800 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 132950 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 114801 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 132949 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247750 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11854380 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11937211 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 11854288 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 11937303 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 23791591 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11854380 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11937211 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11854288 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 11937303 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 23791591 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027677 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026722 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027678 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026720 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.027200 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024605 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024407 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024606 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024406 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.024505 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048841 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.043685 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048849 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.043678 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046074 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026367 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025719 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026368 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025718 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.026042 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026367 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025719 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026368 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025718 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.026042 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14267.246831 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14155.890582 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14212.672724 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31619.883276 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 32551.209498 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 32088.839578 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13890.315677 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13359.159780 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13620.061323 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21173.414150 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21715.433398 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 21441.998331 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21173.414150 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21715.433398 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 21441.998331 # average overall miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14265.219794 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14158.017994 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14212.684919 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31620.617861 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 32547.377682 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 32087.271116 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13890.156919 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13356.982952 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13618.922470 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21172.276556 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21715.347357 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 21441.371290 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21172.276556 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21715.347357 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 21441.371290 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -887,79 +872,79 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 596435 # number of writebacks system.cpu0.dcache.writebacks::total 596435 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188165 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 180848 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188176 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 180837 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 369013 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 124396 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 126168 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 124397 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 126167 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 250564 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5607 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5808 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5608 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5807 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11415 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 312561 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 307016 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 312573 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 307004 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 619577 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 312561 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 307016 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 312573 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 307004 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 619577 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2308266500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2198368500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4506635000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3684595000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3854585000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7539180000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66669000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 65974000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 132643000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5992861500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6052953500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12045815000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5992861500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6052953500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12045815000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91377449500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90718593500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182096043000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 9611433000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 9088267500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 18699700500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2308020000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2198619500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4506639500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3684716000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3854071000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7538787000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66680000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 65950000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 132630000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5992736000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6052690500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12045426500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5992736000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6052690500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12045426500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91377755000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90718296000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182096051000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 9611257000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 9088544500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 18699801500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 117500 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 117500 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 100988882500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 99806861000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200795743500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027677 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026722 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 100989012000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 99806840500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200795852500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027678 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026720 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027200 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024605 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024407 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024606 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024406 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048841 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043685 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048849 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043678 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046074 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026367 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025719 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026368 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025718 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.026042 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026367 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025719 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026368 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025718 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.026042 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12267.246831 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12155.890582 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12212.672724 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29619.883276 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30551.209498 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30088.839578 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11890.315677 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11359.159780 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11620.061323 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19173.414150 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19715.433398 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19441.998331 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19173.414150 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19715.433398 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19441.998331 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12265.219794 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12158.017994 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12212.684919 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29620.617861 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30547.377682 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30087.271116 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11890.156919 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11356.982952 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11618.922470 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19172.276556 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19715.347357 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19441.371290 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19172.276556 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19715.347357 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19441.371290 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -976,26 +961,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7490923 # DTB read hits -system.cpu1.dtb.read_misses 7080 # DTB read misses -system.cpu1.dtb.write_hits 5680189 # DTB write hits -system.cpu1.dtb.write_misses 1780 # DTB write misses +system.cpu1.dtb.read_hits 7490951 # DTB read hits +system.cpu1.dtb.read_misses 7083 # DTB read misses +system.cpu1.dtb.write_hits 5680260 # DTB write hits +system.cpu1.dtb.write_misses 1778 # DTB write misses system.cpu1.dtb.flush_tlb 1275 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6451 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 6452 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 157 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 207 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7498003 # DTB read accesses -system.cpu1.dtb.write_accesses 5681969 # DTB write accesses +system.cpu1.dtb.read_accesses 7498034 # DTB read accesses +system.cpu1.dtb.write_accesses 5682038 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13171112 # DTB hits -system.cpu1.dtb.misses 8860 # DTB misses -system.cpu1.dtb.accesses 13179972 # DTB accesses -system.cpu1.itb.inst_hits 30733895 # ITB inst hits +system.cpu1.dtb.hits 13171211 # DTB hits +system.cpu1.dtb.misses 8861 # DTB misses +system.cpu1.dtb.accesses 13180072 # DTB accesses +system.cpu1.itb.inst_hits 30733845 # ITB inst hits system.cpu1.itb.inst_misses 3661 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1012,30 +997,30 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 30737556 # ITB inst accesses -system.cpu1.itb.hits 30733895 # DTB hits +system.cpu1.itb.inst_accesses 30737506 # ITB inst accesses +system.cpu1.itb.hits 30733845 # DTB hits system.cpu1.itb.misses 3661 # DTB misses -system.cpu1.itb.accesses 30737556 # DTB accesses -system.cpu1.numCycles 2664665536 # number of cpu cycles simulated +system.cpu1.itb.accesses 30737506 # DTB accesses +system.cpu1.numCycles 2664661810 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30062453 # Number of instructions committed -system.cpu1.committedOps 38319221 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34454483 # Number of integer alu accesses +system.cpu1.committedInsts 30062381 # Number of instructions committed +system.cpu1.committedOps 38319191 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34454554 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 4993 # Number of float alu accesses -system.cpu1.num_func_calls 1098871 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3931518 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34454483 # number of integer instructions +system.cpu1.num_func_calls 1098878 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3931539 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34454554 # number of integer instructions system.cpu1.num_fp_insts 4993 # number of float instructions -system.cpu1.num_int_register_reads 197476279 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37039984 # number of times the integer registers were written +system.cpu1.num_int_register_reads 197476132 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37039734 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3571 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1424 # number of times the floating registers were written -system.cpu1.num_mem_refs 13738954 # number of memory refs -system.cpu1.num_load_insts 7815473 # Number of load instructions -system.cpu1.num_store_insts 5923481 # Number of store instructions -system.cpu1.num_idle_cycles 1359992851.787481 # Number of idle cycles -system.cpu1.num_busy_cycles 1304672684.212520 # Number of busy cycles +system.cpu1.num_mem_refs 13739046 # number of memory refs +system.cpu1.num_load_insts 7815505 # Number of load instructions +system.cpu1.num_store_insts 5923541 # Number of store instructions +system.cpu1.num_idle_cycles 1359990951.127739 # Number of idle cycles +system.cpu1.num_busy_cycles 1304670858.872261 # Number of busy cycles system.cpu1.not_idle_fraction 0.489620 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.510380 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -1054,10 +1039,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1196180344448 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1196180344448 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1196180344448 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1196180344448 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1196198690564 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1196198690564 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1196198690564 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1196198690564 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index f940daeff..171e4af9f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,143 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.140861 # Number of seconds simulated -sim_ticks 5140860798000 # Number of ticks simulated -final_tick 5140860798000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.136865 # Number of seconds simulated +sim_ticks 5136864535500 # Number of ticks simulated +final_tick 5136864535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 170494 # Simulator instruction rate (inst/s) -host_op_rate 337025 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2148706625 # Simulator tick rate (ticks/s) -host_mem_usage 754648 # Number of bytes of host memory used -host_seconds 2392.54 # Real time elapsed on the host -sim_insts 407913764 # Number of instructions simulated -sim_ops 806343994 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2474560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory +host_inst_rate 199949 # Simulator instruction rate (inst/s) +host_op_rate 395248 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2517891877 # Simulator tick rate (ticks/s) +host_mem_usage 755196 # Number of bytes of host memory used +host_seconds 2040.15 # Real time elapsed on the host +sim_insts 407925588 # Number of instructions simulated +sim_ops 806363480 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2498048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3136 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1078400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10800768 # Number of bytes read from this memory -system.physmem.bytes_read::total 14357184 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1078400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1078400 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9566720 # Number of bytes written to this memory -system.physmem.bytes_written::total 9566720 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38665 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1077760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10804608 # Number of bytes read from this memory +system.physmem.bytes_read::total 14383936 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1077760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1077760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9566528 # Number of bytes written to this memory +system.physmem.bytes_written::total 9566528 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 39032 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 49 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16850 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168762 # Number of read requests responded to by this memory -system.physmem.num_reads::total 224331 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149480 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149480 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 481351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 598 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16840 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168822 # Number of read requests responded to by this memory +system.physmem.num_reads::total 224749 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149477 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149477 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 486298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 610 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 209770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2100965 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2792759 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 209770 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 209770 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1860918 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1860918 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1860918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 481351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 209809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2103347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2800139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 209809 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 209809 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1862328 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1862328 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1862328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 486298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 610 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 209770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2100965 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4653677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 224331 # Total number of read requests seen -system.physmem.writeReqs 149480 # Total number of write requests seen -system.physmem.cpureqs 389156 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 14357184 # Total number of bytes read from memory -system.physmem.bytesWritten 9566720 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14357184 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9566720 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 64 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4099 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 14350 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 13262 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 13450 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 16479 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13640 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 13135 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13368 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 16367 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13625 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 12973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 13147 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 15567 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13297 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12659 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 13305 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 15643 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 9342 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 8759 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8814 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 11838 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8747 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 8497 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8701 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 11708 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8726 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8403 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 8587 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 10999 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8504 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8205 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8619 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 11031 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 209809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2103347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4662468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 224749 # Total number of read requests seen +system.physmem.writeReqs 149477 # Total number of write requests seen +system.physmem.cpureqs 378758 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14383936 # Total number of bytes read from memory +system.physmem.bytesWritten 9566528 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14383936 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9566528 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 97 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3970 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 14108 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 13038 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 13174 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 16315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13707 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 13158 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13525 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 16255 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13935 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 13285 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 13290 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 15648 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 13203 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 12660 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 13428 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 15923 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 9005 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 8432 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 8529 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 11625 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 8800 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 8560 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8903 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 11692 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 9007 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 8684 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 8693 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 11170 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8382 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8108 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8695 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 11192 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1147 # Number of times wr buffer was full causing retry -system.physmem.totGap 5140860745500 # Total gap between requests +system.physmem.numWrRetry 562 # Number of times wr buffer was full causing retry +system.physmem.totGap 5136864483000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 224331 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 150627 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4099 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 173172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 19537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3492 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2979 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2415 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1784 # What read queue length does an incoming req see +system.physmem.readPktSize::6 224749 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 149477 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 173174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 19685 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3015 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1773 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1717 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1145 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 886 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 796 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 418 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 885 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 870 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 386 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -149,16 +136,15 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6490 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 6499 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 6499 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 6499 # What write queue length does an incoming req see @@ -173,70 +159,69 @@ system.physmem.wrQLenPdf::19 6499 # Wh system.physmem.wrQLenPdf::20 6499 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 6499 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4794174501 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9303317001 # Sum of mem lat for all requests -system.physmem.totBusLat 1121335000 # Total cycles spent in databus access -system.physmem.totBankLat 3387807500 # Total cycles spent in bank access -system.physmem.avgQLat 21377.08 # Average queueing delay per request -system.physmem.avgBankLat 15106.13 # Average bank access latency per request +system.physmem.wrQLenPdf::23 1140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see +system.physmem.totQLat 4764271250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9277483750 # Sum of mem lat for all requests +system.physmem.totBusLat 1123260000 # Total cycles spent in databus access +system.physmem.totBankLat 3389952500 # Total cycles spent in bank access +system.physmem.avgQLat 21207.34 # Average queueing delay per request +system.physmem.avgBankLat 15089.79 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 41483.22 # Average memory access latency -system.physmem.avgRdBW 2.79 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 41297.13 # Average memory access latency +system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.79 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 8.88 # Average write queue length over time -system.physmem.readRowHits 193356 # Number of row buffer hits during reads -system.physmem.writeRowHits 105797 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.22 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.78 # Row buffer hit rate for writes -system.physmem.avgGap 13752566.79 # Average gap between requests -system.iocache.replacements 47574 # number of replacements -system.iocache.tagsinuse 0.128668 # Cycle average of tags in use +system.physmem.avgWrQLen 11.02 # Average write queue length over time +system.physmem.readRowHits 193727 # Number of row buffer hits during reads +system.physmem.writeRowHits 105780 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.23 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.77 # Row buffer hit rate for writes +system.physmem.avgGap 13726637.07 # Average gap between requests +system.iocache.replacements 47576 # number of replacements +system.iocache.tagsinuse 0.116322 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47590 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4991908358000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.128668 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.008042 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.008042 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses -system.iocache.ReadReq_misses::total 909 # number of ReadReq misses +system.iocache.warmup_cycle 4991909238000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.116322 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.007270 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.007270 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses +system.iocache.ReadReq_misses::total 911 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47629 # number of demand (read+write) misses -system.iocache.demand_misses::total 47629 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47629 # number of overall misses -system.iocache.overall_misses::total 47629 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143200932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 143200932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10097082160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10097082160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10240283092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10240283092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10240283092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10240283092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses +system.iocache.demand_misses::total 47631 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses +system.iocache.overall_misses::total 47631 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151593932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 151593932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10023192160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10023192160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10174786092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10174786092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10174786092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10174786092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47629 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47629 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -245,40 +230,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 157536.778878 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 157536.778878 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 216119.053082 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 216119.053082 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 215001.009721 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 215001.009721 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 215001.009721 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 215001.009721 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 136887 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166403.877058 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 166403.877058 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214537.503425 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 214537.503425 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 213616.890093 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 213616.890093 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 213616.890093 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 213616.890093 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 136470 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 12650 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 12410 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.821107 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.996777 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47629 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47629 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47629 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47629 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95911989 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 95911989 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7666293817 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7666293817 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7762205806 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7762205806 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7762205806 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7762205806 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104200712 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 104200712 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7592410619 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7592410619 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7696611331 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7696611331 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7696611331 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7696611331 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -287,14 +272,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105513.739274 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 105513.739274 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 164090.193001 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 164090.193001 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162972.260724 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 162972.260724 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162972.260724 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 162972.260724 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114380.583974 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 114380.583974 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162508.788934 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 162508.788934 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 161588.279293 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 161588.279293 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 161588.279293 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 161588.279293 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -308,142 +293,142 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 86195570 # Number of BP lookups -system.cpu.branchPred.condPredicted 86195570 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1107298 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 81287324 # Number of BTB lookups -system.cpu.branchPred.BTBHits 79211919 # Number of BTB hits +system.cpu.branchPred.lookups 86198193 # Number of BP lookups +system.cpu.branchPred.condPredicted 86198193 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1106234 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 81290548 # Number of BTB lookups +system.cpu.branchPred.BTBHits 79213904 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.446828 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 97.445405 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.numCycles 448232203 # number of cpu cycles simulated +system.cpu.numCycles 448153841 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27444393 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 425935714 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86195570 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79211919 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 163577459 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4703661 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 120329 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 63100618 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36734 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 50393 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 353 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9010824 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 484273 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3255 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 257888489 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.260624 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.418001 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27415171 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 425937394 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86198193 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79213904 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 163576958 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4698498 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 117961 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 63103393 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36350 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 51299 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 436 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9010068 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 483485 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3126 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 257855511 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.261045 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.418033 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 94737944 36.74% 36.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1567529 0.61% 37.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71915391 27.89% 65.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 936422 0.36% 65.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1600476 0.62% 66.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2419747 0.94% 67.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1072144 0.42% 67.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1374255 0.53% 68.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82264581 31.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 94705411 36.73% 36.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1566235 0.61% 37.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71918028 27.89% 65.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 935930 0.36% 65.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1598963 0.62% 66.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2419267 0.94% 67.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1070398 0.42% 67.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1376464 0.53% 68.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82264815 31.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 257888489 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192301 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.950257 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31158433 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60539785 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159369860 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3262201 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3558210 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 837747525 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 908 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3558210 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33896779 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37429027 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10979367 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159568616 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12456490 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 834117350 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19334 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5870357 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4754276 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 7741 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 995632267 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1810669462 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1810668566 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 896 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964317189 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31315071 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 459232 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 466806 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 28815526 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17065121 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10125717 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1247966 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 991465 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 828007231 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1251140 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 823065161 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 148512 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 22000890 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33478625 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 198442 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 257888489 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.191554 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.384086 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 257855511 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192341 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.950427 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31132857 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60536501 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159370274 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3261936 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3553943 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 837748670 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 951 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3553943 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33869883 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37385632 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 11021591 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159568277 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12456185 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 834115262 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19668 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5867494 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4754545 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 8312 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 995635482 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1810665967 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1810665163 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 804 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964341342 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 31294133 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 459159 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 467055 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 28798095 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17056943 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10123506 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1248285 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 987203 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 827998215 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1251183 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 823066756 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 148002 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21984557 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33441202 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 198541 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 257855511 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.191969 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.384014 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 71416188 27.69% 27.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15522620 6.02% 33.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10297220 3.99% 37.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7470539 2.90% 40.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75900478 29.43% 70.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3837629 1.49% 71.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72511548 28.12% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 780997 0.30% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 151270 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 71390186 27.69% 27.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15517919 6.02% 33.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10294138 3.99% 37.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7464826 2.89% 40.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75904474 29.44% 70.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3838948 1.49% 71.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72513480 28.12% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 779753 0.30% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 151787 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 257888489 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 257855511 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 362608 34.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 553228 51.88% 85.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 150521 14.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 363612 34.06% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 553162 51.82% 85.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 150741 14.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 311367 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 795535215 96.66% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 311137 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 795540449 96.66% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued @@ -472,246 +457,246 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17840146 2.17% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9378433 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17836742 2.17% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9378428 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 823065161 # Type of FU issued -system.cpu.iq.rate 1.836247 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1066357 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001296 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1905364388 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 851269170 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 818594497 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 333 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 414 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 81 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 823820002 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 149 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1640065 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 823066756 # Type of FU issued +system.cpu.iq.rate 1.836572 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1067515 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001297 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1905334904 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 851243829 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 818598323 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 260 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 368 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 63 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 823823020 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 114 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1639481 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3087216 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 23041 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11568 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1713876 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3079539 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 22701 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11520 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1710580 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932419 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12043 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932434 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12204 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3558210 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26163339 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2115746 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 829258371 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 321958 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17065121 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10125717 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 719121 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1615790 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11387 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11568 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 649229 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 593828 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1243057 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 821192043 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17430508 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1873117 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3553943 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26124965 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2116869 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 829249398 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 321104 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17056943 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10123506 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 718931 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1615774 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 10404 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11520 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 649169 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 592997 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1242166 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 821195112 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17426068 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1871643 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26576754 # number of memory reference insts executed -system.cpu.iew.exec_branches 83195358 # Number of branches executed -system.cpu.iew.exec_stores 9146246 # Number of stores executed -system.cpu.iew.exec_rate 1.832068 # Inst execution rate -system.cpu.iew.wb_sent 820730031 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 818594578 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639788924 # num instructions producing a value -system.cpu.iew.wb_consumers 1045548924 # num instructions consuming a value +system.cpu.iew.exec_refs 26572625 # number of memory reference insts executed +system.cpu.iew.exec_branches 83197450 # Number of branches executed +system.cpu.iew.exec_stores 9146557 # Number of stores executed +system.cpu.iew.exec_rate 1.832396 # Inst execution rate +system.cpu.iew.wb_sent 820733466 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 818598386 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639795417 # num instructions producing a value +system.cpu.iew.wb_consumers 1045555736 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.826273 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611917 # average fanout of values written-back +system.cpu.iew.wb_rate 1.826601 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611919 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 22806507 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1052696 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1111685 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 254330279 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.170460 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.853927 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 22777543 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1052640 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1110740 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 254301568 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.170895 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.853974 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82551524 32.46% 32.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11813015 4.64% 37.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3912372 1.54% 38.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74944552 29.47% 68.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2436279 0.96% 69.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1482727 0.58% 69.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 942941 0.37% 70.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70918770 27.88% 97.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5328099 2.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82529406 32.45% 32.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11802979 4.64% 37.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3912644 1.54% 38.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74944166 29.47% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2437687 0.96% 69.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1481720 0.58% 69.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 940520 0.37% 70.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70919321 27.89% 97.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5333125 2.10% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 254330279 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407913764 # Number of instructions committed -system.cpu.commit.committedOps 806343994 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 254301568 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407925588 # Number of instructions committed +system.cpu.commit.committedOps 806363480 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22389743 # Number of memory references committed -system.cpu.commit.loads 13977902 # Number of loads committed -system.cpu.commit.membars 473467 # Number of memory barriers committed -system.cpu.commit.branches 82188680 # Number of branches committed +system.cpu.commit.refs 22390327 # Number of memory references committed +system.cpu.commit.loads 13977401 # Number of loads committed +system.cpu.commit.membars 473457 # Number of memory barriers committed +system.cpu.commit.branches 82191015 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735286834 # Number of committed integer instructions. +system.cpu.commit.int_insts 735304742 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5328099 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5333125 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1078074430 # The number of ROB reads -system.cpu.rob.rob_writes 1661878047 # The number of ROB writes -system.cpu.timesIdled 1220922 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 190343714 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9833486813 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407913764 # Number of Instructions Simulated -system.cpu.committedOps 806343994 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407913764 # Number of Instructions Simulated -system.cpu.cpi 1.098841 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.098841 # CPI: Total CPI of All Threads -system.cpu.ipc 0.910050 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.910050 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1506675506 # number of integer regfile reads -system.cpu.int_regfile_writes 976772305 # number of integer regfile writes -system.cpu.fp_regfile_reads 81 # number of floating regfile reads -system.cpu.misc_regfile_reads 264620330 # number of misc regfile reads -system.cpu.misc_regfile_writes 402287 # number of misc regfile writes -system.cpu.icache.replacements 1047202 # number of replacements -system.cpu.icache.tagsinuse 510.392599 # Cycle average of tags in use -system.cpu.icache.total_refs 7900027 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1047714 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.540251 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 1078031216 # The number of ROB reads +system.cpu.rob.rob_writes 1661854677 # The number of ROB writes +system.cpu.timesIdled 1219790 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 190298330 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9825572650 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407925588 # Number of Instructions Simulated +system.cpu.committedOps 806363480 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407925588 # Number of Instructions Simulated +system.cpu.cpi 1.098617 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.098617 # CPI: Total CPI of All Threads +system.cpu.ipc 0.910236 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.910236 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1506687590 # number of integer regfile reads +system.cpu.int_regfile_writes 976781809 # number of integer regfile writes +system.cpu.fp_regfile_reads 63 # number of floating regfile reads +system.cpu.misc_regfile_reads 264621583 # number of misc regfile reads +system.cpu.misc_regfile_writes 402234 # number of misc regfile writes +system.cpu.icache.replacements 1045798 # number of replacements +system.cpu.icache.tagsinuse 510.125014 # Cycle average of tags in use +system.cpu.icache.total_refs 7900747 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1046310 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.551058 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 56071908000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.392599 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996861 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996861 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7900027 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7900027 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7900027 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7900027 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7900027 # number of overall hits -system.cpu.icache.overall_hits::total 7900027 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1110794 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1110794 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1110794 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1110794 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1110794 # number of overall misses -system.cpu.icache.overall_misses::total 1110794 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15299065993 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15299065993 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15299065993 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15299065993 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15299065993 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15299065993 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9010821 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9010821 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9010821 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9010821 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9010821 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9010821 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123273 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123273 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123273 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123273 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123273 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123273 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13773.090234 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13773.090234 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13773.090234 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13773.090234 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13773.090234 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13773.090234 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 10781 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 510.125014 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996338 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996338 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7900747 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7900747 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7900747 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7900747 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7900747 # number of overall hits +system.cpu.icache.overall_hits::total 7900747 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1109320 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1109320 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1109320 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1109320 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1109320 # number of overall misses +system.cpu.icache.overall_misses::total 1109320 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15268069493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15268069493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15268069493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15268069493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15268069493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15268069493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9010067 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9010067 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9010067 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9010067 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9010067 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9010067 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123120 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123120 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123120 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123120 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123120 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123120 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13763.449224 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13763.449224 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13763.449224 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13763.449224 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13763.449224 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13763.449224 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 12508 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 279 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 293 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 38.641577 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 42.689420 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60632 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 60632 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 60632 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 60632 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 60632 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 60632 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1050162 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1050162 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1050162 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1050162 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1050162 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1050162 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12588415993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12588415993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12588415993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12588415993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12588415993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12588415993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116545 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116545 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116545 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116545 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116545 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116545 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11987.118171 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11987.118171 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11987.118171 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11987.118171 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11987.118171 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11987.118171 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60685 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 60685 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 60685 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 60685 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 60685 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 60685 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1048635 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1048635 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1048635 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1048635 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1048635 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1048635 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12573562493 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12573562493 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12573562493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12573562493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12573562493 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12573562493 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116385 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116385 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116385 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116385 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116385 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116385 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11990.408954 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11990.408954 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11990.408954 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11990.408954 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11990.408954 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11990.408954 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 9719 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.023103 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 25822 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 9733 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.653036 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5104044206500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.023103 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376444 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.376444 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25827 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 25827 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 9600 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.016014 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 25681 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 9614 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.671209 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5103990045500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.016014 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376001 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.376001 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25689 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 25689 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25829 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 25829 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25829 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 25829 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10616 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 10616 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10616 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 10616 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10616 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 10616 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 119043500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 119043500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 119043500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 119043500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 119043500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 119043500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36443 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 36443 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25691 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 25691 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25691 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 25691 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10488 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 10488 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10488 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 10488 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10488 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 10488 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 116654500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 116654500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 116654500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 116654500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 116654500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 116654500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36177 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 36177 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36445 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 36445 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36445 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 36445 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.291304 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.291304 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.291288 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.291288 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.291288 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.291288 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11213.592690 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11213.592690 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11213.592690 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11213.592690 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11213.592690 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11213.592690 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36179 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 36179 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36179 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 36179 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.289908 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.289908 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.289892 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.289892 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.289892 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.289892 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11122.663997 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11122.663997 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11122.663997 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11122.663997 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11122.663997 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11122.663997 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -720,78 +705,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 2031 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 2031 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10616 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10616 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10616 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10616 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10616 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 10616 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 97811500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 97811500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 97811500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 97811500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 97811500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 97811500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.291304 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.291304 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.291288 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.291288 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.291288 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.291288 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9213.592690 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9213.592690 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9213.592690 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9213.592690 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9213.592690 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9213.592690 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1936 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1936 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10488 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10488 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10488 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10488 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10488 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 10488 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 95678500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 95678500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 95678500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 95678500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 95678500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 95678500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.289908 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.289908 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.289892 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.289892 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.289892 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.289892 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9122.663997 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9122.663997 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9122.663997 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 109067 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.961436 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 135080 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 109080 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.238357 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5099784110000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.961436 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.810090 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.810090 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 135158 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 135158 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 135158 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 135158 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 135158 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 135158 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110111 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 110111 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110111 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 110111 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110111 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 110111 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1384932000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1384932000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1384932000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1384932000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1384932000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1384932000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 245269 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 245269 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 245269 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 245269 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 245269 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 245269 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.448940 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.448940 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.448940 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.448940 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.448940 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.448940 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12577.598968 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12577.598968 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12577.598968 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12577.598968 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12577.598968 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12577.598968 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 108181 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 12.959012 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 134869 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 108196 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.246525 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5099781673000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.959012 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809938 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.809938 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 134886 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 134886 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 134886 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 134886 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 134886 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 134886 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 109218 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 109218 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 109218 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 109218 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 109218 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 109218 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1375116000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1375116000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1375116000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1375116000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1375116000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1375116000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 244104 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 244104 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 244104 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 244104 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 244104 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 244104 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.447424 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.447424 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.447424 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.447424 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.447424 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.447424 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12590.561995 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12590.561995 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12590.561995 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12590.561995 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12590.561995 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12590.561995 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -800,146 +785,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 36570 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 36570 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110111 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110111 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110111 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 110111 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110111 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 110111 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1164710000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1164710000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1164710000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1164710000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1164710000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1164710000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.448940 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.448940 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.448940 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.448940 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.448940 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.448940 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10577.598968 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10577.598968 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10577.598968 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10577.598968 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10577.598968 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10577.598968 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 35252 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 35252 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 109218 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 109218 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 109218 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 109218 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 109218 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 109218 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1156680000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1156680000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1156680000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1156680000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1156680000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1156680000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.447424 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.447424 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.447424 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.447424 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.447424 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.447424 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10590.561995 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10590.561995 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10590.561995 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10590.561995 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10590.561995 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10590.561995 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1659765 # number of replacements -system.cpu.dcache.tagsinuse 511.990842 # Cycle average of tags in use -system.cpu.dcache.total_refs 19082473 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1660277 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.493548 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1660118 # number of replacements +system.cpu.dcache.tagsinuse 511.992206 # Cycle average of tags in use +system.cpu.dcache.total_refs 19078637 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1660630 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.488795 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 27985000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.990842 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999982 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999982 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10992813 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10992813 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8084535 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8084535 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19077348 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19077348 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19077348 # number of overall hits -system.cpu.dcache.overall_hits::total 19077348 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2235315 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2235315 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318075 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318075 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2553390 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2553390 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2553390 # number of overall misses -system.cpu.dcache.overall_misses::total 2553390 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32075751500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32075751500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9669659497 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9669659497 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41745410997 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41745410997 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41745410997 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41745410997 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13228128 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13228128 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8402610 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8402610 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21630738 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21630738 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21630738 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21630738 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168982 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.168982 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037854 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037854 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118045 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118045 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118045 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118045 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14349.544248 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14349.544248 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30400.564323 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30400.564323 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16349.014838 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16349.014838 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16349.014838 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16349.014838 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 385443 # number of cycles access was blocked +system.cpu.dcache.occ_blocks::cpu.data 511.992206 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10987895 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10987895 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8085738 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8085738 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19073633 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19073633 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19073633 # number of overall hits +system.cpu.dcache.overall_hits::total 19073633 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2236252 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2236252 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317957 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317957 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2554209 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2554209 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2554209 # number of overall misses +system.cpu.dcache.overall_misses::total 2554209 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32134007500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32134007500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9664278994 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9664278994 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41798286494 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41798286494 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41798286494 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41798286494 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13224147 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13224147 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8403695 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8403695 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21627842 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21627842 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21627842 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21627842 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169104 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.169104 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037835 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037835 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118098 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118098 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118098 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118098 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14369.582453 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14369.582453 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30394.924452 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30394.924452 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16364.473892 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16364.473892 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16364.473892 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16364.473892 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 400642 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42285 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42486 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.115360 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.429977 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1561573 # number of writebacks -system.cpu.dcache.writebacks::total 1561573 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 863477 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 863477 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24970 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 24970 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 888447 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 888447 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 888447 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 888447 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371838 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1371838 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 293105 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 293105 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1664943 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1664943 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1664943 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1664943 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17433703000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17433703000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8829680997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8829680997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26263383997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26263383997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26263383997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26263383997 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296997000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296997000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470922500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470922500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767919500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767919500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103706 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103706 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034883 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034883 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076971 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076971 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076971 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076971 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12708.281153 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12708.281153 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30124.634506 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30124.634506 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15774.344225 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15774.344225 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15774.344225 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15774.344225 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1561388 # number of writebacks +system.cpu.dcache.writebacks::total 1561388 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864027 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 864027 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25006 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 25006 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 889033 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 889033 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 889033 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 889033 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1372225 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1372225 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292951 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 292951 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1665176 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1665176 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1665176 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1665176 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17481793000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17481793000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8820305494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8820305494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26302098494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26302098494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26302098494 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26302098494 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296698500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296698500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470686500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470686500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767385000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767385000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103767 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103767 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034860 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034860 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076992 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076992 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076992 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076992 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12739.742389 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12739.742389 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30108.466925 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30108.466925 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15795.386490 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15795.386490 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15795.386490 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15795.386490 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -947,141 +932,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 113143 # number of replacements -system.cpu.l2cache.tagsinuse 64828.008913 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3933194 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 177289 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.185212 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 113561 # number of replacements +system.cpu.l2cache.tagsinuse 64842.483679 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3930962 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 177626 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.130555 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 50000.769302 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 10.826981 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.134900 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3307.164355 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 11509.113375 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.762951 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000165 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 50033.446344 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 10.888296 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.133449 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3280.677554 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 11517.338036 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.763450 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000166 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.050463 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.175615 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989197 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 102962 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8277 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1030819 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1333964 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2476022 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1600174 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1600174 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 327 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 327 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 156003 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 156003 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 102962 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 8277 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1030819 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1489967 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2632025 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 102962 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 8277 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1030819 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1489967 # number of overall hits -system.cpu.l2cache.overall_hits::total 2632025 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 48 # number of ReadReq misses +system.cpu.l2cache.occ_percent::cpu.inst 0.050059 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.175741 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.989418 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 102246 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8058 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1029420 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1334149 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2473873 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1598576 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1598576 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 345 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 345 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 156103 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 156103 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 102246 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 8058 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1029420 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1490252 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2629976 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 102246 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 8058 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1029420 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1490252 # number of overall hits +system.cpu.l2cache.overall_hits::total 2629976 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 49 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16851 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 36698 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 53603 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3825 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3825 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133009 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133009 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 48 # number of demand (read+write) misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 16841 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 36881 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 53777 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 3693 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 3693 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 132888 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 132888 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 49 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16851 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 169707 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 186612 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 48 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 16841 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 169769 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 186665 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 49 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16851 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 169707 # number of overall misses -system.cpu.l2cache.overall_misses::total 186612 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5800000 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 16841 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 169769 # number of overall misses +system.cpu.l2cache.overall_misses::total 186665 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6312000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1177383500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2492698000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3676271000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16893999 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 16893999 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6881289000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6881289000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5800000 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1177562500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2538376499 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3722640499 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16930000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 16930000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6874050999 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6874050999 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6312000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1177383500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9373987000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10557560000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5800000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1177562500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9412427498 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10596691498 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6312000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1177383500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9373987000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10557560000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 103010 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8283 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1047670 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1370662 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2529625 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1600174 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1600174 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4152 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 4152 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 289012 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 289012 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 103010 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 8283 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1047670 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1659674 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2818637 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 103010 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 8283 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1047670 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1659674 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2818637 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000466 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000724 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016084 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026774 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021190 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.921243 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.921243 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.460220 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.460220 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000466 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000724 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016084 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102253 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.066206 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000466 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000724 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016084 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102253 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.066206 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 120833.333333 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_latency::cpu.inst 1177562500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9412427498 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10596691498 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 102295 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8064 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1046261 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1371030 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2527650 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1598576 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1598576 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4038 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 4038 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 288991 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 288991 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 102295 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 8064 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1046261 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1660021 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2816641 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 102295 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 8064 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1046261 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1660021 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2816641 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000479 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000744 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016096 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026900 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021275 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.914562 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.914562 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.459834 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.459834 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000479 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000744 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016096 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102269 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.066272 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000479 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000744 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016096 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102269 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.066272 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 128816.326531 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 64916.666667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69870.245089 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67924.628045 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68583.306904 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4416.731765 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4416.731765 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51735.514138 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51735.514138 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 120833.333333 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69922.362093 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68826.129959 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69223.655076 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4584.348768 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4584.348768 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51728.154529 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51728.154529 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 128816.326531 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69870.245089 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55236.301390 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 56574.925514 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 120833.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69922.362093 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55442.557228 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 56768.497029 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 128816.326531 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69870.245089 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55236.301390 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 56574.925514 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69922.362093 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55442.557228 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 56768.497029 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1090,8 +1075,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 102813 # number of writebacks -system.cpu.l2cache.writebacks::total 102813 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 102810 # number of writebacks +system.cpu.l2cache.writebacks::total 102810 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits @@ -1101,88 +1086,88 @@ system.cpu.l2cache.demand_mshr_hits::total 2 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 48 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 49 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16850 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36697 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 53601 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3825 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 3825 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133009 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133009 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 48 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16840 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36880 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 53775 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3693 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 3693 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132888 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 132888 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 49 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16850 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 169706 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 186610 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 48 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16840 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 169768 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 186663 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 49 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16850 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 169706 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 186610 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5203838 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 314260 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 967803547 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2036732357 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3010054002 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 39193303 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 39193303 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5240927353 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5240927353 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5203838 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 314260 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 967803547 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7277659710 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8250981355 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5203838 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 314260 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 967803547 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7277659710 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8250981355 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89187688500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89187688500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308713500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308713500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91496402000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91496402000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000466 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000724 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016083 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026773 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021189 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.921243 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.921243 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.460220 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.460220 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000466 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000724 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016083 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102253 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.066206 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000466 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000724 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016083 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102253 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.066206 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 108413.291667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52376.666667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57436.412285 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55501.331362 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56156.676219 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10246.615163 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10246.615163 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39402.802464 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39402.802464 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 108413.291667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52376.666667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57436.412285 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42883.926968 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44215.108274 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 108413.291667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52376.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57436.412285 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42883.926968 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44215.108274 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16840 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 169768 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 186663 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5701045 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 314255 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 968087231 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2080048452 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3054150983 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 37901173 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 37901173 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5235111902 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5235111902 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5701045 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 314255 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 968087231 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7315160354 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8289262885 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5701045 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 314255 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 968087231 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7315160354 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8289262885 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89187415500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89187415500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308505000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308505000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91495920500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91495920500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000744 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016095 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026899 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021275 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.914562 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.914562 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459834 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459834 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000744 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016095 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102269 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.066271 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000744 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016095 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102269 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.066271 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 116347.857143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57487.365261 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56400.446095 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56794.997359 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10262.976713 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10262.976713 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39394.918292 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39394.918292 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 116347.857143 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57487.365261 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43089.159052 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44407.637748 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 116347.857143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57487.365261 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43089.159052 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44407.637748 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index e72c9ec7f..fbbf2dd62 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.204983 # Nu sim_ticks 5204982530500 # Number of ticks simulated final_tick 5204982530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181134 # Simulator instruction rate (inst/s) -host_op_rate 347511 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8731335326 # Simulator tick rate (ticks/s) -host_mem_usage 804468 # Number of bytes of host memory used -host_seconds 596.13 # Real time elapsed on the host +host_inst_rate 107235 # Simulator instruction rate (inst/s) +host_op_rate 205734 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5169140013 # Simulator tick rate (ticks/s) +host_mem_usage 810688 # Number of bytes of host memory used +host_seconds 1006.93 # Real time elapsed on the host sim_insts 107979054 # Number of instructions simulated sim_ops 207160582 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 35152 # Number of bytes read from this memory @@ -123,26 +123,13 @@ system.physmem.readPktSize::3 298 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 512 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 48406 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 46736 # Categorize write packet sizes system.physmem.rdQLenPdf::0 328 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see @@ -175,7 +162,6 @@ system.physmem.rdQLenPdf::28 2 # Wh system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1965 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1971 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1995 # What write queue length does an incoming req see @@ -208,15 +194,14 @@ system.physmem.wrQLenPdf::28 36 # Wh system.physmem.wrQLenPdf::29 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 33 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 40946729 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 52545479 # Sum of mem lat for all requests +system.physmem.totQLat 40945522 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 52544272 # Sum of mem lat for all requests system.physmem.totBusLat 4050000 # Total cycles spent in databus access system.physmem.totBankLat 7548750 # Total cycles spent in bank access -system.physmem.avgQLat 50551.52 # Average queueing delay per request +system.physmem.avgQLat 50550.03 # Average queueing delay per request system.physmem.avgBankLat 9319.44 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 64870.96 # Average memory access latency +system.physmem.avgMemAccLat 64869.47 # Average memory access latency system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 7484e6ff9..c659f4312 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.269672 # Nu sim_ticks 269671683500 # Number of ticks simulated final_tick 269671683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125294 # Simulator instruction rate (inst/s) -host_op_rate 125294 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56139844 # Simulator tick rate (ticks/s) -host_mem_usage 224468 # Number of bytes of host memory used -host_seconds 4803.57 # Real time elapsed on the host +host_inst_rate 149368 # Simulator instruction rate (inst/s) +host_op_rate 149368 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66926769 # Simulator tick rate (ticks/s) +host_mem_usage 224496 # Number of bytes of host memory used +host_seconds 4029.35 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -85,26 +85,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 26294 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1014 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 1014 # Categorize write packet sizes system.physmem.rdQLenPdf::0 16680 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 6777 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1890 # What read queue length does an incoming req see @@ -137,7 +124,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 37 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 384531397 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1096635147 # Sum of mem lat for all requests +system.physmem.totQLat 383646750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1095736750 # Sum of mem lat for all requests system.physmem.totBusLat 131400000 # Total cycles spent in databus access -system.physmem.totBankLat 580703750 # Total cycles spent in bank access -system.physmem.avgQLat 14632.09 # Average queueing delay per request -system.physmem.avgBankLat 22096.79 # Average bank access latency per request +system.physmem.totBankLat 580690000 # Total cycles spent in bank access +system.physmem.avgQLat 14598.43 # Average queueing delay per request +system.physmem.avgBankLat 22096.27 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 41728.89 # Average memory access latency +system.physmem.avgMemAccLat 41694.70 # Average memory access latency system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s @@ -379,14 +364,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53901.754386 system.cpu.icache.overall_avg_mshr_miss_latency::total 53901.754386 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1042 # number of replacements -system.cpu.l2cache.tagsinuse 22879.116549 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22879.116891 # Cycle average of tags in use system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 22.845913 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21684.482794 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 718.953898 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 475.679858 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 21684.482898 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 718.953897 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 475.680097 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.661758 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.021941 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.014517 # Average percentage of cache occupancy @@ -418,14 +403,14 @@ system.cpu.l2cache.overall_misses::total 26294 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45081000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 470660000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 515741000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1199043000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1199043000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1198171500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1198171500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 45081000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1669703000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1714784000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1668831500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1713912500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 45081000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1669703000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1714784000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1668831500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1713912500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses) @@ -453,14 +438,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.057631 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53604.042806 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114099.393939 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 103854.409988 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56219.195424 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56219.195424 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56178.333646 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56178.333646 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65599.457824 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65215.790675 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65565.218245 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65182.646231 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65599.457824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65215.790675 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65565.218245 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65182.646231 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,17 +467,17 @@ system.cpu.l2cache.demand_mshr_misses::total 26294 system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34645117 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418280186 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452925303 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 933604040 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 933604040 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34645117 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1351884226 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1386529343 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34645117 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1351884226 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1386529343 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34644438 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418276481 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452920919 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 932715801 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 932715801 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34644438 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1350992282 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1385636720 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34644438 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1350992282 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1385636720 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses @@ -504,25 +489,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41195.145065 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101401.257212 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91205.256343 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43773.632783 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43773.632783 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41195.145065 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53112.962166 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52731.776945 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41195.145065 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53112.962166 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52731.776945 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41194.337693 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101400.359030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91204.373540 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43731.986168 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43731.986168 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41194.337693 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53077.919381 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52697.829163 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41194.337693 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53077.919381 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52697.829163 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.423527 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4093.423689 # Cycle average of tags in use system.cpu.dcache.total_refs 151786159 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 333.306600 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 332210000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.423527 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 332192000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.423689 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999371 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999371 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 114120811 # number of ReadReq hits @@ -543,12 +528,12 @@ system.cpu.dcache.overall_misses::cpu.data 2179204 # system.cpu.dcache.overall_misses::total 2179204 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 5984681000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 5984681000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23175803000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23175803000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29160484000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29160484000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29160484000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29160484000 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23170641500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23170641500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29155322500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29155322500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29155322500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29155322500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -567,12 +552,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.014154 system.cpu.dcache.overall_miss_rate::total 0.014154 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15219.250263 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 15219.250263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12976.569635 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12976.569635 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13381.254807 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13381.254807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13381.254807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13381.254807 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12973.679613 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12973.679613 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13378.886281 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13378.886281 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13378.886281 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13378.886281 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 191152 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6083 # number of cycles access was blocked @@ -601,12 +586,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 455395 system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643654000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643654000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3783295500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3783295500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426949500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6426949500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426949500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6426949500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3782424000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3782424000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426078000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6426078000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426078000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6426078000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -617,12 +602,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.343961 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.343961 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14885.311788 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14885.311788 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14881.882886 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14881.882886 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14110.998144 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14110.998144 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14110.998144 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14110.998144 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index fd6611525..80e818735 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,65 +1,65 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133806 # Number of seconds simulated -sim_ticks 133806308500 # Number of ticks simulated -final_tick 133806308500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133774 # Number of seconds simulated +sim_ticks 133773851500 # Number of ticks simulated +final_tick 133773851500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 271409 # Simulator instruction rate (inst/s) -host_op_rate 271409 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64213833 # Simulator tick rate (ticks/s) -host_mem_usage 226532 # Number of bytes of host memory used -host_seconds 2083.76 # Real time elapsed on the host +host_inst_rate 262576 # Simulator instruction rate (inst/s) +host_op_rate 262576 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62108832 # Simulator tick rate (ticks/s) +host_mem_usage 226536 # Number of bytes of host memory used +host_seconds 2153.86 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1636352 # Number of bytes read from this memory -system.physmem.bytes_read::total 1697856 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67200 # Number of bytes written to this memory -system.physmem.bytes_written::total 67200 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25568 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26529 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 459649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12229259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12688908 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 459649 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 459649 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 502218 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 502218 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 502218 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 459649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12229259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13191127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 26529 # Total number of read requests seen -system.physmem.writeReqs 1050 # Total number of write requests seen -system.physmem.cpureqs 27579 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1697856 # Total number of bytes read from memory -system.physmem.bytesWritten 67200 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1697856 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 67200 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 60992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1636544 # Number of bytes read from this memory +system.physmem.bytes_read::total 1697536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 60992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 60992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67072 # Number of bytes written to this memory +system.physmem.bytes_written::total 67072 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 953 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25571 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26524 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1048 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1048 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 455934 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12233661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12689595 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 455934 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 455934 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 501383 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 501383 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 501383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 455934 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12233661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13190979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 26524 # Total number of read requests seen +system.physmem.writeReqs 1048 # Total number of write requests seen +system.physmem.cpureqs 27572 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1697536 # Total number of bytes read from memory +system.physmem.bytesWritten 67072 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1697536 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 67072 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1632 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1631 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 1662 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1679 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1680 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1686 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 1626 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1603 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1584 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1608 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1666 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 1722 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1650 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1666 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1676 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1684 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 61 # Track writes on a per bank basis +system.physmem.perBankRdReqs::10 1648 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1647 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1724 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1665 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1675 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1682 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 60 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 68 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 65 # Track writes on a per bank basis @@ -72,44 +72,31 @@ system.physmem.perBankWrReqs::9 75 # Tr system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 61 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 74 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 73 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 81 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 133806263000 # Total gap between requests +system.physmem.totGap 133773818000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 26529 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1050 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 8850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1089 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.physmem.readPktSize::6 26524 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 1048 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 8806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1096 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -137,8 +124,7 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 41 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 46 # What write queue length does an incoming req see @@ -151,8 +137,8 @@ system.physmem.wrQLenPdf::9 46 # Wh system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 45 # What write queue length does an incoming req see @@ -161,7 +147,7 @@ system.physmem.wrQLenPdf::19 45 # Wh system.physmem.wrQLenPdf::20 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 648232398 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1339932398 # Sum of mem lat for all requests -system.physmem.totBusLat 132570000 # Total cycles spent in databus access -system.physmem.totBankLat 559130000 # Total cycles spent in bank access -system.physmem.avgQLat 24448.68 # Average queueing delay per request -system.physmem.avgBankLat 21088.10 # Average bank access latency per request +system.physmem.totQLat 654284750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1345973500 # Sum of mem lat for all requests +system.physmem.totBusLat 132545000 # Total cycles spent in databus access +system.physmem.totBankLat 559143750 # Total cycles spent in bank access +system.physmem.avgQLat 24681.61 # Average queueing delay per request +system.physmem.avgBankLat 21092.60 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 50536.79 # Average memory access latency +system.physmem.avgMemAccLat 50774.21 # Average memory access latency system.physmem.avgRdBW 12.69 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 12.69 # Average consumed read bandwidth in MB/s @@ -186,41 +171,41 @@ system.physmem.avgConsumedWrBW 0.50 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.10 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.03 # Average write queue length over time -system.physmem.readRowHits 16972 # Number of row buffer hits during reads -system.physmem.writeRowHits 273 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.01 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 26.00 # Row buffer hit rate for writes -system.physmem.avgGap 4851744.55 # Average gap between requests -system.cpu.branchPred.lookups 76500721 # Number of BP lookups -system.cpu.branchPred.condPredicted 70919742 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2718676 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 43116993 # Number of BTB lookups -system.cpu.branchPred.BTBHits 41952631 # Number of BTB hits +system.physmem.avgWrQLen 9.24 # Average write queue length over time +system.physmem.readRowHits 16966 # Number of row buffer hits during reads +system.physmem.writeRowHits 271 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.00 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes +system.physmem.avgGap 4851799.58 # Average gap between requests +system.cpu.branchPred.lookups 76502410 # Number of BP lookups +system.cpu.branchPred.condPredicted 70922676 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2717282 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 43095322 # Number of BTB lookups +system.cpu.branchPred.BTBHits 41949760 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.299529 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1606312 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 238 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.341795 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1606512 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 241 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 122623794 # DTB read hits -system.cpu.dtb.read_misses 28860 # DTB read misses +system.cpu.dtb.read_hits 122629608 # DTB read hits +system.cpu.dtb.read_misses 28810 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 122652654 # DTB read accesses -system.cpu.dtb.write_hits 40761180 # DTB write hits -system.cpu.dtb.write_misses 25673 # DTB write misses +system.cpu.dtb.read_accesses 122658418 # DTB read accesses +system.cpu.dtb.write_hits 40760367 # DTB write hits +system.cpu.dtb.write_misses 25602 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40786853 # DTB write accesses -system.cpu.dtb.data_hits 163384974 # DTB hits -system.cpu.dtb.data_misses 54533 # DTB misses +system.cpu.dtb.write_accesses 40785969 # DTB write accesses +system.cpu.dtb.data_hits 163389975 # DTB hits +system.cpu.dtb.data_misses 54412 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 163439507 # DTB accesses -system.cpu.itb.fetch_hits 65534932 # ITB hits +system.cpu.dtb.data_accesses 163444387 # DTB accesses +system.cpu.itb.fetch_hits 65529846 # ITB hits system.cpu.itb.fetch_misses 41 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 65534973 # ITB accesses +system.cpu.itb.fetch_accesses 65529887 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,133 +219,133 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 267612618 # number of cpu cycles simulated +system.cpu.numCycles 267547704 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 67186400 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 699453099 # Number of instructions fetch has processed -system.cpu.fetch.Branches 76500721 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43558943 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 117852914 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11666249 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 73358963 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 67181660 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 699454641 # Number of instructions fetch has processed +system.cpu.fetch.Branches 76502410 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43556272 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 117851527 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11664601 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 73301689 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1199 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 10 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 65534932 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 934826 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 267314333 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.616594 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.444810 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 21 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 65529846 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 933458 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 267250540 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.617224 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.444995 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 149461419 55.91% 55.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10349982 3.87% 59.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11850266 4.43% 64.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10577716 3.96% 68.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7012506 2.62% 70.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2870690 1.07% 71.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3579816 1.34% 73.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3108437 1.16% 74.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 68503501 25.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 149399013 55.90% 55.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10348526 3.87% 59.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11849388 4.43% 64.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10578020 3.96% 68.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7012807 2.62% 70.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2871984 1.07% 71.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3578789 1.34% 73.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3106707 1.16% 74.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 68505306 25.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 267314333 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.285864 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.613678 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 84322022 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57655855 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 102751859 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13670665 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8913932 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3876852 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 942 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 691462372 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3197 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 8913932 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 92304341 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12773232 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1346 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 103106270 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 50215212 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 681285072 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 434 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 38522944 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5472741 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 520920645 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 897379043 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 897376453 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2590 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 267250540 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285939 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.614317 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 84320129 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 57595253 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 102753479 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13668133 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8913546 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3876280 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 932 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 691464517 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3449 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8913546 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 92299678 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12776720 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1189 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 103108433 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50150974 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 681302234 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 431 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 38477727 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5455282 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 520934901 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 897390123 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 897387366 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2757 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 57065756 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 66 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 71 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112077327 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 127005785 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42387861 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14833107 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10089887 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 621266103 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 59 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 604722021 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 299730 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 55073821 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 30009810 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 42 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 267314333 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.262213 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.825151 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 57080012 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 63 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 67 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 112027328 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 127008438 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42384710 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14844783 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10088023 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 621271293 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 604725807 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 299798 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 55080788 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 30005964 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 38 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 267250540 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.262767 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.823653 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52513972 19.65% 19.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55954300 20.93% 40.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53424383 19.99% 60.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 36299246 13.58% 74.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31212895 11.68% 85.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23807225 8.91% 94.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10138155 3.79% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3408674 1.28% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 555483 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52429829 19.62% 19.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55852855 20.90% 40.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53444845 20.00% 60.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36460113 13.64% 74.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31255141 11.70% 85.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23773948 8.90% 94.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10075913 3.77% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3406027 1.27% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 551869 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 267314333 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 267250540 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2798552 71.38% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 39 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 727516 18.56% 89.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 394572 10.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2756472 71.14% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 40 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 728591 18.80% 89.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 389871 10.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 439175234 72.62% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7035 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 439176954 72.62% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7066 0.00% 72.63% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.63% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.63% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.63% # Type of FU issued @@ -388,84 +373,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.63% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 124352577 20.56% 93.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41187127 6.81% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 124356224 20.56% 93.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41185515 6.81% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 604722021 # Type of FU issued -system.cpu.iq.rate 2.259692 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3920679 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006483 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1480975025 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 676343136 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 596595322 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3759 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2270 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1723 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 608640802 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1898 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12279325 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 604725807 # Type of FU issued +system.cpu.iq.rate 2.260254 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3874974 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006408 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1480873086 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 676355161 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 596602519 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3840 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2402 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1730 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 608598846 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1935 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12280408 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12491743 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 36092 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5478 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2936540 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12494396 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 35705 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5495 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2933389 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6432 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 54776 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6442 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 54892 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8913932 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1438086 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 192048 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 664143136 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1694587 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 127005785 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42387861 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 59 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 143884 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7497 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5478 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1342912 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1811100 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3154012 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599591446 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 122652830 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5130575 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8913546 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1440408 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 191911 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 664145675 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1694595 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 127008438 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42384710 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 55 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 143753 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7490 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 5495 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1342563 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1811283 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3153846 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599598114 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 122658565 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5127693 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 42876974 # number of nop insts executed -system.cpu.iew.exec_refs 163458157 # number of memory reference insts executed -system.cpu.iew.exec_branches 66641389 # Number of branches executed -system.cpu.iew.exec_stores 40805327 # Number of stores executed -system.cpu.iew.exec_rate 2.240520 # Inst execution rate -system.cpu.iew.wb_sent 597536756 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 596597045 # cumulative count of insts written-back -system.cpu.iew.wb_producers 415962909 # num instructions producing a value -system.cpu.iew.wb_consumers 530370743 # num instructions consuming a value +system.cpu.iew.exec_nop 42874327 # number of nop insts executed +system.cpu.iew.exec_refs 163462793 # number of memory reference insts executed +system.cpu.iew.exec_branches 66641793 # Number of branches executed +system.cpu.iew.exec_stores 40804228 # Number of stores executed +system.cpu.iew.exec_rate 2.241089 # Inst execution rate +system.cpu.iew.wb_sent 597543507 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 596604249 # cumulative count of insts written-back +system.cpu.iew.wb_producers 415969736 # num instructions producing a value +system.cpu.iew.wb_consumers 530347418 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.229331 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.784287 # average fanout of values written-back +system.cpu.iew.wb_rate 2.229899 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.784334 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 62162261 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 62164646 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2717793 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 258400401 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.329164 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.692856 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2716416 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 258336994 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.329736 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.693311 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 79574518 30.80% 30.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72566023 28.08% 58.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 25599330 9.91% 68.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9197400 3.56% 72.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10258446 3.97% 76.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20921268 8.10% 84.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6836400 2.65% 87.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3734572 1.45% 88.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29712444 11.50% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 79521079 30.78% 30.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72557315 28.09% 58.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 25650829 9.93% 68.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9136101 3.54% 72.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10241480 3.96% 76.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20967757 8.12% 84.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6801640 2.63% 87.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3711202 1.44% 88.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29749591 11.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 258400401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 258336994 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,192 +461,192 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 29712444 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29749591 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 892642792 # The number of ROB reads -system.cpu.rob.rob_writes 1336966756 # The number of ROB writes -system.cpu.timesIdled 34291 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 298285 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 892544623 # The number of ROB reads +system.cpu.rob.rob_writes 1336970755 # The number of ROB writes +system.cpu.timesIdled 34274 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 297164 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.473188 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.473188 # CPI: Total CPI of All Threads -system.cpu.ipc 2.113325 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.113325 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 845166386 # number of integer regfile reads -system.cpu.int_regfile_writes 490617161 # number of integer regfile writes -system.cpu.fp_regfile_reads 389 # number of floating regfile reads +system.cpu.cpi 0.473073 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.473073 # CPI: Total CPI of All Threads +system.cpu.ipc 2.113838 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.113838 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 845171662 # number of integer regfile reads +system.cpu.int_regfile_writes 490625638 # number of integer regfile writes +system.cpu.fp_regfile_reads 396 # number of floating regfile reads system.cpu.fp_regfile_writes 54 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 41 # number of replacements -system.cpu.icache.tagsinuse 825.582407 # Cycle average of tags in use -system.cpu.icache.total_refs 65533545 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 979 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 66939.269663 # Average number of references to valid blocks. +system.cpu.icache.replacements 39 # number of replacements +system.cpu.icache.tagsinuse 824.684718 # Cycle average of tags in use +system.cpu.icache.total_refs 65528462 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 971 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 67485.542739 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 825.582407 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.403116 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.403116 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 65533545 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 65533545 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 65533545 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 65533545 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 65533545 # number of overall hits -system.cpu.icache.overall_hits::total 65533545 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1386 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1386 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1386 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1386 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1386 # number of overall misses -system.cpu.icache.overall_misses::total 1386 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 74542000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 74542000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 74542000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 74542000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 74542000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 74542000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 65534931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 65534931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 65534931 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 65534931 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 65534931 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 65534931 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 824.684718 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.402678 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.402678 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 65528462 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 65528462 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 65528462 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 65528462 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 65528462 # number of overall hits +system.cpu.icache.overall_hits::total 65528462 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1383 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1383 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1383 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1383 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1383 # number of overall misses +system.cpu.icache.overall_misses::total 1383 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 72600500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 72600500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 72600500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 72600500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 72600500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 72600500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 65529845 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 65529845 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 65529845 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 65529845 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 65529845 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 65529845 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53782.106782 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53782.106782 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53782.106782 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53782.106782 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53782.106782 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53782.106782 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 93 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52494.938539 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52494.938539 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52494.938539 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52494.938539 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52494.938539 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52494.938539 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 25.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 407 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 407 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 407 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 407 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 407 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 407 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 979 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 979 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 979 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 979 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 979 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 979 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54570500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 54570500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54570500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 54570500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54570500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 54570500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 412 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 412 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 412 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 412 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 412 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 412 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 971 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 971 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 971 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 971 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 971 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 971 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54205000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 54205000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54205000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 54205000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54205000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 54205000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55741.062308 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55741.062308 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55741.062308 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 55741.062308 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55741.062308 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 55741.062308 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55823.892894 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55823.892894 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55823.892894 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 55823.892894 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55823.892894 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 55823.892894 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1082 # number of replacements -system.cpu.l2cache.tagsinuse 22917.401709 # Cycle average of tags in use -system.cpu.l2cache.total_refs 547365 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23522 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.270343 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1081 # number of replacements +system.cpu.l2cache.tagsinuse 22920.644164 # Cycle average of tags in use +system.cpu.l2cache.total_refs 547028 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23516 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 23.261949 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21471.188255 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 816.032339 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 630.181115 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.655249 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.024903 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019232 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.699384 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21474.762913 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 815.139111 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 630.742140 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.655358 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.024876 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019249 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.699483 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 18 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 206157 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 206175 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 445006 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 445006 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 233310 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 233310 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 206066 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 206084 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 444903 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 444903 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 233285 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 233285 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 439467 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 439485 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 439351 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 439369 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 439467 # number of overall hits -system.cpu.l2cache.overall_hits::total 439485 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 961 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4311 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5272 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21257 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21257 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 961 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 25568 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 26529 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 961 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 25568 # number of overall misses -system.cpu.l2cache.overall_misses::total 26529 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 53397000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 418986500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 472383500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1501574500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1501574500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 53397000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1920561000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1973958000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 53397000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1920561000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1973958000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 979 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 210468 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 211447 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 445006 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 445006 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 979 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 465035 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 466014 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 979 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 465035 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 466014 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.981614 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020483 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.024933 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083503 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083503 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.981614 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.054981 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.056927 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.981614 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.054981 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.056927 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55563.995838 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 97190.095106 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 89602.333080 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70639.060074 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70639.060074 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55563.995838 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75115.808824 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74407.553998 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55563.995838 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75115.808824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74407.553998 # average overall miss latency +system.cpu.l2cache.overall_hits::cpu.data 439351 # number of overall hits +system.cpu.l2cache.overall_hits::total 439369 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 953 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4305 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 5258 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21266 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21266 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 953 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 25571 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 26524 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 953 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 25571 # number of overall misses +system.cpu.l2cache.overall_misses::total 26524 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 53037500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 418895500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 471933000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1507958500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1507958500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 53037500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1926854000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1979891500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 53037500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1926854000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1979891500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 971 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 210371 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 211342 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 444903 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 444903 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 254551 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 254551 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 971 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 464922 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 465893 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 971 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 464922 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 465893 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.981462 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020464 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.024879 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083543 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083543 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.981462 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.055001 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.056932 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.981462 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.055001 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.056932 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55653.200420 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 97304.413473 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 89755.230126 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70909.362362 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70909.362362 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55653.200420 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75353.095303 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74645.283517 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55653.200420 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75353.095303 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74645.283517 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -670,174 +655,174 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1050 # number of writebacks -system.cpu.l2cache.writebacks::total 1050 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 961 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4311 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5272 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21257 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21257 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 961 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 25568 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 26529 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 961 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 25568 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 26529 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41447516 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 363900322 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 405347838 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1236862753 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1236862753 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41447516 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1600763075 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1642210591 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41447516 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1600763075 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1642210591 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.981614 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020483 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024933 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083503 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083503 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.981614 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054981 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.056927 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.981614 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054981 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.056927 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43129.569199 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 84412.044073 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76886.919196 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58186.138825 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58186.138825 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43129.569199 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62608.067702 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61902.468657 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43129.569199 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62608.067702 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61902.468657 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 1049 # number of writebacks +system.cpu.l2cache.writebacks::total 1049 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 953 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4305 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5258 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21266 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21266 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 953 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 25571 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26524 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 953 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 25571 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26524 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41181755 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 363891160 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 405072915 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1243149416 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1243149416 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41181755 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1607040576 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1648222331 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41181755 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1607040576 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1648222331 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.981462 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020464 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024879 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083543 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083543 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.981462 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055001 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.056932 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.981462 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055001 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.056932 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43212.754460 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 84527.563298 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77039.352415 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58457.134205 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58457.134205 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43212.754460 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62846.215478 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62140.790642 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43212.754460 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62846.215478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62140.790642 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 460939 # number of replacements -system.cpu.dcache.tagsinuse 4090.899850 # Cycle average of tags in use -system.cpu.dcache.total_refs 146914514 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 465035 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 315.921412 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 301771000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4090.899850 # Average occupied blocks per requestor +system.cpu.dcache.replacements 460826 # number of replacements +system.cpu.dcache.tagsinuse 4090.898597 # Cycle average of tags in use +system.cpu.dcache.total_refs 146919615 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 464922 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 316.009169 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 301835000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4090.898597 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.998755 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.998755 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 109265934 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 109265934 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37648563 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37648563 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 17 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 17 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 146914497 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 146914497 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 146914497 # number of overall hits -system.cpu.dcache.overall_hits::total 146914497 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1025246 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1025246 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1802758 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1802758 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2828004 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2828004 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2828004 # number of overall misses -system.cpu.dcache.overall_misses::total 2828004 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15342477500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15342477500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26169777829 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26169777829 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 37000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 37000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41512255329 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41512255329 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41512255329 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41512255329 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 110291180 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 110291180 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 109271003 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 109271003 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37648598 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37648598 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 14 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 14 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 146919601 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 146919601 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 146919601 # number of overall hits +system.cpu.dcache.overall_hits::total 146919601 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1024794 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1024794 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1802723 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1802723 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2827517 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2827517 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2827517 # number of overall misses +system.cpu.dcache.overall_misses::total 2827517 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15336763000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15336763000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26197701326 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26197701326 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 20000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 20000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41534464326 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41534464326 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41534464326 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41534464326 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 110295797 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 110295797 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 21 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 21 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 149742501 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 149742501 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 149742501 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 149742501 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009296 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009296 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045696 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045696 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.190476 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.190476 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018886 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018886 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018886 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018886 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14964.679209 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14964.679209 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14516.522922 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14516.522922 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14678.994559 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14678.994559 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14678.994559 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14678.994559 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 301355 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2673 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 17784 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 149747118 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 149747118 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 149747118 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 149747118 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009291 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009291 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045695 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045695 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.125000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.125000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018882 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018882 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018882 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018882 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14965.703351 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14965.703351 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14532.294382 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14532.294382 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14689.377403 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14689.377403 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14689.377403 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14689.377403 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 303569 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2051 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 17829 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.945288 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 243 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.026698 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 186.454545 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 445006 # number of writebacks -system.cpu.dcache.writebacks::total 445006 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 814778 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 814778 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548191 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1548191 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2362969 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2362969 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2362969 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2362969 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210468 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210468 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254567 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254567 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 465035 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 465035 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 465035 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 465035 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2697344500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2697344500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4097543997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4097543997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6794888497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6794888497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6794888497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6794888497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001908 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001908 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006453 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006453 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003106 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003106 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12815.936389 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12815.936389 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16096.131851 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16096.131851 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14611.563639 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14611.563639 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14611.563639 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14611.563639 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 444903 # number of writebacks +system.cpu.dcache.writebacks::total 444903 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 814423 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 814423 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548172 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1548172 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2362595 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2362595 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2362595 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2362595 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210371 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210371 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254551 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254551 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 464922 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 464922 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 464922 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 464922 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2696208000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2696208000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4103693497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4103693497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6799901497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6799901497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6799901497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6799901497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001907 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001907 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003105 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003105 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12816.443331 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12816.443331 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16121.301810 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16121.301810 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14625.897456 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14625.897456 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14625.897456 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14625.897456 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index e289c0e8e..aa7b7ad18 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.164572 # Nu sim_ticks 164572262000 # Number of ticks simulated final_tick 164572262000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164809 # Simulator instruction rate (inst/s) -host_op_rate 174150 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47579904 # Simulator tick rate (ticks/s) -host_mem_usage 241928 # Number of bytes of host memory used -host_seconds 3458.86 # Real time elapsed on the host +host_inst_rate 185108 # Simulator instruction rate (inst/s) +host_op_rate 195599 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53440170 # Simulator tick rate (ticks/s) +host_mem_usage 241944 # Number of bytes of host memory used +host_seconds 3079.56 # Real time elapsed on the host sim_insts 570051585 # Number of instructions simulated sim_ops 602359791 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 47424 # Number of bytes read from this memory @@ -85,26 +85,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 27336 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 2538 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 2538 # Categorize write packet sizes system.physmem.rdQLenPdf::0 14742 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 3442 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 8340 # What read queue length does an incoming req see @@ -137,7 +124,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 71 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 921366434 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1672075184 # Sum of mem lat for all requests +system.physmem.totQLat 921339250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1672034250 # Sum of mem lat for all requests system.physmem.totBusLat 136675000 # Total cycles spent in databus access -system.physmem.totBankLat 614033750 # Total cycles spent in bank access -system.physmem.avgQLat 33705.24 # Average queueing delay per request -system.physmem.avgBankLat 22462.46 # Average bank access latency per request +system.physmem.totBankLat 614020000 # Total cycles spent in bank access +system.physmem.avgQLat 33704.25 # Average queueing delay per request +system.physmem.avgBankLat 22461.95 # Average bank access latency per request system.physmem.avgBusLat 4999.82 # Average bus latency per request -system.physmem.avgMemAccLat 61167.51 # Average memory access latency +system.physmem.avgMemAccLat 61166.02 # Average memory access latency system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s @@ -323,11 +308,11 @@ system.cpu.iq.issued_per_cycle::mean 1.967168 # Nu system.cpu.iq.issued_per_cycle::stdev 1.722204 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 68107234 20.75% 20.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85141417 25.94% 46.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 76162034 23.21% 69.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40819071 12.44% 82.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85141419 25.94% 46.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 76162032 23.21% 69.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40819070 12.44% 82.34% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 28853170 8.79% 91.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14914630 4.54% 95.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14914631 4.54% 95.68% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 5559324 1.69% 97.37% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 6732498 2.05% 99.42% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 1901914 0.58% 100.00% # Number of insts issued each cycle @@ -629,16 +614,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 743 # system.cpu.l2cache.overall_misses::cpu.data 26602 # number of overall misses system.cpu.l2cache.overall_misses::total 27345 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 40442500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 687360500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 727803000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 687347500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 727790000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1581776500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1581776500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 40442500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2269137000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2309579500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2269124000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2309566500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 40442500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2269137000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2309579500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2269124000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2309566500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 831 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 197598 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 198429 # number of ReadReq accesses(hits+misses) @@ -666,16 +651,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.894103 system.cpu.l2cache.overall_miss_rate::cpu.data 0.059811 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.061367 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54431.359354 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 142872.687591 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 131041.231545 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 142869.985450 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 131038.890889 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72588.522785 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72588.522785 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54431.359354 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85299.488760 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84460.760651 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85299.000075 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84460.285244 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54431.359354 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85299.488760 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84460.760651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85299.000075 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84460.285244 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -706,17 +691,17 @@ system.cpu.l2cache.demand_mshr_misses::total 27336 system.cpu.l2cache.overall_mshr_misses::cpu.inst 741 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 26595 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 27336 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31149679 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 627911476 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 659061155 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1310031171 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1310031171 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31149679 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1937942647 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1969092326 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31149679 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1937942647 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1969092326 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31149092 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 627893373 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 659042465 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1310013362 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1310013362 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31149092 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1937906735 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1969055827 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31149092 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1937906735 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1969055827 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024312 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027945 # mshr miss rate for ReadReq accesses @@ -728,17 +713,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.061347 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059795 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.061347 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42037.353576 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 130705.969192 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 118856.835888 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60117.992336 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60117.992336 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42037.353576 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72868.683850 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72032.935543 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42037.353576 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72868.683850 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72032.935543 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42036.561404 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 130702.200874 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 118853.465284 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60117.175072 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60117.175072 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42036.561404 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72867.333521 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72031.600344 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42036.561404 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72867.333521 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72031.600344 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 440669 # number of replacements system.cpu.dcache.tagsinuse 4091.484070 # Cycle average of tags in use @@ -771,16 +756,16 @@ system.cpu.dcache.demand_misses::cpu.data 3718210 # n system.cpu.dcache.demand_misses::total 3718210 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 3718210 # number of overall misses system.cpu.dcache.overall_misses::total 3718210 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5073572500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5073572500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5073533500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5073533500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 40705228766 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 40705228766 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 337500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 337500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45778801266 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45778801266 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45778801266 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45778801266 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45778762266 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45778762266 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45778762266 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45778762266 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 131865640 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 131865640 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) @@ -803,16 +788,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.018473 system.cpu.dcache.demand_miss_rate::total 0.018473 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.018473 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.018473 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14838.521697 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14838.521697 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14838.407635 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14838.407635 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12056.196805 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 12056.196805 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15340.909091 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15340.909091 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12312.053721 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12312.053721 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12312.053721 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12312.053721 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12312.043232 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12312.043232 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12312.043232 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12312.043232 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 148065 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 30 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4947 # number of cycles access was blocked @@ -841,14 +826,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 444768 system.cpu.dcache.demand_mshr_misses::total 444768 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 444768 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 444768 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2836417500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2836417500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2836404500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2836404500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096422821 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096422821 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6932840321 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6932840321 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6932840321 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6932840321 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6932827321 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6932827321 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6932827321 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6932827321 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001498 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001498 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003561 # mshr miss rate for WriteReq accesses @@ -857,14 +842,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14354.412219 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14354.412219 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14354.346429 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14354.346429 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16573.368104 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16573.368104 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15587.542991 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15587.542991 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15587.542991 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15587.542991 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15587.513762 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15587.513762 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15587.513762 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15587.513762 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index dd62eb55a..4f3b9b27a 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.387316 # Number of seconds simulated -sim_ticks 387315507500 # Number of ticks simulated -final_tick 387315507500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.387321 # Number of seconds simulated +sim_ticks 387320726500 # Number of ticks simulated +final_tick 387320726500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183094 # Simulator instruction rate (inst/s) -host_op_rate 183671 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50610731 # Simulator tick rate (ticks/s) -host_mem_usage 233664 # Number of bytes of host memory used -host_seconds 7652.83 # Real time elapsed on the host +host_inst_rate 176162 # Simulator instruction rate (inst/s) +host_op_rate 176717 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48695201 # Simulator tick rate (ticks/s) +host_mem_usage 235496 # Number of bytes of host memory used +host_seconds 7953.98 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 76544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1678528 # Number of bytes read from this memory -system.physmem.bytes_read::total 1755072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 76544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 76544 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 76480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1678784 # Number of bytes read from this memory +system.physmem.bytes_read::total 1755264 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 76480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 76480 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory system.physmem.bytes_written::total 162112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1196 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26227 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27423 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1195 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26231 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27426 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 197627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4333749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4531375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197627 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197627 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 418553 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 418553 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 418553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4333749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4949928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27424 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 197459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4334351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4531810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197459 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197459 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 418547 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 418547 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 418547 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4334351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4950357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27427 # Total number of read requests seen system.physmem.writeReqs 2533 # Total number of write requests seen -system.physmem.cpureqs 29957 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1755072 # Total number of bytes read from memory +system.physmem.cpureqs 29960 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1755264 # Total number of bytes read from memory system.physmem.bytesWritten 162112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1755072 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1755264 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 1660 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 1716 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 1723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1744 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1743 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 1702 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1707 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1721 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1697 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1767 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1768 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 1765 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1769 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1770 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1755 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1673 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1676 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1660 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1628 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 157 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 155 # Track writes on a per bank basis @@ -77,37 +77,24 @@ system.physmem.perBankWrReqs::14 154 # Tr system.physmem.perBankWrReqs::15 153 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 387315479500 # Total gap between requests +system.physmem.totGap 387320698500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27424 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 2533 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 7981 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5076 # What read queue length does an incoming req see +system.physmem.readPktSize::6 27427 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 2533 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 7983 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5082 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 974 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -137,7 +124,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 88 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 107 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 713274952 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1439334952 # Sum of mem lat for all requests -system.physmem.totBusLat 137120000 # Total cycles spent in databus access -system.physmem.totBankLat 588940000 # Total cycles spent in bank access -system.physmem.avgQLat 26009.15 # Average queueing delay per request -system.physmem.avgBankLat 21475.35 # Average bank access latency per request +system.physmem.totQLat 712904000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1439226500 # Sum of mem lat for all requests +system.physmem.totBusLat 137135000 # Total cycles spent in databus access +system.physmem.totBankLat 589187500 # Total cycles spent in bank access +system.physmem.avgQLat 25992.78 # Average queueing delay per request +system.physmem.avgBankLat 21482.03 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52484.50 # Average memory access latency +system.physmem.avgMemAccLat 52474.81 # Average memory access latency system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s @@ -186,252 +171,252 @@ system.physmem.avgConsumedWrBW 0.42 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 16.51 # Average write queue length over time -system.physmem.readRowHits 17585 # Number of row buffer hits during reads +system.physmem.avgWrQLen 16.63 # Average write queue length over time +system.physmem.readRowHits 17586 # Number of row buffer hits during reads system.physmem.writeRowHits 1048 # Number of row buffer hits during writes system.physmem.readRowHitRate 64.12 # Row buffer hit rate for reads system.physmem.writeRowHitRate 41.37 # Row buffer hit rate for writes -system.physmem.avgGap 12929047.62 # Average gap between requests -system.cpu.branchPred.lookups 97759655 # Number of BP lookups -system.cpu.branchPred.condPredicted 88050231 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 3614520 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 65786552 # Number of BTB lookups -system.cpu.branchPred.BTBHits 65492883 # Number of BTB hits +system.physmem.avgGap 12927927.19 # Average gap between requests +system.cpu.branchPred.lookups 97754812 # Number of BP lookups +system.cpu.branchPred.condPredicted 88045070 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 3614513 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 65790839 # Number of BTB lookups +system.cpu.branchPred.BTBHits 65487235 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.553603 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1341 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 221 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.538531 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1327 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 219 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 774631016 # number of cpu cycles simulated +system.cpu.numCycles 774641454 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 164855721 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1642251558 # Number of instructions fetch has processed -system.cpu.fetch.Branches 97759655 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65494224 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 329204399 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20834739 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 263342259 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 64 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2502 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 164855086 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1642226882 # Number of instructions fetch has processed +system.cpu.fetch.Branches 97754812 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65488562 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 329193327 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20835132 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 263364086 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 66 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2508 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 161937023 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 736247 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 774398184 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.126696 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.146676 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 161933823 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 733897 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 774407665 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.126639 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.146663 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 445193785 57.49% 57.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74062525 9.56% 67.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37899229 4.89% 71.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9077552 1.17% 73.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28106227 3.63% 76.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18772117 2.42% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11485912 1.48% 80.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3791430 0.49% 81.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146009407 18.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 445214338 57.49% 57.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74055584 9.56% 67.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37896707 4.89% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9077649 1.17% 73.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28106182 3.63% 76.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18772378 2.42% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11485240 1.48% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3791473 0.49% 81.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146008114 18.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 774398184 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126202 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.120044 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 215922553 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 214452390 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 284209898 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42820116 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16993227 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1636550752 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16993227 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 239771948 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36701097 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52424917 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 302039391 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 126467604 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1625687860 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 146 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 30927407 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73464560 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3152152 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1356365192 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2746429093 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2712307786 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34121307 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 774407665 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126194 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.119983 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 215996576 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 214396476 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 284196048 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42825985 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16992580 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1636523781 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16992580 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 239852916 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36748965 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52423247 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302028125 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 126361832 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1625670094 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 144 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 30926636 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 73309992 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3198488 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1356344294 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2746400105 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2712277962 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34122143 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 111594753 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2643851 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2663506 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 271777312 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 436941235 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 179754378 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 254555015 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 82904621 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1512542697 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2609193 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1459339312 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 53583 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 109245499 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 130204517 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 365522 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 774398184 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.884482 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.431065 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 111573855 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2642593 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2663144 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271720784 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 436941817 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 179749373 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 254480906 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 83188791 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1512511277 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2608080 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1459319933 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 52996 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 109213691 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 130186216 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 364409 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 774407665 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.884434 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.431122 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 145558409 18.80% 18.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 184658706 23.85% 42.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 209828049 27.10% 69.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131187469 16.94% 86.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70686123 9.13% 95.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20416273 2.64% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7987184 1.03% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3894628 0.50% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181343 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145648239 18.81% 18.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 184522685 23.83% 42.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 209864984 27.10% 69.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131209019 16.94% 86.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70693972 9.13% 95.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20392101 2.63% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8014841 1.03% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3879808 0.50% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 182016 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 774398184 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 774407665 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 118946 7.04% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 95273 5.64% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1158517 68.57% 81.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 316903 18.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 140362 8.20% 8.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 95230 5.57% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1159729 67.79% 81.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 315506 18.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 866474644 59.37% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 866449380 59.37% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2644797 0.18% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419098125 28.72% 88.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171121746 11.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2644870 0.18% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419102646 28.72% 88.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171123037 11.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1459339312 # Type of FU issued -system.cpu.iq.rate 1.883915 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1689639 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001158 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3676979008 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1615425319 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1443226704 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17841022 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9210458 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8545776 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1451900530 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9128421 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215265115 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1459319933 # Type of FU issued +system.cpu.iq.rate 1.883865 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1710827 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001172 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3676966203 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1615362108 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1443197913 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17845151 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9210352 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8546882 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1451899562 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9131198 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215327027 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 34428392 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 58884 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 245184 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12906236 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 34428974 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 58580 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 245871 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12901231 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3305 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 101102 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3337 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 100836 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16993227 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3018866 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 247688 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1608835504 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4126277 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 436941235 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 179754378 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2526244 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 149012 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1899 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 245184 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2269311 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1473063 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3742374 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1454021381 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 416550474 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5317931 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16992580 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3019126 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 247748 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1608802731 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4125538 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 436941817 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 179749373 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2524925 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 149083 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1915 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 245871 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2268919 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1473448 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3742367 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1454001167 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 416555573 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5318766 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 93683614 # number of nop insts executed -system.cpu.iew.exec_refs 586997386 # number of memory reference insts executed -system.cpu.iew.exec_branches 89036634 # Number of branches executed -system.cpu.iew.exec_stores 170446912 # Number of stores executed -system.cpu.iew.exec_rate 1.877050 # Inst execution rate -system.cpu.iew.wb_sent 1452648479 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1451772480 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1153427719 # num instructions producing a value -system.cpu.iew.wb_consumers 1204682131 # num instructions consuming a value +system.cpu.iew.exec_nop 93683374 # number of nop insts executed +system.cpu.iew.exec_refs 587003910 # number of memory reference insts executed +system.cpu.iew.exec_branches 89035290 # Number of branches executed +system.cpu.iew.exec_stores 170448337 # Number of stores executed +system.cpu.iew.exec_rate 1.876999 # Inst execution rate +system.cpu.iew.wb_sent 1452626666 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1451744795 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1153395564 # num instructions producing a value +system.cpu.iew.wb_consumers 1204642088 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.874147 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957454 # average fanout of values written-back +system.cpu.iew.wb_rate 1.874086 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957459 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 119216890 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 119183948 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3614520 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 757404957 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.966614 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.509691 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3614513 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 757415085 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.966588 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.509597 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 239974569 31.68% 31.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 275852046 36.42% 68.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42571811 5.62% 73.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54691782 7.22% 80.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19624283 2.59% 83.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13282059 1.75% 85.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30580381 4.04% 89.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10561653 1.39% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70266373 9.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 240000251 31.69% 31.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 275796766 36.41% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42566622 5.62% 73.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54725654 7.23% 80.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19677570 2.60% 83.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13283245 1.75% 85.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30556171 4.03% 89.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10517669 1.39% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70291137 9.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 757404957 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 757415085 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -442,70 +427,70 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70266373 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70291137 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2295813886 # The number of ROB reads -system.cpu.rob.rob_writes 3234496299 # The number of ROB writes -system.cpu.timesIdled 25967 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 232832 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2295766308 # The number of ROB reads +system.cpu.rob.rob_writes 3234429823 # The number of ROB writes +system.cpu.timesIdled 26016 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 233789 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188945 # Number of Instructions Simulated system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated -system.cpu.cpi 0.552838 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.552838 # CPI: Total CPI of All Threads -system.cpu.ipc 1.808847 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.808847 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1979103244 # number of integer regfile reads -system.cpu.int_regfile_writes 1275174788 # number of integer regfile writes -system.cpu.fp_regfile_reads 16962430 # number of floating regfile reads -system.cpu.fp_regfile_writes 10491706 # number of floating regfile writes -system.cpu.misc_regfile_reads 592650972 # number of misc regfile reads +system.cpu.cpi 0.552846 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.552846 # CPI: Total CPI of All Threads +system.cpu.ipc 1.808823 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.808823 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1979081340 # number of integer regfile reads +system.cpu.int_regfile_writes 1275150411 # number of integer regfile writes +system.cpu.fp_regfile_reads 16965180 # number of floating regfile reads +system.cpu.fp_regfile_writes 10491866 # number of floating regfile writes +system.cpu.misc_regfile_reads 592655969 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 197 # number of replacements -system.cpu.icache.tagsinuse 1035.237714 # Cycle average of tags in use -system.cpu.icache.total_refs 161935084 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1336 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 121208.895210 # Average number of references to valid blocks. +system.cpu.icache.replacements 200 # number of replacements +system.cpu.icache.tagsinuse 1035.615179 # Cycle average of tags in use +system.cpu.icache.total_refs 161931886 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1338 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 121025.325859 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1035.237714 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.505487 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.505487 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161935084 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161935084 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161935084 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161935084 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161935084 # number of overall hits -system.cpu.icache.overall_hits::total 161935084 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1939 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1939 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1939 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1939 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1939 # number of overall misses -system.cpu.icache.overall_misses::total 1939 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 84566500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 84566500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 84566500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 84566500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 84566500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 84566500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 161937023 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 161937023 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 161937023 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 161937023 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 161937023 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 161937023 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1035.615179 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.505671 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.505671 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161931886 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161931886 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161931886 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161931886 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161931886 # number of overall hits +system.cpu.icache.overall_hits::total 161931886 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1937 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1937 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1937 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1937 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1937 # number of overall misses +system.cpu.icache.overall_misses::total 1937 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 85579500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 85579500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 85579500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 85579500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 85579500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 85579500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 161933823 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 161933823 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 161933823 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 161933823 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 161933823 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 161933823 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43613.460547 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43613.460547 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43613.460547 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43613.460547 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43613.460547 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43613.460547 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44181.466185 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44181.466185 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44181.466185 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44181.466185 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44181.466185 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44181.466185 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -514,120 +499,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 31.750000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 602 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 602 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 602 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 602 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 602 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 602 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1337 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1337 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1337 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1337 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1337 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1337 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62189000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 62189000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62189000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 62189000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62189000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 62189000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 598 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 598 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 598 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 598 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 598 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 598 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1339 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1339 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1339 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1339 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1339 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1339 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62434000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 62434000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62434000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 62434000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62434000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 62434000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 46513.836948 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 46513.836948 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 46513.836948 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 46513.836948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 46513.836948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 46513.836948 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 46627.333831 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 46627.333831 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 46627.333831 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 46627.333831 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 46627.333831 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 46627.333831 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2556 # number of replacements -system.cpu.l2cache.tagsinuse 22451.693912 # Cycle average of tags in use -system.cpu.l2cache.total_refs 550222 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24270 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.670869 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22454.455372 # Cycle average of tags in use +system.cpu.l2cache.total_refs 550476 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24273 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.678532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20743.567402 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1060.766368 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 647.360142 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.633043 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.032372 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019756 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.685171 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 140 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 196406 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 196546 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 443933 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 443933 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 240653 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 240653 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 140 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 437059 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 437199 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 140 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 437059 # number of overall hits -system.cpu.l2cache.overall_hits::total 437199 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1197 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4444 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5641 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21783 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21783 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1197 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26227 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27424 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1197 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 26227 # number of overall misses -system.cpu.l2cache.overall_misses::total 27424 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 59434000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 444973500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 504407500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1588740500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1588740500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 59434000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2033714000 # number of demand (read+write) miss cycles +system.cpu.l2cache.occ_blocks::writebacks 20744.724619 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1061.167682 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 648.563071 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.633079 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.032384 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019793 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.685256 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 143 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 196431 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 196574 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 443982 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 443982 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 240656 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 240656 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 143 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 437087 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 437230 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 143 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 437087 # number of overall hits +system.cpu.l2cache.overall_hits::total 437230 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1196 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4446 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 5642 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21785 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21785 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1196 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 26231 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 27427 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1196 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 26231 # number of overall misses +system.cpu.l2cache.overall_misses::total 27427 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 59648000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 445587500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 505235500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1587912500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1587912500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 59648000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2033500000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 2093148000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 59434000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2033714000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 59648000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2033500000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 2093148000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1337 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 200850 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 202187 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 443933 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 443933 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 262436 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 262436 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1337 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 463286 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 464623 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1337 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 463286 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 464623 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.895288 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022126 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.027900 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083003 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083003 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.895288 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.056611 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.059024 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.895288 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.056611 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.059024 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49652.464495 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 100129.050405 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 89418.099628 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72934.880411 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72934.880411 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49652.464495 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77542.761277 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76325.408401 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49652.464495 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77542.761277 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76325.408401 # average overall miss latency +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1339 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 200877 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 202216 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 443982 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 443982 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 262441 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 262441 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1339 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 463318 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 464657 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1339 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 463318 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 464657 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.893204 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022133 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.027901 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083009 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083009 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.893204 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.056616 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.059026 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.893204 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.056616 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.059026 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49872.909699 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 100222.109762 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 89549.007444 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72890.176727 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72890.176727 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49872.909699 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77522.778392 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76317.059832 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49872.909699 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77522.778392 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76317.059832 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -638,160 +623,160 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 2533 # number of writebacks system.cpu.l2cache.writebacks::total 2533 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1197 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4444 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5641 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21783 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21783 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1197 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26227 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27424 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1197 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26227 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27424 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44575992 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 389548209 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 434124201 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1319276658 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1319276658 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44575992 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1708824867 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1753400859 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44575992 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1708824867 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1753400859 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.895288 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022126 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027900 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083003 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083003 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.895288 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056611 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059024 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.895288 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056611 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.059024 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37239.759398 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 87657.112736 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76958.730899 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60564.507093 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60564.507093 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37239.759398 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65155.178518 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63936.729106 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37239.759398 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65155.178518 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63936.729106 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1196 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4446 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5642 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21785 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21785 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1196 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26231 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27427 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1196 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26231 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27427 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44803245 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 390135886 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 434939131 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1318424366 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1318424366 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44803245 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1708560252 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1753363497 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44803245 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1708560252 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1753363497 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.893204 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022133 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027901 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083009 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083009 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.893204 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056616 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059026 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.893204 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056616 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059026 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37460.907191 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 87749.861898 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77089.530486 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60519.824007 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60519.824007 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37460.907191 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65135.155046 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63928.373391 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37460.907191 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65135.155046 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63928.373391 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 459190 # number of replacements -system.cpu.dcache.tagsinuse 4093.797590 # Cycle average of tags in use -system.cpu.dcache.total_refs 365198263 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 463286 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 788.278219 # Average number of references to valid blocks. +system.cpu.dcache.replacements 459222 # number of replacements +system.cpu.dcache.tagsinuse 4093.797620 # Cycle average of tags in use +system.cpu.dcache.total_refs 365142346 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 463318 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 788.103087 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 340173000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.797590 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4093.797620 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999462 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999462 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 200241495 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 200241495 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164955449 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164955449 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 200185442 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 200185442 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164955585 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164955585 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 365196944 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 365196944 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 365196944 # number of overall hits -system.cpu.dcache.overall_hits::total 365196944 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 923055 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 923055 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1891367 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1891367 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 365141027 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 365141027 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 365141027 # number of overall hits +system.cpu.dcache.overall_hits::total 365141027 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 923072 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 923072 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1891231 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1891231 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 2814422 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2814422 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2814422 # number of overall misses -system.cpu.dcache.overall_misses::total 2814422 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14739603500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14739603500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31907348686 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31907348686 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 2814303 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2814303 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2814303 # number of overall misses +system.cpu.dcache.overall_misses::total 2814303 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14740246000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14740246000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31916028682 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31916028682 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 150000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 150000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46646952186 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46646952186 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46646952186 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46646952186 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201164550 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201164550 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 46656274682 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46656274682 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46656274682 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46656274682 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201108514 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201108514 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 368011366 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 368011366 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 368011366 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 368011366 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004589 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004589 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011336 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.011336 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 367955330 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 367955330 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 367955330 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 367955330 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004590 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004590 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011335 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011335 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.007648 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.007648 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.007648 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.007648 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15968.283038 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15968.283038 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16869.993336 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16869.993336 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15968.685000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15968.685000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16875.796073 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16875.796073 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 21428.571429 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 21428.571429 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16574.256521 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16574.256521 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16574.256521 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16574.256521 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 590116 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 35661 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16578.269888 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16578.269888 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16578.269888 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16578.269888 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 588860 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 17 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 35662 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.547938 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.512254 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 443933 # number of writebacks -system.cpu.dcache.writebacks::total 443933 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722205 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 722205 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628938 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1628938 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2351143 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2351143 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2351143 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2351143 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200850 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200850 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262429 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262429 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 443982 # number of writebacks +system.cpu.dcache.writebacks::total 443982 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722195 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 722195 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628797 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1628797 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2350992 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2350992 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2350992 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2350992 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200877 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200877 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262434 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262434 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 463279 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 463279 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 463279 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 463279 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2612152000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2612152000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4357934500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4357934500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 463311 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 463311 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 463311 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 463311 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2613052500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2613052500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4357141500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4357141500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 136000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 136000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6970086500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6970086500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6970086500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6970086500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000998 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6970194000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6970194000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6970194000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6970194000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000999 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses @@ -800,16 +785,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001259 system.cpu.dcache.demand_mshr_miss_rate::total 0.001259 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001259 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13005.486682 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13005.486682 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16606.146805 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16606.146805 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13008.221449 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13008.221449 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16602.808706 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16602.808706 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 19428.571429 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 19428.571429 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15045.116442 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15045.116442 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15045.116442 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15045.116442 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15044.309330 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15044.309330 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15044.309330 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15044.309330 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index dc034cfd1..6ca2fc4f2 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.607292 # Nu sim_ticks 607292111000 # Number of ticks simulated final_tick 607292111000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91190 # Simulator instruction rate (inst/s) -host_op_rate 168022 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62928697 # Simulator tick rate (ticks/s) -host_mem_usage 248736 # Number of bytes of host memory used -host_seconds 9650.48 # Real time elapsed on the host +host_inst_rate 88731 # Simulator instruction rate (inst/s) +host_op_rate 163492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61232046 # Simulator tick rate (ticks/s) +host_mem_usage 248756 # Number of bytes of host memory used +host_seconds 9917.88 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493926 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 57664 # Number of bytes read from this memory @@ -85,26 +85,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 27359 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 2534 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 2534 # Categorize write packet sizes system.physmem.rdQLenPdf::0 26892 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 100 # What read queue length does an incoming req see @@ -137,7 +124,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 90448613 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 895548613 # Sum of mem lat for all requests +system.physmem.totQLat 90421500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 895535250 # Sum of mem lat for all requests system.physmem.totBusLat 136795000 # Total cycles spent in databus access -system.physmem.totBankLat 668305000 # Total cycles spent in bank access -system.physmem.avgQLat 3305.99 # Average queueing delay per request -system.physmem.avgBankLat 24427.25 # Average bank access latency per request +system.physmem.totBankLat 668318750 # Total cycles spent in bank access +system.physmem.avgQLat 3305.00 # Average queueing delay per request +system.physmem.avgBankLat 24427.75 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32733.24 # Average memory access latency +system.physmem.avgMemAccLat 32732.75 # Average memory access latency system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s @@ -235,22 +220,22 @@ system.cpu.fetch.rateDist::max_value 8 # Nu system.cpu.fetch.rateDist::total 1214221440 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.130483 # Number of branch fetches per cycle system.cpu.fetch.rate 1.200203 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 288175293 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 497913619 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 274106217 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 92482436 # Number of cycles decode is unblocking +system.cpu.decode.IdleCycles 288175297 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 497913615 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 274106209 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92482444 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 61543875 # Number of cycles decode is squashing system.cpu.decode.DecodedInsts 2343534245 # Number of instructions handled by decode system.cpu.rename.SquashCycles 61543875 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 336850045 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 336850046 # Number of cycles rename is idle system.cpu.rename.BlockCycles 124204658 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2567 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 303948664 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 387671631 # Number of cycles rename is unblocking +system.cpu.rename.RunCycles 303948666 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 387671628 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 2247678746 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 360 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 242705543 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 120202916 # Number of times rename has blocked due to LSQ full +system.cpu.rename.IQFullEvents 242705531 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 120202926 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 2618040036 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 5722358621 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 5722353197 # Number of integer rename lookups @@ -259,11 +244,11 @@ system.cpu.rename.CommittedMaps 1886895258 # Nu system.cpu.rename.UndoneMaps 731144778 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 87 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 731406447 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 731406444 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 531670409 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 219217246 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 342048419 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 144614488 # Number of conflicting stores. +system.cpu.memDep0.conflictingStores 144614487 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 1993488562 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 286 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 1783952231 # Number of instructions issued @@ -275,12 +260,12 @@ system.cpu.iq.issued_per_cycle::samples 1214221440 # Nu system.cpu.iq.issued_per_cycle::mean 1.469215 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.421905 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 360233763 29.67% 29.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 364161192 29.99% 59.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234288879 19.30% 78.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 141409866 11.65% 90.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 60623194 4.99% 95.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 39782569 3.28% 98.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 360233765 29.67% 29.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 364161190 29.99% 59.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234288875 19.30% 78.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 141409873 11.65% 90.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 60623190 4.99% 95.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39782570 3.28% 98.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 11078669 0.91% 99.78% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 2040416 0.17% 99.95% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 602892 0.05% 100.00% # Number of insts issued each cycle @@ -368,7 +353,7 @@ system.cpu.iq.fp_inst_queue_writes 1776 # Nu system.cpu.iq.fp_inst_queue_wakeup_accesses 123 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 1740037802 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 245 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 210029942 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 210029946 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 112628288 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 39424 # Number of memory responses ignored because the instruction is squashed @@ -404,8 +389,8 @@ system.cpu.iew.exec_stores 191706202 # Nu system.cpu.iew.exec_rate 1.454114 # Inst execution rate system.cpu.iew.wb_sent 1725748007 # cumulative count of insts sent to commit system.cpu.iew.wb_count 1724635217 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1267063012 # num instructions producing a value -system.cpu.iew.wb_consumers 1828799696 # num instructions consuming a value +system.cpu.iew.wb_producers 1267063011 # num instructions producing a value +system.cpu.iew.wb_consumers 1828799692 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.419939 # insts written-back per cycle system.cpu.iew.wb_fanout 0.692839 # average fanout of values written-back @@ -583,14 +568,14 @@ system.cpu.l2cache.overall_misses::total 27359 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46268500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 330234500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 376503000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1134971000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1134971000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1134984000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1134984000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 46268500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1465205500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1511474000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1465218500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1511487000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 46268500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1465205500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1511474000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1465218500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1511487000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 918 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 203811 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 204729 # number of ReadReq accesses(hits+misses) @@ -620,14 +605,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.060649 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51352.386238 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72403.968428 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 68931.343830 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51832.260127 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51832.260127 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51832.853816 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51832.853816 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51352.386238 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55378.543352 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 55245.951972 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55379.034697 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 55246.427135 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51352.386238 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55378.543352 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 55245.951972 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55379.034697 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 55246.427135 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,17 +634,17 @@ system.cpu.l2cache.demand_mshr_misses::total 27359 system.cpu.l2cache.overall_mshr_misses::cpu.inst 901 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 26458 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 27359 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35083215 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 273211469 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 308294684 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 862598556 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 862598556 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35083215 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1135810025 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1170893240 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35083215 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1135810025 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1170893240 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35082483 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 273207016 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 308289499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 862590617 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 862590617 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35082483 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1135797633 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1170880116 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35082483 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1135797633 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1170880116 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022379 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026679 # mshr miss rate for ReadReq accesses @@ -671,35 +656,35 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.060649 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.981481 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058772 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.060649 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38938.085461 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59901.659504 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56443.552545 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39393.458282 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39393.458282 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38938.085461 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42928.793749 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42797.369787 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38938.085461 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42928.793749 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42797.369787 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38937.273030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59900.683184 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56442.603259 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39393.095721 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39393.095721 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38937.273030 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42928.325384 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42796.890091 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38937.273030 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42928.325384 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42796.890091 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 446086 # number of replacements system.cpu.dcache.tagsinuse 4092.713768 # Cycle average of tags in use -system.cpu.dcache.total_refs 452307982 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 452307978 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 450182 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1004.722494 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1004.722486 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 861652000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 4092.713768 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999198 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999198 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 264368372 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 264368372 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 264368368 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 264368368 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 187939603 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 187939603 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 452307975 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 452307975 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 452307975 # number of overall hits -system.cpu.dcache.overall_hits::total 452307975 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 452307971 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 452307971 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 452307971 # number of overall hits +system.cpu.dcache.overall_hits::total 452307971 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 211281 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 211281 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 246455 # number of WriteReq misses @@ -710,20 +695,20 @@ system.cpu.dcache.overall_misses::cpu.data 457736 # system.cpu.dcache.overall_misses::total 457736 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 3022618500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 3022618500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4119755500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4119755500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7142374000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7142374000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7142374000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7142374000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264579653 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264579653 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4119768500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4119768500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7142387000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7142387000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7142387000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7142387000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264579649 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264579649 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 452765711 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 452765711 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 452765711 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 452765711 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 452765707 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 452765707 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 452765707 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 452765707 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000799 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000799 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001310 # miss rate for WriteReq accesses @@ -734,12 +719,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.001011 system.cpu.dcache.overall_miss_rate::total 0.001011 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14306.153890 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 14306.153890 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16716.055669 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16716.055669 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15603.697328 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15603.697328 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15603.697328 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15603.697328 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16716.108417 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16716.108417 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15603.725728 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15603.725728 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15603.725728 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15603.725728 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 365 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 40 # number of cycles access was blocked @@ -768,12 +753,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 450191 system.cpu.dcache.overall_mshr_misses::total 450191 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2528414500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2528414500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3626209000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3626209000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6154623500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6154623500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6154623500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6154623500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3626222000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3626222000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6154636500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6154636500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6154636500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6154636500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses @@ -784,12 +769,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12405.317025 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12405.317025 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14718.310374 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14718.310374 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13671.138472 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13671.138472 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13671.138472 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13671.138472 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14718.363139 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14718.363139 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13671.167349 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13671.167349 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13671.167349 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13671.167349 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index b0849c006..e47377a85 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026779 # Number of seconds simulated -sim_ticks 26779468500 # Number of ticks simulated -final_tick 26779468500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026786 # Number of seconds simulated +sim_ticks 26785824500 # Number of ticks simulated +final_tick 26785824500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196675 # Simulator instruction rate (inst/s) -host_op_rate 198087 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58139571 # Simulator tick rate (ticks/s) -host_mem_usage 373976 # Number of bytes of host memory used -host_seconds 460.61 # Real time elapsed on the host +host_inst_rate 121944 # Simulator instruction rate (inst/s) +host_op_rate 122819 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36056613 # Simulator tick rate (ticks/s) +host_mem_usage 374016 # Number of bytes of host memory used +host_seconds 742.88 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 947840 # Number of bytes read from this memory -system.physmem.bytes_read::total 993088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 992832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44992 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 703 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14810 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15517 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1689653 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35394280 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37083932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1689653 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1689653 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1689653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35394280 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 37083932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15517 # Total number of read requests seen +system.physmem.num_reads::total 15513 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1679694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35385881 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37065575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1679694 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1679694 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1679694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35385881 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 37065575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15513 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 15520 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 993088 # Total number of bytes read from memory +system.physmem.cpureqs 15516 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 992832 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 993088 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 992832 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 996 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 960 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 997 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1012 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 996 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1013 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 926 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 925 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 882 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 885 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 993 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 992 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1001 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 966 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 968 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 968 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1002 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1001 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,37 +70,24 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26779289500 # Total gap between requests +system.physmem.totGap 26785652500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 15517 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 3 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 10168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5067 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 252 # What read queue length does an incoming req see +system.physmem.readPktSize::6 15513 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 10163 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 255 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,37 +149,36 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 52084984 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 311719984 # Sum of mem lat for all requests -system.physmem.totBusLat 77585000 # Total cycles spent in databus access -system.physmem.totBankLat 182050000 # Total cycles spent in bank access -system.physmem.avgQLat 3356.64 # Average queueing delay per request -system.physmem.avgBankLat 11732.29 # Average bank access latency per request +system.physmem.totQLat 55611750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 315006750 # Sum of mem lat for all requests +system.physmem.totBusLat 77565000 # Total cycles spent in databus access +system.physmem.totBankLat 181830000 # Total cycles spent in bank access +system.physmem.avgQLat 3584.85 # Average queueing delay per request +system.physmem.avgBankLat 11721.14 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 20088.93 # Average memory access latency -system.physmem.avgRdBW 37.08 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 20305.99 # Average memory access latency +system.physmem.avgRdBW 37.07 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 37.08 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 37.07 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.29 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 14783 # Number of row buffer hits during reads +system.physmem.readRowHits 14781 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.27 # Row buffer hit rate for reads +system.physmem.readRowHitRate 95.28 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1725803.28 # Average gap between requests -system.cpu.branchPred.lookups 26678818 # Number of BP lookups -system.cpu.branchPred.condPredicted 21998913 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 842318 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11366409 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11281153 # Number of BTB hits +system.physmem.avgGap 1726658.45 # Average gap between requests +system.cpu.branchPred.lookups 26682480 # Number of BP lookups +system.cpu.branchPred.condPredicted 22002618 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 841998 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11368270 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11282813 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.249930 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 69723 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 201 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.248285 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 69658 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 194 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -237,239 +222,239 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53558938 # number of cpu cycles simulated +system.cpu.numCycles 53571650 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14172731 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127871641 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26678818 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11350876 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24033181 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4760167 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11226793 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 14170612 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127882618 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26682480 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11352471 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24034762 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4762849 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11235788 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13844867 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 331224 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53334396 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.414044 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.215935 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 13843090 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 329835 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53345786 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.413719 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.215837 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29339451 55.01% 55.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3389540 6.36% 61.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2028066 3.80% 65.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1555662 2.92% 68.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1667100 3.13% 71.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2918330 5.47% 76.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1510510 2.83% 79.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1090066 2.04% 81.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9835671 18.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29349323 55.02% 55.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3389433 6.35% 61.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2028287 3.80% 65.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1555177 2.92% 68.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1667492 3.13% 71.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2918592 5.47% 76.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1510888 2.83% 79.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1090794 2.04% 81.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9835800 18.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53334396 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.498121 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.387494 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16935376 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9075535 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22432463 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 998016 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3893006 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4442432 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8659 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126044255 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42607 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3893006 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18714710 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3545279 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 156066 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21549370 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5475965 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123134352 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 422701 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4592939 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1259 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143588919 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536358187 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 536353466 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4721 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 53345786 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.498071 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.387132 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16933018 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9083258 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22434897 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 998703 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3895910 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4442085 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8696 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126062223 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42630 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3895910 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18712984 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3548131 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 156179 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21551652 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5480930 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123149853 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 423091 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4597179 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1286 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143608098 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536423645 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 536418417 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5228 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36174733 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4601 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4599 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12509318 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29470006 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5522308 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2104178 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1264650 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118149095 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8470 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105144375 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 78107 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26722736 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65554797 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 252 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53334396 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.971418 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.910922 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 36193912 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4607 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4605 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12518412 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29475899 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5522776 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2125822 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1253238 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118167784 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8472 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105151160 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 77497 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26739027 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65605268 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 254 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53345786 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.971124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.910487 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15312252 28.71% 28.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11634281 21.81% 50.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8274633 15.51% 66.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6753758 12.66% 78.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4949297 9.28% 87.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2972831 5.57% 93.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2466224 4.62% 98.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 528093 0.99% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 443027 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15316861 28.71% 28.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11639595 21.82% 50.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8263506 15.49% 66.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6760248 12.67% 78.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4974624 9.33% 88.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2955128 5.54% 93.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2464546 4.62% 98.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 527827 0.99% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 443451 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53334396 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53345786 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 44474 6.73% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 340155 51.46% 58.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 276363 41.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 44563 6.73% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 340033 51.38% 58.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 277229 41.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74414194 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10982 0.01% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 3 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 143 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 186 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25601639 24.35% 95.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5117225 4.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74420309 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10977 0.01% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 155 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 201 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25602989 24.35% 95.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5116524 4.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105144375 # Type of FU issued -system.cpu.iq.rate 1.963153 # Inst issue rate -system.cpu.iq.fu_busy_cnt 661019 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006287 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264361545 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144884747 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102673470 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 727 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1011 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 322 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105805031 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 363 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 444404 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105151160 # Type of FU issued +system.cpu.iq.rate 1.962814 # Inst issue rate +system.cpu.iq.fu_busy_cnt 661852 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006294 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 264386671 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144919691 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102682625 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 784 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1077 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 339 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105812622 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 390 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 443741 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6896040 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6651 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6197 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 777464 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6901933 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6293 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6180 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 777932 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31327 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 31373 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3893006 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 929576 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 127351 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118170277 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 309597 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29470006 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5522308 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4582 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 66448 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6858 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6197 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 446675 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 445546 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892221 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104166430 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25281924 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 977945 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3895910 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 928973 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 127070 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118188976 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 309212 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29475899 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5522776 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4584 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 66075 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6911 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6180 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 446439 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 445443 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 891882 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104175676 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25284542 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 975484 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12712 # number of nop insts executed -system.cpu.iew.exec_refs 30342174 # number of memory reference insts executed -system.cpu.iew.exec_branches 21323986 # Number of branches executed -system.cpu.iew.exec_stores 5060250 # Number of stores executed -system.cpu.iew.exec_rate 1.944893 # Inst execution rate -system.cpu.iew.wb_sent 102951824 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102673792 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62219945 # num instructions producing a value -system.cpu.iew.wb_consumers 104261628 # num instructions consuming a value +system.cpu.iew.exec_nop 12720 # number of nop insts executed +system.cpu.iew.exec_refs 30343976 # number of memory reference insts executed +system.cpu.iew.exec_branches 21325145 # Number of branches executed +system.cpu.iew.exec_stores 5059434 # Number of stores executed +system.cpu.iew.exec_rate 1.944605 # Inst execution rate +system.cpu.iew.wb_sent 102960011 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102682964 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62233069 # num instructions producing a value +system.cpu.iew.wb_consumers 104282875 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.917024 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596767 # average fanout of values written-back +system.cpu.iew.wb_rate 1.916741 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596772 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26920302 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 26939053 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 833747 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49441390 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.845680 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.541256 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 833398 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49449876 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.845363 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.541608 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19945415 40.34% 40.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13149428 26.60% 66.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4162611 8.42% 75.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3435070 6.95% 82.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1540295 3.12% 85.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 748484 1.51% 86.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 932633 1.89% 88.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 245930 0.50% 89.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5281524 10.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19967148 40.38% 40.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13135707 26.56% 66.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4163389 8.42% 75.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3434332 6.95% 82.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1535763 3.11% 85.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 744463 1.51% 86.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 942034 1.91% 88.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 246412 0.50% 89.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5280628 10.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49441390 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 49449876 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -480,70 +465,70 @@ system.cpu.commit.branches 18732304 # Nu system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5281524 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5280628 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162327394 # The number of ROB reads -system.cpu.rob.rob_writes 240259263 # The number of ROB writes -system.cpu.timesIdled 43763 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 224542 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 162355527 # The number of ROB reads +system.cpu.rob.rob_writes 240299704 # The number of ROB writes +system.cpu.timesIdled 43654 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 225864 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated -system.cpu.cpi 0.591225 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.591225 # CPI: Total CPI of All Threads -system.cpu.ipc 1.691404 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.691404 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495495273 # number of integer regfile reads -system.cpu.int_regfile_writes 120530797 # number of integer regfile writes -system.cpu.fp_regfile_reads 175 # number of floating regfile reads -system.cpu.fp_regfile_writes 405 # number of floating regfile writes -system.cpu.misc_regfile_reads 29088840 # number of misc regfile reads +system.cpu.cpi 0.591365 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.591365 # CPI: Total CPI of All Threads +system.cpu.ipc 1.691003 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.691003 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495535708 # number of integer regfile reads +system.cpu.int_regfile_writes 120542575 # number of integer regfile writes +system.cpu.fp_regfile_reads 173 # number of floating regfile reads +system.cpu.fp_regfile_writes 431 # number of floating regfile writes +system.cpu.misc_regfile_reads 29089632 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 630.551988 # Cycle average of tags in use -system.cpu.icache.total_refs 13843878 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 733 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 18886.600273 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 630.397373 # Cycle average of tags in use +system.cpu.icache.total_refs 13842106 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 728 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 19013.881868 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 630.551988 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.307887 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.307887 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13843878 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13843878 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13843878 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13843878 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13843878 # number of overall hits -system.cpu.icache.overall_hits::total 13843878 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 988 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 988 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 988 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 988 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 988 # number of overall misses -system.cpu.icache.overall_misses::total 988 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 49634499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 49634499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 49634499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 49634499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 49634499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 49634499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13844866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13844866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13844866 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13844866 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13844866 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13844866 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 630.397373 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.307811 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.307811 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13842106 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13842106 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13842106 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13842106 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13842106 # number of overall hits +system.cpu.icache.overall_hits::total 13842106 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses +system.cpu.icache.overall_misses::total 983 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 49432499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 49432499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 49432499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 49432499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 49432499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 49432499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13843089 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13843089 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13843089 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13843089 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13843089 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13843089 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50237.347166 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50237.347166 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50237.347166 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50237.347166 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50237.347166 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50237.347166 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50287.384537 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 50287.384537 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 50287.384537 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 50287.384537 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 50287.384537 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 50287.384537 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked @@ -552,128 +537,128 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 55.777778 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 251 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 251 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 251 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 251 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 251 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 251 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 737 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 737 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 737 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 737 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 737 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 737 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38036999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 38036999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38036999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 38036999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38036999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 38036999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 250 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 250 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 250 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 250 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 250 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 250 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 733 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 733 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 733 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 733 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37907999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 37907999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37907999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 37907999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37907999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 37907999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51610.582090 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51610.582090 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51610.582090 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51610.582090 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51610.582090 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51610.582090 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51716.233288 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51716.233288 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51716.233288 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51716.233288 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51716.233288 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51716.233288 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 10759.564287 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1831570 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15500 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 118.165806 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 10760.479556 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1831525 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15496 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 118.193405 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 9910.782646 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 616.871655 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 231.909986 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.302453 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.018825 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 9911.805562 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 616.761334 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 231.912660 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.302484 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.018822 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.007077 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.328356 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 903763 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903788 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942924 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942924 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 29047 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 29047 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932810 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932835 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932810 # number of overall hits -system.cpu.l2cache.overall_hits::total 932835 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 708 # number of ReadReq misses +system.cpu.l2cache.occ_percent::total 0.328384 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 903743 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 903767 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 942900 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 942900 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 2 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 29045 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 29045 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 932788 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 932812 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 932788 # number of overall hits +system.cpu.l2cache.overall_hits::total 932812 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 704 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 281 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 989 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 985 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 14539 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14539 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 708 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 704 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 14820 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15528 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 708 # number of overall misses +system.cpu.l2cache.demand_misses::total 15524 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 704 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14820 # number of overall misses -system.cpu.l2cache.overall_misses::total 15528 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37036500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15642500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 52679000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 625286000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 625286000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 37036500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 640928500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 677965000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 37036500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 640928500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 677965000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 733 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 904044 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 904777 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 942924 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 942924 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 4 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 43586 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 43586 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 733 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 947630 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 948363 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 733 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 947630 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 948363 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965894 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_misses::total 15524 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 36918500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15609500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 52528000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 628655000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 628655000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 36918500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 644264500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 681183000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 36918500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 644264500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 681183000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 728 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 904024 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 904752 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 942900 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 942900 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 43584 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 43584 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 728 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 947608 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 948336 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 728 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 947608 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 948336 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967033 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000311 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001093 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.333570 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.333570 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965894 # miss rate for demand accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001089 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.600000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.333586 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.333586 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967033 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015639 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016373 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965894 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.016370 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967033 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015639 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016373 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52311.440678 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55667.259786 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53264.914055 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43007.497077 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43007.497077 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52311.440678 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 43247.537112 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 43660.806285 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52311.440678 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 43247.537112 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 43660.806285 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.016370 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52441.051136 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55549.822064 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53327.918782 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43239.218653 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43239.218653 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52441.051136 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 43472.638327 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 43879.348106 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52441.051136 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 43472.638327 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 43879.348106 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -691,184 +676,184 @@ system.cpu.l2cache.demand_mshr_hits::total 11 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 707 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 703 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 978 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 974 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14539 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14539 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 707 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 703 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 14810 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15517 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 707 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15513 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 703 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14810 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15517 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28010860 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11866667 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 39877527 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 15513 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27943554 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11832709 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 39776263 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 30003 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 30003 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 445060185 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 445060185 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28010860 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 456926852 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 484937712 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28010860 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 456926852 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 484937712 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964529 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 448424221 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 448424221 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27943554 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 460256930 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 488200484 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27943554 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 460256930 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 488200484 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000300 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001081 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.750000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.750000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.333570 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.333570 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964529 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016362 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964529 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016362 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39619.321075 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43788.439114 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40774.567485 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001077 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.333586 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.333586 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015629 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016358 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015629 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016358 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39749.009957 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43663.132841 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40838.052361 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30611.471559 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30611.471559 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39619.321075 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 30852.589602 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31252.027583 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39619.321075 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 30852.589602 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31252.027583 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30842.851709 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30842.851709 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39749.009957 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31077.442944 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31470.410881 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39749.009957 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31077.442944 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31470.410881 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943534 # number of replacements -system.cpu.dcache.tagsinuse 3674.806480 # Cycle average of tags in use -system.cpu.dcache.total_refs 28135871 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947630 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.690777 # Average number of references to valid blocks. +system.cpu.dcache.replacements 943512 # number of replacements +system.cpu.dcache.tagsinuse 3674.906425 # Cycle average of tags in use +system.cpu.dcache.total_refs 28139228 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947608 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 29.695009 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 7938358000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3674.806480 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.897170 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.897170 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23591287 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23591287 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4536767 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4536767 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3920 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3920 # number of LoadLockedReq hits +system.cpu.dcache.occ_blocks::cpu.data 3674.906425 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.897194 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.897194 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23594668 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23594668 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4536751 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4536751 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3908 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3908 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28128054 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28128054 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28128054 # number of overall hits -system.cpu.dcache.overall_hits::total 28128054 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1173096 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1173096 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 198214 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 198214 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 28131419 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28131419 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28131419 # number of overall hits +system.cpu.dcache.overall_hits::total 28131419 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1172935 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1172935 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 198230 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 198230 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1371310 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1371310 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1371310 # number of overall misses -system.cpu.dcache.overall_misses::total 1371310 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13884435000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13884435000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5574763392 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5574763392 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1371165 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1371165 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1371165 # number of overall misses +system.cpu.dcache.overall_misses::total 1371165 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13884681000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13884681000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5602018407 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5602018407 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 247000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 247000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19459198392 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19459198392 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19459198392 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19459198392 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24764383 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24764383 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 19486699407 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19486699407 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19486699407 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19486699407 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24767603 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24767603 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3926 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3926 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3914 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29499364 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29499364 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29499364 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29499364 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047370 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047370 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041862 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.041862 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001528 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001528 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046486 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046486 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046486 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046486 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.719327 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.719327 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28124.972969 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28124.972969 # average WriteReq miss latency +system.cpu.dcache.demand_accesses::cpu.data 29502584 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29502584 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29502584 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29502584 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047358 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047358 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041865 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.041865 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001533 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001533 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046476 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046476 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046476 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046476 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11837.553658 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11837.553658 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28260.194759 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28260.194759 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 41166.666667 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 41166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14190.225691 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14190.225691 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14190.225691 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14190.225691 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 152485 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14211.782978 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14211.782978 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14211.782978 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14211.782978 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 152466 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23871 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23833 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.387877 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.397264 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942924 # number of writebacks -system.cpu.dcache.writebacks::total 942924 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269038 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 269038 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154638 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 154638 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 942900 # number of writebacks +system.cpu.dcache.writebacks::total 942900 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 268897 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 268897 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154655 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 154655 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 423676 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 423676 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 423676 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 423676 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904058 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 904058 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43576 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43576 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947634 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947634 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947634 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947634 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9990434000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9990434000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 980693945 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 980693945 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10971127945 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10971127945 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10971127945 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10971127945 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036506 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036506 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 423552 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 423552 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 423552 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 423552 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904038 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 904038 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43575 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43575 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947613 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947613 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947613 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947613 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9990153500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9990153500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 984037459 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 984037459 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10974190959 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10974190959 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10974190959 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10974190959 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036501 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036501 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009203 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009203 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032124 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032124 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032124 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032124 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.656042 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.656042 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22505.368666 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22505.368666 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11577.389525 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11577.389525 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11577.389525 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11577.389525 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032120 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032120 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032120 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032120 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.590241 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.590241 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22582.615238 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22582.615238 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11580.878438 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11580.878438 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11580.878438 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11580.878438 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 8e442dc5d..c14a5bb89 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,114 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.066005 # Number of seconds simulated -sim_ticks 66004575000 # Number of ticks simulated -final_tick 66004575000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.066022 # Number of seconds simulated +sim_ticks 66021796500 # Number of ticks simulated +final_tick 66021796500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124260 # Simulator instruction rate (inst/s) -host_op_rate 218802 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51913433 # Simulator tick rate (ticks/s) -host_mem_usage 384868 # Number of bytes of host memory used -host_seconds 1271.44 # Real time elapsed on the host +host_inst_rate 92381 # Simulator instruction rate (inst/s) +host_op_rate 162668 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38604948 # Simulator tick rate (ticks/s) +host_mem_usage 384888 # Number of bytes of host memory used +host_seconds 1710.19 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192463 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 65088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1882560 # Number of bytes read from this memory -system.physmem.bytes_read::total 1947648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10816 # Number of bytes written to this memory -system.physmem.bytes_written::total 10816 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1017 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29415 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30432 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 169 # Number of write requests responded to by this memory -system.physmem.num_writes::total 169 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 986113 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28521659 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29507773 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 986113 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 986113 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 163867 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 163867 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 163867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 986113 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28521659 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29671640 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30434 # Total number of read requests seen -system.physmem.writeReqs 169 # Total number of write requests seen -system.physmem.cpureqs 30604 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1947648 # Total number of bytes read from memory -system.physmem.bytesWritten 10816 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1947648 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 10816 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1881664 # Number of bytes read from this memory +system.physmem.bytes_read::total 1946496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9856 # Number of bytes written to this memory +system.physmem.bytes_written::total 9856 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29401 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30414 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 154 # Number of write requests responded to by this memory +system.physmem.num_writes::total 154 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 981979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28500648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29482627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 981979 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 981979 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 149284 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 149284 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 149284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 981979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28500648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29631911 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30416 # Total number of read requests seen +system.physmem.writeReqs 154 # Total number of write requests seen +system.physmem.cpureqs 30571 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1946496 # Total number of bytes read from memory +system.physmem.bytesWritten 9856 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1946496 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9856 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 46 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed system.physmem.perBankRdReqs::0 1928 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1909 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1972 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1959 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1865 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1906 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1973 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1961 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1879 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1864 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1928 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1952 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1932 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1937 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1870 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1874 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1846 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1891 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1931 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1939 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1872 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1873 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1845 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1890 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 1830 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1798 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1799 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 61 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 46 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 14 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 39 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 2 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 7 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 3 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 1 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 9 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 9 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 8 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 3 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 13 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 66004558000 # Total gap between requests +system.physmem.totGap 66021783500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 30434 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 169 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 1 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 29835 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see +system.physmem.readPktSize::6 30416 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 154 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 29836 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -137,15 +124,14 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 7 # What write queue length does an incoming req see @@ -154,13 +140,13 @@ system.physmem.wrQLenPdf::12 7 # Wh system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -170,164 +156,163 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 12335337 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 610214087 # Sum of mem lat for all requests -system.physmem.totBusLat 151870000 # Total cycles spent in databus access -system.physmem.totBankLat 446008750 # Total cycles spent in bank access -system.physmem.avgQLat 406.11 # Average queueing delay per request -system.physmem.avgBankLat 14683.90 # Average bank access latency per request +system.physmem.totQLat 12785750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 610218250 # Sum of mem lat for all requests +system.physmem.totBusLat 151850000 # Total cycles spent in databus access +system.physmem.totBankLat 445582500 # Total cycles spent in bank access +system.physmem.avgQLat 421.00 # Average queueing delay per request +system.physmem.avgBankLat 14671.80 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 20090.01 # Average memory access latency -system.physmem.avgRdBW 29.51 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 29.51 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.16 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 20092.80 # Average memory access latency +system.physmem.avgRdBW 29.48 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 29.48 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.15 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 1.18 # Average write queue length over time -system.physmem.readRowHits 29113 # Number of row buffer hits during reads -system.physmem.writeRowHits 87 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.85 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 51.48 # Row buffer hit rate for writes -system.physmem.avgGap 2156800.25 # Average gap between requests -system.cpu.branchPred.lookups 34551755 # Number of BP lookups -system.cpu.branchPred.condPredicted 34551755 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 910403 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24766802 # Number of BTB lookups -system.cpu.branchPred.BTBHits 24665055 # Number of BTB hits +system.physmem.avgWrQLen 1.30 # Average write queue length over time +system.physmem.readRowHits 29116 # Number of row buffer hits during reads +system.physmem.writeRowHits 69 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.87 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 44.81 # Row buffer hit rate for writes +system.physmem.avgGap 2159691.97 # Average gap between requests +system.cpu.branchPred.lookups 34555739 # Number of BP lookups +system.cpu.branchPred.condPredicted 34555739 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 911751 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24769004 # Number of BTB lookups +system.cpu.branchPred.BTBHits 24665056 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.589180 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 99.580330 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 132009151 # number of cpu cycles simulated +system.cpu.numCycles 132043594 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 26590977 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 185543024 # Number of instructions fetch has processed -system.cpu.fetch.Branches 34551755 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24665055 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 56499392 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6118358 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 43667810 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 138 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 25944504 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 189453 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 131930197 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.484743 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.326414 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 26598616 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 185589305 # Number of instructions fetch has processed +system.cpu.fetch.Branches 34555739 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24665056 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 56508781 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6124933 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 43680261 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 134 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25951098 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 190273 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 131964855 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.484572 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.326415 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 77978275 59.11% 59.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1995894 1.51% 60.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2955143 2.24% 62.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3921314 2.97% 65.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7795304 5.91% 71.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4757842 3.61% 75.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2730359 2.07% 77.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1578596 1.20% 78.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 28217470 21.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 78003722 59.11% 59.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1996961 1.51% 60.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2955104 2.24% 62.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3922098 2.97% 65.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7793741 5.91% 71.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4759235 3.61% 75.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2730671 2.07% 77.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1579089 1.20% 78.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 28224234 21.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 131930197 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.261738 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.405532 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 37427999 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 35920173 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 44744893 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8665277 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5171855 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 324565548 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 5171855 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42969195 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8593654 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9092 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 47590664 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27595737 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 320190802 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 211 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 56984 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25724332 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 365 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 322194206 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 849198017 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 849196232 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1785 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131964855 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.261699 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.405515 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 37438024 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 35931161 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 44761152 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8657481 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5177037 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 324625052 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 5177037 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42998776 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8560534 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9611 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 47593573 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27625324 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 320243292 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 235 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 57194 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25761475 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 370 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 322250586 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 849328812 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 849326947 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1865 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212745 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 42981461 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 43037841 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 469 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 463 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62356862 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 102568377 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 35231338 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 39589479 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6005074 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 315870239 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1674 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 302163622 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 115310 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 37046058 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 54286160 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1229 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 131930197 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.290329 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.700150 # Number of insts issued each cycle +system.cpu.rename.skidInsts 62395647 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 102574673 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 35240496 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 39587079 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6070451 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 315904307 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1659 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 302190238 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 114769 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 37077809 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 54333314 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1214 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131964855 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.289930 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.700500 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24515615 18.58% 18.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23292289 17.66% 36.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25896464 19.63% 55.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25797972 19.55% 75.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18916380 14.34% 89.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8292938 6.29% 96.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4139203 3.14% 99.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 915627 0.69% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 163709 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24574614 18.62% 18.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23238985 17.61% 36.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25913680 19.64% 55.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25803819 19.55% 75.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18917522 14.34% 89.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8297062 6.29% 96.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4140134 3.14% 99.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 916078 0.69% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 162961 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 131930197 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131964855 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 38493 1.98% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1820587 93.51% 95.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 87813 4.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 38351 1.96% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1834339 93.53% 95.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 88449 4.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 31282 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 171146899 56.64% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 171161474 56.64% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 35 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.65% # Type of FU issued @@ -353,84 +338,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.65% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97755630 32.35% 89.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33229776 11.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97761295 32.35% 89.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33236158 11.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 302163622 # Type of FU issued -system.cpu.iq.rate 2.288960 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1946893 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006443 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 738319072 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 352950108 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 299522625 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 572 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 867 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 162 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 304078975 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 258 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 53992768 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 302190238 # Type of FU issued +system.cpu.iq.rate 2.288564 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1961139 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006490 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 738420696 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 353016005 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 299545946 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 543 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 861 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 304119846 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 249 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 53994204 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11788993 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26852 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33996 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3791586 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11795289 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26124 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34117 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3800744 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3239 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8506 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3243 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8488 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5171855 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1763635 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 159728 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 315871913 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 195728 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 102568377 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 35231338 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 5177037 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1758271 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 159446 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 315905966 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 197291 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 102574673 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 35240496 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 464 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3188 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73556 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33996 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 522451 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 444817 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 967268 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 300543939 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 97286160 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1619683 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 3186 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73305 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34117 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 522582 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 446237 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 968819 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 300569422 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 97293064 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1620816 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 130298049 # number of memory reference insts executed -system.cpu.iew.exec_branches 30887567 # Number of branches executed -system.cpu.iew.exec_stores 33011889 # Number of stores executed -system.cpu.iew.exec_rate 2.276690 # Inst execution rate -system.cpu.iew.wb_sent 299950982 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 299522787 # cumulative count of insts written-back -system.cpu.iew.wb_producers 219513248 # num instructions producing a value -system.cpu.iew.wb_consumers 298024509 # num instructions consuming a value +system.cpu.iew.exec_refs 130310023 # number of memory reference insts executed +system.cpu.iew.exec_branches 30888402 # Number of branches executed +system.cpu.iew.exec_stores 33016959 # Number of stores executed +system.cpu.iew.exec_rate 2.276289 # Inst execution rate +system.cpu.iew.wb_sent 299975987 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 299546100 # cumulative count of insts written-back +system.cpu.iew.wb_producers 219510783 # num instructions producing a value +system.cpu.iew.wb_consumers 298009836 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.268955 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736561 # average fanout of values written-back +system.cpu.iew.wb_rate 2.268539 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736589 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 37692291 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 37726716 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 910422 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 126758342 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.194668 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.965617 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 911770 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126787818 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.194158 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.965410 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58200495 45.91% 45.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19281721 15.21% 61.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11800672 9.31% 70.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9590531 7.57% 78.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1751465 1.38% 79.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2073903 1.64% 81.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1296843 1.02% 82.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 720324 0.57% 82.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22042388 17.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58221604 45.92% 45.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19287083 15.21% 61.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11808302 9.31% 70.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9592177 7.57% 78.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1746716 1.38% 79.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2074829 1.64% 81.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1294024 1.02% 82.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 717572 0.57% 82.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22045511 17.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 126758342 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126787818 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192463 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -441,69 +426,69 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186172 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22042388 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22045511 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 420600708 # The number of ROB reads -system.cpu.rob.rob_writes 636946432 # The number of ROB writes -system.cpu.timesIdled 13762 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 78954 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 420661486 # The number of ROB reads +system.cpu.rob.rob_writes 637020452 # The number of ROB writes +system.cpu.timesIdled 13945 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 78739 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192463 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.835562 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.835562 # CPI: Total CPI of All Threads -system.cpu.ipc 1.196800 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.196800 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 592847791 # number of integer regfile reads -system.cpu.int_regfile_writes 300194164 # number of integer regfile writes -system.cpu.fp_regfile_reads 150 # number of floating regfile reads -system.cpu.fp_regfile_writes 76 # number of floating regfile writes -system.cpu.misc_regfile_reads 192689354 # number of misc regfile reads -system.cpu.icache.replacements 61 # number of replacements -system.cpu.icache.tagsinuse 835.847711 # Cycle average of tags in use -system.cpu.icache.total_refs 25943160 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1033 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25114.385286 # Average number of references to valid blocks. +system.cpu.cpi 0.835780 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.835780 # CPI: Total CPI of All Threads +system.cpu.ipc 1.196488 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.196488 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 592874208 # number of integer regfile reads +system.cpu.int_regfile_writes 300213863 # number of integer regfile writes +system.cpu.fp_regfile_reads 139 # number of floating regfile reads +system.cpu.fp_regfile_writes 70 # number of floating regfile writes +system.cpu.misc_regfile_reads 192707426 # number of misc regfile reads +system.cpu.icache.replacements 62 # number of replacements +system.cpu.icache.tagsinuse 835.762840 # Cycle average of tags in use +system.cpu.icache.total_refs 25949757 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1029 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 25218.422741 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 835.847711 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.408129 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.408129 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25943160 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25943160 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25943160 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25943160 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25943160 # number of overall hits -system.cpu.icache.overall_hits::total 25943160 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1344 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1344 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1344 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1344 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1344 # number of overall misses -system.cpu.icache.overall_misses::total 1344 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 65684000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 65684000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 65684000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 65684000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 65684000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 65684000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25944504 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25944504 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25944504 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25944504 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25944504 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25944504 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 835.762840 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.408087 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.408087 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25949757 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25949757 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25949757 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25949757 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25949757 # number of overall hits +system.cpu.icache.overall_hits::total 25949757 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1341 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1341 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1341 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1341 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1341 # number of overall misses +system.cpu.icache.overall_misses::total 1341 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 65663000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 65663000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 65663000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 65663000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 65663000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 65663000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25951098 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25951098 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25951098 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25951098 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25951098 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25951098 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48872.023810 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48872.023810 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48872.023810 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48872.023810 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48872.023810 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48872.023810 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48965.697241 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48965.697241 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48965.697241 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48965.697241 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48965.697241 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48965.697241 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -512,126 +497,126 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 26.600000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 310 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 310 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 310 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 310 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 310 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 310 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1034 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1034 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1034 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1034 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1034 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1034 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51833500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 51833500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51833500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 51833500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51833500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 51833500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 311 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 311 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 311 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 311 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 311 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1030 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1030 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1030 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1030 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1030 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1030 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51831000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 51831000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51831000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 51831000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51831000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 51831000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50129.110251 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50129.110251 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50129.110251 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50129.110251 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50129.110251 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50129.110251 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50321.359223 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50321.359223 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50321.359223 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50321.359223 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50321.359223 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50321.359223 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 480 # number of replacements -system.cpu.l2cache.tagsinuse 20802.892196 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4028440 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 30411 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 132.466542 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 462 # number of replacements +system.cpu.l2cache.tagsinuse 20805.290602 # Cycle average of tags in use +system.cpu.l2cache.total_refs 4028325 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 30393 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 132.541210 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19867.143947 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 689.298857 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 246.449393 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.606297 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.021036 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.007521 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.634854 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 19869.756423 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 689.265972 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 246.268207 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.606377 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.021035 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.007516 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.634927 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1993529 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1993545 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2066104 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2066104 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 53248 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 53248 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1993469 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1993485 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2066038 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2066038 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 53254 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 53254 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2046777 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2046793 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2046723 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2046739 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2046777 # number of overall hits -system.cpu.l2cache.overall_hits::total 2046793 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1017 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 417 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1434 # number of ReadReq misses +system.cpu.l2cache.overall_hits::cpu.data 2046723 # number of overall hits +system.cpu.l2cache.overall_hits::total 2046739 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1013 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 404 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1417 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 29000 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 29000 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1017 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 29417 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 30434 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1017 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 29417 # number of overall misses -system.cpu.l2cache.overall_misses::total 30434 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50633000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21040000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 71673000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1219810500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1219810500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 50633000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1240850500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1291483500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 50633000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1240850500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1291483500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1033 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1993946 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1994979 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2066104 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2066104 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 28999 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 28999 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1013 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29403 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30416 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1013 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 29403 # number of overall misses +system.cpu.l2cache.overall_misses::total 30416 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50632500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20596000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 71228500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1219887500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1219887500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 50632500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1240483500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1291116000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 50632500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1240483500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1291116000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1029 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1993873 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1994902 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2066038 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2066038 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 82248 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 82248 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1033 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2076194 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2077227 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1033 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2076194 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2077227 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984511 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000209 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000719 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 82253 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 82253 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1029 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076126 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077155 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1029 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2076126 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077155 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984451 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000203 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000710 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352592 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.352592 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984511 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014169 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014651 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984511 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014169 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014651 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49786.627335 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50455.635492 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49981.171548 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42062.431034 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42062.431034 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49786.627335 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42181.408709 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 42435.549057 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49786.627335 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42181.408709 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 42435.549057 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352559 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.352559 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984451 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014162 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014643 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984451 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014162 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014643 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49982.724580 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50980.198020 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 50267.113620 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42066.536777 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42066.536777 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49982.724580 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42189.011325 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 42448.579695 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49982.724580 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42189.011325 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 42448.579695 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -640,168 +625,168 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 169 # number of writebacks -system.cpu.l2cache.writebacks::total 169 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1017 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1434 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 154 # number of writebacks +system.cpu.l2cache.writebacks::total 154 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1013 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 404 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1417 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29000 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 29000 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1017 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29417 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30434 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1017 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29417 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30434 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38011868 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15869892 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53881760 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28999 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28999 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1013 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29403 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30416 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1013 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29403 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30416 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38064309 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15602084 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53666393 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 862092136 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 862092136 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38011868 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 877962028 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 915973896 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38011868 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 877962028 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 915973896 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984511 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000209 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000719 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 862137460 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 862137460 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38064309 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 877739544 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 915803853 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38064309 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 877739544 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 915803853 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984451 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000203 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000710 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352592 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352592 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984511 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014651 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984511 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014651 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37376.468043 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38057.294964 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37574.449093 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352559 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352559 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984451 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014162 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014643 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984451 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014162 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014643 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37575.823297 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38619.019802 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37873.248412 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 29727.315034 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 29727.315034 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37376.468043 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29845.396471 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30097.059079 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37376.468043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29845.396471 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30097.059079 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 29729.903100 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 29729.903100 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37575.823297 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29852.040404 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30109.279754 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37575.823297 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29852.040404 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30109.279754 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2072095 # number of replacements -system.cpu.dcache.tagsinuse 4072.471954 # Cycle average of tags in use -system.cpu.dcache.total_refs 71964033 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2076191 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.661567 # Average number of references to valid blocks. +system.cpu.dcache.replacements 2072027 # number of replacements +system.cpu.dcache.tagsinuse 4072.478091 # Cycle average of tags in use +system.cpu.dcache.total_refs 71969321 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2076123 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.665249 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 21154875000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.471954 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994256 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994256 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 40622570 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40622570 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31341456 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31341456 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71964026 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71964026 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71964026 # number of overall hits -system.cpu.dcache.overall_hits::total 71964026 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2625435 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2625435 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 98296 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 98296 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2723731 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2723731 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2723731 # number of overall misses -system.cpu.dcache.overall_misses::total 2723731 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31317831000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31317831000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2109058498 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2109058498 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33426889498 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33426889498 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33426889498 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33426889498 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 43248005 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 43248005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 4072.478091 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994257 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994257 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 40627855 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40627855 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31341459 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31341459 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71969314 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71969314 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71969314 # number of overall hits +system.cpu.dcache.overall_hits::total 71969314 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2625363 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2625363 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 98293 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 98293 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2723656 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2723656 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2723656 # number of overall misses +system.cpu.dcache.overall_misses::total 2723656 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31317935000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31317935000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2109133999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2109133999 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33427068999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33427068999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33427068999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33427068999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 43253218 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 43253218 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74687757 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74687757 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74687757 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74687757 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060706 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.060706 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 74692970 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74692970 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74692970 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74692970 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060698 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.060698 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036468 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036468 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036468 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036468 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11928.625542 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11928.625542 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21456.198604 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21456.198604 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12272.463580 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12272.463580 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12272.463580 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12272.463580 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32211 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.036465 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036465 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036465 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036465 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11928.992296 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11928.992296 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21457.621591 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21457.621591 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12272.867425 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12272.867425 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12272.867425 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12272.867425 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 31969 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9475 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9433 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.399578 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.389060 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066104 # number of writebacks -system.cpu.dcache.writebacks::total 2066104 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631384 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 631384 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16152 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16152 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 647536 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 647536 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 647536 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 647536 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994051 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994051 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82144 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82144 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076195 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076195 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076195 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076195 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21987856500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21987856500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1833812998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1833812998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23821669498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23821669498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23821669498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23821669498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046107 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046107 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 2066038 # number of writebacks +system.cpu.dcache.writebacks::total 2066038 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631383 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 631383 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16146 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16146 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 647529 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 647529 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 647529 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 647529 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1993980 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1993980 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82147 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82147 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076127 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076127 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076127 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076127 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21982224500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21982224500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1833925499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1833925499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23816149999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23816149999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23816149999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23816149999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046100 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046100 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002613 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002613 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027798 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027798 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027798 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027798 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11026.727250 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11026.727250 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22324.369376 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22324.369376 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11473.714896 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11473.714896 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11473.714896 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11473.714896 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027795 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027795 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027795 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027795 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.295379 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.295379 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22324.923600 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22324.923600 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11471.432142 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11471.432142 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11471.432142 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11471.432142 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index f32034add..1e537017c 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,117 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.434532 # Number of seconds simulated -sim_ticks 434531908500 # Number of ticks simulated -final_tick 434531908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.434431 # Number of seconds simulated +sim_ticks 434430920500 # Number of ticks simulated +final_tick 434430920500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91853 # Simulator instruction rate (inst/s) -host_op_rate 169847 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48269802 # Simulator tick rate (ticks/s) -host_mem_usage 425632 # Number of bytes of host memory used -host_seconds 9002.15 # Real time elapsed on the host +host_inst_rate 103951 # Simulator instruction rate (inst/s) +host_op_rate 192218 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54614710 # Simulator tick rate (ticks/s) +host_mem_usage 421552 # Number of bytes of host memory used +host_seconds 7954.47 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988700 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 206656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24475072 # Number of bytes read from this memory -system.physmem.bytes_read::total 24681728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24473856 # Number of bytes read from this memory +system.physmem.bytes_read::total 24680512 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 206656 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 206656 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18793472 # Number of bytes written to this memory -system.physmem.bytes_written::total 18793472 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 18792192 # Number of bytes written to this memory +system.physmem.bytes_written::total 18792192 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 3229 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382423 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385652 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293648 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293648 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 475583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 56325143 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 56800726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 475583 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 475583 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43249924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43249924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43249924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 475583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 56325143 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 100050650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385654 # Total number of read requests seen -system.physmem.writeReqs 293648 # Total number of write requests seen -system.physmem.cpureqs 897087 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 24681728 # Total number of bytes read from memory -system.physmem.bytesWritten 18793472 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24681728 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18793472 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 151 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 214401 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 23129 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 24463 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 23958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 22626 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 23437 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24746 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 24520 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24217 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 24346 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 24649 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 24306 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 24351 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 24467 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 23427 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 24871 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 23990 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 17780 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 18806 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18330 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 17563 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 18009 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18654 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18318 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 18307 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 18738 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 18746 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 18443 # Track writes on a per bank basis +system.physmem.num_reads::cpu.data 382404 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385633 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293628 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293628 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 475694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 56335438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 56811131 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 475694 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 475694 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43257031 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43257031 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43257031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 475694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 56335438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 100068163 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385635 # Total number of read requests seen +system.physmem.writeReqs 293628 # Total number of write requests seen +system.physmem.cpureqs 897306 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 24680512 # Total number of bytes read from memory +system.physmem.bytesWritten 18792192 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24680512 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18792192 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 135 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 215167 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 23200 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 24440 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 23926 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 22603 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 23455 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24726 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 24470 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24228 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 24367 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 24672 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 24294 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 24362 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 24487 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 23459 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 24852 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 23959 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 17796 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 18805 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18324 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 17566 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 18019 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18653 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18315 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 18311 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 18728 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 18743 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 18429 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 18564 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 18554 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 17877 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 18850 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 18109 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 18552 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 17863 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 18856 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 18104 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 3384 # Number of times wr buffer was full causing retry -system.physmem.totGap 434531891500 # Total gap between requests +system.physmem.numWrRetry 2876 # Number of times wr buffer was full causing retry +system.physmem.totGap 434430903500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385654 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 297032 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 214401 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 380704 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.readPktSize::6 385635 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 293628 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 380797 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -137,195 +124,194 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 12706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 12717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 12721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 12709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 12719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 12720 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 12722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 12726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 12730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 12725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 12729 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 12733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 12733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 12737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 12739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 12741 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 48 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3414434563 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12002683313 # Sum of mem lat for all requests -system.physmem.totBusLat 1927515000 # Total cycles spent in databus access -system.physmem.totBankLat 6660733750 # Total cycles spent in bank access -system.physmem.avgQLat 8857.09 # Average queueing delay per request -system.physmem.avgBankLat 17278.03 # Average bank access latency per request +system.physmem.wrQLenPdf::29 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 26 # What write queue length does an incoming req see +system.physmem.totQLat 3409479750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11997177250 # Sum of mem lat for all requests +system.physmem.totBusLat 1927500000 # Total cycles spent in databus access +system.physmem.totBankLat 6660197500 # Total cycles spent in bank access +system.physmem.avgQLat 8844.31 # Average queueing delay per request +system.physmem.avgBankLat 17276.78 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31135.12 # Average memory access latency -system.physmem.avgRdBW 56.80 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 43.25 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 56.80 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 43.25 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31121.08 # Average memory access latency +system.physmem.avgRdBW 56.81 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 43.26 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 56.81 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 43.26 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.78 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 9.81 # Average write queue length over time -system.physmem.readRowHits 331850 # Number of row buffer hits during reads -system.physmem.writeRowHits 191739 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.08 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.30 # Row buffer hit rate for writes -system.physmem.avgGap 639674.09 # Average gap between requests -system.cpu.branchPred.lookups 214985170 # Number of BP lookups -system.cpu.branchPred.condPredicted 214985170 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13134974 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 150557498 # Number of BTB lookups -system.cpu.branchPred.BTBHits 147831953 # Number of BTB hits +system.physmem.avgWrQLen 9.17 # Average write queue length over time +system.physmem.readRowHits 331860 # Number of row buffer hits during reads +system.physmem.writeRowHits 191798 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.32 # Row buffer hit rate for writes +system.physmem.avgGap 639562.15 # Average gap between requests +system.cpu.branchPred.lookups 214905339 # Number of BP lookups +system.cpu.branchPred.condPredicted 214905339 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13127433 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 150477516 # Number of BTB lookups +system.cpu.branchPred.BTBHits 147823689 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.189698 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 98.236396 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 869063818 # number of cpu cycles simulated +system.cpu.numCycles 868861842 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 180571756 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1193203975 # Number of instructions fetch has processed -system.cpu.fetch.Branches 214985170 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 147831953 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 371215101 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 83387755 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 231673075 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33185 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 322843 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 173439567 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3823649 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 853812868 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.595051 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.389323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180577504 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1192973241 # Number of instructions fetch has processed +system.cpu.fetch.Branches 214905339 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 147823689 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 371150852 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83341611 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 231393952 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33171 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 324598 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 87 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 173446874 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3818726 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 853436670 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.595518 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.389389 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 486992667 57.04% 57.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24704335 2.89% 59.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 27327411 3.20% 63.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28832283 3.38% 66.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 18475468 2.16% 68.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 24603692 2.88% 71.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30623589 3.59% 75.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28857730 3.38% 78.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183395693 21.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 486691437 57.03% 57.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24707790 2.90% 59.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 27346098 3.20% 63.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28808795 3.38% 66.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18459850 2.16% 68.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 24598509 2.88% 71.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30642263 3.59% 75.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28856964 3.38% 78.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183324964 21.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 853812868 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.247376 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.372976 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 237064473 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 188186572 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 313399146 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 45165837 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 69996840 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2166788008 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 69996840 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 270473923 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 53975472 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17892 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 322682449 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 136666292 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2119871980 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 32012 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 21236600 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 101165935 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 102 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2216234467 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5355317387 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5355179179 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 138208 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 853436670 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.247341 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.373030 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 237036597 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 187932241 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 313348177 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 45163149 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69956506 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2166370172 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 69956506 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 270406129 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 53950609 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16000 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 322641702 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 136465724 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2119600897 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 32452 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20939189 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 101244294 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 109 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2216054849 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5354933162 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5354796739 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 136423 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040852 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 602193615 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1385 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1348 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 330022122 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 512693840 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 204894369 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 196280742 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 55580246 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2033860002 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 23240 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1808188122 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 845695 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 499369913 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 817987835 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 22688 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 853812868 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.117780 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.887735 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 602013997 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1381 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1341 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 329887917 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 512569621 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 204871608 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 196009794 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 55366102 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2033547368 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 23672 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1807958991 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 824800 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 499056334 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 817700270 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 23120 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 853436670 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.118445 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.887633 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 233534658 27.35% 27.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 145245329 17.01% 44.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 138299025 16.20% 60.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 133036648 15.58% 76.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 95993641 11.24% 87.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 58825628 6.89% 94.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34908775 4.09% 98.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12073867 1.41% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1895297 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 233342895 27.34% 27.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 145008680 16.99% 44.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 138353825 16.21% 60.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 133057886 15.59% 76.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 96025914 11.25% 87.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 58740201 6.88% 94.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34984970 4.10% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12023870 1.41% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1898429 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 853812868 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 853436670 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4968961 32.44% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7761394 50.67% 83.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2587769 16.89% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4945296 32.31% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7774785 50.79% 83.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2587375 16.90% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2719358 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1190817504 65.86% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2719757 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1190688442 65.86% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.01% # Type of FU issued @@ -354,84 +340,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 438925166 24.27% 90.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 175726094 9.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 438864121 24.27% 90.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 175686671 9.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1808188122 # Type of FU issued -system.cpu.iq.rate 2.080616 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15318124 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008472 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4486330411 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2533466617 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1768665835 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22520 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43644 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 4990 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1820776414 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 10474 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 170620885 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1807958991 # Type of FU issued +system.cpu.iq.rate 2.080836 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15307456 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008467 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4485463564 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2532842226 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1768511816 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23344 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 44056 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 5298 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1820535825 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 10865 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 170531860 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 128591684 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 469733 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 268884 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 55734548 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 128467465 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 477996 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 270600 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 55711763 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12443 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 683 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12158 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 637 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 69996840 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16364844 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2884009 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2033883242 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2403682 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 512693840 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 204894734 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6182 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1820537 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 77063 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 268884 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 9113160 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4488782 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 13601942 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1780436006 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 431388742 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 27752116 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69956506 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16270481 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2882420 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2033571040 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2388116 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 512569621 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 204871949 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6204 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1819124 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 76761 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 270600 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 9107192 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4485988 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 13593180 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1780284053 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 431339374 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 27674938 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 602101798 # number of memory reference insts executed -system.cpu.iew.exec_branches 169273677 # Number of branches executed -system.cpu.iew.exec_stores 170713056 # Number of stores executed -system.cpu.iew.exec_rate 2.048683 # Inst execution rate -system.cpu.iew.wb_sent 1775376016 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1768670825 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1341566013 # num instructions producing a value -system.cpu.iew.wb_consumers 1964312147 # num instructions consuming a value +system.cpu.iew.exec_refs 602039294 # number of memory reference insts executed +system.cpu.iew.exec_branches 169246967 # Number of branches executed +system.cpu.iew.exec_stores 170699920 # Number of stores executed +system.cpu.iew.exec_rate 2.048984 # Inst execution rate +system.cpu.iew.wb_sent 1775206038 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1768517114 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1341481369 # num instructions producing a value +system.cpu.iew.wb_consumers 1964281102 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.035145 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.682970 # average fanout of values written-back +system.cpu.iew.wb_rate 2.035441 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.682938 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 504930562 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 504616245 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 13167809 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 783816028 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.950698 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.458733 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 13160386 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 783480164 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.951535 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.459630 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 290605318 37.08% 37.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 195507197 24.94% 62.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 61957017 7.90% 69.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92299201 11.78% 81.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25131164 3.21% 84.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28287004 3.61% 88.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9364104 1.19% 89.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10794618 1.38% 91.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69870405 8.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 290390176 37.06% 37.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 195527314 24.96% 62.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 61904118 7.90% 69.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92200524 11.77% 81.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25009746 3.19% 84.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28276907 3.61% 88.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9452853 1.21% 89.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10837267 1.38% 91.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69881259 8.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 783816028 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 783480164 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988700 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -442,203 +428,203 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317559 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69870405 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69881259 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2747864885 # The number of ROB reads -system.cpu.rob.rob_writes 4138016116 # The number of ROB writes -system.cpu.timesIdled 327647 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 15250950 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2747203850 # The number of ROB reads +system.cpu.rob.rob_writes 4137345189 # The number of ROB writes +system.cpu.timesIdled 333192 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 15425172 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988700 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.051019 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.051019 # CPI: Total CPI of All Threads -system.cpu.ipc 0.951457 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.951457 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3357381544 # number of integer regfile reads -system.cpu.int_regfile_writes 1848396157 # number of integer regfile writes -system.cpu.fp_regfile_reads 4985 # number of floating regfile reads -system.cpu.fp_regfile_writes 5 # number of floating regfile writes -system.cpu.misc_regfile_reads 980232069 # number of misc regfile reads -system.cpu.icache.replacements 5428 # number of replacements -system.cpu.icache.tagsinuse 1035.426880 # Cycle average of tags in use -system.cpu.icache.total_refs 173198733 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7017 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24682.732364 # Average number of references to valid blocks. +system.cpu.cpi 1.050775 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.050775 # CPI: Total CPI of All Threads +system.cpu.ipc 0.951678 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.951678 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3357185623 # number of integer regfile reads +system.cpu.int_regfile_writes 1848288300 # number of integer regfile writes +system.cpu.fp_regfile_reads 5295 # number of floating regfile reads +system.cpu.fp_regfile_writes 3 # number of floating regfile writes +system.cpu.misc_regfile_reads 980095444 # number of misc regfile reads +system.cpu.icache.replacements 5498 # number of replacements +system.cpu.icache.tagsinuse 1034.775539 # Cycle average of tags in use +system.cpu.icache.total_refs 173205275 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7087 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 24439.858191 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1035.426880 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.505580 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.505580 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 173214256 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 173214256 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 173214256 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 173214256 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 173214256 # number of overall hits -system.cpu.icache.overall_hits::total 173214256 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 225311 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 225311 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 225311 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 225311 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 225311 # number of overall misses -system.cpu.icache.overall_misses::total 225311 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1422825499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1422825499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1422825499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1422825499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1422825499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1422825499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 173439567 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 173439567 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 173439567 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 173439567 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 173439567 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 173439567 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001299 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001299 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001299 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001299 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001299 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001299 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6314.940234 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6314.940234 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6314.940234 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6314.940234 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6314.940234 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6314.940234 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 893 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1034.775539 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.505261 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.505261 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 173220667 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 173220667 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 173220667 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 173220667 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 173220667 # number of overall hits +system.cpu.icache.overall_hits::total 173220667 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 226207 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 226207 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 226207 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 226207 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 226207 # number of overall misses +system.cpu.icache.overall_misses::total 226207 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1445018998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1445018998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1445018998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1445018998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1445018998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1445018998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 173446874 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 173446874 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 173446874 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 173446874 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 173446874 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 173446874 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001304 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001304 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001304 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001304 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001304 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001304 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6388.038381 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6388.038381 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6388.038381 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6388.038381 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6388.038381 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6388.038381 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 531 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 63.785714 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 33.187500 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2350 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2350 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2350 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2350 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2350 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2350 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 222961 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 222961 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 222961 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 222961 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 222961 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 222961 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 908771999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 908771999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 908771999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 908771999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 908771999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 908771999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001286 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001286 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001286 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001286 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001286 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001286 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4075.923588 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4075.923588 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4075.923588 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4075.923588 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4075.923588 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4075.923588 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2416 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2416 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2416 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2416 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2416 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2416 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 223791 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 223791 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 223791 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 223791 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 223791 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 223791 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 922806998 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 922806998 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 922806998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 922806998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 922806998 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 922806998 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001290 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001290 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001290 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001290 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001290 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001290 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4123.521491 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4123.521491 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4123.521491 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4123.521491 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4123.521491 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4123.521491 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 352967 # number of replacements -system.cpu.l2cache.tagsinuse 29623.610985 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3697581 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 385328 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 9.595931 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 202031394500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21046.511292 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 232.202938 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8344.896755 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.642289 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.007086 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.254666 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.904041 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3753 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1586557 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1590310 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2331178 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2331178 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1519 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1519 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 564630 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 564630 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3753 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2151187 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2154940 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3753 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2151187 # number of overall hits -system.cpu.l2cache.overall_hits::total 2154940 # number of overall hits +system.cpu.l2cache.replacements 352952 # number of replacements +system.cpu.l2cache.tagsinuse 29623.817782 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3697849 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 385320 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 9.596826 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 201967197500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 21048.763248 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 234.229259 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 8340.825274 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.642357 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.007148 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.254542 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.904047 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3812 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1586582 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1590394 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2331083 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2331083 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1524 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1524 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 564588 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 564588 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3812 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2151170 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2154982 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3812 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2151170 # number of overall hits +system.cpu.l2cache.overall_hits::total 2154982 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 3230 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 175686 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 178916 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 214369 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 214369 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206771 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206771 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 175670 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 178900 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 215135 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 215135 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206768 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206768 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 3230 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 382457 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 385687 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 382438 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 385668 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3230 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 382457 # number of overall misses -system.cpu.l2cache.overall_misses::total 385687 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 196335000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10103953956 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 10300288956 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7210000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 7210000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10386868500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10386868500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 196335000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20490822456 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20687157456 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 196335000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20490822456 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20687157456 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 6983 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1762243 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1769226 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2331178 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2331178 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 215888 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 215888 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 771401 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 771401 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6983 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2533644 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2540627 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6983 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2533644 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2540627 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.462552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099695 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.101127 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.992964 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.992964 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268046 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.268046 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.462552 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150951 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151808 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.462552 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150951 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151808 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60784.829721 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57511.434924 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 57570.530059 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 33.633594 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 33.633594 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50233.681222 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50233.681222 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60784.829721 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53576.800676 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 53637.165515 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60784.829721 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53576.800676 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 53637.165515 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.data 382438 # number of overall misses +system.cpu.l2cache.overall_misses::total 385668 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 200745500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10125783456 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 10326528956 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7277000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 7277000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10354954000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10354954000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 200745500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 20480737456 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20681482956 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 200745500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 20480737456 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20681482956 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 7042 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1762252 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1769294 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2331083 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2331083 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 216659 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 216659 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 771356 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 771356 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 7042 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2533608 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2540650 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 7042 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2533608 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2540650 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.458677 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099685 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.101114 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.992966 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.992966 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268058 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.268058 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.458677 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150946 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151799 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.458677 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150946 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151799 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62150.309598 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57640.937303 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 57722.353024 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 33.825273 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 33.825273 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50080.060744 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50080.060744 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62150.309598 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53553.092151 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53625.094527 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62150.309598 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53553.092151 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53625.094527 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -647,168 +633,168 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 293648 # number of writebacks -system.cpu.l2cache.writebacks::total 293648 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 293628 # number of writebacks +system.cpu.l2cache.writebacks::total 293628 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3230 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175686 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 178916 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 214369 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 214369 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206771 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206771 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175670 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 178900 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 215135 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 215135 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206768 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206768 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 3230 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 382457 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 385687 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 382438 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 385668 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3230 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 382457 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 385687 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 156219180 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7929842195 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8086061375 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2149350076 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2149350076 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7799617575 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7799617575 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 156219180 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15729459770 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15885678950 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 156219180 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15729459770 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15885678950 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.462552 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099695 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101127 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992964 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992964 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268046 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268046 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.462552 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150951 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151808 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.462552 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150951 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151808 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48365.071207 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45136.449091 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45194.735938 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.403426 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.403426 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37721.041998 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37721.041998 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48365.071207 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41127.394112 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41188.007244 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48365.071207 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41127.394112 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41188.007244 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.data 382438 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 385668 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 160592502 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7951741535 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8112334037 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2156878107 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2156878107 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7767550023 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7767550023 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 160592502 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15719291558 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15879884060 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 160592502 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15719291558 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15879884060 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.458677 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099685 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101114 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992966 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992966 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268058 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268058 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.458677 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150946 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151799 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.458677 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150946 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151799 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49719.040867 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45265.221922 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45345.634639 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10025.695991 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10025.695991 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37566.499763 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37566.499763 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49719.040867 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41102.849502 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41175.010786 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49719.040867 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41102.849502 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41175.010786 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2529546 # number of replacements -system.cpu.dcache.tagsinuse 4087.815974 # Cycle average of tags in use -system.cpu.dcache.total_refs 405263721 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2533642 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 159.953032 # Average number of references to valid blocks. +system.cpu.dcache.replacements 2529510 # number of replacements +system.cpu.dcache.tagsinuse 4087.814071 # Cycle average of tags in use +system.cpu.dcache.total_refs 405300363 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2533606 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 159.969768 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 1790563000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.815974 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998002 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998002 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 256525921 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 256525921 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148156323 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148156323 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 404682244 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 404682244 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 404682244 # number of overall hits -system.cpu.dcache.overall_hits::total 404682244 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2897766 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2897766 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1003879 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1003879 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3901645 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3901645 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3901645 # number of overall misses -system.cpu.dcache.overall_misses::total 3901645 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 51407808000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 51407808000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23879895000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23879895000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 75287703000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 75287703000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 75287703000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 75287703000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 259423687 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 259423687 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 4087.814071 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998001 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998001 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 256561451 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 256561451 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148155645 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148155645 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 404717096 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 404717096 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 404717096 # number of overall hits +system.cpu.dcache.overall_hits::total 404717096 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2903042 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2903042 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1004557 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1004557 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3907599 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3907599 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3907599 # number of overall misses +system.cpu.dcache.overall_misses::total 3907599 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 51581963000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 51581963000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23867126500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23867126500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75449089500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75449089500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75449089500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75449089500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 259464493 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 259464493 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 408583889 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 408583889 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 408583889 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 408583889 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011170 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011170 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006730 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006730 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009549 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009549 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009549 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009549 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17740.496645 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17740.496645 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23787.622811 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23787.622811 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19296.400108 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19296.400108 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19296.400108 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19296.400108 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6861 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 408624695 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 408624695 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 408624695 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 408624695 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011189 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011189 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006735 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006735 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009563 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009563 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009563 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009563 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17768.245516 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17768.245516 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23758.857387 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23758.857387 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19308.298907 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19308.298907 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19308.298907 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19308.298907 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6217 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 663 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 681 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.348416 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.129222 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2331178 # number of writebacks -system.cpu.dcache.writebacks::total 2331178 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1135254 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1135254 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16862 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16862 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1152116 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1152116 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1152116 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1152116 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762512 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762512 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 987017 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 987017 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2749529 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2749529 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2749529 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2749529 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27769073500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27769073500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21705384500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 21705384500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49474458000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 49474458000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49474458000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 49474458000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006794 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006794 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006617 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006617 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006729 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006729 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006729 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006729 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15755.395424 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15755.395424 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21990.892254 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21990.892254 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17993.793846 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17993.793846 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17993.793846 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17993.793846 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2331083 # number of writebacks +system.cpu.dcache.writebacks::total 2331083 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1140525 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1140525 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16809 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16809 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1157334 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1157334 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1157334 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1157334 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762517 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762517 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 987748 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 987748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2750265 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2750265 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2750265 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2750265 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27791691500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27791691500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21690054500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 21690054500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49481746000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 49481746000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49481746000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 49481746000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006793 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006793 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006622 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006622 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006731 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006731 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006731 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006731 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15768.183513 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15768.183513 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21959.097361 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21959.097361 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17991.628443 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17991.628443 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17991.628443 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17991.628443 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 6c858f4a6..188ee6566 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.139855 # Nu sim_ticks 139855372500 # Number of ticks simulated final_tick 139855372500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164436 # Simulator instruction rate (inst/s) -host_op_rate 164436 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57685897 # Simulator tick rate (ticks/s) -host_mem_usage 230388 # Number of bytes of host memory used -host_seconds 2424.43 # Real time elapsed on the host +host_inst_rate 118034 # Simulator instruction rate (inst/s) +host_op_rate 118034 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41407532 # Simulator tick rate (ticks/s) +host_mem_usage 230404 # Number of bytes of host memory used +host_seconds 3377.53 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 7328 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 4560 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1887 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 585 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 47661305 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 197340055 # Sum of mem lat for all requests +system.physmem.totQLat 47654000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 197332750 # Sum of mem lat for all requests system.physmem.totBusLat 36640000 # Total cycles spent in databus access system.physmem.totBankLat 113038750 # Total cycles spent in bank access -system.physmem.avgQLat 6504.00 # Average queueing delay per request +system.physmem.avgQLat 6503.00 # Average queueing delay per request system.physmem.avgBankLat 15425.59 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26929.59 # Average memory access latency +system.physmem.avgMemAccLat 26928.60 # Average memory access latency system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s @@ -473,17 +458,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128897344 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35549956 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 164447300 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120759327 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120759327 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128897344 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156309283 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 285206627 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128897344 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156309283 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 285206627 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128894552 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35549355 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 164443907 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120757665 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120757665 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128894552 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156307020 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 285201572 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128894552 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156307020 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 285201572 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses @@ -495,17 +480,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38373.725514 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43143.150485 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39313.244083 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38397.242289 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38397.242289 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38373.725514 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39382.535399 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38920.118313 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38373.725514 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39382.535399 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38920.118313 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38372.894314 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43142.421117 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39312.432943 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38396.713831 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38396.713831 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38372.894314 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39381.965231 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38919.428493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38372.894314 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39381.965231 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38919.428493 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.tagsinuse 3285.521075 # Cycle average of tags in use diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index f63466b63..8274182ca 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.077334 # Nu sim_ticks 77333663500 # Number of ticks simulated final_tick 77333663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196388 # Simulator instruction rate (inst/s) -host_op_rate 196388 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40437661 # Simulator tick rate (ticks/s) -host_mem_usage 232448 # Number of bytes of host memory used -host_seconds 1912.42 # Real time elapsed on the host +host_inst_rate 154881 # Simulator instruction rate (inst/s) +host_op_rate 154881 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31891174 # Simulator tick rate (ticks/s) +host_mem_usage 232452 # Number of bytes of host memory used +host_seconds 2424.92 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 221120 # Number of bytes read from this memory @@ -78,30 +78,17 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 7448 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2085 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 804 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 307 # What read queue length does an incoming req see +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 4137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 306 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 111 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 53873160 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 207011910 # Sum of mem lat for all requests +system.physmem.totQLat 53845750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 206984500 # Sum of mem lat for all requests system.physmem.totBusLat 37240000 # Total cycles spent in databus access system.physmem.totBankLat 115898750 # Total cycles spent in bank access -system.physmem.avgQLat 7233.24 # Average queueing delay per request +system.physmem.avgQLat 7229.56 # Average queueing delay per request system.physmem.avgBankLat 15561.06 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27794.30 # Average memory access latency +system.physmem.avgMemAccLat 27790.61 # Average memory access latency system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s @@ -198,18 +183,18 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 101791406 # DTB read hits +system.cpu.dtb.read_hits 101791407 # DTB read hits system.cpu.dtb.read_misses 78057 # DTB read misses system.cpu.dtb.read_acv 48605 # DTB read access violations -system.cpu.dtb.read_accesses 101869463 # DTB read accesses +system.cpu.dtb.read_accesses 101869464 # DTB read accesses system.cpu.dtb.write_hits 78427886 # DTB write hits system.cpu.dtb.write_misses 1487 # DTB write misses system.cpu.dtb.write_acv 4 # DTB write access violations system.cpu.dtb.write_accesses 78429373 # DTB write accesses -system.cpu.dtb.data_hits 180219292 # DTB hits +system.cpu.dtb.data_hits 180219293 # DTB hits system.cpu.dtb.data_misses 79544 # DTB misses system.cpu.dtb.data_acv 48609 # DTB access violations -system.cpu.dtb.data_accesses 180298836 # DTB accesses +system.cpu.dtb.data_accesses 180298837 # DTB accesses system.cpu.itb.fetch_hits 50219857 # ITB hits system.cpu.itb.fetch_misses 371 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv @@ -230,23 +215,23 @@ system.cpu.workload.num_syscalls 215 # Nu system.cpu.numCycles 154667329 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 51106120 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 51106123 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 448669005 # Number of instructions fetch has processed system.cpu.fetch.Branches 50250166 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 32239639 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 78764977 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 6110488 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19721587 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 19721562 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 9420 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 50219857 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 408750 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 154473509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 154473487 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.904505 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.325354 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75708532 49.01% 49.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75708510 49.01% 49.01% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 4277779 2.77% 51.78% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 6877340 4.45% 56.23% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 5358744 3.47% 59.70% # Number of instructions fetched each cycle (Total) @@ -258,11 +243,11 @@ system.cpu.fetch.rateDist::8 35257809 22.82% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154473509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 154473487 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.324892 # Number of branch fetches per cycle system.cpu.fetch.rate 2.900865 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 56459553 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15066363 # Number of cycles decode is blocked +system.cpu.decode.IdleCycles 56459555 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15066339 # Number of cycles decode is blocked system.cpu.decode.RunCycles 74129391 # Number of cycles decode is running system.cpu.decode.UnblockCycles 3951215 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 4866987 # Number of cycles decode is squashing @@ -271,15 +256,15 @@ system.cpu.decode.BranchMispred 4302 # Nu system.cpu.decode.DecodedInsts 444763327 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 12199 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 4866987 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 59590768 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4877628 # Number of cycles rename is blocking +system.cpu.rename.IdleCycles 59590769 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4877606 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 403370 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 75043534 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9691222 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 440325296 # Number of instructions processed by rename +system.cpu.rename.UnblockCycles 9691221 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 440325297 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 81 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 19775 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8008636 # Number of times rename has blocked due to LSQ full +system.cpu.rename.LSQFullEvents 8008634 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 287258509 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 578891151 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 306269628 # Number of integer rename lookups @@ -288,35 +273,35 @@ system.cpu.rename.CommittedMaps 259532329 # Nu system.cpu.rename.UndoneMaps 27726180 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 36829 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 293 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27858963 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 27858970 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 104659356 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 80576509 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 8905764 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 6378561 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 408090088 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 408090089 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 285 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 401700569 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 966818 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32383170 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 966819 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32383171 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 15203599 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 70 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154473509 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 154473487 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.600450 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.995226 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28241568 18.28% 18.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 25850506 16.73% 35.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25557985 16.55% 51.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24263587 15.71% 67.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21289313 13.78% 81.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15479662 10.02% 91.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8473783 5.49% 96.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28241547 18.28% 18.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25850500 16.73% 35.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25557992 16.55% 51.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24263583 15.71% 67.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21289316 13.78% 81.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15479664 10.02% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8473780 5.49% 96.56% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 3991768 2.58% 99.14% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 1325337 0.86% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154473509 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154473487 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 34109 0.29% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available @@ -347,12 +332,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.08% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5072339 42.83% 74.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5072338 42.83% 74.92% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 2970257 25.08% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 155713729 38.76% 38.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 155713730 38.76% 38.77% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 2126194 0.53% 39.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 32798014 8.16% 47.47% # Type of FU issued @@ -381,21 +366,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.54% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103367731 25.73% 80.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103367730 25.73% 80.27% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 79244441 19.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 401700569 # Type of FU issued system.cpu.iq.rate 2.597191 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11841746 # FU busy when requested +system.cpu.iq.fu_busy_cnt 11841745 # FU busy when requested system.cpu.iq.fu_busy_rate 0.029479 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 633918884 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 260111127 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 234694704 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 633918862 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 260111129 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 234694703 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 336764327 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 180411325 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 161341889 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 241419354 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 241419353 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 172089380 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 15066516 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -409,10 +394,10 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 260879 # system.cpu.iew.lsq.thread0.cacheBlocked 2892 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 4866987 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2513908 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 367539 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 432875837 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 130046 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewBlockCycles 2513893 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 367538 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 432875839 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 130047 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 104659356 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 80576509 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 285 # Number of dispatched non-speculative instructions @@ -423,42 +408,42 @@ system.cpu.iew.predictedTakenIncorrect 945508 # Nu system.cpu.iew.predictedNotTakenIncorrect 405299 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1350807 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 398189954 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101918110 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts 101918111 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 3510615 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24785464 # number of nop insts executed -system.cpu.iew.exec_refs 180347520 # number of memory reference insts executed +system.cpu.iew.exec_nop 24785465 # number of nop insts executed +system.cpu.iew.exec_refs 180347521 # number of memory reference insts executed system.cpu.iew.exec_branches 46544583 # Number of branches executed system.cpu.iew.exec_stores 78429410 # Number of stores executed system.cpu.iew.exec_rate 2.574493 # Inst execution rate -system.cpu.iew.wb_sent 396666494 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 396036593 # cumulative count of insts written-back -system.cpu.iew.wb_producers 193534236 # num instructions producing a value +system.cpu.iew.wb_sent 396666493 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396036592 # cumulative count of insts written-back +system.cpu.iew.wb_producers 193534237 # num instructions producing a value system.cpu.iew.wb_consumers 271064264 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.560570 # insts written-back per cycle system.cpu.iew.wb_fanout 0.713979 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34241397 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34241399 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1196652 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149606522 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 149606500 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.664754 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.996488 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 55299818 36.96% 36.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 55299795 36.96% 36.96% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 22506360 15.04% 52.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13038976 8.72% 60.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11456394 7.66% 68.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8182427 5.47% 73.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5460458 3.65% 77.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13038980 8.72% 60.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11456393 7.66% 68.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8182424 5.47% 73.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5460459 3.65% 77.50% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 5170598 3.46% 80.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3276425 2.19% 83.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 25215066 16.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3276423 2.19% 83.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 25215068 16.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149606522 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149606500 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -469,12 +454,12 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 25215066 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 25215068 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 557294459 # The number of ROB reads -system.cpu.rob.rob_writes 870687579 # The number of ROB writes -system.cpu.timesIdled 3435 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 193820 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 557294437 # The number of ROB reads +system.cpu.rob.rob_writes 870687583 # The number of ROB writes +system.cpu.timesIdled 3434 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 193842 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated @@ -483,18 +468,18 @@ system.cpu.cpi_total 0.411815 # CP system.cpu.ipc 2.428275 # IPC: Instructions Per Cycle system.cpu.ipc_total 2.428275 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 398027050 # number of integer regfile reads -system.cpu.int_regfile_writes 170092718 # number of integer regfile writes +system.cpu.int_regfile_writes 170092717 # number of integer regfile writes system.cpu.fp_regfile_reads 156507210 # number of floating regfile reads system.cpu.fp_regfile_writes 104024348 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 2144 # number of replacements -system.cpu.icache.tagsinuse 1832.992748 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1832.992783 # Cycle average of tags in use system.cpu.icache.total_refs 50214380 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 4071 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 12334.654876 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1832.992748 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1832.992783 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.895016 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.895016 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 50214380 # number of ReadReq hits @@ -509,12 +494,12 @@ system.cpu.icache.demand_misses::cpu.inst 5477 # n system.cpu.icache.demand_misses::total 5477 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5477 # number of overall misses system.cpu.icache.overall_misses::total 5477 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 242175000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 242175000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 242175000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 242175000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 242175000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 242175000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 242151500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 242151500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 242151500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 242151500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 242151500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 242151500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 50219857 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 50219857 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 50219857 # number of demand (read+write) accesses @@ -527,12 +512,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000109 system.cpu.icache.demand_miss_rate::total 0.000109 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000109 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000109 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44216.724484 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44216.724484 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44216.724484 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44216.724484 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44216.724484 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44216.724484 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44212.433814 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44212.433814 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44212.433814 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44212.433814 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44212.433814 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44212.433814 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 692 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -553,34 +538,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4071 system.cpu.icache.demand_mshr_misses::total 4071 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4071 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4071 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185126500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 185126500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185126500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 185126500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185126500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 185126500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185116500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 185116500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185116500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 185116500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185116500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 185116500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45474.453451 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45474.453451 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45474.453451 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 45474.453451 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45474.453451 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 45474.453451 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45471.997052 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45471.997052 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45471.997052 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 45471.997052 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45471.997052 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 45471.997052 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 4012.712180 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 4012.712247 # Cycle average of tags in use system.cpu.l2cache.total_refs 831 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4852 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.171270 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 372.528713 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2978.555345 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 661.628123 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 372.528715 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2978.555395 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 661.628136 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.011369 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.090898 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.020191 # Average percentage of cache occupancy @@ -609,17 +594,17 @@ system.cpu.l2cache.demand_misses::total 7448 # nu system.cpu.l2cache.overall_misses::cpu.inst 3455 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3993 # number of overall misses system.cpu.l2cache.overall_misses::total 7448 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 174877500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51530000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 226407500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163360500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 163360500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 174877500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 214890500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 389768000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 174877500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 214890500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 389768000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 174867500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51533000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 226400500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163361000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 163361000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 174867500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 214894000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 389761500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 174867500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 214894000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 389761500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4071 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 990 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5061 # number of ReadReq accesses(hits+misses) @@ -644,17 +629,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.902460 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.848686 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.954806 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.902460 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50615.774240 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59849.012776 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52457.715477 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52158.524904 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52158.524904 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50615.774240 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53816.804408 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52331.901182 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50615.774240 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53816.804408 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52331.901182 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50612.879884 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59852.497096 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52456.093605 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52158.684547 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52158.684547 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50612.879884 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53817.680942 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52331.028464 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50612.879884 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53817.680942 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52331.028464 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -674,17 +659,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7448 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3455 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3993 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7448 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 131818904 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40942458 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 172761362 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 125001233 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 125001233 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131818904 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 165943691 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 297762595 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131818904 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 165943691 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 297762595 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 131805705 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40944982 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 172750687 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 124998745 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 124998745 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131805705 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 165943727 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 297749432 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131805705 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 165943727 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 297749432 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.848686 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869697 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.852796 # mshr miss rate for ReadReq accesses @@ -696,37 +681,37 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.902460 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.848686 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954806 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.902460 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38153.083647 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47552.216028 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40028.119092 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39910.993934 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39910.993934 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38153.083647 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41558.650388 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39978.866139 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38153.083647 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41558.650388 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39978.866139 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38149.263386 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47555.147503 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40025.645737 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39910.199553 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39910.199553 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38149.263386 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41558.659404 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39977.098818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38149.263386 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41558.659404 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39977.098818 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 780 # number of replacements -system.cpu.dcache.tagsinuse 3297.047040 # Cycle average of tags in use -system.cpu.dcache.total_refs 159960718 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3297.047136 # Cycle average of tags in use +system.cpu.dcache.total_refs 159960719 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38249.813008 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 38249.813247 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3297.047040 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 3297.047136 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.804943 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.804943 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 86459752 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86459752 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 86459753 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86459753 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73500960 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 73500960 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 159960712 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 159960712 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 159960712 # number of overall hits -system.cpu.dcache.overall_hits::total 159960712 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 159960713 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 159960713 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 159960713 # number of overall hits +system.cpu.dcache.overall_hits::total 159960713 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1811 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1811 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 19769 # number of WriteReq misses @@ -735,24 +720,24 @@ system.cpu.dcache.demand_misses::cpu.data 21580 # n system.cpu.dcache.demand_misses::total 21580 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 21580 # number of overall misses system.cpu.dcache.overall_misses::total 21580 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 89987500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 89987500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 779488110 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 779488110 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 869475610 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 869475610 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 869475610 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 869475610 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86461563 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86461563 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 89990500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 89990500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 779566610 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 779566610 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 869557110 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 869557110 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 869557110 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 869557110 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86461564 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86461564 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 159982292 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 159982292 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 159982292 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 159982292 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 159982293 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 159982293 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 159982293 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 159982293 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses @@ -761,19 +746,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000135 system.cpu.dcache.demand_miss_rate::total 0.000135 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000135 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000135 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49689.398123 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49689.398123 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39429.819920 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39429.819920 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40290.806766 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40290.806766 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40290.806766 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40290.806766 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28165 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49691.054666 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49691.054666 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39433.790784 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39433.790784 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40294.583411 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40294.583411 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40294.583411 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40294.583411 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28158 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 631 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.635499 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.624406 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -795,14 +780,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4182 system.cpu.dcache.demand_mshr_misses::total 4182 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4182 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4182 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53863000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 53863000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167256500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 167256500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 221119500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 221119500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221119500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 221119500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53866000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 53866000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167257000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 167257000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 221123000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 221123000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221123000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 221123000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -811,14 +796,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54407.070707 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54407.070707 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52398.652882 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52398.652882 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52874.103300 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52874.103300 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52874.103300 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52874.103300 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54410.101010 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54410.101010 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52398.809524 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52398.809524 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52874.940220 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52874.940220 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52874.940220 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52874.940220 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index c2e0aed87..3aa47fab4 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.068358 # Nu sim_ticks 68358106500 # Number of ticks simulated final_tick 68358106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 148173 # Simulator instruction rate (inst/s) -host_op_rate 189432 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37097000 # Simulator tick rate (ticks/s) -host_mem_usage 250340 # Number of bytes of host memory used -host_seconds 1842.69 # Real time elapsed on the host +host_inst_rate 161957 # Simulator instruction rate (inst/s) +host_op_rate 207054 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40547923 # Simulator tick rate (ticks/s) +host_mem_usage 250356 # Number of bytes of host memory used +host_seconds 1685.86 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 193152 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 7278 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 2 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 4253 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 2167 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 597 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 46727256 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 192182256 # Sum of mem lat for all requests +system.physmem.totQLat 46720000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 192175000 # Sum of mem lat for all requests system.physmem.totBusLat 36390000 # Total cycles spent in databus access system.physmem.totBankLat 109065000 # Total cycles spent in bank access -system.physmem.avgQLat 6420.34 # Average queueing delay per request +system.physmem.avgQLat 6419.35 # Average queueing delay per request system.physmem.avgBankLat 14985.57 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26405.92 # Average memory access latency +system.physmem.avgMemAccLat 26404.92 # Average memory access latency system.physmem.avgRdBW 6.81 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.81 # Average consumed read bandwidth in MB/s @@ -584,7 +569,7 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18773.979853 system.cpu.icache.overall_avg_mshr_miss_latency::total 18773.979853 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3956.608159 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3956.608160 # Cycle average of tags in use system.cpu.l2cache.total_refs 13151 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 5398 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.436273 # Average number of references to valid blocks. @@ -702,19 +687,19 @@ system.cpu.l2cache.demand_mshr_misses::total 7278 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3019 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4259 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7278 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115050359 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 62984754 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 178035113 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115047807 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 62983881 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 178031688 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100922692 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100922692 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115050359 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 163907446 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 278957805 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115050359 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 163907446 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 278957805 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100921221 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100921221 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115047807 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 163905102 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 278952909 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115047807 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 163905102 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 278952909 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.815000 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255176 # mshr miss rate for ReadReq accesses @@ -728,19 +713,19 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.356940 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923861 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.356940 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38108.764160 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42934.392638 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39686.828578 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38107.918847 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42933.797546 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39686.065091 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36147.095989 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36147.095989 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36146.569126 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36146.569126 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38107.918847 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38484.409955 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38328.237016 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38107.918847 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38484.409955 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38328.237016 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1413 # number of replacements system.cpu.dcache.tagsinuse 3109.949983 # Cycle average of tags in use diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 5cf480155..c87b3b35f 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.629815 # Number of seconds simulated -sim_ticks 629814900000 # Number of ticks simulated -final_tick 629814900000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.629620 # Number of seconds simulated +sim_ticks 629619966000 # Number of ticks simulated +final_tick 629619966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 180734 # Simulator instruction rate (inst/s) -host_op_rate 180734 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62438874 # Simulator tick rate (ticks/s) -host_mem_usage 248904 # Number of bytes of host memory used -host_seconds 10086.90 # Real time elapsed on the host +host_inst_rate 178339 # Simulator instruction rate (inst/s) +host_op_rate 178339 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61592425 # Simulator tick rate (ticks/s) +host_mem_usage 247872 # Number of bytes of host memory used +host_seconds 10222.36 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 176256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30295232 # Number of bytes read from this memory -system.physmem.bytes_read::total 30471488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 176256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 176256 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 176384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30295936 # Number of bytes read from this memory +system.physmem.bytes_read::total 30472320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176384 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2754 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473363 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476117 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2756 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 473374 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476130 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 279854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48101803 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48381656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 279854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 279854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6799001 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6799001 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6799001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 279854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48101803 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55180657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476117 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 280144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48117813 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48397957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 280144 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 280144 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6801106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6801106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6801106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 280144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48117813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55199063 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476130 # Total number of read requests seen system.physmem.writeReqs 66908 # Total number of write requests seen -system.physmem.cpureqs 543025 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30471488 # Total number of bytes read from memory +system.physmem.cpureqs 543038 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30472320 # Total number of bytes read from memory system.physmem.bytesWritten 4282112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30471488 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30472320 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 84 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29663 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29645 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 29664 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29737 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29644 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 29657 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29698 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29699 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 29716 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 29817 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29814 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29793 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29817 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29794 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 29811 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29703 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 29776 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29780 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29752 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29783 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29754 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 29855 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 29819 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 4150 # Track writes on a per bank basis @@ -77,38 +77,25 @@ system.physmem.perBankWrReqs::14 4205 # Tr system.physmem.perBankWrReqs::15 4210 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 629814837500 # Total gap between requests +system.physmem.totGap 629619903500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 476117 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 66908 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 406568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66991 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 165 # What read queue length does an incoming req see +system.physmem.readPktSize::6 476130 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 66908 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 406575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66997 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 167 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -137,7 +124,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 2899 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2909 # What write queue length does an incoming req see @@ -170,57 +156,56 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2509077325 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 20518523575 # Sum of mem lat for all requests -system.physmem.totBusLat 2380165000 # Total cycles spent in databus access -system.physmem.totBankLat 15629281250 # Total cycles spent in bank access -system.physmem.avgQLat 5270.81 # Average queueing delay per request -system.physmem.avgBankLat 32832.35 # Average bank access latency per request +system.physmem.totQLat 2394780250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 20405886500 # Sum of mem lat for all requests +system.physmem.totBusLat 2380230000 # Total cycles spent in databus access +system.physmem.totBankLat 15630876250 # Total cycles spent in bank access +system.physmem.avgQLat 5030.56 # Average queueing delay per request +system.physmem.avgBankLat 32834.80 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43103.15 # Average memory access latency -system.physmem.avgRdBW 48.38 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 42865.37 # Average memory access latency +system.physmem.avgRdBW 48.40 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 6.80 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 48.38 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 48.40 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 6.80 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.43 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time system.physmem.avgWrQLen 11.00 # Average write queue length over time -system.physmem.readRowHits 143855 # Number of row buffer hits during reads +system.physmem.readRowHits 143857 # Number of row buffer hits during reads system.physmem.writeRowHits 46184 # Number of row buffer hits during writes system.physmem.readRowHitRate 30.22 # Row buffer hit rate for reads system.physmem.writeRowHitRate 69.03 # Row buffer hit rate for writes -system.physmem.avgGap 1159826.60 # Average gap between requests -system.cpu.branchPred.lookups 389306486 # Number of BP lookups -system.cpu.branchPred.condPredicted 255918117 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 25837227 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 318716729 # Number of BTB lookups -system.cpu.branchPred.BTBHits 258426851 # Number of BTB hits +system.physmem.avgGap 1159439.86 # Average gap between requests +system.cpu.branchPred.lookups 389447649 # Number of BP lookups +system.cpu.branchPred.condPredicted 255913711 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 25827412 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 318653162 # Number of BTB lookups +system.cpu.branchPred.BTBHits 258406685 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.083554 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 57314223 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 6830 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.093401 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 57304748 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 7060 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 523161150 # DTB read hits -system.cpu.dtb.read_misses 589917 # DTB read misses +system.cpu.dtb.read_hits 523436365 # DTB read hits +system.cpu.dtb.read_misses 589877 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 523751067 # DTB read accesses -system.cpu.dtb.write_hits 283054328 # DTB write hits -system.cpu.dtb.write_misses 50219 # DTB write misses +system.cpu.dtb.read_accesses 524026242 # DTB read accesses +system.cpu.dtb.write_hits 283043527 # DTB write hits +system.cpu.dtb.write_misses 50254 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 283104547 # DTB write accesses -system.cpu.dtb.data_hits 806215478 # DTB hits -system.cpu.dtb.data_misses 640136 # DTB misses +system.cpu.dtb.write_accesses 283093781 # DTB write accesses +system.cpu.dtb.data_hits 806479892 # DTB hits +system.cpu.dtb.data_misses 640131 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 806855614 # DTB accesses -system.cpu.itb.fetch_hits 394785394 # ITB hits -system.cpu.itb.fetch_misses 699 # ITB misses +system.cpu.dtb.data_accesses 807120023 # DTB accesses +system.cpu.itb.fetch_hits 394546295 # ITB hits +system.cpu.itb.fetch_misses 717 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 394786093 # ITB accesses +system.cpu.itb.fetch_accesses 394547012 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,98 +219,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1259629801 # number of cpu cycles simulated +system.cpu.numCycles 1259239933 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 410360591 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3276218906 # Number of instructions fetch has processed -system.cpu.fetch.Branches 389306486 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 315741074 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 630494032 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 158021665 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 72839727 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 148 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7225 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 64 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 394785394 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10887979 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1245397368 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.630661 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.141486 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 410282333 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3275811622 # Number of instructions fetch has processed +system.cpu.fetch.Branches 389447649 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 315711433 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 630410102 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 157985911 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 72865288 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 149 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7390 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 394546295 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10716533 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1245235231 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.630677 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.141977 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 614903336 49.37% 49.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 57906135 4.65% 54.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43369742 3.48% 57.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71861713 5.77% 63.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 128784934 10.34% 73.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 45918421 3.69% 77.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41219044 3.31% 80.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7530301 0.60% 81.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 233903742 18.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 614825129 49.37% 49.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 58056687 4.66% 54.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43354375 3.48% 57.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71856761 5.77% 63.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 128610709 10.33% 73.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 45745044 3.67% 77.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41218746 3.31% 80.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7546870 0.61% 81.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 234020910 18.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1245397368 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.309064 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.600938 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 438252598 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 59249665 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 607151892 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9059684 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 131683529 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 32106155 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12464 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3195982000 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46456 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 131683529 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 467489876 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 24458626 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 27637 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 586624719 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 35112981 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3097789893 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 99 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 15390 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 28842141 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2055592035 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3582007579 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3461235411 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 120772168 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1245235231 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.309272 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.601420 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 438008414 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 59262942 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 607236165 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9069872 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 131657838 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 32266957 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12470 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3196223031 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46480 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 131657838 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 467254081 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 24463646 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 27494 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 586711565 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 35120607 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3098173488 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 98 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 15446 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 28849573 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2055567023 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3582389843 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3461627532 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 120762311 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 670622965 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4249 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 110 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 109569448 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 744863024 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 351426191 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 68774306 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8838853 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2625568629 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 106 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2161657606 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17941272 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 802459111 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 727402983 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 67 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1245397368 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.735717 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.803838 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 670597953 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4242 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 103 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 109579430 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 745093938 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 351398329 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68579657 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8864385 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2626006003 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 100 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2162044617 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17925122 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 802898808 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 727596475 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1245235231 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.736254 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.804060 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 448194916 35.99% 35.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 197399515 15.85% 51.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 251498314 20.19% 72.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120129049 9.65% 81.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 104781180 8.41% 90.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79785428 6.41% 96.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 24208472 1.94% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17632328 1.42% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1768166 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 447917303 35.97% 35.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 197535103 15.86% 51.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 251432136 20.19% 72.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120080138 9.64% 81.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 104735346 8.41% 90.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79904704 6.42% 96.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 24241740 1.95% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17620604 1.42% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1768157 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1245397368 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1245235231 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1146254 3.12% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1146296 3.12% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available @@ -354,15 +339,15 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 25630359 69.68% 72.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 10007683 27.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 25620524 69.67% 72.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 10007560 27.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1235285403 57.15% 57.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1235570303 57.15% 57.15% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 17096 0.00% 57.15% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27851426 1.29% 58.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27851417 1.29% 58.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 8254694 0.38% 58.82% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 7204648 0.33% 59.15% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.15% # Type of FU issued @@ -388,84 +373,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.15% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.15% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.15% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 589902835 27.29% 86.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 293138748 13.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 590015596 27.29% 86.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 293128107 13.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2161657606 # Type of FU issued -system.cpu.iq.rate 1.716105 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36784296 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017017 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5472336078 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3339899399 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1991115322 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 151102070 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88201964 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 73610146 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2120988960 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 77450190 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62844771 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2162044617 # Type of FU issued +system.cpu.iq.rate 1.716944 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36774380 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017009 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5472922147 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3340796044 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1991352678 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 151101820 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 88182161 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 73610057 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2121366202 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 77450043 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63177927 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 233792998 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 726346 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76067 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 140631295 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 234023912 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1058362 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 75850 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 140603433 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 4418 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2432 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 2424 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 131683529 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10419712 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 524131 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2988971416 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 730880 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 744863024 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 351426191 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 106 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 195253 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 131657838 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10420983 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 524239 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2989422700 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 731121 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 745093938 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 351398329 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 100 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 195339 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 1467 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76067 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 25831488 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 28075 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 25859563 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2067932709 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 523751206 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 93724897 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 75850 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 25820235 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 27779 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25848014 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2068492319 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 524026374 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 93552298 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363402681 # number of nop insts executed -system.cpu.iew.exec_refs 806856273 # number of memory reference insts executed -system.cpu.iew.exec_branches 278042301 # Number of branches executed -system.cpu.iew.exec_stores 283105067 # Number of stores executed -system.cpu.iew.exec_rate 1.641699 # Inst execution rate -system.cpu.iew.wb_sent 2067106315 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2064725468 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1181149065 # num instructions producing a value -system.cpu.iew.wb_consumers 1753530061 # num instructions consuming a value +system.cpu.iew.exec_nop 363416597 # number of nop insts executed +system.cpu.iew.exec_refs 807120680 # number of memory reference insts executed +system.cpu.iew.exec_branches 278196977 # Number of branches executed +system.cpu.iew.exec_stores 283094306 # Number of stores executed +system.cpu.iew.exec_rate 1.642651 # Inst execution rate +system.cpu.iew.wb_sent 2067333908 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2064962735 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1181126750 # num instructions producing a value +system.cpu.iew.wb_consumers 1753498514 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.639153 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.673584 # average fanout of values written-back +system.cpu.iew.wb_rate 1.639849 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.673583 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 963038308 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 963484022 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 25825176 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1113713839 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.803863 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.507965 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 25815357 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1113577393 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.804084 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.508160 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 494406511 44.39% 44.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 228855545 20.55% 64.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119827890 10.76% 75.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 58850017 5.28% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 50714183 4.55% 85.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24146625 2.17% 87.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19124586 1.72% 89.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 16719001 1.50% 90.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101069481 9.07% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 494309525 44.39% 44.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 228815920 20.55% 64.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119838693 10.76% 75.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 58859369 5.29% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 50684004 4.55% 85.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24146580 2.17% 87.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19115188 1.72% 89.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 16708765 1.50% 90.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101099349 9.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1113713839 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1113577393 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,192 +461,192 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 101069481 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 101099349 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3979033860 # The number of ROB reads -system.cpu.rob.rob_writes 6075737407 # The number of ROB writes -system.cpu.timesIdled 331555 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 14232433 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3979313260 # The number of ROB reads +system.cpu.rob.rob_writes 6076602940 # The number of ROB writes +system.cpu.timesIdled 331541 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 14004702 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.690949 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.690949 # CPI: Total CPI of All Threads -system.cpu.ipc 1.447285 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.447285 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2629419671 # number of integer regfile reads -system.cpu.int_regfile_writes 1497304474 # number of integer regfile writes -system.cpu.fp_regfile_reads 78811610 # number of floating regfile reads -system.cpu.fp_regfile_writes 52661263 # number of floating regfile writes +system.cpu.cpi 0.690735 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.690735 # CPI: Total CPI of All Threads +system.cpu.ipc 1.447733 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.447733 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2629807592 # number of integer regfile reads +system.cpu.int_regfile_writes 1497388428 # number of integer regfile writes +system.cpu.fp_regfile_reads 78811502 # number of floating regfile reads +system.cpu.fp_regfile_writes 52661191 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8336 # number of replacements -system.cpu.icache.tagsinuse 1655.843165 # Cycle average of tags in use -system.cpu.icache.total_refs 394772509 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10048 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 39288.665307 # Average number of references to valid blocks. +system.cpu.icache.replacements 8338 # number of replacements +system.cpu.icache.tagsinuse 1655.801182 # Cycle average of tags in use +system.cpu.icache.total_refs 394533427 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10050 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 39257.057413 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1655.843165 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.808517 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.808517 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 394772509 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 394772509 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 394772509 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 394772509 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 394772509 # number of overall hits -system.cpu.icache.overall_hits::total 394772509 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12885 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12885 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12885 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12885 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12885 # number of overall misses -system.cpu.icache.overall_misses::total 12885 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 310466999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 310466999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 310466999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 310466999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 310466999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 310466999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 394785394 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 394785394 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 394785394 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 394785394 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 394785394 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 394785394 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1655.801182 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.808497 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.808497 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 394533427 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 394533427 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 394533427 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 394533427 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 394533427 # number of overall hits +system.cpu.icache.overall_hits::total 394533427 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12868 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12868 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12868 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12868 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12868 # number of overall misses +system.cpu.icache.overall_misses::total 12868 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 310260499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 310260499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 310260499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 310260499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 310260499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 310260499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 394546295 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 394546295 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 394546295 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 394546295 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 394546295 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 394546295 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24095.226931 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24095.226931 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24095.226931 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24095.226931 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24095.226931 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24095.226931 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1110 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24111.011735 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24111.011735 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24111.011735 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24111.011735 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24111.011735 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24111.011735 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1217 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 69.375000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 71.588235 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2836 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2836 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2836 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2836 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2836 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2836 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10049 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10049 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10049 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10049 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10049 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10049 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 233497999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 233497999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 233497999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 233497999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 233497999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 233497999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2817 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2817 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2817 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2817 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2817 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2817 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10051 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10051 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10051 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10051 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10051 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10051 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 233282499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 233282499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 233282499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 233282499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 233282499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 233282499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23235.943776 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23235.943776 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23235.943776 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23235.943776 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23235.943776 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23235.943776 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23209.879514 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23209.879514 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23209.879514 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23209.879514 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23209.879514 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23209.879514 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 443339 # number of replacements -system.cpu.l2cache.tagsinuse 32702.171158 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1090083 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 476075 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.289730 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 443352 # number of replacements +system.cpu.l2cache.tagsinuse 32702.161581 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1090053 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 476088 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.289604 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1306.977523 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 33.798931 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31361.394703 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.039886 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001031 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.957074 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 1307.378151 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 33.870078 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31360.913353 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.039898 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001034 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.957059 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.997991 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 7294 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1053750 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1061044 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1053720 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1061014 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 95989 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 95989 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4788 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4788 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4789 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4789 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 7294 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1058538 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1065832 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1058509 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1065803 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 7294 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1058538 # number of overall hits -system.cpu.l2cache.overall_hits::total 1065832 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2755 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 406509 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 409264 # number of ReadReq misses +system.cpu.l2cache.overall_hits::cpu.data 1058509 # number of overall hits +system.cpu.l2cache.overall_hits::total 1065803 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2757 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 406520 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 409277 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 66854 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66854 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2755 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 473363 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 476118 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2755 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 473363 # number of overall misses -system.cpu.l2cache.overall_misses::total 476118 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 150496500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 27603201000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27753697500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3778888000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3778888000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 150496500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 31382089000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31532585500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 150496500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 31382089000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31532585500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 10049 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1460259 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1470308 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 2757 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 473374 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 476131 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2757 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 473374 # number of overall misses +system.cpu.l2cache.overall_misses::total 476131 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 150279500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 27491647500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27641927000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3779391500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3779391500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 150279500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 31271039000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31421318500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 150279500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 31271039000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31421318500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 10051 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1460240 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1470291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 95989 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 95989 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 71642 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 71642 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 10049 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1531901 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1541950 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 10049 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1531901 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1541950 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.274157 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278381 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.278353 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933168 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.933168 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.274157 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.309004 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.308777 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.274157 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.309004 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.308777 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54626.678766 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67903.050117 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67813.678946 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56524.486194 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56524.486194 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54626.678766 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66296.032854 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66228.509529 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54626.678766 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66296.032854 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66228.509529 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 71643 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 71643 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 10051 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1531883 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1541934 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 10051 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1531883 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1541934 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.274301 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278393 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.278365 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933155 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.933155 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.274301 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.309014 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.308788 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.274301 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.309014 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.308788 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54508.342401 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67626.801879 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67538.432406 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56532.017531 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56532.017531 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54508.342401 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66059.899783 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65993.011377 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54508.342401 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66059.899783 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65993.011377 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -672,178 +657,178 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks system.cpu.l2cache.writebacks::total 66908 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2755 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406509 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 409264 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2757 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406520 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 409277 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66854 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66854 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2755 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 473363 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 476118 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2755 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 473363 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 476118 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 116276173 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22528768631 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22645044804 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2972753104 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2972753104 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116276173 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25501521735 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25617797908 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116276173 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25501521735 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25617797908 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.274157 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278381 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278353 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933168 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933168 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.274157 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309004 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.308777 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.274157 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309004 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.308777 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42205.507441 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55420.098032 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55331.142744 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44466.346127 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44466.346127 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42205.507441 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53873.077818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53805.564814 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42205.507441 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53873.077818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53805.564814 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2757 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 473374 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 476131 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2757 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 473374 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 476131 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 116032718 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22416103108 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22532135826 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2973259427 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2973259427 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116032718 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25389362535 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25505395253 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116032718 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25389362535 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25505395253 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.274301 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278393 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278365 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933155 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933155 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.274301 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309014 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.308788 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.274301 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309014 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.308788 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42086.586144 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55141.452101 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55053.511011 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44473.919691 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44473.919691 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42086.586144 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53634.890245 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53568.020677 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42086.586144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53634.890245 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53568.020677 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1527805 # number of replacements -system.cpu.dcache.tagsinuse 4094.859699 # Cycle average of tags in use -system.cpu.dcache.total_refs 668117069 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1531901 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 436.135931 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 314208000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.859699 # Average occupied blocks per requestor +system.cpu.dcache.replacements 1527787 # number of replacements +system.cpu.dcache.tagsinuse 4094.859370 # Cycle average of tags in use +system.cpu.dcache.total_refs 668059061 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1531883 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 436.103189 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 314057000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.859370 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999722 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999722 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 458383895 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 458383895 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 209733146 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 209733146 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 28 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 28 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 668117041 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 668117041 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 668117041 # number of overall hits -system.cpu.dcache.overall_hits::total 668117041 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1925777 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1925777 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1061750 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1061750 # number of WriteReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 458325911 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 458325911 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 209733124 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 209733124 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 26 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 26 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 668059035 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 668059035 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 668059035 # number of overall hits +system.cpu.dcache.overall_hits::total 668059035 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1925830 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1925830 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1061772 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1061772 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2987527 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2987527 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2987527 # number of overall misses -system.cpu.dcache.overall_misses::total 2987527 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 64904546500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 64904546500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 35420882879 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 35420882879 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 44000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 44000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 100325429379 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 100325429379 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 100325429379 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 100325429379 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 460309672 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 460309672 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2987602 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2987602 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2987602 # number of overall misses +system.cpu.dcache.overall_misses::total 2987602 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 64791591000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 64791591000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 35422596379 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 35422596379 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 44500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 44500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 100214187379 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 100214187379 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 100214187379 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 100214187379 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 460251741 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 460251741 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 29 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 671104568 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 671104568 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 671104568 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 671104568 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 27 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 27 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 671046637 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 671046637 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 671046637 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 671046637 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004184 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004184 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005037 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005037 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034483 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034483 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.037037 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.037037 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.004452 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.004452 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004452 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004452 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33703.043758 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33703.043758 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33360.850369 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33360.850369 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 44000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 44000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33581.430186 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33581.430186 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33581.430186 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33581.430186 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 14466 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33643.463338 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33643.463338 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33361.772941 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33361.772941 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 44500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 44500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33543.352622 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33543.352622 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33543.352622 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33543.352622 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14428 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 113 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 388 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 387 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.283505 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.281654 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 113 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 95989 # number of writebacks system.cpu.dcache.writebacks::total 95989 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465519 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 465519 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990108 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 990108 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1455627 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1455627 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1455627 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1455627 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460258 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460258 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71642 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71642 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465591 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 465591 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990129 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 990129 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1455720 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1455720 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1455720 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1455720 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460239 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460239 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71643 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71643 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1531900 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1531900 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1531900 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1531900 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39601531500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 39601531500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3899018500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3899018500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 42000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 42000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43500550000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 43500550000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43500550000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 43500550000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003172 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003172 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1531882 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1531882 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1531882 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1531882 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39489667000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 39489667000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3899533000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3899533000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 42500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 42500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43389200000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 43389200000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43389200000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 43389200000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003173 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003173 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.034483 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.034483 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.037037 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.037037 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002283 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002283 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27119.544286 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27119.544286 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54423.641160 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54423.641160 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 42000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 42000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28396.468438 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28396.468438 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28396.468438 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28396.468438 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27043.290174 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27043.290174 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54430.062951 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54430.062951 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 42500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 42500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28324.113737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28324.113737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28324.113737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28324.113737 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 2843a5b3f..675c50cd2 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.627778 # Nu sim_ticks 627777658000 # Number of ticks simulated final_tick 627777658000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102547 # Simulator instruction rate (inst/s) -host_op_rate 139655 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46502403 # Simulator tick rate (ticks/s) -host_mem_usage 263380 # Number of bytes of host memory used -host_seconds 13499.90 # Real time elapsed on the host +host_inst_rate 109787 # Simulator instruction rate (inst/s) +host_op_rate 149515 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49785649 # Simulator tick rate (ticks/s) +host_mem_usage 262368 # Number of bytes of host memory used +host_seconds 12609.61 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 154944 # Number of bytes read from this memory @@ -36,13 +36,13 @@ system.physmem.bw_total::cpu.data 48174508 # To system.physmem.bw_total::total 55159809 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 474966 # Total number of read requests seen system.physmem.writeReqs 66098 # Total number of write requests seen -system.physmem.cpureqs 545370 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 545372 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 30397824 # Total number of bytes read from memory system.physmem.bytesWritten 4230272 # Total number of bytes written to memory system.physmem.bytesConsumedRd 30397824 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 160 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4306 # Reqs where no action is needed +system.physmem.neitherReadNorWrite 4308 # Reqs where no action is needed system.physmem.perBankRdReqs::0 29710 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 29703 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 29690 # Track reads on a per bank basis @@ -85,26 +85,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 474966 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 66098 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4306 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 66098 # Categorize write packet sizes system.physmem.rdQLenPdf::0 405913 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 66670 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 2123 # What read queue length does an incoming req see @@ -137,7 +124,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 2873 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3183088396 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 21162955896 # Sum of mem lat for all requests +system.physmem.totQLat 3182824500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 21162788250 # Sum of mem lat for all requests system.physmem.totBusLat 2374030000 # Total cycles spent in databus access -system.physmem.totBankLat 15605837500 # Total cycles spent in bank access -system.physmem.avgQLat 6703.98 # Average queueing delay per request -system.physmem.avgBankLat 32867.82 # Average bank access latency per request +system.physmem.totBankLat 15605933750 # Total cycles spent in bank access +system.physmem.avgQLat 6703.42 # Average queueing delay per request +system.physmem.avgBankLat 32868.02 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 44571.80 # Average memory access latency +system.physmem.avgMemAccLat 44571.44 # Average memory access latency system.physmem.avgRdBW 48.42 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 6.74 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 48.42 # Average consumed read bandwidth in MB/s @@ -192,11 +177,11 @@ system.physmem.writeRowHits 45521 # Nu system.physmem.readRowHitRate 30.19 # Row buffer hit rate for reads system.physmem.writeRowHitRate 68.87 # Row buffer hit rate for writes system.physmem.avgGap 1160264.94 # Average gap between requests -system.cpu.branchPred.lookups 438315949 # Number of BP lookups -system.cpu.branchPred.condPredicted 349727895 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 30635218 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 247833729 # Number of BTB lookups -system.cpu.branchPred.BTBHits 226959272 # Number of BTB hits +system.cpu.branchPred.lookups 438315942 # Number of BP lookups +system.cpu.branchPred.condPredicted 349727890 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 30635219 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 247833723 # Number of BTB lookups +system.cpu.branchPred.BTBHits 226959266 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 91.577233 # BTB Hit Percentage system.cpu.branchPred.usedRAS 52304914 # Number of times the RAS was used to get a target. @@ -247,94 +232,94 @@ system.cpu.workload.num_syscalls 1411 # Nu system.cpu.numCycles 1255555317 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 353470069 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2285596028 # Number of instructions fetch has processed -system.cpu.fetch.Branches 438315949 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 279264186 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 600835407 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 353470076 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2285596018 # Number of instructions fetch has processed +system.cpu.fetch.Branches 438315942 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 279264180 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 600835401 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 157814267 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 132516295 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 132517239 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 11276 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 79 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 333121638 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10719820 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1213960668 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.592464 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 333121635 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10719821 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1213961612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.592462 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.190927 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 613169619 50.51% 50.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42771995 3.52% 54.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 613170569 50.51% 50.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42771992 3.52% 54.03% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 95714848 7.88% 61.92% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 55497081 4.57% 66.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 71974347 5.93% 72.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 42167025 3.47% 75.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30997749 2.55% 78.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 71974346 5.93% 72.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 42167023 3.47% 75.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30997748 2.55% 78.45% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 31607119 2.60% 81.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 230060885 18.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 230060886 18.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1213960668 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1213961612 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.349101 # Number of branch fetches per cycle system.cpu.fetch.rate 1.820387 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 402973564 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105163486 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 561876522 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16833920 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 127113176 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 44705456 # Number of times decode resolved a branch +system.cpu.decode.IdleCycles 402973570 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105164432 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 561876513 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16833922 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 127113175 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 44705454 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 15362 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3047243338 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 3047243320 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 28333 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 127113176 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 438520822 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 34436909 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 439020 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 541081767 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 72368974 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2975054938 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 127113175 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 438520828 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 34437480 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 439400 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 541081761 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 72368968 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2975054899 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 69 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4810929 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 57090218 # Number of times rename has blocked due to LSQ full +system.cpu.rename.IQFullEvents 4810930 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 57090211 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2946030157 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14164065012 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13593632114 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 570432898 # Number of floating rename lookups +system.cpu.rename.RenamedOperands 2946030115 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14164064845 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13593631976 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 570432869 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 952890067 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25235 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 952890025 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25236 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 22720 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 195466607 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 973207419 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 490834558 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 195466614 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 973207403 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 490834559 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 36203648 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 40613994 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2806590548 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.memDep0.conflictingStores 40613980 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2806590515 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 29404 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2437414927 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13391010 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 908731725 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2361150738 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 2437414876 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13391013 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 908731819 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2361150824 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 8020 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1213960668 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.007820 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875088 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1213961612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.007819 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.875089 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 377941740 31.13% 31.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183591562 15.12% 46.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 202672032 16.70% 62.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 169721528 13.98% 76.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 132842997 10.94% 87.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 93759242 7.72% 95.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37926001 3.12% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12454015 1.03% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 377942739 31.13% 31.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183591536 15.12% 46.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 202672014 16.70% 62.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 169721523 13.98% 76.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 132842970 10.94% 87.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 93759245 7.72% 95.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 37926008 3.12% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12454026 1.03% 99.75% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 3051551 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1213960668 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1213961612 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 716787 0.82% 0.82% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 24382 0.03% 0.85% # attempts to use FU when none available @@ -365,12 +350,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55152383 62.89% 63.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55152382 62.89% 63.74% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 31800755 36.26% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1108357182 45.47% 45.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1108357154 45.47% 45.47% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 11223525 0.46% 45.93% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.93% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 45.93% # Type of FU issued @@ -393,90 +378,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.93% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.99% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.99% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5502589 0.23% 46.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5502588 0.23% 46.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23405387 0.96% 47.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23405386 0.96% 47.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 838249114 34.39% 81.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 442425362 18.15% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 838249094 34.39% 81.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 442425361 18.15% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2437414927 # Type of FU issued +system.cpu.iq.FU_type_0::total 2437414876 # Type of FU issued system.cpu.iq.rate 1.941304 # Inst issue rate -system.cpu.iq.fu_busy_cnt 87694307 # FU busy when requested +system.cpu.iq.fu_busy_cnt 87694306 # FU busy when requested system.cpu.iq.fu_busy_rate 0.035978 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6067361460 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3632711634 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2254358298 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 122514379 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82707337 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56439823 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2461788389 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 63320845 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 84306518 # Number of loads that had data forwarded from stores +system.cpu.iq.int_inst_queue_reads 6067362312 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3632711697 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2254358254 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 122514371 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 82707334 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56439819 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2461788341 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63320841 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 84306513 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 341820238 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 8584 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1429957 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 213839261 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 341820222 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8583 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1429956 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 213839262 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 315 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 127113176 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12638060 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1558330 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2806632420 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 127113175 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12638633 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1558332 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2806632387 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 1396294 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 973207419 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 490834558 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 973207403 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 490834559 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 19418 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1554339 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 1554341 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 2519 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1429957 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 32461973 # Number of branches that were predicted taken incorrectly +system.cpu.iew.memOrderViolationEvents 1429956 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 32461974 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 1494406 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 33956379 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2363518803 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 792548176 # Number of load instructions executed +system.cpu.iew.branchMispredicts 33956380 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2363518752 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 792548156 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 73896124 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 12468 # number of nop insts executed -system.cpu.iew.exec_refs 1216269109 # number of memory reference insts executed -system.cpu.iew.exec_branches 322574295 # Number of branches executed -system.cpu.iew.exec_stores 423720933 # Number of stores executed +system.cpu.iew.exec_refs 1216269086 # number of memory reference insts executed +system.cpu.iew.exec_branches 322574286 # Number of branches executed +system.cpu.iew.exec_stores 423720930 # Number of stores executed system.cpu.iew.exec_rate 1.882449 # Inst execution rate -system.cpu.iew.wb_sent 2336489279 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2310798121 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1347631532 # num instructions producing a value -system.cpu.iew.wb_consumers 2523967593 # num instructions consuming a value +system.cpu.iew.wb_sent 2336489228 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2310798073 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1347631579 # num instructions producing a value +system.cpu.iew.wb_consumers 2523967689 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.840459 # insts written-back per cycle system.cpu.iew.wb_fanout 0.533934 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 921296208 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 921296175 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 30621417 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1086847492 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.734683 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.398806 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 30621418 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1086848437 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.734682 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.398805 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 446547765 41.09% 41.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288590720 26.55% 67.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95114963 8.75% 76.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 446548721 41.09% 41.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288590719 26.55% 67.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95114953 8.75% 76.39% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 70229595 6.46% 82.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46461872 4.27% 87.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22187807 2.04% 89.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15847038 1.46% 90.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10983680 1.01% 91.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90884052 8.36% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46461870 4.27% 87.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22187798 2.04% 89.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15847039 1.46% 90.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10983692 1.01% 91.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 90884050 8.36% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1086847492 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1086848437 # Number of insts commited each cycle system.cpu.commit.committedInsts 1384381606 # Number of instructions committed system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -487,12 +472,12 @@ system.cpu.commit.branches 299634395 # Nu system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 90884052 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 90884050 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3802577661 # The number of ROB reads -system.cpu.rob.rob_writes 5740389540 # The number of ROB writes -system.cpu.timesIdled 353175 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 41594649 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3802578575 # The number of ROB reads +system.cpu.rob.rob_writes 5740389473 # The number of ROB writes +system.cpu.timesIdled 353174 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 41593705 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384370590 # Number of Instructions Simulated system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated @@ -500,57 +485,57 @@ system.cpu.cpi 0.906950 # CP system.cpu.cpi_total 0.906950 # CPI: Total CPI of All Threads system.cpu.ipc 1.102596 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.102596 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11774707522 # number of integer regfile reads -system.cpu.int_regfile_writes 2226782313 # number of integer regfile writes -system.cpu.fp_regfile_reads 68797358 # number of floating regfile reads -system.cpu.fp_regfile_writes 49551948 # number of floating regfile writes -system.cpu.misc_regfile_reads 1364040381 # number of misc regfile reads +system.cpu.int_regfile_reads 11774707263 # number of integer regfile reads +system.cpu.int_regfile_writes 2226782267 # number of integer regfile writes +system.cpu.fp_regfile_reads 68797357 # number of floating regfile reads +system.cpu.fp_regfile_writes 49551943 # number of floating regfile writes +system.cpu.misc_regfile_reads 1364040345 # number of misc regfile reads system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes system.cpu.icache.replacements 22740 # number of replacements -system.cpu.icache.tagsinuse 1642.119595 # Cycle average of tags in use -system.cpu.icache.total_refs 333085984 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1642.119596 # Cycle average of tags in use +system.cpu.icache.total_refs 333085977 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 24420 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13639.884685 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 13639.884398 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1642.119595 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1642.119596 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.801816 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.801816 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 333090009 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 333090009 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 333090009 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 333090009 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 333090009 # number of overall hits -system.cpu.icache.overall_hits::total 333090009 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 31628 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 31628 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 31628 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 31628 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 31628 # number of overall misses -system.cpu.icache.overall_misses::total 31628 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 481224999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 481224999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 481224999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 481224999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 481224999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 481224999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 333121637 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 333121637 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 333121637 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 333121637 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 333121637 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 333121637 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 333090004 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 333090004 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 333090004 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 333090004 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 333090004 # number of overall hits +system.cpu.icache.overall_hits::total 333090004 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 31630 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 31630 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 31630 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 31630 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 31630 # number of overall misses +system.cpu.icache.overall_misses::total 31630 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 481232999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 481232999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 481232999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 481232999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 481232999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 481232999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 333121634 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 333121634 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 333121634 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 333121634 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 333121634 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 333121634 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000095 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000095 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000095 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000095 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000095 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000095 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15215.157424 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15215.157424 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15215.157424 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15215.157424 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15215.157424 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15215.157424 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15214.448277 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15214.448277 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15214.448277 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15214.448277 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15214.448277 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15214.448277 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 850 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked @@ -565,40 +550,40 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 2899 system.cpu.icache.demand_mshr_hits::total 2899 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 2899 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 2899 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28729 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 28729 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 28729 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 28729 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 28729 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 28729 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 386560499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 386560499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 386560499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 386560499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 386560499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 386560499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28731 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 28731 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 28731 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 28731 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 28731 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 28731 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 386564499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 386564499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 386564499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 386564499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 386564499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 386564499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13455.410874 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13455.410874 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13455.410874 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13455.410874 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13455.410874 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13455.410874 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13454.613449 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13454.613449 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13454.613449 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13454.613449 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13454.613449 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13454.613449 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 442184 # number of replacements -system.cpu.l2cache.tagsinuse 32692.569161 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32692.574562 # Cycle average of tags in use system.cpu.l2cache.total_refs 1110053 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 474931 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.337293 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1286.526974 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 50.225034 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31355.817153 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 1286.532429 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 50.222145 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31355.819987 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.039262 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001533 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.956904 # Average percentage of cache occupancy @@ -621,8 +606,8 @@ system.cpu.l2cache.overall_hits::total 1086653 # nu system.cpu.l2cache.ReadReq_misses::cpu.inst 2425 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 406491 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 408916 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4306 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4306 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 4308 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 4308 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 66075 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66075 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 2425 # number of demand (read+write) misses @@ -632,23 +617,23 @@ system.cpu.l2cache.overall_misses::cpu.inst 2425 # system.cpu.l2cache.overall_misses::cpu.data 472566 # number of overall misses system.cpu.l2cache.overall_misses::total 474991 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 133322500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 28783784000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28917106500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3174044000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3174044000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 28783806000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28917128500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3174251000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3174251000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 133322500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 31957828000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32091150500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 31958057000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32091379500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 133322500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 31957828000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32091150500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 31958057000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32091379500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 24421 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1464706 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1489127 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 96321 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 96321 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4309 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 4309 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4311 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 4311 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 72517 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 72517 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 24421 # number of demand (read+write) accesses @@ -671,16 +656,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099300 system.cpu.l2cache.overall_miss_rate::cpu.data 0.307415 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.304161 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54978.350515 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70810.384486 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70716.495564 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48036.988271 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48036.988271 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70810.438607 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70716.549365 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48040.121075 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48040.121075 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54978.350515 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67626.168620 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67561.596957 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67626.653208 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67562.079071 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54978.350515 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67626.168620 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67561.596957 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67626.653208 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67562.079071 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -703,8 +688,8 @@ system.cpu.l2cache.overall_mshr_hits::total 25 # system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2421 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406470 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 408891 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4306 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 4306 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4308 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 4308 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66075 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66075 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2421 # number of demand (read+write) MSHR misses @@ -713,19 +698,19 @@ system.cpu.l2cache.demand_mshr_misses::total 474966 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2421 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 472545 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 474966 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 103136612 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23729331565 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23832468177 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43064306 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43064306 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2356932012 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2356932012 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 103136612 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26086263577 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26189400189 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 103136612 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26086263577 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26189400189 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 103134689 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23729007693 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23832142382 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43084308 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43084308 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2357071286 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2357071286 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 103134689 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26086078979 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26189213668 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 103134689 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26086078979 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26189213668 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277510 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274584 # mshr miss rate for ReadReq accesses @@ -739,73 +724,73 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.304145 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307402 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.304145 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42600.831062 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58379.047814 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58285.626676 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42600.036762 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58378.251022 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58284.829898 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35670.556368 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35670.556368 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42600.831062 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55203.765942 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55139.526175 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42600.831062 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55203.765942 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55139.526175 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35672.664185 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35672.664185 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42600.036762 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55203.375295 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55139.133471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42600.036762 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55203.375295 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55139.133471 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1533127 # number of replacements system.cpu.dcache.tagsinuse 4094.656080 # Cycle average of tags in use -system.cpu.dcache.total_refs 969988260 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 969988245 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1537223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 631.000356 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 631.000346 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 319304000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 4094.656080 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999672 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999672 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 693861551 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 693861551 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276093814 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276093814 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 693861536 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 693861536 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276093810 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276093810 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9998 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9998 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 969955365 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 969955365 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 969955365 # number of overall hits -system.cpu.dcache.overall_hits::total 969955365 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 969955346 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 969955346 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 969955346 # number of overall hits +system.cpu.dcache.overall_hits::total 969955346 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1953541 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1953541 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 841864 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 841864 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 841868 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 841868 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2795405 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2795405 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2795405 # number of overall misses -system.cpu.dcache.overall_misses::total 2795405 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 66482799000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 66482799000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 39425610969 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 39425610969 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 2795409 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2795409 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2795409 # number of overall misses +system.cpu.dcache.overall_misses::total 2795409 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 66484216000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 66484216000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 39427025969 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 39427025969 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 215500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 215500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 105908409969 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 105908409969 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 105908409969 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 105908409969 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 695815092 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 695815092 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 105911241969 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 105911241969 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 105911241969 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 105911241969 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 695815077 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 695815077 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10001 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10001 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 972750770 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 972750770 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 972750770 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 972750770 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 972750755 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 972750755 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 972750755 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 972750755 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002808 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002808 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003040 # miss rate for WriteReq accesses @@ -816,16 +801,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002874 system.cpu.dcache.demand_miss_rate::total 0.002874 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002874 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002874 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34031.944556 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34031.944556 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46831.330202 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46831.330202 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34032.669906 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34032.669906 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46832.788476 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46832.788476 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71833.333333 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37886.606760 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37886.606760 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37886.606760 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37886.606760 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37887.565637 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37887.565637 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37887.565637 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37887.565637 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 1756 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 747 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 57 # number of cycles access was blocked @@ -838,30 +823,30 @@ system.cpu.dcache.writebacks::writebacks 96321 # nu system.cpu.dcache.writebacks::total 96321 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488834 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 488834 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765039 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 765039 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765041 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 765041 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1253873 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1253873 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1253873 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1253873 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1253875 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1253875 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1253875 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1253875 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464707 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1464707 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76825 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76825 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541532 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541532 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541532 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541532 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40831551000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 40831551000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3409167500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3409167500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44240718500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 44240718500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44240718500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 44240718500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76827 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76827 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541534 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541534 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541534 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541534 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40831573000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 40831573000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3409419500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3409419500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44240992500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 44240992500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44240992500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 44240992500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses @@ -870,14 +855,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27876.941259 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27876.941259 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44375.756590 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44375.756590 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28699.189183 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28699.189183 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28699.189183 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28699.189183 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27876.956279 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27876.956279 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44377.881474 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44377.881474 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28699.329694 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28699.329694 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28699.329694 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28699.329694 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 2f98c15fc..a79a513d0 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.042726 # Nu sim_ticks 42726055500 # Number of ticks simulated final_tick 42726055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 156388 # Simulator instruction rate (inst/s) -host_op_rate 156388 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75637274 # Simulator tick rate (ticks/s) -host_mem_usage 259292 # Number of bytes of host memory used -host_seconds 564.88 # Real time elapsed on the host +host_inst_rate 89848 # Simulator instruction rate (inst/s) +host_op_rate 89848 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43455006 # Simulator tick rate (ticks/s) +host_mem_usage 257260 # Number of bytes of host memory used +host_seconds 983.23 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 454848 # Number of bytes read from this memory @@ -85,30 +85,17 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 165519 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 114011 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 62480 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 76428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7913 # What read queue length does an incoming req see +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 113997 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 62479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 76432 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18692 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7912 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -137,9 +124,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 2065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3856 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 4866 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4917 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 4945 # What write queue length does an incoming req see @@ -162,7 +148,7 @@ system.physmem.wrQLenPdf::20 4956 # Wh system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 2892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1101 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 91 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 40 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 1 # Wh system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 7053628221 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9647149471 # Sum of mem lat for all requests +system.physmem.totQLat 7053839750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9647402250 # Sum of mem lat for all requests system.physmem.totBusLat 827595000 # Total cycles spent in databus access -system.physmem.totBankLat 1765926250 # Total cycles spent in bank access -system.physmem.avgQLat 42615.22 # Average queueing delay per request -system.physmem.avgBankLat 10669.02 # Average bank access latency per request +system.physmem.totBankLat 1765967500 # Total cycles spent in bank access +system.physmem.avgQLat 42616.50 # Average queueing delay per request +system.physmem.avgBankLat 10669.27 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 58284.24 # Average memory access latency +system.physmem.avgMemAccLat 58285.77 # Average memory access latency system.physmem.avgRdBW 247.93 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 170.76 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 247.93 # Average consumed read bandwidth in MB/s @@ -188,7 +173,7 @@ system.physmem.busUtil 3.27 # Da system.physmem.avgRdQLen 0.23 # Average read queue length over time system.physmem.avgWrQLen 10.42 # Average write queue length over time system.physmem.readRowHits 148856 # Number of row buffer hits during reads -system.physmem.writeRowHits 71620 # Number of row buffer hits during writes +system.physmem.writeRowHits 71619 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.93 # Row buffer hit rate for reads system.physmem.writeRowHitRate 62.83 # Row buffer hit rate for writes system.physmem.avgGap 152857.21 # Average gap between requests @@ -256,9 +241,9 @@ system.cpu.execution_unit.executions 44777871 # Nu system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77185122 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77185132 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 229327 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 229329 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 15874710 # Number of cycles cpu's stages were not processed system.cpu.runCycles 69577402 # Number of cycles cpu stages are processed. system.cpu.activity 81.422683 # Percentage of cycles cpu is active @@ -295,12 +280,12 @@ system.cpu.stage4.idleCycles 39402909 # Nu system.cpu.stage4.runCycles 46049203 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 53.888900 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 84308 # number of replacements -system.cpu.icache.tagsinuse 1908.296965 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1908.296945 # Cycle average of tags in use system.cpu.icache.total_refs 12251160 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 86354 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 141.871367 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1908.296965 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1908.296945 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.931786 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.931786 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 12251160 # number of ReadReq hits @@ -315,12 +300,12 @@ system.cpu.icache.demand_misses::cpu.inst 117106 # n system.cpu.icache.demand_misses::total 117106 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 117106 # number of overall misses system.cpu.icache.overall_misses::total 117106 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1888398500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1888398500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1888398500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1888398500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1888398500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1888398500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1889037500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1889037500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1889037500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1889037500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1889037500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1889037500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 12368266 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 12368266 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 12368266 # number of demand (read+write) accesses @@ -333,12 +318,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.009468 system.cpu.icache.demand_miss_rate::total 0.009468 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.009468 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.009468 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16125.548648 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16125.548648 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16125.548648 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16125.548648 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16125.548648 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16125.548648 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16131.005243 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16131.005243 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16131.005243 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16131.005243 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16131.005243 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16131.005243 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 271 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 28 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked @@ -359,34 +344,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 86354 system.cpu.icache.demand_mshr_misses::total 86354 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 86354 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 86354 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1336296000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1336296000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1336296000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1336296000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1336296000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1336296000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1336921000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1336921000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1336921000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1336921000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1336921000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1336921000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006982 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.006982 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.006982 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15474.627695 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15474.627695 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15474.627695 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15474.627695 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15474.627695 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15474.627695 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15481.865345 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15481.865345 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15481.865345 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15481.865345 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15481.865345 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15481.865345 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 131595 # number of replacements -system.cpu.l2cache.tagsinuse 30966.013927 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 30966.013370 # Cycle average of tags in use system.cpu.l2cache.total_refs 151363 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 163654 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.924896 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 27281.106507 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2018.513793 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1666.393626 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 27281.106918 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2018.513701 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1666.392751 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.832553 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.061600 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.050854 # Average percentage of cache occupancy @@ -415,17 +400,17 @@ system.cpu.l2cache.demand_misses::total 165519 # nu system.cpu.l2cache.overall_misses::cpu.inst 7107 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 158412 # number of overall misses system.cpu.l2cache.overall_misses::total 165519 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 454675000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1513576000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1968251000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11996247000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11996247000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 454675000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13509823000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13964498000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 454675000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13509823000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13964498000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 455300000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1513155000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1968455000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11996427000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 11996427000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 455300000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13509582000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13964882000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 455300000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13509582000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13964882000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 86354 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60575 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 146929 # number of ReadReq accesses(hits+misses) @@ -450,17 +435,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.569383 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082301 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.775218 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.569383 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 63975.657802 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54997.129465 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 56839.869470 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91650.663529 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91650.663529 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 63975.657802 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85282.825796 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84367.945674 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 63975.657802 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85282.825796 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84367.945674 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 64063.599268 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54981.832056 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 56845.760656 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91652.038719 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91652.038719 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 64063.599268 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85281.304447 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84370.265649 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 64063.599268 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85281.304447 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84370.265649 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,17 +467,17 @@ system.cpu.l2cache.demand_mshr_misses::total 165519 system.cpu.l2cache.overall_mshr_misses::cpu.inst 7107 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 165519 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 366278633 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1171229430 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1537508063 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10407065579 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10407065579 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 366278633 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11578295009 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11944573642 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 366278633 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11578295009 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11944573642 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 366897656 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1170781845 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1537679501 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10407190958 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10407190958 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 366897656 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11577972803 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11944870459 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 366897656 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11577972803 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11944870459 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454329 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235678 # mshr miss rate for ReadReq accesses @@ -504,17 +489,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.569383 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775218 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.569383 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51537.728015 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42557.662512 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44400.718003 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79509.405375 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79509.405375 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51537.728015 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73089.759671 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72164.365674 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51537.728015 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73089.759671 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72164.365674 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51624.828479 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42541.399113 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44405.668852 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79510.363264 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79510.363264 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51624.828479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73087.725696 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72166.158924 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51624.828479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73087.725696 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72166.158924 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200249 # number of replacements system.cpu.dcache.tagsinuse 4078.188712 # Cycle average of tags in use @@ -541,14 +526,14 @@ system.cpu.dcache.demand_misses::cpu.data 1135133 # n system.cpu.dcache.demand_misses::total 1135133 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1135133 # number of overall misses system.cpu.dcache.overall_misses::total 1135133 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3868219500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3868219500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 76703201000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 76703201000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 80571420500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 80571420500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 80571420500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 80571420500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3867683500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3867683500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 76704328000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 76704328000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 80572011500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 80572011500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 80572011500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 80572011500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -565,19 +550,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40139.666283 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40139.666283 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73840.834877 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73840.834877 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70979.718236 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70979.718236 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 70979.718236 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 70979.718236 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5030029 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40134.104328 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40134.104328 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73841.919820 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73841.919820 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70980.238879 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70980.238879 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70980.238879 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70980.238879 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5030125 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 519 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 116378 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.221477 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.222301 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 519 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -599,14 +584,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204345 system.cpu.dcache.demand_mshr_misses::total 204345 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204345 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204345 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1908697000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1908697000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12268407000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12268407000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14177104000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14177104000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14177104000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14177104000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1908276000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1908276000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12268587000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12268587000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14176863000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14176863000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14176863000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14176863000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -615,14 +600,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31411.124825 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31411.124825 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85446.489762 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85446.489762 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69378.276934 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 69378.276934 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69378.276934 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 69378.276934 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31404.196495 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31404.196495 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85447.743418 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85447.743418 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69377.097556 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 69377.097556 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69377.097556 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 69377.097556 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 2c49ec916..74c8f08b1 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,116 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023883 # Number of seconds simulated -sim_ticks 23882696000 # Number of ticks simulated -final_tick 23882696000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023888 # Number of seconds simulated +sim_ticks 23888231000 # Number of ticks simulated +final_tick 23888231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 224964 # Simulator instruction rate (inst/s) -host_op_rate 224964 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67503934 # Simulator tick rate (ticks/s) -host_mem_usage 262380 # Number of bytes of host memory used -host_seconds 353.80 # Real time elapsed on the host +host_inst_rate 143918 # Simulator instruction rate (inst/s) +host_op_rate 143918 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43194720 # Simulator tick rate (ticks/s) +host_mem_usage 260336 # Number of bytes of host memory used +host_seconds 553.04 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 490816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10154176 # Number of bytes read from this memory -system.physmem.bytes_read::total 10644992 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 490816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 490816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7297024 # Number of bytes written to this memory -system.physmem.bytes_written::total 7297024 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7669 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158659 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166328 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114016 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114016 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 20551114 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 425168750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 445719863 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 20551114 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 20551114 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 305536025 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 305536025 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 305536025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 20551114 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 425168750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 751255888 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166328 # Total number of read requests seen -system.physmem.writeReqs 114016 # Total number of write requests seen -system.physmem.cpureqs 280344 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10644992 # Total number of bytes read from memory -system.physmem.bytesWritten 7297024 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10644992 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7297024 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 490944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10154112 # Number of bytes read from this memory +system.physmem.bytes_read::total 10645056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 490944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 490944 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7296832 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296832 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7671 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158658 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166329 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114013 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114013 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 20551710 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 425067557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 445619267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 20551710 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 20551710 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 305457194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 305457194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 305457194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 20551710 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 425067557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 751076461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166329 # Total number of read requests seen +system.physmem.writeReqs 114013 # Total number of write requests seen +system.physmem.cpureqs 280342 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10645056 # Total number of bytes read from memory +system.physmem.bytesWritten 7296832 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 10645056 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7296832 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 4 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 10650 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10530 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10319 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10261 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10573 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10797 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10412 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10353 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10494 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10479 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10254 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10521 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10326 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10267 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10582 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10798 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10408 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10348 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10490 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10474 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10257 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 9973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10566 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10395 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10156 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10115 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10565 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 10397 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10153 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10116 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 7374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7243 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7242 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 6949 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6836 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7243 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6837 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7244 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 7385 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7027 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7026 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 7008 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 7264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7155 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 7041 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 6935 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7275 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7274 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 7040 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 6989 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23882663000 # Total gap between requests +system.physmem.totGap 23888198000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 166328 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 114016 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 67939 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63061 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 27665 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7639 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.readPktSize::6 166329 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 114013 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 67947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 27555 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7700 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -137,15 +124,14 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4946 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4957 # What write queue length does an incoming req see @@ -161,66 +147,65 @@ system.physmem.wrQLenPdf::19 4957 # Wh system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 7244561154 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9788827404 # Sum of mem lat for all requests -system.physmem.totBusLat 831635000 # Total cycles spent in databus access -system.physmem.totBankLat 1712631250 # Total cycles spent in bank access -system.physmem.avgQLat 43556.13 # Average queueing delay per request -system.physmem.avgBankLat 10296.77 # Average bank access latency per request +system.physmem.totQLat 7273642250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9818352250 # Sum of mem lat for all requests +system.physmem.totBusLat 831625000 # Total cycles spent in databus access +system.physmem.totBankLat 1713085000 # Total cycles spent in bank access +system.physmem.avgQLat 43731.50 # Average queueing delay per request +system.physmem.avgBankLat 10299.62 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 58852.91 # Average memory access latency -system.physmem.avgRdBW 445.72 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 305.54 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 445.72 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 305.54 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 59031.13 # Average memory access latency +system.physmem.avgRdBW 445.62 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 305.46 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 445.62 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 305.46 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 5.87 # Data bus utilization in percentage system.physmem.avgRdQLen 0.41 # Average read queue length over time -system.physmem.avgWrQLen 10.04 # Average write queue length over time -system.physmem.readRowHits 149202 # Number of row buffer hits during reads -system.physmem.writeRowHits 70865 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.70 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.15 # Row buffer hit rate for writes -system.physmem.avgGap 85190.56 # Average gap between requests -system.cpu.branchPred.lookups 16542352 # Number of BP lookups -system.cpu.branchPred.condPredicted 10681130 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 417709 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11519084 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7344749 # Number of BTB hits +system.physmem.avgWrQLen 10.09 # Average write queue length over time +system.physmem.readRowHits 149212 # Number of row buffer hits during reads +system.physmem.writeRowHits 70966 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.24 # Row buffer hit rate for writes +system.physmem.avgGap 85210.91 # Average gap between requests +system.cpu.branchPred.lookups 16542734 # Number of BP lookups +system.cpu.branchPred.condPredicted 10685518 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 416834 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11542683 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7340422 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 63.761572 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1990053 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 40943 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 63.593724 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1986948 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 41598 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22396635 # DTB read hits -system.cpu.dtb.read_misses 219070 # DTB read misses -system.cpu.dtb.read_acv 53 # DTB read access violations -system.cpu.dtb.read_accesses 22615705 # DTB read accesses -system.cpu.dtb.write_hits 15704107 # DTB write hits -system.cpu.dtb.write_misses 40999 # DTB write misses -system.cpu.dtb.write_acv 6 # DTB write access violations -system.cpu.dtb.write_accesses 15745106 # DTB write accesses -system.cpu.dtb.data_hits 38100742 # DTB hits -system.cpu.dtb.data_misses 260069 # DTB misses -system.cpu.dtb.data_acv 59 # DTB access violations -system.cpu.dtb.data_accesses 38360811 # DTB accesses -system.cpu.itb.fetch_hits 13916224 # ITB hits -system.cpu.itb.fetch_misses 34938 # ITB misses +system.cpu.dtb.read_hits 22395624 # DTB read hits +system.cpu.dtb.read_misses 219289 # DTB read misses +system.cpu.dtb.read_acv 61 # DTB read access violations +system.cpu.dtb.read_accesses 22614913 # DTB read accesses +system.cpu.dtb.write_hits 15707380 # DTB write hits +system.cpu.dtb.write_misses 41224 # DTB write misses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_accesses 15748604 # DTB write accesses +system.cpu.dtb.data_hits 38103004 # DTB hits +system.cpu.dtb.data_misses 260513 # DTB misses +system.cpu.dtb.data_acv 62 # DTB access violations +system.cpu.dtb.data_accesses 38363517 # DTB accesses +system.cpu.itb.fetch_hits 13912342 # ITB hits +system.cpu.itb.fetch_misses 34675 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13951162 # ITB accesses +system.cpu.itb.fetch_accesses 13947017 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,238 +219,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 47765395 # number of cpu cycles simulated +system.cpu.numCycles 47776465 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15792461 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105331722 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16542352 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9334802 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19546012 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2000871 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 6407929 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 309888 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13916224 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 206477 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43516697 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.420490 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.137268 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15792140 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105356372 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16542734 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9327370 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19544101 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1999173 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 6408053 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7580 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 309115 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13912342 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 209427 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43512690 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.421279 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.137905 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23970685 55.08% 55.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1532413 3.52% 58.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1373284 3.16% 61.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1510754 3.47% 65.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4137026 9.51% 74.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1849440 4.25% 78.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 675147 1.55% 80.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1069291 2.46% 83.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7398657 17.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23968589 55.08% 55.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1529417 3.51% 58.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1370330 3.15% 61.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1513065 3.48% 65.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4135878 9.50% 74.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1846880 4.24% 78.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 674126 1.55% 80.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1070808 2.46% 82.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7403597 17.01% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43516697 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.346325 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.205189 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16865376 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5950414 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18541793 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 811002 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1348112 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3746218 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 106835 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103623462 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 302130 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1348112 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17322335 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3664232 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 84922 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18847631 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2249465 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102361026 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 441 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2593 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2123305 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61634933 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123335826 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122884489 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 451337 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43512690 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.346253 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.205194 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16866618 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5950644 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18537765 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 810794 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1346869 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3745393 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 107096 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103623154 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 304519 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1346869 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17322284 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3660735 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 85948 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18844978 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2251876 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102372237 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 493 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2675 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2125269 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61644392 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123362389 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122911717 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 450672 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9088052 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5535 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5532 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4634659 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23233430 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16268738 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1206800 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 454955 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90740192 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5270 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88424187 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 96369 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10688335 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4670210 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 687 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43516697 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.031960 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.108941 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9097511 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5543 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5541 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4645908 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23234130 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16272775 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1204976 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 463178 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90743430 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5284 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88424765 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 96747 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10698511 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4674782 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 701 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43512690 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.032160 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.108847 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15243033 35.03% 35.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6914940 15.89% 50.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5620995 12.92% 63.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4761900 10.94% 74.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4675938 10.75% 85.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2651856 6.09% 91.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1932644 4.44% 96.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1300467 2.99% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 414924 0.95% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15237669 35.02% 35.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6914925 15.89% 50.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5623850 12.92% 63.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4759728 10.94% 74.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4676300 10.75% 85.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2652660 6.10% 91.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1932814 4.44% 96.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1300380 2.99% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 414364 0.95% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43516697 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43512690 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 125783 6.76% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 785729 42.22% 48.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 949726 51.03% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 125555 6.75% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 785994 42.27% 49.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 947743 50.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49355625 55.82% 55.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43814 0.05% 55.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49355125 55.82% 55.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43912 0.05% 55.87% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121422 0.14% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121345 0.14% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 53 0.00% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38953 0.04% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22849621 25.84% 82.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15893267 17.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121242 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 91 0.00% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121107 0.14% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38943 0.04% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22848081 25.84% 82.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15896208 17.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88424187 # Type of FU issued -system.cpu.iq.rate 1.851219 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1861238 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021049 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 221719097 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101035757 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86539045 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 603581 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 415879 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294278 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 89983556 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 301869 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1467344 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88424765 # Type of FU issued +system.cpu.iq.rate 1.850802 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1859292 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021027 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 221714954 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101050466 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86544122 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 603305 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 414877 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294005 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 89982323 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 301734 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1469012 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2956792 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4757 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18083 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1655361 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2957492 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4689 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18546 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1659398 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2846 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 90923 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2825 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 92449 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1348112 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2689881 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 74163 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100228982 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 217751 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23233430 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16268738 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5270 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 60091 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 514 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18083 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 196583 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 160586 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 357169 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87578672 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22618883 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 845515 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1346869 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2686448 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 74137 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100230193 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 219543 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23234130 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16272775 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5284 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 60080 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 507 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18546 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 196235 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 160668 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 356903 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87583307 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22618160 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 841458 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9483520 # number of nop insts executed -system.cpu.iew.exec_refs 38364354 # number of memory reference insts executed -system.cpu.iew.exec_branches 15084185 # Number of branches executed -system.cpu.iew.exec_stores 15745471 # Number of stores executed -system.cpu.iew.exec_rate 1.833517 # Inst execution rate -system.cpu.iew.wb_sent 87223381 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86833323 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33358386 # num instructions producing a value -system.cpu.iew.wb_consumers 43765374 # num instructions consuming a value +system.cpu.iew.exec_nop 9481479 # number of nop insts executed +system.cpu.iew.exec_refs 38367101 # number of memory reference insts executed +system.cpu.iew.exec_branches 15084952 # Number of branches executed +system.cpu.iew.exec_stores 15748941 # Number of stores executed +system.cpu.iew.exec_rate 1.833189 # Inst execution rate +system.cpu.iew.wb_sent 87228229 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86838127 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33365194 # num instructions producing a value +system.cpu.iew.wb_consumers 43783216 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.817913 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762210 # average fanout of values written-back +system.cpu.iew.wb_rate 1.817592 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762054 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8889050 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8889017 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 313123 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42168585 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.094940 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.806680 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 312044 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42165821 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.095078 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.806430 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19301880 45.77% 45.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7026183 16.66% 62.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3423669 8.12% 70.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2056444 4.88% 75.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2047690 4.86% 80.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1162920 2.76% 83.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1093248 2.59% 85.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 719437 1.71% 87.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5337114 12.66% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19296165 45.76% 45.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7025692 16.66% 62.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3426859 8.13% 70.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2055479 4.87% 75.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2052042 4.87% 80.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1160972 2.75% 83.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1093221 2.59% 85.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 720657 1.71% 87.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5334734 12.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42168585 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42165821 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,192 +461,192 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5337114 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5334734 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132743851 # The number of ROB reads -system.cpu.rob.rob_writes 195810249 # The number of ROB writes -system.cpu.timesIdled 70469 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 4248698 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 132743434 # The number of ROB reads +system.cpu.rob.rob_writes 195808907 # The number of ROB writes +system.cpu.timesIdled 70658 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 4263775 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.600130 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.600130 # CPI: Total CPI of All Threads -system.cpu.ipc 1.666306 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.666306 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115907691 # number of integer regfile reads -system.cpu.int_regfile_writes 57507162 # number of integer regfile writes -system.cpu.fp_regfile_reads 249392 # number of floating regfile reads -system.cpu.fp_regfile_writes 240337 # number of floating regfile writes -system.cpu.misc_regfile_reads 38035 # number of misc regfile reads +system.cpu.cpi 0.600269 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.600269 # CPI: Total CPI of All Threads +system.cpu.ipc 1.665920 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.665920 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115915036 # number of integer regfile reads +system.cpu.int_regfile_writes 57508829 # number of integer regfile writes +system.cpu.fp_regfile_reads 249335 # number of floating regfile reads +system.cpu.fp_regfile_writes 239876 # number of floating regfile writes +system.cpu.misc_regfile_reads 38020 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 91216 # number of replacements -system.cpu.icache.tagsinuse 1928.922459 # Cycle average of tags in use -system.cpu.icache.total_refs 13810559 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 93264 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 148.080277 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 19641578000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1928.922459 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.941857 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.941857 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13810559 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13810559 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13810559 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13810559 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13810559 # number of overall hits -system.cpu.icache.overall_hits::total 13810559 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 105664 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 105664 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 105664 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 105664 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 105664 # number of overall misses -system.cpu.icache.overall_misses::total 105664 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1863781999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1863781999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1863781999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1863781999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1863781999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1863781999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13916223 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13916223 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13916223 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13916223 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13916223 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13916223 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007593 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007593 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007593 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007593 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007593 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007593 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17638.760590 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17638.760590 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17638.760590 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17638.760590 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17638.760590 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17638.760590 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1009 # number of cycles access was blocked +system.cpu.icache.replacements 91603 # number of replacements +system.cpu.icache.tagsinuse 1929.170608 # Cycle average of tags in use +system.cpu.icache.total_refs 13806208 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 93651 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 147.421896 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 19644478000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1929.170608 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.941978 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.941978 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13806208 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13806208 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13806208 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13806208 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13806208 # number of overall hits +system.cpu.icache.overall_hits::total 13806208 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 106133 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 106133 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 106133 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 106133 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 106133 # number of overall misses +system.cpu.icache.overall_misses::total 106133 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1879500499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1879500499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1879500499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1879500499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1879500499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1879500499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13912341 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13912341 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13912341 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13912341 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13912341 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13912341 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007629 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007629 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007629 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007629 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007629 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007629 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17708.917104 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17708.917104 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17708.917104 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17708.917104 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17708.917104 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17708.917104 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 329 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 72.071429 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 25.307692 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12399 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12399 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12399 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12399 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12399 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12399 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93265 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 93265 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 93265 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 93265 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 93265 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 93265 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1450659000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1450659000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1450659000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1450659000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1450659000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1450659000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006702 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006702 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006702 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006702 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006702 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006702 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15554.162869 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15554.162869 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15554.162869 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15554.162869 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15554.162869 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15554.162869 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12481 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 12481 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 12481 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 12481 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 12481 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 12481 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93652 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 93652 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 93652 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 93652 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 93652 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 93652 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1448205000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1448205000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1448205000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1448205000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1448205000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1448205000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006732 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006732 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006732 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006732 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006732 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006732 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15463.684705 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15463.684705 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15463.684705 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15463.684705 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15463.684705 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15463.684705 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 132416 # number of replacements -system.cpu.l2cache.tagsinuse 30823.572935 # Cycle average of tags in use -system.cpu.l2cache.total_refs 159534 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 164488 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.969882 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 132413 # number of replacements +system.cpu.l2cache.tagsinuse 30824.130718 # Cycle average of tags in use +system.cpu.l2cache.total_refs 159933 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 164484 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.972332 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26655.364859 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2126.856896 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 2041.351180 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.813457 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.064907 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.062297 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.940661 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 85595 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 34249 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 119844 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168913 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168913 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12619 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12619 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 85595 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46868 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 132463 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 85595 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46868 # number of overall hits -system.cpu.l2cache.overall_hits::total 132463 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 7670 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 27858 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 35528 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130801 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130801 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 7670 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158659 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 166329 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 7670 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158659 # number of overall misses -system.cpu.l2cache.overall_misses::total 166329 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 500468500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1609621000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2110089500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12172380500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12172380500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 500468500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13782001500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14282470000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 500468500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13782001500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14282470000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 93265 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 62107 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 155372 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 168913 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 168913 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143420 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143420 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 93265 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 205527 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 298792 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 93265 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 205527 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 298792 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082239 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448548 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.228664 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912014 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.912014 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082239 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.771962 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.556672 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082239 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.771962 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.556672 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65250.130378 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57779.488836 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 59392.296217 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 93060.301527 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 93060.301527 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65250.130378 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86865.551277 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 85868.790169 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65250.130378 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86865.551277 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 85868.790169 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 26654.476755 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2125.293059 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 2044.360903 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.813430 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.064859 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.062389 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.940678 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 85980 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 34244 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 120224 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 168922 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 168922 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12628 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12628 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 85980 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 46872 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 132852 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 85980 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 46872 # number of overall hits +system.cpu.l2cache.overall_hits::total 132852 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 7672 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 27862 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 35534 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 130796 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 130796 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 7672 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158658 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 166330 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 7672 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158658 # number of overall misses +system.cpu.l2cache.overall_misses::total 166330 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 493837000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1614539500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2108376500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12203454500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12203454500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 493837000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13817994000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14311831000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 493837000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13817994000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14311831000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 93652 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 62106 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 155758 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 168922 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168922 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143424 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143424 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 93652 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 205530 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 299182 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 93652 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 205530 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 299182 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.081920 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448620 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.228136 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911953 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911953 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.081920 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.771946 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.555949 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.081920 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.771946 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.555949 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 64368.743483 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57947.724499 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 59334.060337 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 93301.435059 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 93301.435059 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 64368.743483 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87092.954657 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86044.796489 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 64368.743483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87092.954657 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86044.796489 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -670,164 +655,164 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114016 # number of writebacks -system.cpu.l2cache.writebacks::total 114016 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7670 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27858 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 35528 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130801 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130801 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7670 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158659 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 166329 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7670 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158659 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 166329 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 404789823 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1267031559 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1671821382 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10582502021 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10582502021 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 404789823 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11849533580 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12254323403 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 404789823 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11849533580 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12254323403 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082239 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448548 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228664 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912014 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912014 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082239 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771962 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.556672 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082239 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771962 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.556672 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52775.726597 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45481.784730 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 47056.445114 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80905.360211 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80905.360211 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52775.726597 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74685.543083 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73675.206386 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52775.726597 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74685.543083 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73675.206386 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 114013 # number of writebacks +system.cpu.l2cache.writebacks::total 114013 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7672 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27862 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 35534 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130796 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130796 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7672 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158658 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166330 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7672 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158658 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166330 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 398141894 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1271865950 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1670007844 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10613542919 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10613542919 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 398141894 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11885408869 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12283550763 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 398141894 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11885408869 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12283550763 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081920 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448620 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228136 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911953 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911953 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081920 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771946 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.555949 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081920 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771946 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.555949 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51895.450209 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45648.767138 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46997.462824 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81145.776010 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81145.776010 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51895.450209 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74912.130929 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73850.482553 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51895.450209 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74912.130929 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73850.482553 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201431 # number of replacements -system.cpu.dcache.tagsinuse 4076.502318 # Cycle average of tags in use -system.cpu.dcache.total_refs 34195386 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205527 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 166.379045 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 178801000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.502318 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995240 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995240 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20621336 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20621336 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13573997 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13573997 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 53 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 53 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34195333 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34195333 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34195333 # number of overall hits -system.cpu.dcache.overall_hits::total 34195333 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 266907 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 266907 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1039380 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1039380 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1306287 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1306287 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1306287 # number of overall misses -system.cpu.dcache.overall_misses::total 1306287 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12007604500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12007604500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 79088080451 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 79088080451 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91095684951 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91095684951 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91095684951 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91095684951 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20888243 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20888243 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 201434 # number of replacements +system.cpu.dcache.tagsinuse 4076.506217 # Cycle average of tags in use +system.cpu.dcache.total_refs 34191197 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205530 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 166.356235 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 178802000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.506217 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995241 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995241 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20617082 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20617082 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574055 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574055 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 60 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 60 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34191137 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34191137 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34191137 # number of overall hits +system.cpu.dcache.overall_hits::total 34191137 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 267027 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 267027 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1039322 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1039322 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1306349 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1306349 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1306349 # number of overall misses +system.cpu.dcache.overall_misses::total 1306349 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12066091500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12066091500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 79222219902 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 79222219902 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91288311402 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91288311402 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91288311402 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91288311402 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20884109 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20884109 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 53 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 53 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35501620 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35501620 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35501620 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35501620 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012778 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012778 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071125 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071125 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036795 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036795 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036795 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036795 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44987.971466 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 44987.971466 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76091.593499 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76091.593499 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69736.348100 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69736.348100 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69736.348100 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69736.348100 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4377310 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 60 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 60 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35497486 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35497486 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35497486 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35497486 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012786 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012786 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071121 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071121 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036801 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036801 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036801 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036801 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45186.784482 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 45186.784482 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76224.904218 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76224.904218 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69880.492427 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69880.492427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69880.492427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69880.492427 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4400680 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 119 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 112282 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112252 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 38.984966 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.203578 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 119 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168913 # number of writebacks -system.cpu.dcache.writebacks::total 168913 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204795 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 204795 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895965 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895965 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1100760 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1100760 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1100760 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1100760 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62112 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62112 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143415 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143415 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205527 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205527 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205527 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205527 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2016329500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2016329500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12443477492 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12443477492 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14459806992 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14459806992 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14459806992 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14459806992 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 168922 # number of writebacks +system.cpu.dcache.writebacks::total 168922 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204918 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 204918 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895901 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895901 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1100819 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1100819 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1100819 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1100819 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62109 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62109 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143421 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143421 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205530 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205530 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205530 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205530 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2021126000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2021126000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12474690492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12474690492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14495816492 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14495816492 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14495816492 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14495816492 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002974 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002974 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005789 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005789 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32462.801069 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32462.801069 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86765.523076 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86765.523076 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70354.780598 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70354.780598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70354.780598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70354.780598 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005790 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005790 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005790 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005790 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32541.596226 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32541.596226 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86979.525258 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86979.525258 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70528.956804 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70528.956804 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70528.956804 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70528.956804 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index bdf692e24..bd8287e69 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.025578 # Nu sim_ticks 25577832000 # Number of ticks simulated final_tick 25577832000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 153227 # Simulator instruction rate (inst/s) -host_op_rate 217448 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55271946 # Simulator tick rate (ticks/s) -host_mem_usage 270340 # Number of bytes of host memory used -host_seconds 462.76 # Real time elapsed on the host +host_inst_rate 133487 # Simulator instruction rate (inst/s) +host_op_rate 189436 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48151664 # Simulator tick rate (ticks/s) +host_mem_usage 268312 # Number of bytes of host memory used +host_seconds 531.19 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory @@ -85,29 +85,16 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 128779 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 83944 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 312 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 70134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56500 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2062 # What read queue length does an incoming req see +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 83944 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 70150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56485 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2061 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -137,8 +124,7 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3543 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 3645 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see @@ -161,7 +147,7 @@ system.physmem.wrQLenPdf::19 3649 # Wh system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 107 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3204614448 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 5248634448 # Sum of mem lat for all requests +system.physmem.totQLat 3204596500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 5248699000 # Sum of mem lat for all requests system.physmem.totBusLat 643885000 # Total cycles spent in databus access -system.physmem.totBankLat 1400135000 # Total cycles spent in bank access -system.physmem.avgQLat 24884.99 # Average queueing delay per request -system.physmem.avgBankLat 10872.55 # Average bank access latency per request +system.physmem.totBankLat 1400217500 # Total cycles spent in bank access +system.physmem.avgQLat 24884.85 # Average queueing delay per request +system.physmem.avgBankLat 10873.20 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 40757.55 # Average memory access latency +system.physmem.avgMemAccLat 40758.05 # Average memory access latency system.physmem.avgRdBW 322.23 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 210.04 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 322.23 # Average consumed read bandwidth in MB/s @@ -247,23 +232,23 @@ system.cpu.workload.num_syscalls 1946 # Nu system.cpu.numCycles 51155665 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12532709 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 12532708 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 85214691 # Number of instructions fetch has processed system.cpu.fetch.Branches 16629564 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 9594774 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 21193802 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2370777 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10561174 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 10561405 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 619 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 11680132 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 179650 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46029302 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.592220 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.335381 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 179651 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46029532 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.592208 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.335378 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24855702 54.00% 54.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24855932 54.00% 54.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 2137922 4.64% 58.64% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 1963242 4.27% 62.91% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 2041100 4.43% 67.34% # Number of instructions fetched each cycle (Total) @@ -275,42 +260,42 @@ system.cpu.fetch.rateDist::8 10031713 21.79% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46029302 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 46029532 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.325078 # Number of branch fetches per cycle system.cpu.fetch.rate 1.665792 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14615111 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8910636 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19475070 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1390460 # Number of cycles decode is unblocking +system.cpu.decode.IdleCycles 14615115 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8910863 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19475067 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1390462 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1638025 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 3332403 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 104704 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116875392 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 116875388 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 362618 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 1638025 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16327930 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2553995 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 876400 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19102314 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5530638 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 115006216 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 16327942 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2554176 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 876402 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19102307 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5530680 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 115006208 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 128 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 16441 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4672566 # Number of times rename has blocked due to LSQ full +system.cpu.rename.LSQFullEvents 4672604 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 267 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115315088 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529845526 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529838425 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 115315076 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529845478 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 529838377 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 7101 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16182416 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 16182404 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 20249 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 20243 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13070329 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 13070399 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 29628857 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 22448482 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3867260 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4365711 # Number of conflicting stores. +system.cpu.memDep0.conflictingStores 4365710 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 111562544 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 35868 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 107265054 # Number of instructions issued @@ -318,23 +303,23 @@ system.cpu.iq.iqSquashedInstsIssued 274406 # Nu system.cpu.iq.iqSquashedInstsExamined 10824806 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 25919657 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2082 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46029302 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.330365 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.988633 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 46029532 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.330353 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.988634 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10776543 23.41% 23.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8085599 17.57% 40.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7427656 16.14% 57.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7135117 15.50% 72.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5408591 11.75% 84.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3911102 8.50% 92.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1839411 4.00% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10776737 23.41% 23.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8085644 17.57% 40.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7427640 16.14% 57.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7135127 15.50% 72.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5408613 11.75% 84.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3911083 8.50% 92.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1839405 4.00% 96.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 869812 1.89% 98.75% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 575471 1.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46029302 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46029532 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 112614 4.57% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available @@ -366,7 +351,7 @@ system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # at system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 1347948 54.70% 59.28% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1003479 40.72% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1003472 40.72% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -405,15 +390,15 @@ system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Ty system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 107265054 # Type of FU issued system.cpu.iq.rate 2.096836 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2464043 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022972 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263297262 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 2464036 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022971 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263297485 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 122451085 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105577839 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 105577838 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 597 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 998 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 169 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109728805 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 109728798 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 292 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 2178424 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -427,32 +412,32 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 29 # system.cpu.iew.lsq.thread0.cacheBlocked 510 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1638025 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1048423 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45681 # Number of cycles IEW is unblocking +system.cpu.iew.iewBlockCycles 1048533 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45693 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 111608173 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 293378 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 29628857 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 22448482 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 19948 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6875 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5224 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5227 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 30026 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 391684 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 181878 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 573562 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106234972 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 106234971 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 28603939 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1030082 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 1030083 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9761 # number of nop insts executed system.cpu.iew.exec_refs 49948503 # number of memory reference insts executed system.cpu.iew.exec_branches 14602542 # Number of branches executed system.cpu.iew.exec_stores 21344564 # Number of stores executed system.cpu.iew.exec_rate 2.076700 # Inst execution rate -system.cpu.iew.wb_sent 105797759 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105578008 # cumulative count of insts written-back +system.cpu.iew.wb_sent 105797758 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105578007 # cumulative count of insts written-back system.cpu.iew.wb_producers 53282087 # num instructions producing a value -system.cpu.iew.wb_consumers 103565148 # num instructions consuming a value +system.cpu.iew.wb_consumers 103565099 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.063858 # insts written-back per cycle system.cpu.iew.wb_fanout 0.514479 # average fanout of values written-back @@ -460,23 +445,23 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 10976636 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 500410 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44391277 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.266941 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.764740 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 44391507 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.266930 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.764737 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15317735 34.51% 34.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11646185 26.24% 60.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3462928 7.80% 68.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15317930 34.51% 34.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11646230 26.24% 60.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3462929 7.80% 68.54% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 2873664 6.47% 75.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1875712 4.23% 79.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1949355 4.39% 83.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 685853 1.55% 85.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 564106 1.27% 86.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6015739 13.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1875708 4.23% 79.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1949349 4.39% 83.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 685850 1.55% 85.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 564105 1.27% 86.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6015742 13.55% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44391277 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44391507 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -487,12 +472,12 @@ system.cpu.commit.branches 13741505 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6015739 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6015742 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 149959303 # The number of ROB reads +system.cpu.rob.rob_reads 149959530 # The number of ROB reads system.cpu.rob.rob_writes 224865260 # The number of ROB writes -system.cpu.timesIdled 74068 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5126363 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 74070 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5126133 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated @@ -500,19 +485,19 @@ system.cpu.cpi 0.721441 # CP system.cpu.cpi_total 0.721441 # CPI: Total CPI of All Threads system.cpu.ipc 1.386115 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.386115 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511661177 # number of integer regfile reads -system.cpu.int_regfile_writes 103341315 # number of integer regfile writes +system.cpu.int_regfile_reads 511661173 # number of integer regfile reads +system.cpu.int_regfile_writes 103341311 # number of integer regfile writes system.cpu.fp_regfile_reads 804 # number of floating regfile reads system.cpu.fp_regfile_writes 688 # number of floating regfile writes system.cpu.misc_regfile_reads 49186243 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes system.cpu.icache.replacements 28586 # number of replacements -system.cpu.icache.tagsinuse 1814.278230 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1814.278271 # Cycle average of tags in use system.cpu.icache.total_refs 11645439 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 30619 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 380.333747 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1814.278230 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1814.278271 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.885878 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.885878 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 11645446 # number of ReadReq hits @@ -527,12 +512,12 @@ system.cpu.icache.demand_misses::cpu.inst 34686 # n system.cpu.icache.demand_misses::total 34686 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 34686 # number of overall misses system.cpu.icache.overall_misses::total 34686 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 739119000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 739119000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 739119000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 739119000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 739119000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 739119000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 739337000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 739337000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 739337000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 739337000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 739337000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 739337000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 11680132 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 11680132 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 11680132 # number of demand (read+write) accesses @@ -545,12 +530,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.002970 system.cpu.icache.demand_miss_rate::total 0.002970 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.002970 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.002970 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21308.856599 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21308.856599 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21308.856599 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21308.856599 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21308.856599 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21308.856599 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21315.141556 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21315.141556 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21315.141556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21315.141556 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 761 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked @@ -571,34 +556,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 30945 system.cpu.icache.demand_mshr_misses::total 30945 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 30945 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 30945 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 600341000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 600341000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 600341000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 600341000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 600341000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 600341000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 600567000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 600567000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 600567000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 600567000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 600567000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 600567000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002649 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.002649 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.002649 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19400.258523 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19400.258523 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19400.258523 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19400.258523 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19400.258523 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19400.258523 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19407.561803 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19407.561803 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 95649 # number of replacements -system.cpu.l2cache.tagsinuse 30090.049168 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 30090.044330 # Cycle average of tags in use system.cpu.l2cache.total_refs 88124 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 126758 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.695215 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26935.644891 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1374.538058 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1779.866218 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 26935.640674 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1374.538102 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1779.865554 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.822011 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.041948 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.054317 # Average percentage of cache occupancy @@ -631,19 +616,19 @@ system.cpu.l2cache.demand_misses::total 128855 # nu system.cpu.l2cache.overall_misses::cpu.inst 4676 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124179 # number of overall misses system.cpu.l2cache.overall_misses::total 128855 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 310311500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1482845500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1793157000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 310537500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1482354000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1792891500 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6640773000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6640773000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 310311500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8123618500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8433930000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 310311500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8123618500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8433930000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6641217500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6641217500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 310537500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8123571500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8434109000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 310537500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8123571500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8434109000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 30501 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55382 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 85883 # number of ReadReq accesses(hits+misses) @@ -672,19 +657,19 @@ system.cpu.l2cache.demand_miss_rate::total 0.667902 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.153306 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.764536 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.667902 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66362.596236 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67641.889426 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67416.986240 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66410.928144 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67619.469027 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67407.004286 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 73.717949 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 73.717949 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64941.989301 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64941.989301 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66362.596236 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65418.617480 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65452.873385 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66362.596236 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65418.617480 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65452.873385 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64946.336192 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64946.336192 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65454.262543 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65454.262543 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -717,19 +702,19 @@ system.cpu.l2cache.demand_mshr_misses::total 128779 system.cpu.l2cache.overall_mshr_misses::cpu.inst 4661 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 124118 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 128779 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 251333698 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209966181 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1461299879 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 251555285 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209463318 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1461018603 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3131809 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3131809 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5384861495 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5384861495 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251333698 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6594827676 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6846161374 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251333698 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6594827676 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6846161374 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5385248857 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5385248857 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251555285 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6594712175 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6846267460 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251555285 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6594712175 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6846267460 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394731 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308815 # mshr miss rate for ReadReq accesses @@ -743,61 +728,61 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.667508 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764160 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.667508 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53922.698563 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55348.162527 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55097.650215 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53970.239219 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55325.159782 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55087.044831 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10037.849359 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10037.849359 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52660.077012 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52660.077012 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53922.698563 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53133.531607 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53162.094550 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53922.698563 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53133.531607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53162.094550 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52663.865134 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52663.865134 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 158328 # number of replacements -system.cpu.dcache.tagsinuse 4072.315266 # Cycle average of tags in use -system.cpu.dcache.total_refs 44370475 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4072.315155 # Cycle average of tags in use +system.cpu.dcache.total_refs 44370468 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 162424 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 273.176840 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 273.176797 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 284606000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.315266 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4072.315155 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.994218 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.994218 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26070698 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26070698 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 26070691 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26070691 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18267224 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 18267224 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15981 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15981 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44337922 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44337922 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44337922 # number of overall hits -system.cpu.dcache.overall_hits::total 44337922 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 124470 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 124470 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 44337915 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44337915 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44337915 # number of overall hits +system.cpu.dcache.overall_hits::total 44337915 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 124477 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 124477 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1582677 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1582677 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 45 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 45 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1707147 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1707147 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1707147 # number of overall misses -system.cpu.dcache.overall_misses::total 1707147 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4247957000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4247957000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 98254010480 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 98254010480 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1707154 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1707154 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1707154 # number of overall misses +system.cpu.dcache.overall_misses::total 1707154 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4246899000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4246899000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 98261042480 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 98261042480 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 892500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 892500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102501967480 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102501967480 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102501967480 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102501967480 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102507941480 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102507941480 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102507941480 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102507941480 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 26195168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 26195168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) @@ -820,16 +805,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.037076 system.cpu.dcache.demand_miss_rate::total 0.037076 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.037076 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.037076 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34128.360247 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34128.360247 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62080.898680 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62080.898680 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34117.941467 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34117.941467 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62085.341785 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62085.341785 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19833.333333 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60042.847792 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60042.847792 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60042.847792 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60042.847792 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60046.100984 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60046.100984 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 5655 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 122 # number of cycles access was blocked @@ -840,16 +825,16 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 129109 # number of writebacks system.cpu.dcache.writebacks::total 129109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69057 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69057 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69064 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69064 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475334 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1475334 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 45 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1544391 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1544391 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1544391 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1544391 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1544398 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1544398 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1544398 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1544398 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107343 # number of WriteReq MSHR misses @@ -858,14 +843,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 162756 system.cpu.dcache.demand_mshr_misses::total 162756 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 162756 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 162756 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878248000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878248000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6802862990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6802862990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681110990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8681110990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681110990 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8681110990 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1877758500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1877758500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6803307490 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6803307490 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681065990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8681065990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681065990 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8681065990 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002115 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002115 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses @@ -874,14 +859,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33895.439698 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33895.439698 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63375.003400 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63375.003400 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53338.193308 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53338.193308 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53338.193308 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53338.193308 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33886.606031 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33886.606031 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63379.144332 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63379.144332 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index bbfef95ab..4d872659d 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.993559 # Nu sim_ticks 993559170500 # Number of ticks simulated final_tick 993559170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 148425 # Simulator instruction rate (inst/s) -host_op_rate 148425 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 81036604 # Simulator tick rate (ticks/s) -host_mem_usage 464668 # Number of bytes of host memory used -host_seconds 12260.62 # Real time elapsed on the host +host_inst_rate 139940 # Simulator instruction rate (inst/s) +host_op_rate 139940 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 76403951 # Simulator tick rate (ticks/s) +host_mem_usage 449176 # Number of bytes of host memory used +host_seconds 13004.03 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory @@ -85,30 +85,17 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 1959688 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1018171 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1630106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 205346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 87736 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 35917 # What read queue length does an incoming req see +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 1018058 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1630116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 205318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 87737 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 35934 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -137,9 +124,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 41624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 43771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 43773 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 44240 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44256 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 44259 # What write queue length does an incoming req see @@ -162,7 +148,7 @@ system.physmem.wrQLenPdf::20 44263 # Wh system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 2640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 491 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 5 # Wh system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 35848625999 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 104288840999 # Sum of mem lat for all requests +system.physmem.totQLat 35843451500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 104284202750 # Sum of mem lat for all requests system.physmem.totBusLat 9795530000 # Total cycles spent in databus access -system.physmem.totBankLat 58644685000 # Total cycles spent in bank access -system.physmem.avgQLat 18298.46 # Average queueing delay per request -system.physmem.avgBankLat 29934.41 # Average bank access latency per request +system.physmem.totBankLat 58645221250 # Total cycles spent in bank access +system.physmem.avgQLat 18295.82 # Average queueing delay per request +system.physmem.avgBankLat 29934.69 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 53232.87 # Average memory access latency +system.physmem.avgMemAccLat 53230.51 # Average memory access latency system.physmem.avgRdBW 126.23 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 65.58 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 126.23 # Average consumed read bandwidth in MB/s @@ -187,13 +172,13 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 1.50 # Data bus utilization in percentage system.physmem.avgRdQLen 0.10 # Average read queue length over time system.physmem.avgWrQLen 10.46 # Average write queue length over time -system.physmem.readRowHits 770935 # Number of row buffer hits during reads -system.physmem.writeRowHits 285714 # Number of row buffer hits during writes +system.physmem.readRowHits 770937 # Number of row buffer hits during reads +system.physmem.writeRowHits 285715 # Number of row buffer hits during writes system.physmem.readRowHitRate 39.35 # Row buffer hit rate for reads system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes system.physmem.avgGap 333661.47 # Average gap between requests system.cpu.branchPred.lookups 326540496 # Number of BP lookups -system.cpu.branchPred.condPredicted 252608544 # Number of conditional branches predicted +system.cpu.branchPred.condPredicted 252608543 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 138248451 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 220022753 # Number of BTB lookups system.cpu.branchPred.BTBHits 135563778 # Number of BTB hits @@ -205,22 +190,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444796007 # DTB read hits +system.cpu.dtb.read_hits 444796009 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449693085 # DTB read accesses -system.cpu.dtb.write_hits 160833351 # DTB write hits +system.cpu.dtb.read_accesses 449693087 # DTB read accesses +system.cpu.dtb.write_hits 160833358 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162534655 # DTB write accesses -system.cpu.dtb.data_hits 605629358 # DTB hits +system.cpu.dtb.write_accesses 162534662 # DTB write accesses +system.cpu.dtb.data_hits 605629367 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612227740 # DTB accesses -system.cpu.itb.fetch_hits 232025962 # ITB hits +system.cpu.dtb.data_accesses 612227749 # DTB accesses +system.cpu.itb.fetch_hits 232025963 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 232025984 # ITB accesses +system.cpu.itb.fetch_accesses 232025985 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -237,16 +222,16 @@ system.cpu.workload.num_syscalls 29 # Nu system.cpu.numCycles 1987118342 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 172378846 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 154161650 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1667662469 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 172378847 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154161649 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1667662468 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3043865086 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 3043865085 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651727789 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617884568 # Number of Address Generations +system.cpu.regfile_manager.regForwards 651727790 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617884569 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 120519408 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 11130585 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 131649993 # Number of Branches Incorrectly Predicted @@ -256,12 +241,12 @@ system.cpu.execution_unit.executions 1139371391 # Nu system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1741838166 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1741838474 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7484554 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 415293759 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1571824583 # Number of cycles cpu stages are processed. -system.cpu.activity 79.100703 # Percentage of cycles cpu is active +system.cpu.timesIdled 7484621 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 415293731 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571824611 # Number of cycles cpu stages are processed. +system.cpu.activity 79.100705 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -279,66 +264,66 @@ system.cpu.cpi_total 1.091955 # CP system.cpu.ipc 0.915789 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.ipc_total 0.915789 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 800261653 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1186856689 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 59.727529 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1053419210 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933699132 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.idleCycles 800261647 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186856695 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 59.727530 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1053419200 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933699142 # Number of cycles 1+ instructions are processed. system.cpu.stage1.utilization 46.987596 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1014725197 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 972393145 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.934838 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1577495451 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409622891 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.idleCycles 1014725184 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972393158 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 48.934839 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1577495448 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409622894 # Number of cycles 1+ instructions are processed. system.cpu.stage3.utilization 20.613915 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 965781597 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1021336745 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.idleCycles 965781598 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021336744 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 51.397882 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.tagsinuse 667.839755 # Cycle average of tags in use -system.cpu.icache.total_refs 232024853 # Total number of references to valid blocks. +system.cpu.icache.total_refs 232024854 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 270110.422584 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 270110.423749 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 667.839755 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.326094 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.326094 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 232024853 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 232024853 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 232024853 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 232024853 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 232024853 # number of overall hits -system.cpu.icache.overall_hits::total 232024853 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 232024854 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 232024854 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 232024854 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 232024854 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 232024854 # number of overall hits +system.cpu.icache.overall_hits::total 232024854 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1109 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1109 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1109 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1109 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1109 # number of overall misses system.cpu.icache.overall_misses::total 1109 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 64824000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 64824000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 64824000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 64824000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 64824000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 64824000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 232025962 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 232025962 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 232025962 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 232025962 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 232025962 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 232025962 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 64819000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 64819000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 64819000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 64819000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 64819000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 64819000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 232025963 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 232025963 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 232025963 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 232025963 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 232025963 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 232025963 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58452.660054 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 58452.660054 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 58452.660054 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 58452.660054 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 58452.660054 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 58452.660054 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58448.151488 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 58448.151488 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 58448.151488 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 58448.151488 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 58448.151488 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 58448.151488 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -359,34 +344,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 859 system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51094000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 51094000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51094000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 51094000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51094000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 51094000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51089000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 51089000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51089000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 51089000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51089000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 51089000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59480.791618 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59480.791618 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59480.791618 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 59480.791618 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59480.791618 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 59480.791618 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59474.970896 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59474.970896 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59474.970896 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 59474.970896 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59474.970896 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 59474.970896 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1926957 # number of replacements -system.cpu.l2cache.tagsinuse 30901.189493 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 30901.189526 # Cycle average of tags in use system.cpu.l2cache.total_refs 8958712 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 1956750 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 4.578363 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 67146389752 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15036.220551 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 34.907128 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15830.061814 # Average occupied blocks per requestor +system.cpu.l2cache.warmup_cycle 67146389751 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 15036.225587 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 34.907127 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15830.056812 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.458869 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001065 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.483095 # Average percentage of cache occupancy @@ -412,17 +397,17 @@ system.cpu.l2cache.demand_misses::total 1959688 # nu system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1958829 # number of overall misses system.cpu.l2cache.overall_misses::total 1959688 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50231000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 83163632000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 83213863000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66179053000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 66179053000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 50231000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 149342685000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 149392916000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 50231000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 149342685000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 149392916000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50226000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 83163468000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 83213694000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66176738000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 66176738000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 50226000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 149340206000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 149390432000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 50226000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 149340206000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 149390432000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7221841 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7222700 # number of ReadReq accesses(hits+misses) @@ -447,17 +432,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.215059 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214985 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.215059 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58476.135041 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70625.488947 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70616.632538 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84703.875213 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84703.875213 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58476.135041 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76240.797436 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76233.010561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58476.135041 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76240.797436 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76233.010561 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58470.314319 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70625.349673 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70616.489122 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84700.912199 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84700.912199 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58470.314319 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76239.531884 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76231.743012 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58470.314319 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76239.531884 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76231.743012 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -479,17 +464,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1959688 system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1958829 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1959688 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39571189 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 68487354640 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 68526925829 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 56485658700 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 56485658700 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39571189 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 124973013340 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 125012584529 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39571189 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 124973013340 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 125012584529 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39565474 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 68486082132 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 68525647606 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 56482752358 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 56482752358 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39565474 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 124968834490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 125008399964 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39565474 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 124968834490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 125008399964 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163051 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses @@ -501,51 +486,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46066.576251 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58161.876674 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58153.059668 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72297.108661 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72297.108661 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46066.576251 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63799.858660 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63792.085541 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46066.576251 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63799.858660 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63792.085541 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46059.923166 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58160.796015 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58151.974947 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72293.388777 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72293.388777 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46059.923166 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63797.725320 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63789.950219 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46059.923166 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63797.725320 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63789.950219 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107372 # number of replacements system.cpu.dcache.tagsinuse 4082.262475 # Cycle average of tags in use -system.cpu.dcache.total_refs 593512880 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 593512840 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9111468 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.139106 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 65.139102 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 12624962000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 4082.262475 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.996646 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.996646 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437268758 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437268758 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156244122 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156244122 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 593512880 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 593512880 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 593512880 # number of overall hits -system.cpu.dcache.overall_hits::total 593512880 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 156244082 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156244082 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593512840 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593512840 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593512840 # number of overall hits +system.cpu.dcache.overall_hits::total 593512840 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7326905 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7326905 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4484380 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4484380 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 11811285 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 11811285 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 11811285 # number of overall misses -system.cpu.dcache.overall_misses::total 11811285 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 167288165500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 167288165500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 202507086500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 202507086500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 369795252000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 369795252000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 369795252000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 369795252000 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 4484420 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4484420 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 11811325 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 11811325 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 11811325 # number of overall misses +system.cpu.dcache.overall_misses::total 11811325 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 167288000500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 167288000500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 202511222000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 202511222000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 369799222500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 369799222500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 369799222500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 369799222500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -556,38 +541,38 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027900 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027900 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027901 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027901 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.019512 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.019512 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.019512 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.019512 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22832.036924 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22832.036924 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45158.324339 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45158.324339 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31308.638476 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31308.638476 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31308.638476 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31308.638476 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13465460 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4770860 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 372579 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22832.014404 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22832.014404 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45158.843730 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45158.843730 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31308.868607 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31308.868607 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31308.868607 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31308.868607 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13465422 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4771270 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 372557 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 65753 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.141221 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 72.557298 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.143253 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 72.563533 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3693293 # number of writebacks system.cpu.dcache.writebacks::total 3693293 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104622 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 104622 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595195 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2595195 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2699817 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2699817 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2699817 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2699817 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595235 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2595235 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2699857 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2699857 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2699857 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2699857 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222283 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222283 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889185 # number of WriteReq MSHR misses @@ -596,14 +581,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111468 system.cpu.dcache.demand_mshr_misses::total 9111468 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111468 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111468 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150964459500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 150964459500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79317190500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 79317190500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230281650000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 230281650000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230281650000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 230281650000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150964297500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 150964297500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79314869000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 79314869000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230279166500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 230279166500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230279166500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 230279166500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -612,14 +597,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20902.595412 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20902.595412 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41984.872048 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41984.872048 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25273.825250 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25273.825250 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25273.825250 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25273.825250 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20902.572981 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20902.572981 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41983.643211 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41983.643211 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25273.552681 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25273.552681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25273.552681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25273.552681 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index db2985766..e183c5fce 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,117 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.665563 # Number of seconds simulated -sim_ticks 665562897500 # Number of ticks simulated -final_tick 665562897500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.665771 # Number of seconds simulated +sim_ticks 665770972500 # Number of ticks simulated +final_tick 665770972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181531 # Simulator instruction rate (inst/s) -host_op_rate 181531 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69595242 # Simulator tick rate (ticks/s) -host_mem_usage 467736 # Number of bytes of host memory used -host_seconds 9563.34 # Real time elapsed on the host +host_inst_rate 179472 # Simulator instruction rate (inst/s) +host_op_rate 179472 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68827168 # Simulator tick rate (ticks/s) +host_mem_usage 452252 # Number of bytes of host memory used +host_seconds 9673.08 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125801472 # Number of bytes read from this memory -system.physmem.bytes_read::total 125863104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65262912 # Number of bytes written to this memory -system.physmem.bytes_written::total 65262912 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965648 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966611 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019733 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019733 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 92601 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 189015152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 189107753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 92601 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 92601 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 98056716 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 98056716 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 98056716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 92601 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 189015152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 287164469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966611 # Total number of read requests seen -system.physmem.writeReqs 1019733 # Total number of write requests seen -system.physmem.cpureqs 2988993 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125863104 # Total number of bytes read from memory -system.physmem.bytesWritten 65262912 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125863104 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65262912 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 562 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 62016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125796608 # Number of bytes read from this memory +system.physmem.bytes_read::total 125858624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 62016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 62016 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65265344 # Number of bytes written to this memory +system.physmem.bytes_written::total 65265344 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 969 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965572 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966541 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019771 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019771 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 93149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 188948772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 189041922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 93149 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 93149 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 98029723 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 98029723 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 98029723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 93149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 188948772 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 287071645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966541 # Total number of read requests seen +system.physmem.writeReqs 1019771 # Total number of write requests seen +system.physmem.cpureqs 2988947 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125858624 # Total number of bytes read from memory +system.physmem.bytesWritten 65265344 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125858624 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65265344 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 566 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 122665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 122306 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 122208 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 124220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 123661 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 122580 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 120700 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 121417 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 122611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 122314 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 122187 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 124202 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 123643 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122594 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 120701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 121432 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 121606 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 122292 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 121462 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 123460 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 125578 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 124270 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 123173 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 124451 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 63478 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 62392 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 63122 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 63842 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 64138 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 63875 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 63473 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 63461 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 63474 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 63840 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 63360 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 64241 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64652 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64261 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 63751 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64373 # Track writes on a per bank basis +system.physmem.perBankRdReqs::9 122264 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 121460 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 123481 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 125598 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 124291 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 123180 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 124411 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63480 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 62406 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 63107 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 63843 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 64137 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 63874 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 63470 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 63464 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 63489 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 63818 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63362 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 64260 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64664 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64287 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 63760 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64350 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2649 # Number of times wr buffer was full causing retry -system.physmem.totGap 665562829000 # Total gap between requests +system.physmem.numWrRetry 2635 # Number of times wr buffer was full causing retry +system.physmem.totGap 665770904000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1966611 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1022382 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1625792 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 234895 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 77536 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 27805 # What read queue length does an incoming req see +system.physmem.readPktSize::6 1966541 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 1019771 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1625771 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 234883 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 77503 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 27794 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -137,90 +124,88 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 43965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 43943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 38 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 34363983237 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 102498683237 # Sum of mem lat for all requests -system.physmem.totBusLat 9830245000 # Total cycles spent in databus access -system.physmem.totBankLat 58304455000 # Total cycles spent in bank access -system.physmem.avgQLat 17478.70 # Average queueing delay per request -system.physmem.avgBankLat 29655.65 # Average bank access latency per request +system.physmem.totQLat 34478547500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 102599787500 # Sum of mem lat for all requests +system.physmem.totBusLat 9829875000 # Total cycles spent in databus access +system.physmem.totBankLat 58291365000 # Total cycles spent in bank access +system.physmem.avgQLat 17537.63 # Average queueing delay per request +system.physmem.avgBankLat 29650.10 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52134.35 # Average memory access latency -system.physmem.avgRdBW 189.11 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 98.06 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 189.11 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 98.06 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 52187.74 # Average memory access latency +system.physmem.avgRdBW 189.04 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 98.03 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 189.04 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 98.03 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.24 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 10.79 # Average write queue length over time -system.physmem.readRowHits 776053 # Number of row buffer hits during reads -system.physmem.writeRowHits 286138 # Number of row buffer hits during writes -system.physmem.readRowHitRate 39.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes -system.physmem.avgGap 222868.77 # Average gap between requests -system.cpu.branchPred.lookups 381322658 # Number of BP lookups -system.cpu.branchPred.condPredicted 296346711 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16069927 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 262182430 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259521497 # Number of BTB hits +system.physmem.avgWrQLen 10.14 # Average write queue length over time +system.physmem.readRowHits 776350 # Number of row buffer hits during reads +system.physmem.writeRowHits 285987 # Number of row buffer hits during writes +system.physmem.readRowHitRate 39.49 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.04 # Row buffer hit rate for writes +system.physmem.avgGap 222940.84 # Average gap between requests +system.cpu.branchPred.lookups 381390262 # Number of BP lookups +system.cpu.branchPred.condPredicted 296397889 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16086653 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 262140629 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259559256 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.985083 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24701305 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3076 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.015272 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24699160 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3055 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613798645 # DTB read hits -system.cpu.dtb.read_misses 11251599 # DTB read misses +system.cpu.dtb.read_hits 613788534 # DTB read hits +system.cpu.dtb.read_misses 11249325 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625050244 # DTB read accesses -system.cpu.dtb.write_hits 212271089 # DTB write hits -system.cpu.dtb.write_misses 7143652 # DTB write misses +system.cpu.dtb.read_accesses 625037859 # DTB read accesses +system.cpu.dtb.write_hits 212245958 # DTB write hits +system.cpu.dtb.write_misses 7142739 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219414741 # DTB write accesses -system.cpu.dtb.data_hits 826069734 # DTB hits -system.cpu.dtb.data_misses 18395251 # DTB misses +system.cpu.dtb.write_accesses 219388697 # DTB write accesses +system.cpu.dtb.data_hits 826034492 # DTB hits +system.cpu.dtb.data_misses 18392064 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 844464985 # DTB accesses -system.cpu.itb.fetch_hits 390709896 # ITB hits -system.cpu.itb.fetch_misses 44 # ITB misses +system.cpu.dtb.data_accesses 844426556 # DTB accesses +system.cpu.itb.fetch_hits 390787767 # ITB hits +system.cpu.itb.fetch_misses 43 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 390709940 # ITB accesses +system.cpu.itb.fetch_accesses 390787810 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,98 +219,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1331125796 # number of cpu cycles simulated +system.cpu.numCycles 1331541946 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402151320 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3159313188 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381322658 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 284222802 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 574163176 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140279243 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 173671179 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 90 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1322 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 390709896 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8056983 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1266457048 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.494607 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.152796 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402238482 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3159760476 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381390262 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284258416 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574242721 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140320135 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 173885771 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1317 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 44 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 390787767 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8065204 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1266865295 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.494157 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.152669 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 692293872 54.66% 54.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42630313 3.37% 58.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21744461 1.72% 59.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39673370 3.13% 62.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129246893 10.21% 73.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61513639 4.86% 77.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38552077 3.04% 80.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28113770 2.22% 83.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212688653 16.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 692622574 54.67% 54.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42615431 3.36% 58.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21758353 1.72% 59.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39697295 3.13% 62.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129259260 10.20% 73.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61526950 4.86% 77.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38544819 3.04% 80.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28129154 2.22% 83.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212711459 16.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1266457048 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.286466 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.373414 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 433835858 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 155176701 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542390430 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18584911 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116469148 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58290582 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 824 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3086789571 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2029 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116469148 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 456704578 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 101399871 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7042 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535436988 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 56439421 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3004825157 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 566473 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1727265 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 50367655 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2246602827 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3897066108 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3895827965 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1238143 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1266865295 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.286428 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.373009 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 433949818 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 155380202 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542435049 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18604092 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116496134 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58311036 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 855 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3087126857 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2089 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116496134 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 456815247 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 101557658 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5194 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535499027 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 56492035 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3005134049 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 566488 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1739616 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 50408333 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2246840239 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3897438135 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3896197591 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1240544 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 870399864 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 162 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 161 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 121306422 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679329311 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255341435 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67772546 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 36892101 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2723405673 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2508908939 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3097394 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 978157995 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 414914582 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1266457048 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.981045 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.973109 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 870637276 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 168 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 166 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 121366950 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679350790 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255350759 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67967300 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 37114772 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2723579625 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 126 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2508981641 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3091159 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 978310045 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 415071720 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 97 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1266865295 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.980464 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.972855 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 426262331 33.66% 33.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 201879469 15.94% 49.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185440300 14.64% 64.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153069981 12.09% 76.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133127020 10.51% 86.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 81075751 6.40% 93.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65263497 5.15% 98.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15238482 1.20% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5100217 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 426523141 33.67% 33.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 201951837 15.94% 49.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185492394 14.64% 64.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153160708 12.09% 76.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133131866 10.51% 86.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 81031270 6.40% 93.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65244416 5.15% 98.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15224722 1.20% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5104941 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1266457048 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1266865295 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2147356 11.64% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2143481 11.64% 11.64% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 11.64% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 11.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.64% # attempts to use FU when none available @@ -354,118 +339,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.64% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11882629 64.43% 76.08% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4412064 23.92% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11871999 64.46% 76.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4401590 23.90% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643457358 65.50% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 108 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 284 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 162 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 38 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641426814 25.57% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224024134 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643559437 65.51% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 106 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 261 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 162 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 31 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641411468 25.56% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224010136 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2508908939 # Type of FU issued -system.cpu.iq.rate 1.884802 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18442049 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007351 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6303917077 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3700456251 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2412530118 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1897292 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1213669 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 850482 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2526413076 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 937912 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62601543 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2508981641 # Type of FU issued +system.cpu.iq.rate 1.884268 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18417070 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007340 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6304440735 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3700781380 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2412589185 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1896071 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1214370 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 849902 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2526461544 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 937167 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62583251 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 234733648 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 263681 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 107887 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94612933 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 234755127 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 263530 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 107682 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94622257 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 149 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1508556 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 167 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1505929 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116469148 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 45249808 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1153798 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2865411802 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8865893 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679329311 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255341435 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 296621 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17062 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 107887 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10351897 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8549059 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18900956 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2461552831 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625050873 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47356108 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116496134 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 45259128 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1153276 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2865598045 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8882954 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679350790 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255350759 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 126 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 296462 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17110 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 107682 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10363121 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8561161 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18924282 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2461596227 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625038408 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47385414 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142006007 # number of nop insts executed -system.cpu.iew.exec_refs 844465652 # number of memory reference insts executed -system.cpu.iew.exec_branches 300780520 # Number of branches executed -system.cpu.iew.exec_stores 219414779 # Number of stores executed -system.cpu.iew.exec_rate 1.849226 # Inst execution rate -system.cpu.iew.wb_sent 2441340597 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2413380600 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388547079 # num instructions producing a value -system.cpu.iew.wb_consumers 1764258867 # num instructions consuming a value +system.cpu.iew.exec_nop 142018294 # number of nop insts executed +system.cpu.iew.exec_refs 844427141 # number of memory reference insts executed +system.cpu.iew.exec_branches 300792164 # Number of branches executed +system.cpu.iew.exec_stores 219388733 # Number of stores executed +system.cpu.iew.exec_rate 1.848681 # Inst execution rate +system.cpu.iew.wb_sent 2441396740 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2413439087 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388573479 # num instructions producing a value +system.cpu.iew.wb_consumers 1764243384 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.813037 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.787043 # average fanout of values written-back +system.cpu.iew.wb_rate 1.812515 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.787065 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 824496541 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 824671147 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16069169 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1149987900 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.582434 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.513328 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16085857 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1150369161 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.581910 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.512649 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 636582703 55.36% 55.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174528815 15.18% 70.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86154838 7.49% 78.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53696009 4.67% 82.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34510870 3.00% 85.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25214106 2.19% 87.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21871895 1.90% 89.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22921084 1.99% 91.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94507580 8.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 636844570 55.36% 55.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174611268 15.18% 70.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86171312 7.49% 78.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53631613 4.66% 82.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34569452 3.01% 85.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25367501 2.21% 87.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21831937 1.90% 89.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22907604 1.99% 91.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94433904 8.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1149987900 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1150369161 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,189 +461,189 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94507580 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94433904 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3613977787 # The number of ROB reads -system.cpu.rob.rob_writes 5405122718 # The number of ROB writes -system.cpu.timesIdled 818240 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 64668748 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3614607330 # The number of ROB reads +system.cpu.rob.rob_writes 5405498913 # The number of ROB writes +system.cpu.timesIdled 817784 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 64676651 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.766758 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.766758 # CPI: Total CPI of All Threads -system.cpu.ipc 1.304192 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.304192 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3317304663 # number of integer regfile reads -system.cpu.int_regfile_writes 1931628776 # number of integer regfile writes -system.cpu.fp_regfile_reads 30090 # number of floating regfile reads -system.cpu.fp_regfile_writes 557 # number of floating regfile writes +system.cpu.cpi 0.766998 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.766998 # CPI: Total CPI of All Threads +system.cpu.ipc 1.303785 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.303785 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3317361939 # number of integer regfile reads +system.cpu.int_regfile_writes 1931707111 # number of integer regfile writes +system.cpu.fp_regfile_reads 30073 # number of floating regfile reads +system.cpu.fp_regfile_writes 529 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 772.264197 # Cycle average of tags in use -system.cpu.icache.total_refs 390708412 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 963 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 405720.053998 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 776.168102 # Cycle average of tags in use +system.cpu.icache.total_refs 390786293 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 969 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 403288.228070 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 772.264197 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.377082 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.377082 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 390708412 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 390708412 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 390708412 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 390708412 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 390708412 # number of overall hits -system.cpu.icache.overall_hits::total 390708412 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1482 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1482 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1482 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1482 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1482 # number of overall misses -system.cpu.icache.overall_misses::total 1482 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 83554999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 83554999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 83554999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 83554999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 83554999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 83554999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 390709894 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 390709894 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 390709894 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 390709894 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 390709894 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 390709894 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 776.168102 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.378988 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.378988 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 390786293 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 390786293 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 390786293 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 390786293 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 390786293 # number of overall hits +system.cpu.icache.overall_hits::total 390786293 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1474 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1474 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1474 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1474 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1474 # number of overall misses +system.cpu.icache.overall_misses::total 1474 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 87004499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 87004499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 87004499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 87004499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 87004499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 87004499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 390787767 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 390787767 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 390787767 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 390787767 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 390787767 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 390787767 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56379.891363 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56379.891363 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56379.891363 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56379.891363 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56379.891363 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56379.891363 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 398 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59026.118725 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59026.118725 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59026.118725 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59026.118725 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59026.118725 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59026.118725 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1157 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 56.857143 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 289.250000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 519 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 519 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 519 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 519 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 519 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 519 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 963 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 963 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 963 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59079999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 59079999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59079999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 59079999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59079999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 59079999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 505 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 505 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 505 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 505 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 505 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 505 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 969 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 969 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 969 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 969 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 969 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61752999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 61752999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61752999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 61752999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61752999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 61752999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61349.947040 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61349.947040 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61349.947040 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61349.947040 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61349.947040 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61349.947040 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63728.585139 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63728.585139 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63728.585139 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 63728.585139 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63728.585139 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 63728.585139 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1933906 # number of replacements -system.cpu.l2cache.tagsinuse 31417.619654 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9058583 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1963686 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.613051 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 27417124252 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14685.670328 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 26.375738 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16705.573589 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.448171 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000805 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.509814 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.958790 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 6106242 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6106242 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3725054 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3725054 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108469 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108469 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7214711 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7214711 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7214711 # number of overall hits -system.cpu.l2cache.overall_hits::total 7214711 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 963 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1190539 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1191502 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 775109 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 775109 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 963 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1965648 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1966611 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 963 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1965648 # number of overall misses -system.cpu.l2cache.overall_misses::total 1966611 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58109000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 90112899500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 90171008500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58086526000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 58086526000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 58109000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 148199425500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 148257534500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 58109000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 148199425500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 148257534500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 963 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7296781 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7297744 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3725054 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3725054 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1883578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 963 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9180359 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9181322 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 963 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9180359 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9181322 # number of overall (read+write) accesses +system.cpu.l2cache.replacements 1933842 # number of replacements +system.cpu.l2cache.tagsinuse 31417.862121 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9058109 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1963616 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.612974 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 27417124251 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14684.455679 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 26.907136 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16706.499305 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.448134 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000821 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.509842 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.958797 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 6106130 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6106130 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3724718 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3724718 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108431 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108431 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7214561 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7214561 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7214561 # number of overall hits +system.cpu.l2cache.overall_hits::total 7214561 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 969 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1190438 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1191407 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 775134 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 775134 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 969 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1965572 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1966541 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 969 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1965572 # number of overall misses +system.cpu.l2cache.overall_misses::total 1966541 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 60777000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 90110538000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 90171315000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58186183500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 58186183500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 60777000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 148296721500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 148357498500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 60777000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 148296721500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 148357498500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 969 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7296568 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7297537 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3724718 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3724718 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883565 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1883565 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 969 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9180133 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9181102 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 969 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9180133 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9181102 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163159 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.163270 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411509 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.411509 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163150 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163262 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411525 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.411525 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214115 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214197 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214111 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214194 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.214115 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214197 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60341.640706 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75690.842131 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75678.436545 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74939.816206 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74939.816206 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60341.640706 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75394.691979 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75387.320878 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60341.640706 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75394.691979 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75387.320878 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214111 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214194 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62721.362229 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75695.280225 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75684.728225 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75065.967304 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75065.967304 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62721.362229 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75447.107254 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75440.836728 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62721.362229 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75447.107254 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75440.836728 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -667,180 +652,180 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1019733 # number of writebacks -system.cpu.l2cache.writebacks::total 1019733 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190539 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1191502 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775109 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 775109 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1965648 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1966611 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1965648 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1966611 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 46150301 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 75292068672 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 75338218973 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48421097021 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48421097021 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 46150301 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 123713165693 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 123759315994 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 46150301 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 123713165693 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 123759315994 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1019771 # number of writebacks +system.cpu.l2cache.writebacks::total 1019771 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 969 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190438 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1191407 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775134 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 775134 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 969 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1965572 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1966541 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 969 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1965572 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1966541 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48746029 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 75289506732 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 75338252761 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48519819623 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48519819623 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48746029 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 123809326355 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 123858072384 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48746029 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 123809326355 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 123858072384 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163159 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163270 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411509 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411509 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163150 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163262 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411525 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411525 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214115 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214197 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214111 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214194 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214115 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214197 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47923.469367 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63242.001037 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63229.620238 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62470.048756 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62470.048756 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47923.469367 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62937.599048 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62930.247006 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47923.469367 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62937.599048 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62930.247006 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214111 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214194 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 50305.499484 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63245.214561 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63234.690380 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62595.395923 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62595.395923 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50305.499484 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62988.955050 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62982.705361 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50305.499484 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62988.955050 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62982.705361 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9176263 # number of replacements -system.cpu.dcache.tagsinuse 4087.522413 # Cycle average of tags in use -system.cpu.dcache.total_refs 694338200 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9180359 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 75.633012 # Average number of references to valid blocks. +system.cpu.dcache.replacements 9176037 # number of replacements +system.cpu.dcache.tagsinuse 4087.525084 # Cycle average of tags in use +system.cpu.dcache.total_refs 694351222 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9180133 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 75.636292 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 5069314000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.522413 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997930 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997930 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 538691860 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 538691860 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155646338 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155646338 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 694338198 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694338198 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 694338198 # number of overall hits -system.cpu.dcache.overall_hits::total 694338198 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11282428 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11282428 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5082164 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5082164 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 4087.525084 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997931 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997931 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 538704902 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 538704902 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155646317 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155646317 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 694351219 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694351219 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 694351219 # number of overall hits +system.cpu.dcache.overall_hits::total 694351219 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11279943 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11279943 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5082185 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5082185 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16364592 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16364592 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16364592 # number of overall misses -system.cpu.dcache.overall_misses::total 16364592 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 295012100000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 295012100000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 224191521595 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 224191521595 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 431500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 431500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 519203621595 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 519203621595 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 519203621595 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 519203621595 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 549974288 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 549974288 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 16362128 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16362128 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16362128 # number of overall misses +system.cpu.dcache.overall_misses::total 16362128 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 294923775000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 294923775000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 224062273308 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 224062273308 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 49500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 49500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 518986048308 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 518986048308 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 518986048308 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 518986048308 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 549984845 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 549984845 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710702790 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710702790 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710702790 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710702790 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020514 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020514 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 710713347 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710713347 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710713347 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710713347 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020510 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020510 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031620 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.031620 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023026 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023026 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023026 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023026 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26147.926670 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26147.926670 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44113.397678 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44113.397678 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 431500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 431500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31727.257337 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31727.257337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31727.257337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31727.257337 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12329196 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5816488 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 735313 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023022 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023022 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023022 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023022 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26145.856854 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26145.856854 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44087.783760 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44087.783760 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31718.737826 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31718.737826 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31718.737826 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31718.737826 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12309965 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5809756 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 734892 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.767276 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 89.300335 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.750713 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 89.196979 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3725054 # number of writebacks -system.cpu.dcache.writebacks::total 3725054 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3985636 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3985636 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3198598 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3198598 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7184234 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7184234 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7184234 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7184234 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296792 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296792 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883566 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883566 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3724718 # number of writebacks +system.cpu.dcache.writebacks::total 3724718 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3983366 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3983366 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3198630 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3198630 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7181996 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7181996 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7181996 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7181996 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296577 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296577 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883555 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883555 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180358 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180358 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180358 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180358 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 159255490500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 159255490500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71503545346 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 71503545346 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 429500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 429500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230759035846 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 230759035846 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230759035846 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 230759035846 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013268 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013268 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 9180132 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180132 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180132 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180132 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 159251608500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 159251608500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71602703007 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 71602703007 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 47500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 47500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230854311507 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 230854311507 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230854311507 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 230854311507 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013267 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013267 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.012917 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012917 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21825.411839 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21825.411839 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37961.794461 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37961.794461 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 429500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 429500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25136.169618 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25136.169618 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25136.169618 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25136.169618 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21825.522913 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21825.522913 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38014.660048 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38014.660048 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 47500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 47500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25147.166893 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25147.166893 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25147.166893 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25147.166893 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index fe58c49f1..dd9108dcd 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,115 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.517386 # Number of seconds simulated -sim_ticks 517386177000 # Number of ticks simulated -final_tick 517386177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517371 # Number of seconds simulated +sim_ticks 517371024000 # Number of ticks simulated +final_tick 517371024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165493 # Simulator instruction rate (inst/s) -host_op_rate 184620 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55435711 # Simulator tick rate (ticks/s) -host_mem_usage 502788 # Number of bytes of host memory used -host_seconds 9333.08 # Real time elapsed on the host +host_inst_rate 170437 # Simulator instruction rate (inst/s) +host_op_rate 190135 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57090080 # Simulator tick rate (ticks/s) +host_mem_usage 485276 # Number of bytes of host memory used +host_seconds 9062.36 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143728256 # Number of bytes read from this memory -system.physmem.bytes_read::total 143776256 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70436224 # Number of bytes written to this memory -system.physmem.bytes_written::total 70436224 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 750 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245754 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246504 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100566 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100566 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 92774 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 277796861 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 277889635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 92774 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 92774 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136138589 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136138589 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136138589 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 92774 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 277796861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 414028224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246504 # Total number of read requests seen -system.physmem.writeReqs 1100566 # Total number of write requests seen -system.physmem.cpureqs 3350665 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 143776256 # Total number of bytes read from memory -system.physmem.bytesWritten 70436224 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 143776256 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 70436224 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 651 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143734144 # Number of bytes read from this memory +system.physmem.bytes_read::total 143782208 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48064 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70446784 # Number of bytes written to this memory +system.physmem.bytes_written::total 70446784 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 751 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2245846 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246597 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100731 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100731 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92900 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 277816378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 277909279 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92900 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92900 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136162987 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136162987 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136162987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92900 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 277816378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 414072265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246597 # Total number of read requests seen +system.physmem.writeReqs 1100731 # Total number of write requests seen +system.physmem.cpureqs 3350452 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 143782208 # Total number of bytes read from memory +system.physmem.bytesWritten 70446784 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 143782208 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 70446784 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 642 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 141458 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 139475 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 141540 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 141707 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 142337 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 139999 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 141291 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 140517 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 138551 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 136478 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 140625 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 140699 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 141026 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 139159 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 139234 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 141757 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 69121 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 68349 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 69146 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 69473 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 69281 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 68946 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 69052 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 68358 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 67825 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 67029 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 69533 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 69302 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 69105 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 68630 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 141495 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 139690 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 141603 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 141749 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 142295 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 140068 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 141091 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 140693 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 138519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 136203 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 140642 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 140693 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 141066 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 139208 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 139271 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 141669 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 69094 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 68448 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 69171 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 69468 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 69338 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 68952 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 69046 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 68406 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 67828 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 66957 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 69534 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 69263 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 69109 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 68653 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 68505 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 68911 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 68959 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 3595 # Number of times wr buffer was full causing retry -system.physmem.totGap 517386097500 # Total gap between requests +system.physmem.numWrRetry 3124 # Number of times wr buffer was full causing retry +system.physmem.totGap 517370944500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2246504 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1104161 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1563469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 451045 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 162632 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 68688 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.readPktSize::6 2246597 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 1100731 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1563680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 451075 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 162592 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 68583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -137,70 +124,68 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 44097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 47155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 47801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 47826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 47832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 47832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 47832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 47851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 47851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 47851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 47851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 47851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 47851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 47851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 51687050307 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 131176334057 # Sum of mem lat for all requests -system.physmem.totBusLat 11229265000 # Total cycles spent in databus access -system.physmem.totBankLat 68260018750 # Total cycles spent in bank access -system.physmem.avgQLat 23014.44 # Average queueing delay per request -system.physmem.avgBankLat 30393.81 # Average bank access latency per request +system.physmem.wrQLenPdf::0 44125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 47135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 47809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 47829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 47835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 47837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 47838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 47857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 47857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see +system.physmem.totQLat 51812524750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 131293078500 # Sum of mem lat for all requests +system.physmem.totBusLat 11229775000 # Total cycles spent in databus access +system.physmem.totBankLat 68250778750 # Total cycles spent in bank access +system.physmem.avgQLat 23069.26 # Average queueing delay per request +system.physmem.avgBankLat 30388.31 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 58408.25 # Average memory access latency -system.physmem.avgRdBW 277.89 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 136.14 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 277.89 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 136.14 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 58457.57 # Average memory access latency +system.physmem.avgRdBW 277.91 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 136.16 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 277.91 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 136.16 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.23 # Data bus utilization in percentage system.physmem.avgRdQLen 0.25 # Average read queue length over time -system.physmem.avgWrQLen 10.38 # Average write queue length over time -system.physmem.readRowHits 827421 # Number of row buffer hits during reads -system.physmem.writeRowHits 271011 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 24.62 # Row buffer hit rate for writes -system.physmem.avgGap 154578.81 # Average gap between requests -system.cpu.branchPred.lookups 303247532 # Number of BP lookups -system.cpu.branchPred.condPredicted 249450034 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15218023 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 175041543 # Number of BTB lookups -system.cpu.branchPred.BTBHits 161435617 # Number of BTB hits +system.physmem.avgWrQLen 10.92 # Average write queue length over time +system.physmem.readRowHits 827855 # Number of row buffer hits during reads +system.physmem.writeRowHits 271156 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.86 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 24.63 # Row buffer hit rate for writes +system.physmem.avgGap 154562.37 # Average gap between requests +system.cpu.branchPred.lookups 303290886 # Number of BP lookups +system.cpu.branchPred.condPredicted 249488582 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15222231 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 174596646 # Number of BTB lookups +system.cpu.branchPred.BTBHits 161469311 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.227030 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17558020 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 197 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.481336 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17557313 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 202 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -244,133 +229,133 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1034772355 # number of cpu cycles simulated +system.cpu.numCycles 1034742049 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 298171037 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2186159989 # Number of instructions fetch has processed -system.cpu.fetch.Branches 303247532 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 178993637 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 435067157 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 87822274 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 155469980 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 663 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 288529454 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5728473 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 958589014 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.523348 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.213310 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 298209547 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2186343540 # Number of instructions fetch has processed +system.cpu.fetch.Branches 303290886 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 179026624 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 435120674 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 87852250 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 155399906 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 380 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 288562414 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5732154 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 958634216 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.523474 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.213325 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 523521931 54.61% 54.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25504837 2.66% 57.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39086427 4.08% 61.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48350867 5.04% 66.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43002654 4.49% 70.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46446539 4.85% 75.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38408277 4.01% 79.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18709630 1.95% 81.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175557852 18.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 523513675 54.61% 54.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25518990 2.66% 57.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39095186 4.08% 61.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48349741 5.04% 66.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43010158 4.49% 70.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46440341 4.84% 75.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38425121 4.01% 79.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18710957 1.95% 81.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175570047 18.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 958589014 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.293057 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.112697 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 329732299 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 133726687 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 405163333 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20087198 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 69879497 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46055159 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 678 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2366957956 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2458 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 69879497 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 353264569 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 63487571 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 18775 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 400193247 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 71745355 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2304463172 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 133379 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5038858 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 58609164 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 17 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2279851599 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10642208168 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10642204755 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3413 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 958634216 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.293108 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.112936 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 329763250 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 133666994 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 405221512 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20079412 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69903048 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46058380 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 679 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2367190993 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2433 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 69903048 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 353304996 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 63447183 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15614 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 400231748 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 71731627 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2304653779 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 133097 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5040028 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 58589233 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 7 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2280042978 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10643127773 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10643124880 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2893 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 573531669 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 681 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 678 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 158828994 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624462299 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220966139 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 86157140 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 71007424 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2201342631 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 714 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2018151759 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3999657 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 473702297 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1125076843 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 544 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 958589014 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.105336 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906417 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 573723048 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 497 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 494 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 158827938 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624515157 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220983969 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 86332349 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 71315853 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2201513470 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 522 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2018112827 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4002858 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 473886256 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1126241029 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 958634216 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.105196 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906381 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 277560944 28.96% 28.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151408943 15.79% 44.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 161184316 16.81% 61.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119741050 12.49% 74.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 124054843 12.94% 87.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73850392 7.70% 94.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38407609 4.01% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9813288 1.02% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2567629 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 277594004 28.96% 28.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 151404549 15.79% 44.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 161201477 16.82% 61.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119812250 12.50% 74.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 123999377 12.94% 87.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73820536 7.70% 94.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38419650 4.01% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9808498 1.02% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2573875 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 958589014 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 958634216 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 872793 3.65% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5710 0.02% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18283969 76.42% 80.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4762893 19.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 872312 3.66% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5645 0.02% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18268766 76.62% 80.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4697940 19.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236667909 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 925774 0.05% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236677496 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 926030 0.05% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -392,90 +377,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 51 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 33 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 24 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 5 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587469094 29.11% 90.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193088896 9.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587482532 29.11% 90.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193026708 9.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2018151759 # Type of FU issued -system.cpu.iq.rate 1.950334 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23925365 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011855 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5022817228 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2675235301 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1957490366 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 326 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 628 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 132 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2042076961 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 163 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64626006 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2018112827 # Type of FU issued +system.cpu.iq.rate 1.950354 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23844663 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011815 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5022707128 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2675590256 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957438118 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 556 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2041957357 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64629974 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138535530 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 270863 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192819 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 46119094 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138588388 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 271831 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192988 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 46136924 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4653355 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4659196 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 69879497 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28935964 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1499081 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2201343583 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6151222 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624462299 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220966139 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 652 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 473850 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 90091 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192819 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8153540 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9614603 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17768143 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1988132356 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 573881676 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30019403 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69903048 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28888784 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1501235 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2201514122 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6139547 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624515157 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220983969 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 460 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 475783 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 89669 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192988 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8156378 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9617829 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17774207 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1988116656 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 573901246 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29996171 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 238 # number of nop insts executed -system.cpu.iew.exec_refs 764075762 # number of memory reference insts executed -system.cpu.iew.exec_branches 238335526 # Number of branches executed -system.cpu.iew.exec_stores 190194086 # Number of stores executed -system.cpu.iew.exec_rate 1.921323 # Inst execution rate -system.cpu.iew.wb_sent 1965930006 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1957490498 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1296385031 # num instructions producing a value -system.cpu.iew.wb_consumers 2061135459 # num instructions consuming a value +system.cpu.iew.exec_nop 130 # number of nop insts executed +system.cpu.iew.exec_refs 764045166 # number of memory reference insts executed +system.cpu.iew.exec_branches 238330381 # Number of branches executed +system.cpu.iew.exec_stores 190143920 # Number of stores executed +system.cpu.iew.exec_rate 1.921365 # Inst execution rate +system.cpu.iew.wb_sent 1965882705 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957438221 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1296419261 # num instructions producing a value +system.cpu.iew.wb_consumers 2061223018 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.891711 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.628966 # average fanout of values written-back +system.cpu.iew.wb_rate 1.891716 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.628956 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 478367692 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 478537797 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15217365 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 888709517 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.938849 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.727981 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15221576 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 888731168 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.938802 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.727796 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 401294450 45.15% 45.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 192123349 21.62% 66.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72572906 8.17% 74.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35244916 3.97% 78.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18969010 2.13% 81.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30763331 3.46% 84.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20056672 2.26% 86.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11441847 1.29% 88.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106243036 11.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 401249220 45.15% 45.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 192209497 21.63% 66.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72554391 8.16% 74.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35214687 3.96% 78.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19001350 2.14% 81.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30768614 3.46% 84.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20079948 2.26% 86.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11444333 1.29% 88.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106209128 11.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 888709517 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 888731168 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -486,70 +471,70 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106243036 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106209128 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2983907427 # The number of ROB reads -system.cpu.rob.rob_writes 4472910463 # The number of ROB writes -system.cpu.timesIdled 1017511 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 76183341 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2984133091 # The number of ROB reads +system.cpu.rob.rob_writes 4473274350 # The number of ROB writes +system.cpu.timesIdled 1017651 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76107833 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.669945 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.669945 # CPI: Total CPI of All Threads -system.cpu.ipc 1.492660 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.492660 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9956386896 # number of integer regfile reads -system.cpu.int_regfile_writes 1937427158 # number of integer regfile writes -system.cpu.fp_regfile_reads 137 # number of floating regfile reads -system.cpu.fp_regfile_writes 146 # number of floating regfile writes -system.cpu.misc_regfile_reads 737590270 # number of misc regfile reads +system.cpu.cpi 0.669925 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.669925 # CPI: Total CPI of All Threads +system.cpu.ipc 1.492703 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.492703 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9956233395 # number of integer regfile reads +system.cpu.int_regfile_writes 1937436072 # number of integer regfile writes +system.cpu.fp_regfile_reads 98 # number of floating regfile reads +system.cpu.fp_regfile_writes 104 # number of floating regfile writes +system.cpu.misc_regfile_reads 737527238 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.icache.replacements 21 # number of replacements -system.cpu.icache.tagsinuse 626.247624 # Cycle average of tags in use -system.cpu.icache.total_refs 288528273 # Total number of references to valid blocks. +system.cpu.icache.replacements 22 # number of replacements +system.cpu.icache.tagsinuse 625.709575 # Cycle average of tags in use +system.cpu.icache.total_refs 288561231 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 779 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 370382.892169 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 370425.200257 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 626.247624 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.305785 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.305785 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 288528273 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 288528273 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 288528273 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 288528273 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 288528273 # number of overall hits -system.cpu.icache.overall_hits::total 288528273 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1181 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1181 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1181 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1181 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1181 # number of overall misses -system.cpu.icache.overall_misses::total 1181 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 66140500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 66140500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 66140500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 66140500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 66140500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 66140500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 288529454 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 288529454 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 288529454 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 288529454 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 288529454 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 288529454 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 625.709575 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.305522 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.305522 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 288561231 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 288561231 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 288561231 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 288561231 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 288561231 # number of overall hits +system.cpu.icache.overall_hits::total 288561231 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1183 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1183 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1183 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1183 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1183 # number of overall misses +system.cpu.icache.overall_misses::total 1183 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 68862000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 68862000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 68862000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 68862000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 68862000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 68862000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 288562414 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 288562414 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 288562414 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 288562414 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 288562414 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 288562414 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56003.810330 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56003.810330 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56003.810330 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56003.810330 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56003.810330 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56003.810330 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58209.636517 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 58209.636517 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 58209.636517 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 58209.636517 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 58209.636517 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 58209.636517 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 195 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -558,120 +543,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 65 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 402 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 402 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 402 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 402 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 402 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 402 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 404 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 404 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 404 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 404 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 404 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 404 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 779 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 779 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 779 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 779 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 779 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 779 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46510000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46510000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46510000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46510000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46510000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46510000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46813500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46813500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46813500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46813500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46813500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46813500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59704.749679 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59704.749679 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59704.749679 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 59704.749679 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59704.749679 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 59704.749679 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60094.351733 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60094.351733 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60094.351733 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60094.351733 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60094.351733 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60094.351733 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2213813 # number of replacements -system.cpu.l2cache.tagsinuse 31531.943712 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9246179 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2243587 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.121159 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 20448147252 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14437.603993 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 20.351640 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 17073.988080 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.440601 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 2213910 # number of replacements +system.cpu.l2cache.tagsinuse 31531.957469 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9247495 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2243685 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.121566 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 20448147251 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14435.927117 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 20.343245 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 17075.687107 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.440550 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.000621 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.521057 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.521109 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.962279 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6289367 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6289395 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3781250 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3781250 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1066794 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1066794 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7356161 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7356189 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7356161 # number of overall hits -system.cpu.l2cache.overall_hits::total 7356189 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 751 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1419105 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1419856 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 826656 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 826656 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 751 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2245761 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2246512 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 751 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2245761 # number of overall misses -system.cpu.l2cache.overall_misses::total 2246512 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45442000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 113741424500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 113786866500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70408170000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 70408170000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 45442000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 184149594500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 184195036500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 45442000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 184149594500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 184195036500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6290241 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6290268 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3781695 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3781695 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1066899 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1066899 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7357140 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7357167 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7357140 # number of overall hits +system.cpu.l2cache.overall_hits::total 7357167 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 752 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1419201 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1419953 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 826653 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 826653 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 752 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2245854 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2246606 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 752 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2245854 # number of overall misses +system.cpu.l2cache.overall_misses::total 2246606 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45758500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 113786309000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 113832067500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70488863500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 70488863500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 45758500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 184275172500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 184320931000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 45758500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 184275172500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 184320931000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 779 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7708472 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7709251 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3781250 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3781250 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893450 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1893450 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7709442 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7710221 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3781695 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3781695 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893552 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1893552 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 779 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9601922 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9602701 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9602994 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9603773 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 779 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9601922 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9602701 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964056 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184097 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.184176 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436587 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.436587 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964056 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.233887 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.233946 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964056 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.233887 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.233946 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60508.655126 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80150.111866 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 80139.722972 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85172.272384 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85172.272384 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60508.655126 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81998.749867 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81991.565814 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60508.655126 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81998.749867 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81991.565814 # average overall miss latency +system.cpu.l2cache.overall_accesses::cpu.data 9602994 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9603773 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965340 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184086 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.184165 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436562 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.436562 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965340 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.233870 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.233930 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965340 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.233870 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.233930 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60849.069149 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80176.316815 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80166.081201 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85270.196201 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85270.196201 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60849.069149 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82051.269806 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82044.172855 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60849.069149 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82051.269806 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82044.172855 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -680,187 +665,187 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1100566 # number of writebacks -system.cpu.l2cache.writebacks::total 1100566 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1100731 # number of writebacks +system.cpu.l2cache.writebacks::total 1100731 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 750 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419098 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1419848 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826656 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 826656 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 750 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2245754 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2246504 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 750 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2245754 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2246504 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35808198 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 96120907910 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96156716108 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60148132877 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60148132877 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35808198 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156269040787 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 156304848985 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35808198 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156269040787 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 156304848985 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962773 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184096 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184175 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436587 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436587 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962773 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233886 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.233945 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962773 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233886 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.233945 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47744.264000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67733.805495 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67723.246508 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72760.777006 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72760.777006 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47744.264000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69584.220171 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69576.928857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47744.264000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69584.220171 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69576.928857 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 751 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419193 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1419944 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826653 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 826653 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 751 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2245846 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2246597 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 751 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2245846 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2246597 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 36118599 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 96162576934 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96198695533 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60228963949 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60228963949 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 36118599 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156391540883 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 156427659482 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 36118599 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156391540883 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 156427659482 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964056 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184085 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184164 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436562 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436562 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964056 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233869 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.233929 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964056 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233869 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.233929 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48094.006658 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67758.632500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67748.231996 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72858.822201 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72858.822201 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48094.006658 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69635.914877 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69628.713776 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48094.006658 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69635.914877 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69628.713776 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9597826 # number of replacements -system.cpu.dcache.tagsinuse 4088.019917 # Cycle average of tags in use -system.cpu.dcache.total_refs 656092202 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9601922 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.329258 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3440649000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4088.019917 # Average occupied blocks per requestor +system.cpu.dcache.replacements 9598898 # number of replacements +system.cpu.dcache.tagsinuse 4088.019682 # Cycle average of tags in use +system.cpu.dcache.total_refs 656099070 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9602994 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.322345 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3440663000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4088.019682 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.998052 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.998052 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 489045122 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 489045122 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167046955 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167046955 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 64 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 64 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 489051603 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 489051603 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167047341 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167047341 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 65 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 65 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 656092077 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 656092077 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 656092077 # number of overall hits -system.cpu.dcache.overall_hits::total 656092077 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11476427 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11476427 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5539092 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5539092 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 656098944 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 656098944 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 656098944 # number of overall hits +system.cpu.dcache.overall_hits::total 656098944 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11478513 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11478513 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5538706 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5538706 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17015519 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17015519 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17015519 # number of overall misses -system.cpu.dcache.overall_misses::total 17015519 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 322914399500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 322914399500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 229337265001 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 229337265001 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 188000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 188000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 552251664501 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 552251664501 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 552251664501 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 552251664501 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500521549 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500521549 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17017219 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17017219 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17017219 # number of overall misses +system.cpu.dcache.overall_misses::total 17017219 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 323000428500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 323000428500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 229631369718 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 229631369718 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 423500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 423500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 552631798218 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 552631798218 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 552631798218 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 552631798218 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500530116 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500530116 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 68 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 68 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673107596 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673107596 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673107596 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673107596 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022929 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022929 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032095 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032095 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025279 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025279 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025279 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025279 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28137.189345 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28137.189345 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41403.404204 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41403.404204 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62666.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62666.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32455.763736 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32455.763736 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32455.763736 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32455.763736 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 26327984 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1057907 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1182334 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 64553 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.267806 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16.388193 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 673116163 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673116163 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673116163 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673116163 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022933 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022933 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032092 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032092 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025281 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025281 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025281 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025281 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28139.570735 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28139.570735 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41459.389561 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41459.389561 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 141166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 141166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32474.859624 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32474.859624 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32474.859624 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32474.859624 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 26343962 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1054966 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1182360 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 64552 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.280830 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 16.342886 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3781250 # number of writebacks -system.cpu.dcache.writebacks::total 3781250 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3767955 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3767955 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645642 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3645642 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3781695 # number of writebacks +system.cpu.dcache.writebacks::total 3781695 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3769070 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3769070 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645155 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3645155 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7413597 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7413597 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7413597 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7413597 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708472 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7708472 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893450 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893450 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9601922 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9601922 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9601922 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9601922 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186178488500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 186178488500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508071510 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508071510 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269686560010 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 269686560010 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269686560010 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 269686560010 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015401 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015401 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24152.450512 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24152.450512 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44103.658143 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44103.658143 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28086.726804 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28086.726804 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28086.726804 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28086.726804 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 7414225 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7414225 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7414225 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7414225 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7709443 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7709443 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893551 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893551 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9602994 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9602994 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9602994 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9602994 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186232562000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 186232562000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83589909224 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83589909224 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269822471224 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 269822471224 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269822471224 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 269822471224 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015403 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015403 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010972 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010972 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014266 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014266 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014266 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014266 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24156.422455 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24156.422455 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44144.524876 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44144.524876 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28097.744435 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28097.744435 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28097.744435 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28097.744435 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 7e4c9be17..5e225e744 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.041622 # Nu sim_ticks 41622221000 # Number of ticks simulated final_tick 41622221000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 156492 # Simulator instruction rate (inst/s) -host_op_rate 156492 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 70874179 # Simulator tick rate (ticks/s) -host_mem_usage 228076 # Number of bytes of host memory used -host_seconds 587.27 # Real time elapsed on the host +host_inst_rate 75517 # Simulator instruction rate (inst/s) +host_op_rate 75517 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34200879 # Simulator tick rate (ticks/s) +host_mem_usage 228092 # Number of bytes of host memory used +host_seconds 1216.99 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -78,28 +78,15 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 4938 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 3236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1202 # What read queue length does an incoming req see +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 3235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1203 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 433 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 23375922 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 122137172 # Sum of mem lat for all requests +system.physmem.totQLat 23405750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 122167000 # Sum of mem lat for all requests system.physmem.totBusLat 24690000 # Total cycles spent in databus access system.physmem.totBankLat 74071250 # Total cycles spent in bank access -system.physmem.avgQLat 4733.88 # Average queueing delay per request +system.physmem.avgQLat 4739.93 # Average queueing delay per request system.physmem.avgBankLat 15000.25 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24734.14 # Average memory access latency +system.physmem.avgMemAccLat 24740.18 # Average memory access latency system.physmem.avgRdBW 7.59 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 7.59 # Average consumed read bandwidth in MB/s @@ -288,12 +273,12 @@ system.cpu.stage4.idleCycles 29384711 # Nu system.cpu.stage4.runCycles 53859732 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 64.700694 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 7635 # number of replacements -system.cpu.icache.tagsinuse 1492.649363 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1492.649326 # Cycle average of tags in use system.cpu.icache.total_refs 9945578 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 9520 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1044.703571 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1492.649363 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1492.649326 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.728833 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.728833 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 9945578 # number of ReadReq hits @@ -308,12 +293,12 @@ system.cpu.icache.demand_misses::cpu.inst 11365 # n system.cpu.icache.demand_misses::total 11365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11365 # number of overall misses system.cpu.icache.overall_misses::total 11365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 259189500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 259189500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 259189500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 259189500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 259189500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 259189500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 259175500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 259175500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 259175500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 259175500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 259175500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 259175500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 9956943 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 9956943 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 9956943 # number of demand (read+write) accesses @@ -326,12 +311,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001141 system.cpu.icache.demand_miss_rate::total 0.001141 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001141 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001141 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22805.939287 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22805.939287 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22805.939287 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22805.939287 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22805.939287 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22805.939287 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22804.707435 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22804.707435 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22804.707435 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22804.707435 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22804.707435 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22804.707435 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -352,34 +337,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 9520 system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 209613500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 209613500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209613500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 209613500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209613500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 209613500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 209599500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 209599500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209599500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 209599500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209599500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 209599500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22018.224790 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22018.224790 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22018.224790 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22018.224790 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22018.224790 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22018.224790 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22016.754202 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22016.754202 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22016.754202 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22016.754202 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22016.754202 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22016.754202 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2190.263467 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2190.263404 # Cycle average of tags in use system.cpu.l2cache.total_refs 6793 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.069775 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 17.839012 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1821.325234 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.099221 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1821.325190 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.099202 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000544 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.055582 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.010715 # Average percentage of cache occupancy @@ -408,17 +393,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132557500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132543500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 24069000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 156626500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84092000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 84092000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 132557500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 108161000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 240718500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 132557500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 108161000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 240718500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 156612500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84148000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 84148000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 132543500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 108217000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 240760500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 132543500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 108217000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 240760500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses) @@ -443,17 +428,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47443.629205 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47438.618468 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57035.545024 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 48702.269900 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48833.914053 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48833.914053 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47443.629205 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50448.227612 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 48748.177400 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47443.629205 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50448.227612 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 48748.177400 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 48697.916667 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48866.434379 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48866.434379 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47438.618468 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50474.347015 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 48756.682868 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47438.618468 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50474.347015 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 48756.682868 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -473,17 +458,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97843336 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18812201 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116655537 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63127136 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63127136 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97843336 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 81939337 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 179782673 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97843336 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 81939337 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 179782673 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97826921 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18811852 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116638773 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63182194 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63182194 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97826921 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 81994046 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 179820967 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97826921 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 81994046 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 179820967 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses @@ -495,25 +480,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35019.089477 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44578.675355 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36273.487873 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36659.196283 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36659.196283 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35019.089477 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38217.974347 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36407.993722 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35019.089477 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38217.974347 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36407.993722 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35013.214388 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44577.848341 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36268.275187 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36691.169570 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36691.169570 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35013.214388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38243.491604 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36415.748684 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35013.214388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38243.491604 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36415.748684 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.801688 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1441.801521 # Cycle average of tags in use system.cpu.dcache.total_refs 26488625 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11915.710751 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.801688 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 1441.801521 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.352002 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.352002 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 19995623 # number of ReadReq hits @@ -534,12 +519,12 @@ system.cpu.dcache.overall_misses::cpu.data 8676 # system.cpu.dcache.overall_misses::total 8676 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 31383500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 31383500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 345698500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 345698500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 377082000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 377082000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 377082000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 377082000 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 346048500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 346048500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 377432000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 377432000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 377432000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 377432000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -558,17 +543,17 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54580 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 54580 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42673.558820 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42673.558820 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 43462.655602 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 43462.655602 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 43462.655602 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 43462.655602 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13684 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42716.763363 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42716.763363 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 43502.996773 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 43502.996773 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 43502.996773 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 43502.996773 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13712 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 822 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.647202 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.681265 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -592,12 +577,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 2223 system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25092500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 25092500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86109500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 86109500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 111202000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 111202000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 111202000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 111202000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86165500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 86165500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 111258000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 111258000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 111258000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 111258000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -608,12 +593,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52826.315789 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52826.315789 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49261.727689 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49261.727689 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50023.391813 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50023.391813 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50023.391813 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50023.391813 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49293.764302 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49293.764302 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50048.582996 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50048.582996 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50048.582996 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50048.582996 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index c7256bad9..a102acf91 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.023427 # Nu sim_ticks 23426793000 # Number of ticks simulated final_tick 23426793000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 213464 # Simulator instruction rate (inst/s) -host_op_rate 213464 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59405864 # Simulator tick rate (ticks/s) -host_mem_usage 230136 # Number of bytes of host memory used -host_seconds 394.35 # Real time elapsed on the host +host_inst_rate 128339 # Simulator instruction rate (inst/s) +host_op_rate 128339 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35715987 # Simulator tick rate (ticks/s) +host_mem_usage 230140 # Number of bytes of host memory used +host_seconds 655.92 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory @@ -78,28 +78,15 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 5228 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 3174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1385 # What read queue length does an incoming req see +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 3175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1384 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 549 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 106 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 28657456 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 133887456 # Sum of mem lat for all requests +system.physmem.totQLat 28652250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 133882250 # Sum of mem lat for all requests system.physmem.totBusLat 26140000 # Total cycles spent in databus access system.physmem.totBankLat 79090000 # Total cycles spent in bank access -system.physmem.avgQLat 5481.53 # Average queueing delay per request +system.physmem.avgQLat 5480.54 # Average queueing delay per request system.physmem.avgBankLat 15128.16 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25609.69 # Average memory access latency +system.physmem.avgMemAccLat 25608.69 # Average memory access latency system.physmem.avgRdBW 14.28 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 14.28 # Average consumed read bandwidth in MB/s @@ -579,7 +564,7 @@ system.cpu.l2cache.sampled_refs 3590 # Sa system.cpu.l2cache.avg_refs 2.367688 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 17.668263 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2005.213140 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2005.213141 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 381.714191 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.061194 # Average percentage of cache occupancy @@ -674,17 +659,17 @@ system.cpu.l2cache.demand_mshr_misses::total 5228 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2166 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5228 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106921693 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23470923 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 130392616 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 65567754 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 65567754 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106921693 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 89038677 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 195960370 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106921693 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 89038677 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 195960370 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106919101 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23470588 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 130389689 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 65567128 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 65567128 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106919101 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 89037716 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 195956817 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106919101 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 89037716 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 195956817 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266446 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.893411 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.293388 # mshr miss rate for ReadReq accesses @@ -696,17 +681,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.380523 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266446 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.380523 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34918.906924 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50913.065076 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37011.812660 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38456.160704 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38456.160704 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34918.906924 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41107.422438 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37482.855777 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34918.906924 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41107.422438 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37482.855777 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34918.060418 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50912.338395 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37010.981834 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38455.793548 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38455.793548 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34918.060418 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41106.978763 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37482.176167 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34918.060418 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41106.978763 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37482.176167 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 159 # number of replacements system.cpu.dcache.tagsinuse 1459.874578 # Cycle average of tags in use diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 4d507d8ac..d2046c973 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.074156 # Nu sim_ticks 74155951500 # Number of ticks simulated final_tick 74155951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108940 # Simulator instruction rate (inst/s) -host_op_rate 119280 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46885764 # Simulator tick rate (ticks/s) -host_mem_usage 245224 # Number of bytes of host memory used -host_seconds 1581.63 # Real time elapsed on the host +host_inst_rate 102580 # Simulator instruction rate (inst/s) +host_op_rate 112316 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44148416 # Simulator tick rate (ticks/s) +host_mem_usage 245240 # Number of bytes of host memory used +host_seconds 1679.70 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 131776 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 3811 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 2809 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 787 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 160 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 17813284 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 103885784 # Sum of mem lat for all requests +system.physmem.totQLat 17809500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 103882000 # Sum of mem lat for all requests system.physmem.totBusLat 19055000 # Total cycles spent in databus access system.physmem.totBankLat 67017500 # Total cycles spent in bank access -system.physmem.avgQLat 4674.18 # Average queueing delay per request +system.physmem.avgQLat 4673.18 # Average queueing delay per request system.physmem.avgBankLat 17585.28 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27259.46 # Average memory access latency +system.physmem.avgMemAccLat 27258.46 # Average memory access latency system.physmem.avgRdBW 3.29 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 3.29 # Average consumed read bandwidth in MB/s @@ -699,17 +684,17 @@ system.cpu.l2cache.demand_mshr_misses::total 3811 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2060 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1751 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3811 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 78131980 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30985263 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 109117243 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 36314730 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 36314730 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 78131980 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67299993 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 145431973 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 78131980 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67299993 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 145431973 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 78130246 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30984758 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 109115004 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 36313866 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 36313866 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 78130246 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67298624 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 145428870 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 78130246 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67298624 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 145428870 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.502439 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869845 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.560911 # mshr miss rate for ReadReq accesses @@ -721,17 +706,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.639322 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.502439 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940892 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.639322 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37928.145631 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45904.093333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39896.615356 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33749.749071 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33749.749071 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37928.145631 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38435.175899 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38161.105484 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37928.145631 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38435.175899 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38161.105484 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37927.303883 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45903.345185 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39895.796709 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33748.946097 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33748.946097 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37927.303883 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38434.394061 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38160.291262 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37927.303883 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38434.394061 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38160.291262 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 57 # number of replacements system.cpu.dcache.tagsinuse 1410.136977 # Cycle average of tags in use diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index ea454cb40..f1f025306 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.082836 # Nu sim_ticks 82836235000 # Number of ticks simulated final_tick 82836235000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72340 # Simulator instruction rate (inst/s) -host_op_rate 121249 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45372545 # Simulator tick rate (ticks/s) +host_inst_rate 70076 # Simulator instruction rate (inst/s) +host_op_rate 117454 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43952394 # Simulator tick rate (ticks/s) host_mem_usage 275820 # Number of bytes of host memory used -host_seconds 1825.69 # Real time elapsed on the host +host_seconds 1884.68 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362961 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 218368 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 5362 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 153 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 4169 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 943 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 199 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 15727084 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 132185834 # Sum of mem lat for all requests +system.physmem.totQLat 15721750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 132180500 # Sum of mem lat for all requests system.physmem.totBusLat 26795000 # Total cycles spent in databus access system.physmem.totBankLat 89663750 # Total cycles spent in bank access -system.physmem.avgQLat 2933.06 # Average queueing delay per request +system.physmem.avgQLat 2932.07 # Average queueing delay per request system.physmem.avgBankLat 16722.07 # Average bank access latency per request system.physmem.avgBusLat 4997.20 # Average bus latency per request -system.physmem.avgMemAccLat 24652.34 # Average memory access latency +system.physmem.avgMemAccLat 24651.34 # Average memory access latency system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s @@ -648,19 +633,19 @@ system.cpu.l2cache.demand_mshr_misses::total 5362 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3413 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1949 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5362 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 121268321 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18645617 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 139913938 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 121265541 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18645311 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 139910852 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1530153 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1530153 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49242500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49242500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 121268321 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67888117 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 189156438 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 121268321 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67888117 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 189156438 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49241002 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49241002 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 121265541 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67886313 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 189151854 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 121265541 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67886313 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 189151854 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496581 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929245 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.521721 # mshr miss rate for ReadReq accesses @@ -674,19 +659,19 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.605260 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496581 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981370 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.605260 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35531.298271 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47323.901015 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36751.756764 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35530.483739 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47323.124365 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36750.946152 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31667.202572 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31667.202572 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35531.298271 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34832.281683 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35277.217083 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35531.298271 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34832.281683 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35277.217083 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31666.239228 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31666.239228 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35530.483739 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34831.356080 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35276.362178 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35530.483739 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34831.356080 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35276.362178 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 56 # number of replacements system.cpu.dcache.tagsinuse 1416.460930 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index a5d2b415b..dd98a6573 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.870325 # Nu sim_ticks 1870325497500 # Number of ticks simulated final_tick 1870325497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2356651 # Simulator instruction rate (inst/s) -host_op_rate 2356650 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69796056257 # Simulator tick rate (ticks/s) -host_mem_usage 349376 # Number of bytes of host memory used -host_seconds 26.80 # Real time elapsed on the host +host_inst_rate 3609656 # Simulator instruction rate (inst/s) +host_op_rate 3609654 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 106905838632 # Simulator tick rate (ticks/s) +host_mem_usage 305660 # Number of bytes of host memory used +host_seconds 17.50 # Real time elapsed on the host sim_insts 63151114 # Number of instructions simulated sim_ops 63151114 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 760896 # Number of bytes read from this memory @@ -99,26 +99,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 0 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -151,7 +138,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -184,7 +170,6 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 178493c15..2e73db07d 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829331 # Nu sim_ticks 1829330593000 # Number of ticks simulated final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1133415 # Simulator instruction rate (inst/s) -host_op_rate 1133413 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34534714924 # Simulator tick rate (ticks/s) -host_mem_usage 347332 # Number of bytes of host memory used -host_seconds 52.97 # Real time elapsed on the host +host_inst_rate 3233953 # Simulator instruction rate (inst/s) +host_op_rate 3233951 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 98537371937 # Simulator tick rate (ticks/s) +host_mem_usage 303612 # Number of bytes of host memory used +host_seconds 18.56 # Real time elapsed on the host sim_insts 60037737 # Number of instructions simulated sim_ops 60037737 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory @@ -89,26 +89,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 0 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -141,7 +128,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -174,7 +160,6 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access @@ -608,69 +593,5 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks system.cpu.dcache.writebacks::total 833491 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2042707 # number of replacements -system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.total_refs 14038405 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2043219 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 6.870729 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7807769 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807769 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655968 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655968 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655968 # number of overall hits -system.cpu.dcache.overall_hits::total 13655968 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721709 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721709 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses -system.cpu.dcache.overall_misses::total 2026074 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks -system.cpu.dcache.writebacks::total 833491 # number of writebacks -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index e93e66fed..3e3128027 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,145 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.952724 # Number of seconds simulated -sim_ticks 1952724269500 # Number of ticks simulated -final_tick 1952724269500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.954691 # Number of seconds simulated +sim_ticks 1954691371500 # Number of ticks simulated +final_tick 1954691371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1678586 # Simulator instruction rate (inst/s) -host_op_rate 1678585 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53851852439 # Simulator tick rate (ticks/s) -host_mem_usage 333452 # Number of bytes of host memory used -host_seconds 36.26 # Real time elapsed on the host -sim_insts 60867235 # Number of instructions simulated -sim_ops 60867235 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 830208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24725568 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 35200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 438144 # Number of bytes read from this memory -system.physmem.bytes_read::total 28680000 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 830208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 35200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 865408 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7698816 # Number of bytes written to this memory -system.physmem.bytes_written::total 7698816 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12972 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386337 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 550 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6846 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448125 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120294 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120294 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 425154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12662089 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1357529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 18026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 224376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14687173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 425154 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 18026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443180 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3942603 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3942603 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3942603 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 425154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12662089 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1357529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 18026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 224376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18629776 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 448125 # Total number of read requests seen -system.physmem.writeReqs 120294 # Total number of write requests seen -system.physmem.cpureqs 598443 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28680000 # Total number of bytes read from memory -system.physmem.bytesWritten 7698816 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28680000 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7698816 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 68 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 6945 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28344 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28173 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28017 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27785 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27964 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28022 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27886 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28437 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28288 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28341 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28051 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27575 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27797 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27570 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27856 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7610 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7567 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7380 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7470 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7435 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7506 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7435 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7992 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7835 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7874 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7588 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7131 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7029 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7371 # Track writes on a per bank basis +host_inst_rate 798728 # Simulator instruction rate (inst/s) +host_op_rate 798728 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26318676085 # Simulator tick rate (ticks/s) +host_mem_usage 332420 # Number of bytes of host memory used +host_seconds 74.27 # Real time elapsed on the host +sim_insts 59321614 # Number of instructions simulated +sim_ops 59321614 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 829376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24757440 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 34176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 389696 # Number of bytes read from this memory +system.physmem.bytes_read::total 28661504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 829376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 34176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7676992 # Number of bytes written to this memory +system.physmem.bytes_written::total 7676992 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386835 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 534 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6089 # Number of read requests responded to by this memory +system.physmem.num_reads::total 447836 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 119953 # Number of write requests responded to by this memory +system.physmem.num_writes::total 119953 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 424300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12665652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1356130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 17484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 199364 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14662931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 424300 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 17484 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 441784 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3927470 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3927470 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3927470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 424300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12665652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1356130 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 17484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 199364 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18590401 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 447836 # Total number of read requests seen +system.physmem.writeReqs 119953 # Total number of write requests seen +system.physmem.cpureqs 572898 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28661504 # Total number of bytes read from memory +system.physmem.bytesWritten 7676992 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28661504 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7676992 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3161 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28180 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28120 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28097 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27826 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27944 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27900 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27858 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27869 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28342 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28141 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28250 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28016 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27813 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27987 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27750 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7637 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7504 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7585 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7488 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7379 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7353 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7437 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7887 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7685 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7507 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7382 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7492 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7142 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7280 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1406 # Number of times wr buffer was full causing retry -system.physmem.totGap 1952670553500 # Total gap between requests +system.physmem.numWrRetry 1948 # Number of times wr buffer was full causing retry +system.physmem.totGap 1954684300500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 448125 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 121700 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 6945 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 407346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4785 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3654 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2681 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2639 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1535 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1508 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 771 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.readPktSize::6 447836 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 119953 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 407021 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4814 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3665 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1461 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -151,226 +138,224 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4798545467 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13448530467 # Sum of mem lat for all requests -system.physmem.totBusLat 2240285000 # Total cycles spent in databus access -system.physmem.totBankLat 6409700000 # Total cycles spent in bank access -system.physmem.avgQLat 10709.68 # Average queueing delay per request -system.physmem.avgBankLat 14305.55 # Average bank access latency per request +system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see +system.physmem.totQLat 4783798250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13397999500 # Sum of mem lat for all requests +system.physmem.totBusLat 2238835000 # Total cycles spent in databus access +system.physmem.totBankLat 6375366250 # Total cycles spent in bank access +system.physmem.avgQLat 10683.68 # Average queueing delay per request +system.physmem.avgBankLat 14238.13 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30015.22 # Average memory access latency -system.physmem.avgRdBW 14.69 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.69 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.94 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 29921.81 # Average memory access latency +system.physmem.avgRdBW 14.66 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.66 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 3.93 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.11 # Average write queue length over time -system.physmem.readRowHits 419119 # Number of row buffer hits during reads -system.physmem.writeRowHits 92373 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.79 # Row buffer hit rate for writes -system.physmem.avgGap 3435266.16 # Average gap between requests -system.l2c.replacements 341268 # number of replacements -system.l2c.tagsinuse 65240.270273 # Cycle average of tags in use -system.l2c.total_refs 2443367 # Total number of references to valid blocks. -system.l2c.sampled_refs 406244 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.014531 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6941595752 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55425.253207 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4870.495631 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4790.652765 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 116.277662 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 37.591009 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.845722 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.074318 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.073100 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001774 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000574 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.995488 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 687318 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 665852 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 314877 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 108330 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1776377 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 794206 # number of Writeback hits -system.l2c.Writeback_hits::total 794206 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 172 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 530 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 702 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 40 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 22 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 62 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 126888 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 47007 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 173895 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 687318 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 792740 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 314877 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 155337 # number of demand (read+write) hits -system.l2c.demand_hits::total 1950272 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 687318 # number of overall hits -system.l2c.overall_hits::cpu0.data 792740 # number of overall hits -system.l2c.overall_hits::cpu1.inst 314877 # number of overall hits -system.l2c.overall_hits::cpu1.data 155337 # number of overall hits -system.l2c.overall_hits::total 1950272 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 12972 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271609 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 561 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 240 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285382 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2946 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1731 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4677 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 877 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 894 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1771 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 115472 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6625 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122097 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 12972 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 387081 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 561 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6865 # number of demand (read+write) misses -system.l2c.demand_misses::total 407479 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 12972 # number of overall misses -system.l2c.overall_misses::cpu0.data 387081 # number of overall misses -system.l2c.overall_misses::cpu1.inst 561 # number of overall misses -system.l2c.overall_misses::cpu1.data 6865 # number of overall misses -system.l2c.overall_misses::total 407479 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 816098500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 11712193000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 36330000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 18796500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 12583418000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1197000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 9651997 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 10848997 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 863000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 182500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1045500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5538652000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 375096499 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 5913748499 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 816098500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 17250845000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 36330000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 393892999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 18497166499 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 816098500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 17250845000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 36330000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 393892999 # number of overall miss cycles -system.l2c.overall_miss_latency::total 18497166499 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 700290 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 937461 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 315438 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 108570 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2061759 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 794206 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 794206 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3118 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2261 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5379 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 917 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 916 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1833 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 242360 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 53632 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 295992 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 700290 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1179821 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 315438 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 162202 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2357751 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 700290 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1179821 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 315438 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 162202 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2357751 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.018524 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.289728 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.001778 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.002211 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.138417 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.944836 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.765590 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.869492 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.956379 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975983 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.966176 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.476448 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.123527 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.412501 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018524 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.328085 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.001778 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.042324 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.172825 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018524 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.328085 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.001778 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.042324 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.172825 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 62912.311132 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 43121.520274 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 64759.358289 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 78318.750000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 44093.243442 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 406.313646 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5575.965916 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2319.648706 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 984.036488 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 204.138702 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 590.344438 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 47965.324927 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 56618.339472 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 48434.838686 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 62912.311132 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 44566.499002 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 64759.358289 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 57376.984559 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 45394.158960 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 62912.311132 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 44566.499002 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 64759.358289 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 57376.984559 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 45394.158960 # average overall miss latency +system.physmem.avgWrQLen 10.91 # Average write queue length over time +system.physmem.readRowHits 419870 # Number of row buffer hits during reads +system.physmem.writeRowHits 92076 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.77 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 76.76 # Row buffer hit rate for writes +system.physmem.avgGap 3442624.46 # Average gap between requests +system.l2c.replacements 340771 # number of replacements +system.l2c.tagsinuse 65303.436480 # Cycle average of tags in use +system.l2c.total_refs 2493415 # Total number of references to valid blocks. +system.l2c.sampled_refs 405943 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.142279 # Average number of references to valid blocks. +system.l2c.warmup_cycle 6937754751 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 55559.705668 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4839.489270 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4775.815267 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 117.980929 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 10.445347 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.847774 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.073845 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.072873 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.001800 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000159 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996451 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 902966 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 773506 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 86370 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 33767 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1796609 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 820435 # number of Writeback hits +system.l2c.Writeback_hits::total 820435 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 163 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 56 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 219 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 21 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 19 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 40 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 171833 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 12858 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 184691 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 902966 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 945339 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 86370 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 46625 # number of demand (read+write) hits +system.l2c.demand_hits::total 1981300 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 902966 # number of overall hits +system.l2c.overall_hits::cpu0.data 945339 # number of overall hits +system.l2c.overall_hits::cpu1.inst 86370 # number of overall hits +system.l2c.overall_hits::cpu1.data 46625 # number of overall hits +system.l2c.overall_hits::total 1981300 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 12959 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 271596 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 545 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 189 # number of ReadReq misses +system.l2c.ReadReq_misses::total 285289 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 483 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2925 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 27 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 73 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 100 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 115623 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 5918 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 121541 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 12959 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 387219 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 545 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 6107 # number of demand (read+write) misses +system.l2c.demand_misses::total 406830 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 12959 # number of overall misses +system.l2c.overall_misses::cpu0.data 387219 # number of overall misses +system.l2c.overall_misses::cpu1.inst 545 # number of overall misses +system.l2c.overall_misses::cpu1.data 6107 # number of overall misses +system.l2c.overall_misses::total 406830 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 800348000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 11682390000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 34833000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 14789000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 12532360000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1038000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 229000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1267000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 22500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 115000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 137500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5536684000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 338210000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 5874894000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 800348000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 17219074000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 34833000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 352999000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 18407254000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 800348000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 17219074000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 34833000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 352999000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 18407254000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 915925 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1045102 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 86915 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 33956 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2081898 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 820435 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 820435 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2605 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 539 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3144 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 48 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 92 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 140 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 287456 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 18776 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 306232 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 915925 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1332558 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 86915 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 52732 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2388130 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 915925 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1332558 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 86915 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 52732 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2388130 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014149 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.259875 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.006270 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.005566 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.137033 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.937428 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.896104 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.930344 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.562500 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.793478 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.714286 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.402229 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.315190 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.396892 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014149 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.290583 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.006270 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.115812 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.170355 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014149 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.290583 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.006270 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.115812 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.170355 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 61760.012347 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 43013.851456 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 63913.761468 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 78248.677249 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 43928.647792 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 425.061425 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 474.120083 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 433.162393 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 833.333333 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1575.342466 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1375 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 47885.662887 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 57149.374789 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 48336.725879 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 61760.012347 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 44468.566883 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 63913.761468 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 57802.357950 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 45245.566944 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 61760.012347 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 44468.566883 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 63913.761468 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 57802.357950 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 45245.566944 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,119 +364,119 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 78774 # number of writebacks -system.l2c.writebacks::total 78774 # number of writebacks +system.l2c.writebacks::writebacks 78433 # number of writebacks +system.l2c.writebacks::total 78433 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 12972 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 271609 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 550 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 240 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 285371 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2946 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1731 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 4677 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 877 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 894 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1771 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 115472 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 6625 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 122097 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 12972 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 387081 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 550 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 6865 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 407468 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 12972 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 387081 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 550 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 6865 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 407468 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 652870719 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8377504856 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 28860821 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 15792455 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 9075028851 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29675441 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 17410227 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 47085668 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8897310 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 8940894 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 17838204 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4112913546 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 291507382 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4404420928 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 652870719 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 12490418402 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 28860821 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 307299837 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 13479449779 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 652870719 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 12490418402 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 28860821 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 307299837 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 13479449779 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1372964000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18171500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1391135500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2145152500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 673668500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2818821000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3518116500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 691840000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4209956500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018524 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.289728 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001744 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002211 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.138411 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.944836 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.765590 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.869492 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.956379 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975983 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.966176 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.476448 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.123527 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.412501 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018524 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.328085 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001744 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.042324 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.172821 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018524 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.328085 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001744 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.042324 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.172821 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 50329.225948 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30843.988439 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 52474.220000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65801.895833 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 31800.809651 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10073.130007 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10057.901213 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10067.493693 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10145.165336 # average SCUpgradeReq mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 12959 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 271596 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 534 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 189 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 285278 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2442 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 483 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2925 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 27 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 73 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 100 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 115623 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 5918 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 121541 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 12959 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 387219 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 534 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 6107 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 406819 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 12959 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 387219 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 534 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 6107 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 406819 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 637272201 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8347679089 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 27561783 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12429436 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 9024942509 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 24585937 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4830483 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 29416420 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 270027 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 730073 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 1000100 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4108844602 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 263408851 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4372253453 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 637272201 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 12456523691 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 27561783 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 275838287 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 13397195962 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 637272201 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 12456523691 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 27561783 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 275838287 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 13397195962 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373082000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18171000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1391253000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1972248000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 500755000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2473003000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3345330000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 518926000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3864256000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014149 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.259875 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.006144 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.005566 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.137028 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.937428 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.896104 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.930344 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.562500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.793478 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.714286 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.402229 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.315190 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.396892 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014149 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.290583 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006144 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.115812 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.170350 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014149 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.290583 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006144 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.115812 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.170350 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 49176.032178 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30735.648128 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 51613.825843 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65764.211640 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 31635.606352 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10067.951269 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10056.895726 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10072.390740 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 35618.275824 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 44001.114264 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 36073.129790 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 50329.225948 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32268.229136 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 52474.220000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44763.268318 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 33081.002138 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50329.225948 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32268.229136 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52474.220000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44763.268318 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 33081.002138 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 35536.568001 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 44509.775431 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 35973.485927 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49176.032178 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32169.195445 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 51613.825843 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 45167.559686 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 32931.588648 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49176.032178 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32169.195445 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51613.825843 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 45167.559686 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 32931.588648 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -502,39 +487,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41696 # number of replacements -system.iocache.tagsinuse 0.569993 # Cycle average of tags in use +system.iocache.replacements 41694 # number of replacements +system.iocache.tagsinuse 0.572561 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1746698431000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.569993 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.035625 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.035625 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses -system.iocache.ReadReq_misses::total 176 # number of ReadReq misses +system.iocache.warmup_cycle 1746701282000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.572561 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.035785 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.035785 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses -system.iocache.demand_misses::total 41728 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses -system.iocache.overall_misses::total 41728 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21268998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21268998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10634917806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10634917806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10656186804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10656186804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10656186804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10656186804 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21042998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21042998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10674900806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10674900806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10695943804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10695943804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10695943804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10695943804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -543,40 +528,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255942.380776 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 255942.380776 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 255372.574866 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 255372.574866 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 255372.574866 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 255372.574866 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 284837 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120936.770115 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120936.770115 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256904.620861 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 256904.620861 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 256337.626516 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 256337.626516 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 256337.626516 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 256337.626516 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 286340 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27190 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27291 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.475800 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.492104 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116250 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12116250 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8472911060 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8472911060 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8485027310 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8485027310 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8485027310 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8485027310 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11994249 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11994249 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8512910554 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8512910554 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8524904803 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8524904803 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8524904803 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8524904803 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -585,14 +570,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68842.329545 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68842.329545 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203911.028591 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 203911.028591 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68932.465517 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68932.465517 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204873.665624 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204873.665624 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204306.782414 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 204306.782414 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204306.782414 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 204306.782414 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -610,22 +595,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7490982 # DTB read hits -system.cpu0.dtb.read_misses 7443 # DTB read misses +system.cpu0.dtb.read_hits 8631552 # DTB read hits +system.cpu0.dtb.read_misses 7447 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5068153 # DTB write hits +system.cpu0.dtb.read_accesses 490676 # DTB read accesses +system.cpu0.dtb.write_hits 6044616 # DTB write hits system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12559135 # DTB hits -system.cpu0.dtb.data_misses 8256 # DTB misses +system.cpu0.dtb.data_hits 14676168 # DTB hits +system.cpu0.dtb.data_misses 8260 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations -system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3503456 # ITB hits +system.cpu0.dtb.data_accesses 678128 # DTB accesses +system.cpu0.itb.fetch_hits 3853435 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3507327 # ITB accesses +system.cpu0.itb.fetch_accesses 3857306 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -638,55 +623,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3904305293 # number of cpu cycles simulated +system.cpu0.numCycles 3908211536 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47706703 # Number of instructions committed -system.cpu0.committedOps 47706703 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44241786 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 211423 # Number of float alu accesses -system.cpu0.num_func_calls 1201591 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5601417 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44241786 # number of integer instructions -system.cpu0.num_fp_insts 211423 # number of float instructions -system.cpu0.num_int_register_reads 60797943 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32968604 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102697 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 104564 # number of times the floating registers were written -system.cpu0.num_mem_refs 12599388 # number of memory refs -system.cpu0.num_load_insts 7518173 # Number of load instructions -system.cpu0.num_store_insts 5081215 # Number of store instructions -system.cpu0.num_idle_cycles 3700976170.173713 # Number of idle cycles -system.cpu0.num_busy_cycles 203329122.826288 # Number of busy cycles -system.cpu0.not_idle_fraction 0.052078 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.947922 # Percentage of idle cycles +system.cpu0.committedInsts 54061829 # Number of instructions committed +system.cpu0.committedOps 54061829 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 50032862 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 294101 # Number of float alu accesses +system.cpu0.num_func_calls 1426501 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6236445 # number of instructions that are conditional controls +system.cpu0.num_int_insts 50032862 # number of integer instructions +system.cpu0.num_fp_insts 294101 # number of float instructions +system.cpu0.num_int_register_reads 68513770 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37070851 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 143419 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 146520 # number of times the floating registers were written +system.cpu0.num_mem_refs 14722187 # number of memory refs +system.cpu0.num_load_insts 8662865 # Number of load instructions +system.cpu0.num_store_insts 6059322 # Number of store instructions +system.cpu0.num_idle_cycles 3679287399.643625 # Number of idle cycles +system.cpu0.num_busy_cycles 228924136.356375 # Number of busy cycles +system.cpu0.not_idle_fraction 0.058575 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.941425 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6787 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 165132 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56916 40.19% 40.19% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1973 1.39% 41.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 418 0.30% 41.97% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82194 58.03% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141632 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56372 49.08% 49.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 418 0.36% 51.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55954 48.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114848 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1900150859000 97.34% 97.34% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 92973000 0.00% 97.34% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 760723500 0.04% 97.38% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 310562000 0.02% 97.40% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 50837499000 2.60% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1952152616500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990442 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6369 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 202997 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 72749 40.62% 40.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.07% 40.70% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1975 1.10% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 104220 58.20% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 179081 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 71382 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1975 1.36% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 71376 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 144870 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1898301273000 97.14% 97.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 93023500 0.00% 97.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 762236500 0.04% 97.19% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 5235500 0.00% 97.19% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 54943969500 2.81% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1954105738000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981209 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.680755 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810890 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684859 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808964 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -718,37 +703,37 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 500 0.33% 0.33% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3074 2.05% 2.39% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134771 89.88% 92.30% # number of callpals executed -system.cpu0.kern.callpal::rdps 6676 4.45% 96.75% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::rti 4338 2.89% 99.66% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149953 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6892 # number of protection mode switches +system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3896 2.07% 2.12% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.15% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.15% # number of callpals executed +system.cpu0.kern.callpal::swpipl 172217 91.50% 93.65% # number of callpals executed +system.cpu0.kern.callpal::rdps 6678 3.55% 97.19% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 97.20% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed +system.cpu0.kern.callpal::rti 4751 2.52% 99.73% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed +system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 188224 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7304 # number of protection mode switches system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1283 system.cpu0.kern.mode_good::user 1283 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186158 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.175657 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.313884 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1948377502000 99.82% 99.82% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3456174500 0.18% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.298824 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1950347295500 99.82% 99.82% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3454635500 0.18% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3075 # number of times the context was actually changed +system.cpu0.kern.swap_context 3897 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -780,51 +765,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 699703 # number of replacements -system.cpu0.icache.tagsinuse 509.161264 # Cycle average of tags in use -system.cpu0.icache.total_refs 47014995 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 700215 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 67.143656 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 32599184000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.161264 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.994456 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.994456 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 47014995 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47014995 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47014995 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47014995 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47014995 # number of overall hits -system.cpu0.icache.overall_hits::total 47014995 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 700308 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 700308 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 700308 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 700308 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 700308 # number of overall misses -system.cpu0.icache.overall_misses::total 700308 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9851397000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9851397000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9851397000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9851397000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9851397000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9851397000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47715303 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47715303 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47715303 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47715303 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47715303 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47715303 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014677 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014677 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014677 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014677 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014677 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014677 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14067.234702 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14067.234702 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14067.234702 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14067.234702 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14067.234702 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14067.234702 # average overall miss latency +system.cpu0.icache.replacements 915312 # number of replacements +system.cpu0.icache.tagsinuse 509.170565 # Cycle average of tags in use +system.cpu0.icache.total_refs 53154487 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 915824 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 58.040068 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 32594703000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.170565 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.994474 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.994474 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 53154487 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 53154487 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 53154487 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 53154487 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 53154487 # number of overall hits +system.cpu0.icache.overall_hits::total 53154487 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 915946 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 915946 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 915946 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 915946 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 915946 # number of overall misses +system.cpu0.icache.overall_misses::total 915946 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12645153500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12645153500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12645153500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12645153500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12645153500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12645153500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 54070433 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 54070433 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 54070433 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 54070433 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 54070433 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 54070433 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016940 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.016940 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016940 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.016940 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016940 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.016940 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13805.566595 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13805.566595 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13805.566595 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13805.566595 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13805.566595 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13805.566595 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -833,112 +818,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700308 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 700308 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 700308 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 700308 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 700308 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 700308 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8450781000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8450781000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8450781000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8450781000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8450781000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8450781000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014677 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014677 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014677 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014677 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014677 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014677 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12067.234702 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12067.234702 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12067.234702 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915946 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 915946 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 915946 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 915946 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 915946 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 915946 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10813261500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10813261500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10813261500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10813261500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10813261500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10813261500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016940 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016940 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016940 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11805.566595 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11805.566595 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11805.566595 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1182211 # number of replacements -system.cpu0.dcache.tagsinuse 505.184188 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11367781 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1182629 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.612297 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1337909 # number of replacements +system.cpu0.dcache.tagsinuse 506.537579 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13346950 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1338324 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.972884 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 93616000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.184188 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.986688 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.986688 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6409561 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6409561 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4659572 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4659572 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140562 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 140562 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148239 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 148239 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11069133 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11069133 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11069133 # number of overall hits -system.cpu0.dcache.overall_hits::total 11069133 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 939643 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 939643 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 251886 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 251886 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13649 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13649 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5418 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5418 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1191529 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1191529 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1191529 # number of overall misses -system.cpu0.dcache.overall_misses::total 1191529 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 21121102500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 21121102500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7642676000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7642676000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149168500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 149168500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 41236000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 41236000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 28763778500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 28763778500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 28763778500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 28763778500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7349204 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7349204 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4911458 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4911458 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154211 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 154211 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153657 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153657 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12260662 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12260662 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12260662 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12260662 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127856 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127856 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051285 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051285 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088509 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088509 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035260 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035260 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097183 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097183 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097183 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097183 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22477.794758 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 22477.794758 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30341.805420 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 30341.805420 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10928.895890 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10928.895890 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7610.926541 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7610.926541 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24140.225290 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 24140.225290 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24140.225290 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 24140.225290 # average overall miss latency +system.cpu0.dcache.occ_blocks::cpu0.data 506.537579 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.989331 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.989331 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7419116 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7419116 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5560491 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5560491 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176356 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 176356 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191669 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 191669 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12979607 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12979607 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12979607 # number of overall hits +system.cpu0.dcache.overall_hits::total 12979607 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1035921 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1035921 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 291041 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 291041 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16710 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16710 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 430 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 430 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1326962 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1326962 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1326962 # number of overall misses +system.cpu0.dcache.overall_misses::total 1326962 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 22391252000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 22391252000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8190685500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8190685500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 219165000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 219165000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2509000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 2509000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 30581937500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 30581937500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 30581937500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 30581937500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8455037 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8455037 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5851532 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5851532 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193066 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 193066 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192099 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 192099 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14306569 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14306569 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14306569 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14306569 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122521 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.122521 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049738 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049738 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086551 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086551 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002238 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002238 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092752 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092752 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092752 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092752 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21614.825841 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 21614.825841 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28142.720441 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 28142.720441 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13115.798923 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13115.798923 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5834.883721 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5834.883721 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23046.581213 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 23046.581213 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23046.581213 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23046.581213 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -947,62 +932,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 680601 # number of writebacks -system.cpu0.dcache.writebacks::total 680601 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939643 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 939643 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251886 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 251886 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13649 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13649 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5418 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5418 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1191529 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1191529 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1191529 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1191529 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19241816500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19241816500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7138904000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7138904000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121870500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121870500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30400000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30400000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26380720500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 26380720500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26380720500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 26380720500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465344500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465344500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2274931000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2274931000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3740275500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3740275500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127856 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127856 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051285 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051285 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088509 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088509 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035260 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035260 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097183 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097183 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20477.794758 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20477.794758 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28341.805420 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28341.805420 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8928.895890 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8928.895890 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5610.926541 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5610.926541 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 789805 # number of writebacks +system.cpu0.dcache.writebacks::total 789805 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1035921 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1035921 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291041 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 291041 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16710 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16710 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 430 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 430 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326962 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1326962 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326962 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1326962 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 20319410000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 20319410000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7608603500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7608603500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 185745000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 185745000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1649000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1649000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 27928013500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 27928013500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 27928013500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 27928013500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465455500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465455500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2092162000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092162000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3557617500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3557617500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122521 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122521 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049738 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049738 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086551 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086551 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002238 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002238 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092752 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092752 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092752 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092752 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 19614.825841 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19614.825841 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26142.720441 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26142.720441 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11115.798923 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11115.798923 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3834.883721 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3834.883721 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21046.581213 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21046.581213 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21046.581213 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21046.581213 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1014,22 +999,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2417694 # DTB read hits +system.cpu1.dtb.read_hits 1047086 # DTB read hits system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1754404 # DTB write hits +system.cpu1.dtb.write_hits 650181 # DTB write hits system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4172098 # DTB hits +system.cpu1.dtb.data_hits 1697267 # DTB hits system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1961503 # ITB hits +system.cpu1.itb.fetch_hits 1487534 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1962719 # ITB accesses +system.cpu1.itb.fetch_accesses 1488750 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1042,51 +1027,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3905448539 # number of cpu cycles simulated +system.cpu1.numCycles 3909382743 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13160532 # Number of instructions committed -system.cpu1.committedOps 13160532 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12141335 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 171917 # Number of float alu accesses -system.cpu1.num_func_calls 411397 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1307333 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12141335 # number of integer instructions -system.cpu1.num_fp_insts 171917 # number of float instructions -system.cpu1.num_int_register_reads 16724790 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8912820 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 89976 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 91834 # number of times the floating registers were written -system.cpu1.num_mem_refs 4195541 # number of memory refs -system.cpu1.num_load_insts 2431931 # Number of load instructions -system.cpu1.num_store_insts 1763610 # Number of store instructions -system.cpu1.num_idle_cycles 3855992964.998025 # Number of idle cycles -system.cpu1.num_busy_cycles 49455574.001975 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012663 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987337 # Percentage of idle cycles +system.cpu1.committedInsts 5259785 # Number of instructions committed +system.cpu1.committedOps 5259785 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 4928462 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses +system.cpu1.num_func_calls 156703 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 508760 # number of instructions that are conditional controls +system.cpu1.num_int_insts 4928462 # number of integer instructions +system.cpu1.num_fp_insts 34031 # number of float instructions +system.cpu1.num_int_register_reads 6858583 # number of times the integer registers were read +system.cpu1.num_int_register_writes 3715950 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written +system.cpu1.num_mem_refs 1706720 # number of memory refs +system.cpu1.num_load_insts 1053093 # Number of load instructions +system.cpu1.num_store_insts 653627 # Number of store instructions +system.cpu1.num_idle_cycles 3890042761.998010 # Number of idle cycles +system.cpu1.num_busy_cycles 19339981.001990 # Number of busy cycles +system.cpu1.not_idle_fraction 0.004947 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.995053 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2696 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 78331 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26451 38.35% 38.35% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1967 2.85% 41.20% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 500 0.72% 41.92% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40063 58.08% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 68981 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25618 48.15% 48.15% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1967 3.70% 51.85% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 500 0.94% 52.79% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25118 47.21% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53203 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909244973500 97.77% 97.77% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 705660500 0.04% 97.81% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 346600000 0.02% 97.83% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 42426277500 2.17% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1952723511500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968508 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2297 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 35535 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 8961 31.73% 31.73% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1969 6.97% 38.70% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 88 0.31% 39.01% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 17223 60.99% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 28241 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 8951 45.05% 45.05% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1969 9.91% 54.95% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 88 0.44% 55.40% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 8863 44.60% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 19871 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1917858613000 98.12% 98.12% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 705516000 0.04% 98.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 59546500 0.00% 98.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 36066938000 1.85% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1954690613500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998884 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.626963 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.771270 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.514603 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.703622 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -1102,81 +1087,81 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 418 0.59% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1983 2.78% 3.37% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62750 88.03% 91.41% # number of callpals executed -system.cpu1.kern.callpal::rdps 2168 3.04% 94.46% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed -system.cpu1.kern.callpal::rti 3763 5.28% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 337 1.17% 1.20% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 1.21% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.23% # number of callpals executed +system.cpu1.kern.callpal::swpipl 23653 81.85% 83.08% # number of callpals executed +system.cpu1.kern.callpal::rdps 2170 7.51% 90.59% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 90.59% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 90.61% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 90.62% # number of callpals executed +system.cpu1.kern.callpal::rti 2530 8.75% 99.37% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.47% 99.84% # number of callpals executed +system.cpu1.kern.callpal::imb 44 0.15% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71284 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2048 # number of protection mode switches -system.cpu1.kern.mode_switch::user 465 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2876 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 889 -system.cpu1.kern.mode_good::user 465 -system.cpu1.kern.mode_good::idle 424 -system.cpu1.kern.mode_switch_good::kernel 0.434082 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 28898 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 803 # number of protection mode switches +system.cpu1.kern.mode_switch::user 464 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 477 +system.cpu1.kern.mode_good::user 464 +system.cpu1.kern.mode_good::idle 13 +system.cpu1.kern.mode_switch_good::kernel 0.594022 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.147427 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.329931 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17784732000 0.91% 0.91% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1713538500 0.09% 1.00% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1933225237500 99.00% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1984 # number of times the context was actually changed -system.cpu1.icache.replacements 314891 # number of replacements -system.cpu1.icache.tagsinuse 448.025093 # Cycle average of tags in use -system.cpu1.icache.total_refs 12848456 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 315403 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 40.736632 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1950842738500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 448.025093 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.875049 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.875049 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 12848456 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12848456 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12848456 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12848456 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12848456 # number of overall hits -system.cpu1.icache.overall_hits::total 12848456 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 315439 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 315439 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 315439 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 315439 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 315439 # number of overall misses -system.cpu1.icache.overall_misses::total 315439 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4168917000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4168917000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4168917000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4168917000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4168917000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4168917000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13163895 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13163895 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13163895 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13163895 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13163895 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13163895 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023962 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023962 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023962 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023962 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023962 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023962 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13216.238322 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13216.238322 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13216.238322 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13216.238322 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.006295 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.286315 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 3558805000 0.18% 0.18% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1714794500 0.09% 0.27% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1949417010500 99.73% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 338 # number of times the context was actually changed +system.cpu1.icache.replacements 86368 # number of replacements +system.cpu1.icache.tagsinuse 420.702382 # Cycle average of tags in use +system.cpu1.icache.total_refs 5176232 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 86880 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 59.579098 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1938927920500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 420.702382 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.821684 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.821684 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 5176232 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5176232 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 5176232 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5176232 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 5176232 # number of overall hits +system.cpu1.icache.overall_hits::total 5176232 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 86916 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 86916 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 86916 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 86916 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 86916 # number of overall misses +system.cpu1.icache.overall_misses::total 86916 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1175951500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1175951500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1175951500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1175951500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1175951500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1175951500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 5263148 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5263148 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 5263148 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5263148 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 5263148 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5263148 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016514 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.016514 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016514 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.016514 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016514 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.016514 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.747112 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13529.747112 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13529.747112 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13529.747112 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13529.747112 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13529.747112 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1185,112 +1170,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 315439 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 315439 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 315439 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 315439 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 315439 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 315439 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3538039000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3538039000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3538039000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3538039000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3538039000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3538039000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023962 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.023962 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.023962 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11216.238322 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11216.238322 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11216.238322 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 86916 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 86916 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 86916 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 86916 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 86916 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 86916 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1002119500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1002119500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1002119500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1002119500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1002119500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1002119500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016514 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.016514 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.016514 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11529.747112 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11529.747112 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11529.747112 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 165415 # number of replacements -system.cpu1.dcache.tagsinuse 486.567196 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4004380 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 165927 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 24.133384 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 60834829000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 486.567196 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.950327 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.950327 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 2254351 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2254351 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1637565 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1637565 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47962 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 47962 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50536 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50536 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3891916 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3891916 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3891916 # number of overall hits -system.cpu1.dcache.overall_hits::total 3891916 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 117672 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 117672 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 62334 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 62334 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8861 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8861 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5817 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5817 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 180006 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 180006 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 180006 # number of overall misses -system.cpu1.dcache.overall_misses::total 180006 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1427906500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1427906500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1084822000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1084822000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81394000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 81394000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 42192000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 42192000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2512728500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2512728500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2512728500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2512728500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2372023 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2372023 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1699899 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1699899 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56823 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 56823 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56353 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 56353 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4071922 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4071922 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4071922 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4071922 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049608 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049608 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036669 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.036669 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155940 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155940 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103224 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103224 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044207 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044207 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044207 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044207 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12134.632708 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12134.632708 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17403.375365 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17403.375365 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.644961 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.644961 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7253.223311 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7253.223311 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13959.137473 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 13959.137473 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13959.137473 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 13959.137473 # average overall miss latency +system.cpu1.dcache.replacements 52807 # number of replacements +system.cpu1.dcache.tagsinuse 417.673106 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1641018 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 53319 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 30.777359 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1938580812000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 417.673106 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.815768 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.815768 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1001238 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1001238 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 616220 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 616220 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 10806 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 10806 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11203 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 11203 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1617458 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1617458 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1617458 # number of overall hits +system.cpu1.dcache.overall_hits::total 1617458 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 37008 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 37008 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 20401 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 20401 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 956 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 956 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 500 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 500 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 57409 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 57409 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 57409 # number of overall misses +system.cpu1.dcache.overall_misses::total 57409 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 463706500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 463706500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 540901000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 540901000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 10601500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 10601500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3694000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3694000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 1004607500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 1004607500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 1004607500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 1004607500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1038246 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1038246 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 636621 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 636621 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 11762 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 11762 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 11703 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 11703 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1674867 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1674867 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1674867 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1674867 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035645 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035645 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032046 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.032046 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081279 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.081279 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.042724 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.042724 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034277 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.034277 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034277 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034277 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12529.898941 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12529.898941 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26513.455223 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 26513.455223 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11089.435146 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11089.435146 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7388 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7388 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17499.129056 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17499.129056 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17499.129056 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17499.129056 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1299,62 +1284,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 113605 # number of writebacks -system.cpu1.dcache.writebacks::total 113605 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117672 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 117672 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62334 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 62334 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8861 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8861 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5817 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5817 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 180006 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 180006 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 180006 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 180006 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1192562500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1192562500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 960154000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 960154000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63672000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 63672000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30558000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30558000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2152716500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2152716500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2152716500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2152716500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19380500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19380500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 712390500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 712390500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 731771000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 731771000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049608 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049608 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036669 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036669 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155940 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155940 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103224 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103224 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044207 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044207 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10134.632708 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10134.632708 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15403.375365 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15403.375365 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7185.644961 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7185.644961 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5253.223311 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5253.223311 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 30630 # number of writebacks +system.cpu1.dcache.writebacks::total 30630 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37008 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 37008 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20401 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 20401 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 956 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 956 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 500 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 500 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 57409 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 57409 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 57409 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 57409 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 389690500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 389690500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 500099000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 500099000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8689500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8689500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2694000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2694000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 889789500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 889789500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 889789500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 889789500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19380000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19380000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 529600000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 529600000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 548980000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 548980000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035645 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035645 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032046 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032046 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.081279 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.081279 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.042724 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.042724 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034277 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.034277 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034277 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034277 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10529.898941 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10529.898941 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24513.455223 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24513.455223 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9089.435146 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9089.435146 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5388 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5388 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15499.129056 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15499.129056 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15499.129056 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15499.129056 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 37fa2c1e1..10a028441 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,135 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.910548 # Number of seconds simulated -sim_ticks 1910547559000 # Number of ticks simulated -final_tick 1910547559000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.913475 # Number of seconds simulated +sim_ticks 1913474690000 # Number of ticks simulated +final_tick 1913474690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1284259 # Simulator instruction rate (inst/s) -host_op_rate 1284258 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43720523895 # Simulator tick rate (ticks/s) -host_mem_usage 330356 # Number of bytes of host memory used -host_seconds 43.70 # Real time elapsed on the host -sim_insts 56120911 # Number of instructions simulated -sim_ops 56120911 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858368 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28361344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7404352 # Number of bytes written to this memory -system.physmem.bytes_written::total 7404352 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388412 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443146 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115693 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115693 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 445225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13011122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1388268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14844616 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 445225 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 445225 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3875513 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3875513 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3875513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 445225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13011122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1388268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18720129 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 443146 # Total number of read requests seen -system.physmem.writeReqs 115693 # Total number of write requests seen -system.physmem.cpureqs 561589 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28361344 # Total number of bytes read from memory -system.physmem.bytesWritten 7404352 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28361344 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7404352 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 45 # Number of read reqs serviced by write Q +host_inst_rate 1324010 # Simulator instruction rate (inst/s) +host_op_rate 1324010 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45134311907 # Simulator tick rate (ticks/s) +host_mem_usage 328328 # Number of bytes of host memory used +host_seconds 42.40 # Real time elapsed on the host +sim_insts 56131527 # Number of instructions simulated +sim_ops 56131527 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24859456 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652096 # Number of bytes read from this memory +system.physmem.bytes_read::total 28362112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7404992 # Number of bytes written to this memory +system.physmem.bytes_written::total 7404992 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388429 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41439 # Number of read requests responded to by this memory +system.physmem.num_reads::total 443158 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115703 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115703 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 444511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12991787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1386010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14822308 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 444511 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 444511 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3869919 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3869919 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3869919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 444511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12991787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1386010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18692227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 443158 # Total number of read requests seen +system.physmem.writeReqs 115703 # Total number of write requests seen +system.physmem.cpureqs 560726 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28362112 # Total number of bytes read from memory +system.physmem.bytesWritten 7404992 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28362112 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7404992 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 61 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 27901 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27706 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 27906 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27707 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 27556 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27375 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27383 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 27676 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 27765 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27827 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27615 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28008 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27828 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27614 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28005 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 27777 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 27792 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27562 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27598 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27733 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27646 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27564 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7483 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7263 # Track writes on a per bank basis +system.physmem.perBankRdReqs::11 27558 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27591 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27731 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27648 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27560 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7488 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7264 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 7148 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7032 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7167 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7214 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7312 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7182 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7584 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7040 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7173 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7213 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7315 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7181 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7581 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 7357 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 7354 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7067 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7113 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7079 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7063 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7148 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7186 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7115 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7077 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2065 # Number of times wr buffer was full causing retry -system.physmem.totGap 1910535659000 # Total gap between requests +system.physmem.numWrRetry 1735 # Number of times wr buffer was full causing retry +system.physmem.totGap 1913462790000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 443146 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 117758 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 130 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 402456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4645 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2964 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2589 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1544 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1412 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1360 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1491 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 759 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see +system.physmem.readPktSize::6 443158 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 115703 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 402452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3681 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2703 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2646 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1461 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1423 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1604 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -141,20 +128,19 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5001 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5031 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 5030 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 5030 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 5030 # What write queue length does an incoming req see @@ -165,46 +151,45 @@ system.physmem.wrQLenPdf::19 5030 # Wh system.physmem.wrQLenPdf::20 5030 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5030 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4718066660 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13230246660 # Sum of mem lat for all requests -system.physmem.totBusLat 2215505000 # Total cycles spent in databus access -system.physmem.totBankLat 6296675000 # Total cycles spent in bank access -system.physmem.avgQLat 10647.84 # Average queueing delay per request -system.physmem.avgBankLat 14210.47 # Average bank access latency per request +system.physmem.totQLat 4718928250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13231418250 # Sum of mem lat for all requests +system.physmem.totBusLat 2215485000 # Total cycles spent in databus access +system.physmem.totBankLat 6297005000 # Total cycles spent in bank access +system.physmem.avgQLat 10649.88 # Average queueing delay per request +system.physmem.avgBankLat 14211.35 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29858.31 # Average memory access latency -system.physmem.avgRdBW 14.84 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.88 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.84 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.88 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 29861.22 # Average memory access latency +system.physmem.avgRdBW 14.82 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 3.87 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.82 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 3.87 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 11.47 # Average write queue length over time -system.physmem.readRowHits 415807 # Number of row buffer hits during reads -system.physmem.writeRowHits 89941 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.84 # Row buffer hit rate for reads +system.physmem.avgWrQLen 9.64 # Average write queue length over time +system.physmem.readRowHits 415747 # Number of row buffer hits during reads +system.physmem.writeRowHits 89943 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.83 # Row buffer hit rate for reads system.physmem.writeRowHitRate 77.74 # Row buffer hit rate for writes -system.physmem.avgGap 3418758.64 # Average gap between requests +system.physmem.avgGap 3423861.73 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.342284 # Cycle average of tags in use +system.iocache.tagsinuse 1.364719 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1745701071000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.342284 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.083893 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.083893 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1745699710000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.364719 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.085295 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.085295 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -215,12 +200,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10644331806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10644331806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10665259804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10665259804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10665259804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10665259804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10661973806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10661973806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10682901804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10682901804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10682901804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10682901804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -239,17 +224,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256168.940268 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 256168.940268 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 255608.383559 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 255608.383559 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 255608.383559 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 255608.383559 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 285028 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256593.516702 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 256593.516702 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 256031.199617 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 256031.199617 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 256031.199617 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 256031.199617 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 285723 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27152 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27146 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.497496 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.525418 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -263,14 +248,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931250 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11931250 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8482336109 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8482336109 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8494267359 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8494267359 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8494267359 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8494267359 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8499962078 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8499962078 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8511893327 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8511893327 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8511893327 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8511893327 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -279,14 +264,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204137.853990 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 204137.853990 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203577.408244 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 203577.408244 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203577.408244 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 203577.408244 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204562.044619 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204562.044619 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203999.840072 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203999.840072 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203999.840072 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203999.840072 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -304,22 +289,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9055197 # DTB read hits +system.cpu.dtb.read_hits 9056964 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6350929 # DTB write hits +system.cpu.dtb.write_hits 6352252 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15406126 # DTB hits +system.cpu.dtb.data_hits 15409216 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974131 # ITB hits +system.cpu.itb.fetch_hits 4974658 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979137 # ITB accesses +system.cpu.itb.fetch_accesses 4979664 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -332,51 +317,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3821095118 # number of cpu cycles simulated +system.cpu.numCycles 3826949380 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56120911 # Number of instructions committed -system.cpu.committedOps 56120911 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 51995405 # Number of integer alu accesses +system.cpu.committedInsts 56131527 # Number of instructions committed +system.cpu.committedOps 56131527 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52005592 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses -system.cpu.num_func_calls 1481756 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6462892 # number of instructions that are conditional controls -system.cpu.num_int_insts 51995405 # number of integer instructions +system.cpu.num_func_calls 1482234 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6464100 # number of instructions that are conditional controls +system.cpu.num_int_insts 52005592 # number of integer instructions system.cpu.num_fp_insts 324259 # number of float instructions -system.cpu.num_int_register_reads 71234690 # number of times the integer registers were read -system.cpu.num_int_register_writes 38473511 # number of times the integer registers were written +system.cpu.num_int_register_reads 71250465 # number of times the integer registers were read +system.cpu.num_int_register_writes 38480970 # number of times the integer registers were written system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written -system.cpu.num_mem_refs 15458726 # number of memory refs -system.cpu.num_load_insts 9092044 # Number of load instructions -system.cpu.num_store_insts 6366682 # Number of store instructions -system.cpu.num_idle_cycles 3587142255.998123 # Number of idle cycles -system.cpu.num_busy_cycles 233952862.001878 # Number of busy cycles -system.cpu.not_idle_fraction 0.061227 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.938773 # Percentage of idle cycles +system.cpu.num_mem_refs 15461819 # number of memory refs +system.cpu.num_load_insts 9093811 # Number of load instructions +system.cpu.num_store_insts 6368008 # Number of store instructions +system.cpu.num_idle_cycles 3593003741.998122 # Number of idle cycles +system.cpu.num_busy_cycles 233945638.001878 # Number of busy cycles +system.cpu.not_idle_fraction 0.061131 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.938869 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211970 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74891 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212010 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74899 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1930 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106204 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183156 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73524 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1933 1.06% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106230 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183193 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73532 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1930 1.29% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73524 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149109 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1855675111500 97.13% 97.13% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91586500 0.00% 97.13% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 735892500 0.04% 97.17% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 54044234500 2.83% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1910546825000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1933 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149128 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1858610780000 97.13% 97.13% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91300500 0.00% 97.14% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 737276500 0.04% 97.18% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 54034599000 2.82% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1913473956000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692290 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814109 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692196 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814049 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -415,29 +400,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175939 91.22% 93.42% # number of callpals executed -system.cpu.kern.callpal::rdps 6831 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175970 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6834 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5155 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5158 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192879 # number of callpals executed +system.cpu.kern.callpal::total 192916 # number of callpals executed system.cpu.kern.mode_switch::kernel 5900 # number of protection mode switches -system.cpu.kern.mode_switch::user 1744 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1913 -system.cpu.kern.mode_good::user 1744 +system.cpu.kern.mode_switch::user 1742 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.mode_good::user 1742 system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.324237 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.323898 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392853 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 45393996500 2.38% 2.38% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5132973000 0.27% 2.64% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1860019853500 97.36% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080553 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 45394142000 2.37% 2.37% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5131394000 0.27% 2.64% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1862948418000 97.36% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -470,51 +455,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 927816 # number of replacements -system.cpu.icache.tagsinuse 509.100001 # Cycle average of tags in use -system.cpu.icache.total_refs 55204264 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 928327 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.466399 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 32331359000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.100001 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.994336 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.994336 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55204264 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55204264 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55204264 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55204264 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55204264 # number of overall hits -system.cpu.icache.overall_hits::total 55204264 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928486 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928486 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928486 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 928486 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 928486 # number of overall misses -system.cpu.icache.overall_misses::total 928486 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12769098000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12769098000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12769098000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12769098000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12769098000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12769098000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56132750 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56132750 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56132750 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56132750 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56132750 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56132750 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016541 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016541 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016541 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016541 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016541 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016541 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13752.601547 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13752.601547 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13752.601547 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13752.601547 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13752.601547 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13752.601547 # average overall miss latency +system.cpu.icache.replacements 927958 # number of replacements +system.cpu.icache.tagsinuse 509.106403 # Cycle average of tags in use +system.cpu.icache.total_refs 55214738 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 928469 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 59.468585 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 32313596000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 509.106403 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.994348 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.994348 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55214738 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55214738 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55214738 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55214738 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55214738 # number of overall hits +system.cpu.icache.overall_hits::total 55214738 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 928628 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 928628 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 928628 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 928628 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 928628 # number of overall misses +system.cpu.icache.overall_misses::total 928628 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12770278000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12770278000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12770278000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12770278000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12770278000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12770278000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56143366 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56143366 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56143366 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56143366 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56143366 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56143366 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016540 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016540 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016540 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016540 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016540 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13751.769277 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13751.769277 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13751.769277 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13751.769277 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13751.769277 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13751.769277 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -523,126 +508,126 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928486 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 928486 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 928486 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 928486 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 928486 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 928486 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10912126000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10912126000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10912126000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10912126000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10912126000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10912126000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016541 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016541 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016541 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016541 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016541 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016541 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11752.601547 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11752.601547 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11752.601547 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11752.601547 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11752.601547 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11752.601547 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928628 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 928628 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 928628 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 928628 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 928628 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 928628 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10913022000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10913022000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10913022000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10913022000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10913022000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10913022000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016540 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016540 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016540 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11751.769277 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11751.769277 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11751.769277 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11751.769277 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11751.769277 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11751.769277 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 336232 # number of replacements -system.cpu.l2cache.tagsinuse 65320.349460 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2445455 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 401395 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.092390 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 5253905752 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 55746.369541 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 4781.447334 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 4792.532585 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.850622 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.072959 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.073128 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.996709 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 915175 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 814009 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1729184 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 834499 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 834499 # number of Writeback hits +system.cpu.l2cache.replacements 336244 # number of replacements +system.cpu.l2cache.tagsinuse 65321.744295 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2445552 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 401406 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.092465 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 5250002751 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 55750.890928 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 4786.700552 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 4784.152815 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.850691 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.073039 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.073000 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.996731 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 915318 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 813981 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1729299 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 834498 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 834498 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187516 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187516 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 915175 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1001525 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1916700 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 915175 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1001525 # number of overall hits -system.cpu.l2cache.overall_hits::total 1916700 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 13291 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 271961 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 285252 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 187514 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187514 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 915318 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1001495 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1916813 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 915318 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1001495 # number of overall hits +system.cpu.l2cache.overall_hits::total 1916813 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 13290 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 271963 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 285253 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116841 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116841 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13291 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388802 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 402093 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13291 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388802 # number of overall misses -system.cpu.l2cache.overall_misses::total 402093 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 831870000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11715487000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12547357000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_misses::cpu.data 116856 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116856 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13290 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388819 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 402109 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13290 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 388819 # number of overall misses +system.cpu.l2cache.overall_misses::total 402109 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 831194000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11699138000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12530332000 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 189500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 189500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5599308500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5599308500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 831870000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 17314795500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18146665500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 831870000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 17314795500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18146665500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 928466 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1085970 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2014436 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 834499 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 834499 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5596958000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5596958000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 831194000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 17296096000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18127290000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 831194000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 17296096000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18127290000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 928608 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1085944 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2014552 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 834498 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 834498 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304357 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304357 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 928466 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1390327 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2318793 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 928466 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1390327 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2318793 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014315 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250431 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.141604 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304370 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304370 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 928608 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1390314 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2318922 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 928608 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1390314 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2318922 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014312 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250439 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.141596 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383895 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383895 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014315 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279648 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.173406 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014315 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279648 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.173406 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62588.969980 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43077.819982 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 43986.920337 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383927 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383927 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014312 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279663 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.173403 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014312 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279663 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.173403 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62542.814146 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43017.388395 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 43927.082274 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14576.923077 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14576.923077 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47922.463005 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47922.463005 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62588.969980 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44533.709960 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 45130.518313 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62588.969980 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44533.709960 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 45130.518313 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47896.197029 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47896.197029 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62542.814146 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44483.669780 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 45080.537864 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62542.814146 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44483.669780 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 45080.537864 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -651,66 +636,66 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74181 # number of writebacks -system.cpu.l2cache.writebacks::total 74181 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13291 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271961 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 285252 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 74191 # number of writebacks +system.cpu.l2cache.writebacks::total 74191 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13290 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271963 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 285253 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116841 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116841 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 13291 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388802 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 402093 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 13291 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388802 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 402093 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 666952085 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8376868075 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9043820160 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116856 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116856 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 13290 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388819 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 402109 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 13290 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388819 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 402109 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 666266030 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8360156960 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9026422990 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4162858124 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4162858124 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 666952085 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12539726199 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13206678284 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 666952085 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12539726199 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13206678284 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334145500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334145500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895221000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895221000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229366500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229366500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250431 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141604 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4160193080 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4160193080 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 666266030 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12520350040 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13186616070 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 666266030 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12520350040 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13186616070 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334146000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895853000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895853000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229999000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229999000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014312 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250439 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141596 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383895 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383895 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279648 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173406 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279648 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173406 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 50180.730193 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30801.725523 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31704.668714 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383927 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383927 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014312 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279663 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173403 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014312 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279663 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173403 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 50132.884123 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30740.052728 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31643.569007 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35628.402051 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35628.402051 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50180.730193 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32252.216293 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32844.835110 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50180.730193 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32252.216293 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32844.835110 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35601.022455 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35601.022455 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50132.884123 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32200.972792 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32793.635731 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50132.884123 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32200.972792 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32793.635731 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -718,79 +703,79 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1389814 # number of replacements -system.cpu.dcache.tagsinuse 511.980842 # Cycle average of tags in use -system.cpu.dcache.total_refs 14034828 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1390326 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.094631 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1389801 # number of replacements +system.cpu.dcache.tagsinuse 511.980871 # Cycle average of tags in use +system.cpu.dcache.total_refs 14037928 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1390313 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.096955 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 93552000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.980842 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.980871 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999963 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7805620 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7805620 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5846988 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5846988 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182985 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182985 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199218 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199218 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13652608 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13652608 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13652608 # number of overall hits -system.cpu.dcache.overall_hits::total 13652608 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1068716 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1068716 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304374 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304374 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17254 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17254 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373090 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373090 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373090 # number of overall misses -system.cpu.dcache.overall_misses::total 1373090 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22883646000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22883646000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8388017500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8388017500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229841000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 229841000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31271663500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31271663500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31271663500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31271663500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8874336 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8874336 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6151362 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6151362 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200239 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200239 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199218 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199218 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15025698 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15025698 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15025698 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15025698 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120428 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120428 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049481 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049481 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086167 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086167 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091383 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091383 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091383 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091383 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21412.279782 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21412.279782 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27558.258918 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27558.258918 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13321.027008 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13321.027008 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22774.664079 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22774.664079 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22774.664079 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22774.664079 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 7807394 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807394 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848285 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5848285 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183004 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183004 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199228 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199228 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13655679 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655679 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655679 # number of overall hits +system.cpu.dcache.overall_hits::total 13655679 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1068700 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1068700 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304387 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304387 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17244 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17244 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373087 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373087 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373087 # number of overall misses +system.cpu.dcache.overall_misses::total 1373087 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22867911000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22867911000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8385686000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8385686000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228869000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 228869000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31253597000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31253597000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31253597000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31253597000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8876094 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8876094 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152672 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152672 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200248 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200248 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199228 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199228 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15028766 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15028766 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15028766 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15028766 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120402 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120402 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049472 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049472 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086113 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086113 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091364 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091364 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091364 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091364 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21397.876860 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21397.876860 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27549.422282 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27549.422282 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13272.384598 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13272.384598 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22761.556260 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22761.556260 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22761.556260 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22761.556260 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -799,54 +784,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834499 # number of writebacks -system.cpu.dcache.writebacks::total 834499 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068716 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1068716 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304374 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304374 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17254 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17254 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373090 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373090 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373090 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373090 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20746214000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 20746214000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7779269500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7779269500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 195333000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195333000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28525483500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28525483500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28525483500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28525483500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010997000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010997000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435232500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435232500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120428 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120428 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049481 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049481 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086167 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086167 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091383 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091383 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19412.279782 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19412.279782 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25558.258918 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25558.258918 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11321.027008 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11321.027008 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20774.664079 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20774.664079 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20774.664079 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20774.664079 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 834498 # number of writebacks +system.cpu.dcache.writebacks::total 834498 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068700 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1068700 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304387 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304387 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17244 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17244 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373087 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373087 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373087 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373087 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20730511000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 20730511000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7776912000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7776912000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194381000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194381000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28507423000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28507423000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28507423000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28507423000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011665000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011665000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435901000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435901000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120402 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120402 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049472 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049472 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086113 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086113 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091364 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091364 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091364 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091364 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19397.876860 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19397.876860 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25549.422282 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25549.422282 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.384598 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.384598 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20761.556260 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20761.556260 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20761.556260 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20761.556260 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 839e0acab..9a52baa4f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.912097 # Nu sim_ticks 912096763500 # Number of ticks simulated final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1193297 # Simulator instruction rate (inst/s) -host_op_rate 1536367 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17661410361 # Simulator tick rate (ticks/s) -host_mem_usage 435356 # Number of bytes of host memory used -host_seconds 51.64 # Real time elapsed on the host +host_inst_rate 1025890 # Simulator instruction rate (inst/s) +host_op_rate 1320831 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15183699019 # Simulator tick rate (ticks/s) +host_mem_usage 392232 # Number of bytes of host memory used +host_seconds 60.07 # Real time elapsed on the host sim_insts 61625970 # Number of instructions simulated sim_ops 79343340 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory @@ -117,26 +117,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 0 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -169,7 +156,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -202,7 +188,6 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 9811be55f..9271f187d 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu sim_ticks 2332810264000 # Number of ticks simulated final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1101050 # Simulator instruction rate (inst/s) -host_op_rate 1415882 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42519386287 # Simulator tick rate (ticks/s) -host_mem_usage 435224 # Number of bytes of host memory used -host_seconds 54.86 # Real time elapsed on the host +host_inst_rate 1712706 # Simulator instruction rate (inst/s) +host_op_rate 2202434 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66139785958 # Simulator tick rate (ticks/s) +host_mem_usage 391204 # Number of bytes of host memory used +host_seconds 35.27 # Real time elapsed on the host sim_insts 60408639 # Number of instructions simulated sim_ops 77681819 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory @@ -100,26 +100,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 0 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -152,7 +139,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -185,7 +171,6 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 13c85b6d1..10f005f3e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,159 +1,146 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.183003 # Number of seconds simulated -sim_ticks 1183003114000 # Number of ticks simulated -final_tick 1183003114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.182958 # Number of seconds simulated +sim_ticks 1182958259000 # Number of ticks simulated +final_tick 1182958259000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 673901 # Simulator instruction rate (inst/s) -host_op_rate 858757 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12970235901 # Simulator tick rate (ticks/s) -host_mem_usage 408748 # Number of bytes of host memory used -host_seconds 91.21 # Real time elapsed on the host -sim_insts 61465824 # Number of instructions simulated -sim_ops 78326377 # Number of ops (including micro ops) simulated +host_inst_rate 332432 # Simulator instruction rate (inst/s) +host_op_rate 423606 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6399087906 # Simulator tick rate (ticks/s) +host_mem_usage 408760 # Number of bytes of host memory used +host_seconds 184.86 # Real time elapsed on the host +sim_insts 61454647 # Number of instructions simulated +sim_ops 78309315 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 379748 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4530164 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4709236 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 336668 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4964784 # Number of bytes read from this memory -system.physmem.bytes_read::total 62116388 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 379748 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 336668 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 716416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4089728 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4815472 # Number of bytes read from this memory +system.physmem.bytes_read::total 62146212 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4116096 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7117072 # Number of bytes written to this memory +system.physmem.bytes_written::total 7143440 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12152 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 70856 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73654 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5342 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 77601 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654023 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 63902 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75268 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654489 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64314 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 820738 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43875212 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821150 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43876875 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 162 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 321003 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3829376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 332539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3980898 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 284588 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4196763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52507375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 321003 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 284588 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 605591 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3457073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14370 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2544663 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6016106 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3457073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43875212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 273183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4070703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52534577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 332539 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 273183 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 605722 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3479494 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14371 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2544759 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6038624 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3479494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43876875 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 162 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 321003 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3843746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 332539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3995269 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 284588 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6741426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58523481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654023 # Total number of read requests seen -system.physmem.writeReqs 820738 # Total number of write requests seen -system.physmem.cpureqs 272097 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 425857472 # Total number of bytes read from memory -system.physmem.bytesWritten 52527232 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62116388 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7117072 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.inst 273183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6615462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58573201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654489 # Total number of read requests seen +system.physmem.writeReqs 821150 # Total number of write requests seen +system.physmem.cpureqs 235683 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 425887296 # Total number of bytes read from memory +system.physmem.bytesWritten 52553600 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62146212 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7143440 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 112 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 11760 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 422267 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 415727 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 415213 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 415818 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 415767 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 415004 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 415107 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 415928 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 415784 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 415110 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 415164 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 415654 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 415632 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 415090 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 415000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 415646 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51297 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51187 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50850 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51382 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51290 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50625 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50696 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51406 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51898 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51190 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51758 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51708 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51138 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51768 # Track writes on a per bank basis +system.physmem.neitherReadNorWrite 11769 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 422283 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 415708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 415257 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 415923 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 415836 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 415086 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 415138 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 415982 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 415774 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 415145 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 415183 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 415686 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 415664 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 415065 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 414968 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415679 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51312 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50892 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51475 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51354 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50696 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50735 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51449 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51887 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51295 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51778 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51726 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51254 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51118 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51796 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1182998675500 # Total gap between requests +system.physmem.totGap 1182953705000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6825 # Categorize read packet sizes system.physmem.readPktSize::3 6488064 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159134 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 756836 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 63902 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 11760 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 570635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 408572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 415826 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1537846 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1165216 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1169840 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1140716 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 29537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 48457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 69066 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 48178 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 5864 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 5691 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5515 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5307 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 68 # What read queue length does an incoming req see +system.physmem.readPktSize::6 159600 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 756836 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 64314 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 571059 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 408588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 415867 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1537787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1165425 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1169620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1140545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 29607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 48460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 69110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 48185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 5882 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 5724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 75 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -169,61 +156,59 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 146986341539 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 189297882789 # Sum of mem lat for all requests -system.physmem.totBusLat 33269555000 # Total cycles spent in databus access -system.physmem.totBankLat 9041986250 # Total cycles spent in bank access -system.physmem.avgQLat 22090.22 # Average queueing delay per request -system.physmem.avgBankLat 1358.90 # Average bank access latency per request +system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.totQLat 147016739500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 189339617000 # Sum of mem lat for all requests +system.physmem.totBusLat 33271885000 # Total cycles spent in databus access +system.physmem.totBankLat 9050992500 # Total cycles spent in bank access +system.physmem.avgQLat 22093.24 # Average queueing delay per request +system.physmem.avgBankLat 1360.16 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28449.12 # Average memory access latency -system.physmem.avgRdBW 359.98 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 44.40 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 52.51 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.02 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 28453.39 # Average memory access latency +system.physmem.avgRdBW 360.02 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 44.43 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 52.53 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.04 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.16 # Data bus utilization in percentage system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 12.54 # Average write queue length over time -system.physmem.readRowHits 6611960 # Number of row buffer hits during reads -system.physmem.writeRowHits 800133 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.52 # Average write queue length over time +system.physmem.readRowHits 6612346 # Number of row buffer hits during reads +system.physmem.writeRowHits 800481 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.49 # Row buffer hit rate for writes -system.physmem.avgGap 158265.75 # Average gap between requests +system.physmem.writeRowHitRate 97.48 # Row buffer hit rate for writes +system.physmem.avgGap 158241.15 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -242,237 +227,237 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 69015 # number of replacements -system.l2c.tagsinuse 53041.665406 # Cycle average of tags in use -system.l2c.total_refs 1678594 # Total number of references to valid blocks. -system.l2c.sampled_refs 134211 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.507127 # Average number of references to valid blocks. +system.l2c.replacements 69480 # number of replacements +system.l2c.tagsinuse 53041.287373 # Cycle average of tags in use +system.l2c.total_refs 1677464 # Total number of references to valid blocks. +system.l2c.sampled_refs 134656 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.457403 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40191.767552 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 40190.252096 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000406 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.003100 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3723.993423 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4235.450091 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.742043 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2826.235882 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2061.472909 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.613278 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.itb.walker 0.001419 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3727.107062 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4236.234020 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 2.741995 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2823.629298 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2061.321078 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.613255 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056824 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.064628 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.056871 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.064640 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.043125 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.031456 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.809352 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 3013 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1662 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 349398 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 169915 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6389 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1943 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 534803 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 180813 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1247936 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 573205 # number of Writeback hits -system.l2c.Writeback_hits::total 573205 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1121 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 611 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1732 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 229 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 78 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 307 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 47508 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 62580 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 110088 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 3013 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1662 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 349398 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 217423 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6389 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1943 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 534803 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 243393 # number of demand (read+write) hits -system.l2c.demand_hits::total 1358024 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 3013 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1662 # number of overall hits -system.l2c.overall_hits::cpu0.inst 349398 # number of overall hits -system.l2c.overall_hits::cpu0.data 217423 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6389 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1943 # number of overall hits -system.l2c.overall_hits::cpu1.inst 534803 # number of overall hits -system.l2c.overall_hits::cpu1.data 243393 # number of overall hits -system.l2c.overall_hits::total 1358024 # number of overall hits +system.l2c.occ_percent::cpu1.inst 0.043085 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.031453 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.809346 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 3740 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1661 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 419713 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 206323 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5388 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1856 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 464159 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 143887 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1246727 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 572264 # number of Writeback hits +system.l2c.Writeback_hits::total 572264 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1120 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 606 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1726 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 216 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 100 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 316 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 57066 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 52392 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 109458 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 3740 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1661 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 419713 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 263389 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5388 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1856 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 464159 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 196279 # number of demand (read+write) hits +system.l2c.demand_hits::total 1356185 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 3740 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1661 # number of overall hits +system.l2c.overall_hits::cpu0.inst 419713 # number of overall hits +system.l2c.overall_hits::cpu0.data 263389 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5388 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1856 # number of overall hits +system.l2c.overall_hits::cpu1.inst 464159 # number of overall hits +system.l2c.overall_hits::cpu1.data 196279 # number of overall hits +system.l2c.overall_hits::total 1356185 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 5520 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 7838 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 5733 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 7863 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5255 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 3644 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22265 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 3583 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4723 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8306 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 571 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 461 # number of SCUpgradeReq misses +system.l2c.ReadReq_misses::cpu1.inst 5044 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 3624 # number of ReadReq misses +system.l2c.ReadReq_misses::total 22271 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 4701 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3596 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8297 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 563 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 469 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1032 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63840 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 75452 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139292 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 67050 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 72720 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139770 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 5520 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 71678 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 5733 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 74913 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5255 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 79096 # number of demand (read+write) misses -system.l2c.demand_misses::total 161557 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 5044 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 76344 # number of demand (read+write) misses +system.l2c.demand_misses::total 162041 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 5520 # number of overall misses -system.l2c.overall_misses::cpu0.data 71678 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu0.inst 5733 # number of overall misses +system.l2c.overall_misses::cpu0.data 74913 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu1.inst 5255 # number of overall misses -system.l2c.overall_misses::cpu1.data 79096 # number of overall misses -system.l2c.overall_misses::total 161557 # number of overall misses +system.l2c.overall_misses::cpu1.inst 5044 # number of overall misses +system.l2c.overall_misses::cpu1.data 76344 # number of overall misses +system.l2c.overall_misses::total 162041 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 69000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 151500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 286631500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 416021500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 299840500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 416754500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 247500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 290826000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 222550500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1216497500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 10882997 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 13761999 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 24644996 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1755500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2248500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 4004000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 2848043983 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3574373499 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6422417482 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 276698000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 223564500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1217256500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 12757497 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 11938999 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 24696496 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1598500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2408500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 4007000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3004157980 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3438233497 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6442391477 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 69000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 151500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 286631500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3264065483 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 82500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 299840500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3420912480 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 247500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 290826000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3796923999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 7638914982 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 276698000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3661797997 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 7659647977 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 69000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 151500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 286631500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3264065483 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 82500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 299840500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3420912480 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 247500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 290826000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3796923999 # number of overall miss cycles -system.l2c.overall_miss_latency::total 7638914982 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 3014 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 1665 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 354918 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 177753 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 6393 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1943 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 540058 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 184457 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1270201 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 573205 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 573205 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 4704 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5334 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10038 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 800 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 539 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1339 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111348 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 138032 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 249380 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 3014 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 1665 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 354918 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 289101 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 6393 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1943 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 540058 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 322489 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1519581 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 3014 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 1665 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 354918 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 289101 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 6393 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1943 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 540058 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 322489 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1519581 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000332 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001802 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015553 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.044095 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000626 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009730 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.019755 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.017529 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.761692 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.885452 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.827456 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.713750 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.855288 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.770724 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.573338 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.546627 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.558553 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000332 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.001802 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015553 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.247934 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000626 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009730 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.245267 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.106317 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000332 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.001802 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015553 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.247934 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000626 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009730 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.245267 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.106317 # miss rate for overall accesses +system.l2c.overall_miss_latency::cpu1.inst 276698000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3661797997 # number of overall miss cycles +system.l2c.overall_miss_latency::total 7659647977 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 3741 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1663 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 425446 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 214186 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5392 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1856 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 469203 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 147511 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1268998 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 572264 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 572264 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 5821 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4202 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10023 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 779 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 569 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1348 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 124116 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 125112 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 249228 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 3741 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1663 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 425446 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 338302 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5392 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1856 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 469203 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 272623 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1518226 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 3741 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1663 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 425446 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 338302 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5392 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1856 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 469203 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 272623 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1518226 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000267 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001203 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.013475 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036711 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000742 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010750 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024568 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.017550 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.807593 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.855783 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.827796 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.722721 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.824253 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.765579 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.540220 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.581239 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.560812 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000267 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.001203 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.013475 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.221438 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000742 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010750 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.280035 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.106730 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000267 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.001203 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.013475 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.221438 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000742 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010750 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.280035 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.106730 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 69000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 50500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 51925.996377 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 53077.507017 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 41250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52300.802372 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 53001.971258 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 61875 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55342.721218 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 61073.133919 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 54637.210869 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3037.397991 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2913.825746 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2967.131712 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3074.430823 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4877.440347 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3879.844961 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44612.217779 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47372.813166 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 46107.583221 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 54856.859635 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 61689.983444 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 54656.571326 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2713.783663 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3320.077586 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2976.557310 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2839.253996 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5135.394456 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3882.751938 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44804.742431 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47280.438628 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 46092.805874 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 50500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 51925.996377 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 45537.898421 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 41250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52300.802372 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 45665.137960 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 55342.721218 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 48003.995132 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 47283.095019 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 54856.859635 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 47964.450343 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 47269.814288 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 50500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 51925.996377 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 45537.898421 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 41250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52300.802372 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 45665.137960 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 55342.721218 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 48003.995132 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 47283.095019 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 54856.859635 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 47964.450343 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 47269.814288 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,8 +466,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 63902 # number of writebacks -system.l2c.writebacks::total 63902 # number of writebacks +system.l2c.writebacks::writebacks 64314 # number of writebacks +system.l2c.writebacks::total 64314 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits @@ -490,150 +475,150 @@ system.l2c.demand_mshr_hits::total 1 # nu system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 5519 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 7838 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 5732 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 7863 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 5255 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 3644 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 22264 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 3583 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 4723 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8306 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 571 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 461 # number of SCUpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 5044 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 3624 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 22270 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 4701 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3596 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8297 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 563 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 469 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 1032 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 63840 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 75452 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 139292 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 67050 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 72720 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 139770 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 5519 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 71678 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 5732 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 74913 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 5255 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 79096 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 161556 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 5044 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 76344 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 162040 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 5519 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 71678 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 5732 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 74913 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 5255 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 79096 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 161556 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 56252 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 113756 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 217401709 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 318301323 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 197508 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 225003397 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 176993433 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 938067378 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 35910048 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 47375165 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 83285213 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5731560 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4624957 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 10356517 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2039757737 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2629528179 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4669285916 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 56252 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 113756 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 217401709 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2358059060 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 197508 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 225003397 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2806521612 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 5607353294 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 56252 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 113756 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 217401709 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2358059060 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 197508 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 225003397 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2806521612 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 5607353294 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 209640082 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 11218408858 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3082174 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155565109792 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166996240906 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 994820748 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8214915040 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 9209735788 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 209640082 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12213229606 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3082174 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 163780024832 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 176205976694 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.044095 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.019755 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017528 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.761692 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.885452 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.827456 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.713750 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.855288 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770724 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.573338 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.546627 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.558553 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.247934 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.245267 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.106316 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.247934 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.245267 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.106316 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 37918.666667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39391.503714 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40610.018244 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49377 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 48571.194566 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 42133.820428 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10022.341055 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10030.735761 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10027.114496 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.758319 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.444685 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10035.384690 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 31951.092372 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34850.344312 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 33521.565603 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 37918.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39391.503714 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32897.947208 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49377 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35482.472085 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 34708.418715 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 37918.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39391.503714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32897.947208 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49377 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35482.472085 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 34708.418715 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu1.inst 5044 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 76344 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 162040 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 56251 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 57502 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 227938476 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 318715113 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 197504 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 213513533 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 178263373 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 938741752 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 47096148 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 36051561 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 83147709 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5658050 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4702967 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10361017 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2154770965 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2528315165 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4683086130 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 57502 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 227938476 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2473486078 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 197504 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 213513533 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2706578538 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5621827882 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 56251 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 57502 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 227938476 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2473486078 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 197504 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 213513533 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2706578538 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5621827882 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 209633632 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12454649323 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3082087 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154326885776 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166994250818 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1000448248 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8209486413 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 9209934661 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 209633632 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13455097571 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3082087 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162536372189 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 176204185479 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000267 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001203 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013473 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036711 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000742 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024568 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017549 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.807593 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.855783 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.827796 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.722721 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.824253 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.765579 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540220 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.581239 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.560812 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000267 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001203 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013473 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.221438 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000742 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.280035 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.106730 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000267 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001203 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013473 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.221438 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000742 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.280035 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.106730 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39765.958828 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40533.525754 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42330.200833 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49189.672461 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 42152.750427 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10018.325463 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10025.461902 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10021.418465 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10049.822380 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.648188 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10039.745155 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32136.778001 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34767.810300 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 33505.660228 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39765.958828 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 33018.115387 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42330.200833 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35452.406712 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 34694.074809 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39765.958828 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33018.115387 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42330.200833 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35452.406712 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 34694.074809 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -656,27 +641,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 5883553 # DTB read hits -system.cpu0.dtb.read_misses 2148 # DTB read misses -system.cpu0.dtb.write_hits 4842455 # DTB write hits -system.cpu0.dtb.write_misses 405 # DTB write misses +system.cpu0.dtb.read_hits 7073604 # DTB read hits +system.cpu0.dtb.read_misses 3763 # DTB read misses +system.cpu0.dtb.write_hits 5658971 # DTB write hits +system.cpu0.dtb.write_misses 806 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1536 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 5885701 # DTB read accesses -system.cpu0.dtb.write_accesses 4842860 # DTB write accesses +system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7077367 # DTB read accesses +system.cpu0.dtb.write_accesses 5659777 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 10726008 # DTB hits -system.cpu0.dtb.misses 2553 # DTB misses -system.cpu0.dtb.accesses 10728561 # DTB accesses -system.cpu0.itb.inst_hits 24779849 # ITB inst hits -system.cpu0.itb.inst_misses 1350 # ITB inst misses +system.cpu0.dtb.hits 12732575 # DTB hits +system.cpu0.dtb.misses 4569 # DTB misses +system.cpu0.dtb.accesses 12737144 # DTB accesses +system.cpu0.itb.inst_hits 29573368 # ITB inst hits +system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -685,86 +670,86 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 24781199 # ITB inst accesses -system.cpu0.itb.hits 24779849 # DTB hits -system.cpu0.itb.misses 1350 # DTB misses -system.cpu0.itb.accesses 24781199 # DTB accesses -system.cpu0.numCycles 2364565551 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 29575573 # ITB inst accesses +system.cpu0.itb.hits 29573368 # DTB hits +system.cpu0.itb.misses 2205 # DTB misses +system.cpu0.itb.accesses 29575573 # DTB accesses +system.cpu0.numCycles 2365916518 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 24381823 # Number of instructions committed -system.cpu0.committedOps 31476006 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 28075203 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses -system.cpu0.num_func_calls 1070639 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3752398 # number of instructions that are conditional controls -system.cpu0.num_int_insts 28075203 # number of integer instructions -system.cpu0.num_fp_insts 4364 # number of float instructions -system.cpu0.num_int_register_reads 160702802 # number of times the integer registers were read -system.cpu0.num_int_register_writes 30522196 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written -system.cpu0.num_mem_refs 11318426 # number of memory refs -system.cpu0.num_load_insts 6163151 # Number of load instructions -system.cpu0.num_store_insts 5155275 # Number of store instructions -system.cpu0.num_idle_cycles 2243464250.276980 # Number of idle cycles -system.cpu0.num_busy_cycles 121101300.723020 # Number of busy cycles -system.cpu0.not_idle_fraction 0.051215 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.948785 # Percentage of idle cycles +system.cpu0.committedInsts 28875412 # Number of instructions committed +system.cpu0.committedOps 37222765 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33109279 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses +system.cpu0.num_func_calls 1241807 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4373656 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33109279 # number of integer instructions +system.cpu0.num_fp_insts 3860 # number of float instructions +system.cpu0.num_int_register_reads 190112848 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36234022 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written +system.cpu0.num_mem_refs 13400902 # number of memory refs +system.cpu0.num_load_insts 7411207 # Number of load instructions +system.cpu0.num_store_insts 5989695 # Number of store instructions +system.cpu0.num_idle_cycles 2224988060.360119 # Number of idle cycles +system.cpu0.num_busy_cycles 140928457.639881 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059566 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940434 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 38919 # number of quiesce instructions executed -system.cpu0.icache.replacements 354669 # number of replacements -system.cpu0.icache.tagsinuse 509.601981 # Cycle average of tags in use -system.cpu0.icache.total_refs 24424650 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 355181 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 68.766770 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 46697 # number of quiesce instructions executed +system.cpu0.icache.replacements 425482 # number of replacements +system.cpu0.icache.tagsinuse 509.601890 # Cycle average of tags in use +system.cpu0.icache.total_refs 29147356 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 425994 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 68.421987 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 74995953000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.601981 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 509.601890 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.995316 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.995316 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 24424650 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 24424650 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 24424650 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 24424650 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 24424650 # number of overall hits -system.cpu0.icache.overall_hits::total 24424650 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 355182 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 355182 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 355182 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 355182 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 355182 # number of overall misses -system.cpu0.icache.overall_misses::total 355182 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 4877233500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 4877233500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 4877233500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 4877233500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 4877233500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 4877233500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 24779832 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 24779832 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 24779832 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 24779832 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 24779832 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 24779832 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014334 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014334 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014334 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014334 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014334 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014334 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13731.646029 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13731.646029 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13731.646029 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13731.646029 # average overall miss latency +system.cpu0.icache.ReadReq_hits::cpu0.inst 29147356 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29147356 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29147356 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29147356 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29147356 # number of overall hits +system.cpu0.icache.overall_hits::total 29147356 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 425995 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 425995 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 425995 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 425995 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 425995 # number of overall misses +system.cpu0.icache.overall_misses::total 425995 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5809941500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5809941500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5809941500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5809941500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5809941500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5809941500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29573351 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29573351 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29573351 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29573351 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29573351 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29573351 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014405 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014405 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014405 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014405 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014405 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014405 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13638.520405 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13638.520405 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13638.520405 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13638.520405 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13638.520405 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13638.520405 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -773,120 +758,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 355182 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 355182 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 355182 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 355182 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 355182 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 355182 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4166869500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4166869500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4166869500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4166869500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4166869500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4166869500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425995 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 425995 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 425995 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 425995 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 425995 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 425995 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4957951500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4957951500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4957951500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4957951500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4957951500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4957951500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 299599000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 299599000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 299599000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 299599000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014334 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014334 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014334 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11731.646029 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11731.646029 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11731.646029 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014405 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014405 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014405 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11638.520405 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11638.520405 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11638.520405 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11638.520405 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11638.520405 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11638.520405 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 279602 # number of replacements -system.cpu0.dcache.tagsinuse 452.516720 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10326636 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 279931 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 36.889934 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 331027 # number of replacements +system.cpu0.dcache.tagsinuse 453.640914 # Cycle average of tags in use +system.cpu0.dcache.total_refs 12276777 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 331539 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 37.029662 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 473552000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 452.516720 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.883822 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.883822 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5477555 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5477555 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4571792 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4571792 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129360 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 129360 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 130225 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 130225 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10049347 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10049347 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10049347 # number of overall hits -system.cpu0.dcache.overall_hits::total 10049347 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 191756 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 191756 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 126522 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 126522 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8645 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8645 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7703 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7703 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 318278 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 318278 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 318278 # number of overall misses -system.cpu0.dcache.overall_misses::total 318278 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2678719000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 2678719000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 3810145000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 3810145000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 78655500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 78655500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45606000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 45606000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 6488864000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 6488864000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 6488864000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 6488864000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5669311 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 5669311 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4698314 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4698314 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138005 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 138005 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137928 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 137928 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10367625 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10367625 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10367625 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10367625 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033824 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033824 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026929 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.026929 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062643 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062643 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.055848 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.055848 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030699 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.030699 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030699 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.030699 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13969.414256 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13969.414256 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30114.486018 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 30114.486018 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9098.380567 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9098.380567 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5920.550435 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5920.550435 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20387.409749 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 20387.409749 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 20387.409749 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 20387.409749 # average overall miss latency +system.cpu0.dcache.occ_blocks::cpu0.data 453.640914 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.886017 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.886017 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6603200 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6603200 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5353855 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5353855 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147936 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147936 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149699 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149699 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11957055 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11957055 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11957055 # number of overall hits +system.cpu0.dcache.overall_hits::total 11957055 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 228068 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 228068 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 141674 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 141674 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9338 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9338 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7490 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7490 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 369742 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 369742 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 369742 # number of overall misses +system.cpu0.dcache.overall_misses::total 369742 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3146768000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3146768000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4132891500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4132891500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88585500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88585500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44513500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 44513500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 7279659500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 7279659500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 7279659500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 7279659500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6831268 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6831268 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5495529 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5495529 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157274 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157274 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157189 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157189 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12326797 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12326797 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12326797 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12326797 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033386 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033386 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025780 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025780 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059374 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059374 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047650 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047650 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029995 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029995 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029995 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029995 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13797.498992 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13797.498992 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29171.841693 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 29171.841693 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9486.560291 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9486.560291 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5943.057410 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5943.057410 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19688.484132 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19688.484132 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19688.484132 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 19688.484132 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -895,66 +880,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 257540 # number of writebacks -system.cpu0.dcache.writebacks::total 257540 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191756 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 191756 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126522 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 126522 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8645 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8645 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7700 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7700 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 318278 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 318278 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 318278 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 318278 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2295207000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2295207000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3557101000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3557101000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 61365500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 61365500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30208000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30208000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 306714 # number of writebacks +system.cpu0.dcache.writebacks::total 306714 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228068 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 228068 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141674 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141674 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9338 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9338 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7487 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7487 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369742 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 369742 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 369742 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 369742 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2690632000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2690632000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3849543500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3849543500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69909500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69909500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29541500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29541500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5852308000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5852308000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5852308000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5852308000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12211047000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12211047000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1122364500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1122364500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13333411500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13333411500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033824 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033824 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026929 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026929 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062643 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062643 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.055826 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.055826 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.030699 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.030699 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11969.414256 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11969.414256 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28114.486018 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28114.486018 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7098.380567 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7098.380567 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3923.116883 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3923.116883 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6540175500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6540175500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6540175500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6540175500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13562243000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13562243000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128446000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128446000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14690689000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14690689000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033386 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033386 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025780 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025780 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059374 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059374 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047631 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047631 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029995 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029995 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029995 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029995 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11797.498992 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11797.498992 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27171.841693 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27171.841693 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7486.560291 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7486.560291 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3945.705890 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3945.705890 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17688.484132 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17688.484132 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17688.484132 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17688.484132 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -964,27 +949,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 9504194 # DTB read hits -system.cpu1.dtb.read_misses 5263 # DTB read misses -system.cpu1.dtb.write_hits 6646220 # DTB write hits -system.cpu1.dtb.write_misses 1833 # DTB write misses +system.cpu1.dtb.read_hits 8309714 # DTB read hits +system.cpu1.dtb.read_misses 3643 # DTB read misses +system.cpu1.dtb.write_hits 5826503 # DTB write hits +system.cpu1.dtb.write_misses 1435 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2237 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 191 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 9509457 # DTB read accesses -system.cpu1.dtb.write_accesses 6648053 # DTB write accesses +system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 8313357 # DTB read accesses +system.cpu1.dtb.write_accesses 5827938 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16150414 # DTB hits -system.cpu1.dtb.misses 7096 # DTB misses -system.cpu1.dtb.accesses 16157510 # DTB accesses -system.cpu1.itb.inst_hits 37994467 # ITB inst hits -system.cpu1.itb.inst_misses 3017 # ITB inst misses +system.cpu1.dtb.hits 14136217 # DTB hits +system.cpu1.dtb.misses 5078 # DTB misses +system.cpu1.dtb.accesses 14141295 # DTB accesses +system.cpu1.itb.inst_hits 33189716 # ITB inst hits +system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -993,86 +978,86 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 37997484 # ITB inst accesses -system.cpu1.itb.hits 37994467 # DTB hits -system.cpu1.itb.misses 3017 # DTB misses -system.cpu1.itb.accesses 37997484 # DTB accesses -system.cpu1.numCycles 2366006228 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 33191887 # ITB inst accesses +system.cpu1.itb.hits 33189716 # DTB hits +system.cpu1.itb.misses 2171 # DTB misses +system.cpu1.itb.accesses 33191887 # DTB accesses +system.cpu1.numCycles 2364475282 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 37084001 # Number of instructions committed -system.cpu1.committedOps 46850371 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 42360540 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses -system.cpu1.num_func_calls 1133542 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4355119 # number of instructions that are conditional controls -system.cpu1.num_int_insts 42360540 # number of integer instructions -system.cpu1.num_fp_insts 5457 # number of float instructions -system.cpu1.num_int_register_reads 243148462 # number of times the integer registers were read -system.cpu1.num_int_register_writes 45181015 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written -system.cpu1.num_mem_refs 16764021 # number of memory refs -system.cpu1.num_load_insts 9884261 # Number of load instructions -system.cpu1.num_store_insts 6879760 # Number of store instructions -system.cpu1.num_idle_cycles 1849775265.196436 # Number of idle cycles -system.cpu1.num_busy_cycles 516230962.803564 # Number of busy cycles -system.cpu1.not_idle_fraction 0.218187 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.781813 # Percentage of idle cycles +system.cpu1.committedInsts 32579235 # Number of instructions committed +system.cpu1.committedOps 41086550 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 37310899 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses +system.cpu1.num_func_calls 962009 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3732730 # number of instructions that are conditional controls +system.cpu1.num_int_insts 37310899 # number of integer instructions +system.cpu1.num_fp_insts 6793 # number of float instructions +system.cpu1.num_int_register_reads 213650265 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39453467 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written +system.cpu1.num_mem_refs 14673985 # number of memory refs +system.cpu1.num_load_insts 8631614 # Number of load instructions +system.cpu1.num_store_insts 6042371 # Number of store instructions +system.cpu1.num_idle_cycles 1868339828.826306 # Number of idle cycles +system.cpu1.num_busy_cycles 496135453.173694 # Number of busy cycles +system.cpu1.not_idle_fraction 0.209829 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.790171 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 51687 # number of quiesce instructions executed -system.cpu1.icache.replacements 540342 # number of replacements -system.cpu1.icache.tagsinuse 478.756805 # Cycle average of tags in use -system.cpu1.icache.total_refs 37453609 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 540854 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 69.249019 # Average number of references to valid blocks. +system.cpu1.kern.inst.quiesce 43883 # number of quiesce instructions executed +system.cpu1.icache.replacements 469209 # number of replacements +system.cpu1.icache.tagsinuse 478.755545 # Cycle average of tags in use +system.cpu1.icache.total_refs 32719991 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 469721 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 69.658353 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 92137748500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.756805 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935072 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935072 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 37453609 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 37453609 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 37453609 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 37453609 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 37453609 # number of overall hits -system.cpu1.icache.overall_hits::total 37453609 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 540854 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 540854 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 540854 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 540854 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 540854 # number of overall misses -system.cpu1.icache.overall_misses::total 540854 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7301553500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7301553500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7301553500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7301553500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7301553500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7301553500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 37994463 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 37994463 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 37994463 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 37994463 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 37994463 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 37994463 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014235 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014235 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014235 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014235 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014235 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014235 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13500.045299 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13500.045299 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13500.045299 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13500.045299 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13500.045299 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13500.045299 # average overall miss latency +system.cpu1.icache.occ_blocks::cpu1.inst 478.755545 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.935069 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.935069 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 32719991 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32719991 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 32719991 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 32719991 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 32719991 # number of overall hits +system.cpu1.icache.overall_hits::total 32719991 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 469721 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 469721 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 469721 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 469721 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 469721 # number of overall misses +system.cpu1.icache.overall_misses::total 469721 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6363755000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6363755000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6363755000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6363755000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6363755000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6363755000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 33189712 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 33189712 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 33189712 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 33189712 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 33189712 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 33189712 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014153 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014153 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014153 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014153 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014153 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014153 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13547.946547 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13547.946547 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13547.946547 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13547.946547 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13547.946547 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13547.946547 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1081,120 +1066,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 540854 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 540854 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 540854 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 540854 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 540854 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 540854 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6219845500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6219845500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6219845500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6219845500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6219845500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6219845500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469721 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 469721 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 469721 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 469721 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 469721 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 469721 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5424313000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5424313000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5424313000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5424313000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5424313000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5424313000 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4396000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4396000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4396000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 4396000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014235 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014235 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014235 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014235 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014235 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014235 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11500.045299 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11500.045299 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11500.045299 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11500.045299 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11500.045299 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11500.045299 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014153 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.014153 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.014153 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11547.946547 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11547.946547 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11547.946547 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11547.946547 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11547.946547 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11547.946547 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 343957 # number of replacements -system.cpu1.dcache.tagsinuse 473.088021 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13916365 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 344469 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 40.399470 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 292184 # number of replacements +system.cpu1.dcache.tagsinuse 472.133429 # Cycle average of tags in use +system.cpu1.dcache.total_refs 11959580 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 292554 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 40.879906 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 83709904000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 473.088021 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.924000 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.924000 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8074934 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8074934 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 5611325 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 5611325 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 100335 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 100335 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 102214 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 102214 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 13686259 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 13686259 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 13686259 # number of overall hits -system.cpu1.dcache.overall_hits::total 13686259 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 207178 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 207178 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 165249 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 165249 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11790 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11790 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9834 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 9834 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 372427 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 372427 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 372427 # number of overall misses -system.cpu1.dcache.overall_misses::total 372427 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2639135500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2639135500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4834942000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4834942000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 103120000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 103120000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50505000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 50505000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 7474077500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 7474077500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 7474077500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 7474077500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8282112 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8282112 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5776574 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5776574 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 112125 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 112125 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 112048 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 112048 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14058686 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14058686 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14058686 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14058686 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.025015 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.025015 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028607 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.028607 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.105151 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.105151 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087766 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087766 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026491 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026491 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026491 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.026491 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12738.492987 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12738.492987 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 29258.525014 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 29258.525014 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8746.395250 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8746.395250 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5135.753508 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5135.753508 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20068.570485 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20068.570485 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20068.570485 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20068.570485 # average overall miss latency +system.cpu1.dcache.occ_blocks::cpu1.data 472.133429 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.922136 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.922136 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 6945060 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6945060 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4826351 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4826351 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81758 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 81758 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82709 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 82709 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 11771411 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11771411 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11771411 # number of overall hits +system.cpu1.dcache.overall_hits::total 11771411 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 170725 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 170725 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 149867 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 149867 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11052 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11052 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10028 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10028 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 320592 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 320592 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 320592 # number of overall misses +system.cpu1.dcache.overall_misses::total 320592 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2168241500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2168241500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4524943000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4524943000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 92270500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 92270500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51657000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 51657000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6693184500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6693184500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6693184500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6693184500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7115785 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7115785 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4976218 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4976218 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92810 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 92810 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92737 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92737 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 12092003 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 12092003 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 12092003 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 12092003 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023992 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023992 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030117 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030117 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119082 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119082 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108134 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108134 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026513 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026513 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026513 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026513 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12700.199151 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12700.199151 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30193.057845 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 30193.057845 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8348.760405 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8348.760405 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5151.276426 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5151.276426 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20877.578043 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20877.578043 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20877.578043 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20877.578043 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1203,66 +1188,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 315665 # number of writebacks -system.cpu1.dcache.writebacks::total 315665 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 207178 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 207178 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 165249 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 165249 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11790 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11790 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9830 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 9830 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 372427 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 372427 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 372427 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 372427 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2224779500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2224779500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4504444000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4504444000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79540000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 79540000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30847000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30847000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 265550 # number of writebacks +system.cpu1.dcache.writebacks::total 265550 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170725 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170725 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149867 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 149867 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11052 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11052 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10024 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10024 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320592 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320592 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320592 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320592 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1826791500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1826791500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4225209000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4225209000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70166500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70166500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31611000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31611000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6729223500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6729223500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6729223500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6729223500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169996101000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169996101000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17674592500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17674592500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 187670693500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 187670693500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025015 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025015 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028607 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028607 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.105151 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.105151 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087730 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087730 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026491 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026491 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10738.492987 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10738.492987 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27258.525014 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27258.525014 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6746.395250 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6746.395250 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3138.046796 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3138.046796 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6052000500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6052000500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6052000500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6052000500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168642802500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168642802500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17668343500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17668343500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186311146000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186311146000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023992 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023992 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030117 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030117 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119082 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119082 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108091 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108091 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026513 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026513 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10700.199151 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10700.199151 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28193.057845 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28193.057845 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6348.760405 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6348.760405 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3153.531524 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3153.531524 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18877.578043 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18877.578043 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18877.578043 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18877.578043 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1284,10 +1269,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509652310593 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 509652310593 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509652310593 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 509652310593 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509685021664 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 509685021664 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509685021664 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 509685021664 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 73585121b..4975edc6e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.603665 # Number of seconds simulated -sim_ticks 2603664815000 # Number of ticks simulated -final_tick 2603664815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.603674 # Number of seconds simulated +sim_ticks 2603674284000 # Number of ticks simulated +final_tick 2603674284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 536000 # Simulator instruction rate (inst/s) -host_op_rate 682052 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23183028791 # Simulator tick rate (ticks/s) -host_mem_usage 404656 # Number of bytes of host memory used -host_seconds 112.31 # Real time elapsed on the host -sim_insts 60197643 # Number of instructions simulated -sim_ops 76600583 # Number of ops (including micro ops) simulated +host_inst_rate 271279 # Simulator instruction rate (inst/s) +host_op_rate 345198 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11733407598 # Simulator tick rate (ticks/s) +host_mem_usage 403640 # Number of bytes of host memory used +host_seconds 221.90 # Real time elapsed on the host +sim_insts 60197457 # Number of instructions simulated +sim_ops 76600355 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory -system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory +system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory +system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47119503 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47119332 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 270695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3475919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50866314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 270695 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 270695 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1412434 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1158395 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2570829 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1412434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47119503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 270817 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3475931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50866276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 270817 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 270817 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1412478 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1158391 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2570868 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1412478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47119332 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 270695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4634314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53437143 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494089 # Total number of read requests seen -system.physmem.writeReqs 811479 # Total number of write requests seen -system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991621696 # Total number of bytes read from memory -system.physmem.bytesWritten 51934656 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu.inst 270817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4634322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53437145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494095 # Total number of read requests seen +system.physmem.writeReqs 811481 # Total number of write requests seen +system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 991622080 # Total number of bytes read from memory +system.physmem.bytesWritten 51934784 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed system.physmem.perBankRdReqs::0 974844 # Track reads on a per bank basis @@ -66,13 +66,13 @@ system.physmem.perBankRdReqs::4 968387 # Tr system.physmem.perBankRdReqs::5 967635 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 967737 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 968249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 968097 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 968100 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 967668 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 967710 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 968007 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 968101 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 967570 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 967431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 967434 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 968087 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 50753 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50356 # Track writes on a per bank basis @@ -82,61 +82,48 @@ system.physmem.perBankWrReqs::4 50784 # Tr system.physmem.perBankWrReqs::5 50139 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 50212 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 50710 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51141 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51142 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51058 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 51155 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 50650 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50586 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50587 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 51214 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2603660455000 # Total gap between requests +system.physmem.totGap 2603669924000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6652 # Categorize read packet sizes system.physmem.readPktSize::3 15335424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152013 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 754018 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 57461 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1115727 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 960917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 976016 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3645957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2755251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2758222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2725008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 64130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 62311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 112850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 163186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 112416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 10526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 10120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see +system.physmem.readPktSize::6 152019 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 754018 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 57463 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1115862 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 960938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 976049 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3645924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2755202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2757935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2724600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 64133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 62351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 112886 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 163253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 112534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10838 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 10625 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 10165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 93 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -152,15 +139,14 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35280 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see @@ -169,44 +155,43 @@ system.physmem.wrQLenPdf::12 35282 # Wh system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 341507754589 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 436421735839 # Sum of mem lat for all requests -system.physmem.totBusLat 77468765000 # Total cycles spent in databus access -system.physmem.totBankLat 17445216250 # Total cycles spent in bank access -system.physmem.avgQLat 22041.64 # Average queueing delay per request -system.physmem.avgBankLat 1125.95 # Average bank access latency per request +system.physmem.totQLat 341488215750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 436408620750 # Sum of mem lat for all requests +system.physmem.totBusLat 77468795000 # Total cycles spent in databus access +system.physmem.totBankLat 17451610000 # Total cycles spent in bank access +system.physmem.avgQLat 22040.37 # Average queueing delay per request +system.physmem.avgBankLat 1126.36 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28167.59 # Average memory access latency -system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28166.74 # Average memory access latency +system.physmem.avgRdBW 380.85 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.13 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 12.39 # Average write queue length over time -system.physmem.readRowHits 15418905 # Number of row buffer hits during reads -system.physmem.writeRowHits 794060 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.40 # Average write queue length over time +system.physmem.readRowHits 15418728 # Number of row buffer hits during reads +system.physmem.writeRowHits 794030 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes -system.physmem.avgGap 159679.22 # Average gap between requests +system.physmem.avgGap 159679.73 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -227,9 +212,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995667 # DTB read hits +system.cpu.dtb.read_hits 14995645 # DTB read hits system.cpu.dtb.read_misses 7332 # DTB read misses -system.cpu.dtb.write_hits 11230865 # DTB write hits +system.cpu.dtb.write_hits 11230857 # DTB write hits system.cpu.dtb.write_misses 2203 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -240,13 +225,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15002999 # DTB read accesses -system.cpu.dtb.write_accesses 11233068 # DTB write accesses +system.cpu.dtb.read_accesses 15002977 # DTB read accesses +system.cpu.dtb.write_accesses 11233060 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226532 # DTB hits +system.cpu.dtb.hits 26226502 # DTB hits system.cpu.dtb.misses 9535 # DTB misses -system.cpu.dtb.accesses 26236067 # DTB accesses -system.cpu.itb.inst_hits 61491584 # ITB inst hits +system.cpu.dtb.accesses 26236037 # DTB accesses +system.cpu.itb.inst_hits 61491397 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -263,79 +248,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61496055 # ITB inst accesses -system.cpu.itb.hits 61491584 # DTB hits +system.cpu.itb.inst_accesses 61495868 # ITB inst accesses +system.cpu.itb.hits 61491397 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61496055 # DTB accesses -system.cpu.numCycles 5207329630 # number of cpu cycles simulated +system.cpu.itb.accesses 61495868 # DTB accesses +system.cpu.numCycles 5207348568 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60197643 # Number of instructions committed -system.cpu.committedOps 76600583 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68868344 # Number of integer alu accesses +system.cpu.committedInsts 60197457 # Number of instructions committed +system.cpu.committedOps 76600355 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68868122 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139730 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7947806 # number of instructions that are conditional controls -system.cpu.num_int_insts 68868344 # number of integer instructions +system.cpu.num_func_calls 2139722 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7947784 # number of instructions that are conditional controls +system.cpu.num_int_insts 68868122 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394756284 # number of times the integer registers were read -system.cpu.num_int_register_writes 74176271 # number of times the integer registers were written +system.cpu.num_int_register_reads 394755172 # number of times the integer registers were read +system.cpu.num_int_register_writes 74176013 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27393912 # number of memory refs -system.cpu.num_load_insts 15659685 # Number of load instructions -system.cpu.num_store_insts 11734227 # Number of store instructions -system.cpu.num_idle_cycles 4579092870.576241 # Number of idle cycles -system.cpu.num_busy_cycles 628236759.423759 # Number of busy cycles -system.cpu.not_idle_fraction 0.120645 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.879355 # Percentage of idle cycles +system.cpu.num_mem_refs 27393871 # number of memory refs +system.cpu.num_load_insts 15659652 # Number of load instructions +system.cpu.num_store_insts 11734219 # Number of store instructions +system.cpu.num_idle_cycles 4579092042.576241 # Number of idle cycles +system.cpu.num_busy_cycles 628256525.423759 # Number of busy cycles +system.cpu.not_idle_fraction 0.120648 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.879352 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed -system.cpu.icache.replacements 855486 # number of replacements -system.cpu.icache.tagsinuse 510.979431 # Cycle average of tags in use -system.cpu.icache.total_refs 60635586 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 855998 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.836130 # Average number of references to valid blocks. +system.cpu.icache.replacements 855484 # number of replacements +system.cpu.icache.tagsinuse 510.979435 # Cycle average of tags in use +system.cpu.icache.total_refs 60635401 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 855996 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70.836080 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 18713179000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.979431 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 510.979435 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.998007 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.998007 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60635586 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60635586 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60635586 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60635586 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60635586 # number of overall hits -system.cpu.icache.overall_hits::total 60635586 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 855998 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 855998 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 855998 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 855998 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 855998 # number of overall misses -system.cpu.icache.overall_misses::total 855998 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11569304000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11569304000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11569304000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11569304000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11569304000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11569304000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61491584 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61491584 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61491584 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61491584 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61491584 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61491584 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60635401 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60635401 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60635401 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60635401 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60635401 # number of overall hits +system.cpu.icache.overall_hits::total 60635401 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 855996 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 855996 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 855996 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 855996 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 855996 # number of overall misses +system.cpu.icache.overall_misses::total 855996 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11568776000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11568776000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11568776000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11568776000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11568776000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11568776000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61491397 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61491397 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61491397 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61491397 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61491397 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61491397 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13515.573635 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13515.573635 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13515.573635 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13515.573635 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13515.573635 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13515.573635 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13514.988388 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13514.988388 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13514.988388 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13514.988388 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13514.988388 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13514.988388 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -344,18 +329,18 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855998 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 855998 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 855998 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 855998 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 855998 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 855998 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9857308000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9857308000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9857308000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9857308000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9857308000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9857308000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855996 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 855996 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 855996 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 855996 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 855996 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 855996 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9856784000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9856784000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9856784000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9856784000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9856784000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9856784000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 298856500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 298856500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 298856500 # number of overall MSHR uncacheable cycles @@ -366,152 +351,152 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013921 system.cpu.icache.demand_mshr_miss_rate::total 0.013921 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013921 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11515.573635 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11515.573635 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11515.573635 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11515.573635 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11515.573635 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11515.573635 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11514.988388 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11514.988388 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11514.988388 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11514.988388 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11514.988388 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11514.988388 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 61906 # number of replacements -system.cpu.l2cache.tagsinuse 50893.814517 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1682715 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 127287 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 13.219850 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2553152311000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 37867.919206 # Average occupied blocks per requestor +system.cpu.l2cache.replacements 61912 # number of replacements +system.cpu.l2cache.tagsinuse 50892.966587 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1682705 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 127293 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 13.219148 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2553153097000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 37868.000507 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885514 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001401 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 6996.279505 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6025.728892 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.577819 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 6995.362387 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6025.716777 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.577820 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.106755 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.106741 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.091945 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.776578 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.776565 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8701 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3548 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 843761 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 370335 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226345 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 596039 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 596039 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 843754 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 370328 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1226331 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 596040 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 596040 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 114427 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 114427 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 114438 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 114438 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 8701 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3548 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 843761 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 484762 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1340772 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 843754 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 484766 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1340769 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 8701 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3548 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 843761 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 484762 # number of overall hits -system.cpu.l2cache.overall_hits::total 1340772 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 843754 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 484766 # number of overall hits +system.cpu.l2cache.overall_hits::total 1340769 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 10599 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 9858 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 20465 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 9859 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 20471 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2875 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2875 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 133183 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 133183 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 10599 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143041 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 153648 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143042 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 153654 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 10599 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143041 # number of overall misses -system.cpu.l2cache.overall_misses::total 153648 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143042 # number of overall misses +system.cpu.l2cache.overall_misses::total 153654 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 315500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 151000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 562062000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 534519000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1097047500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 460000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 460000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6075862000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6075862000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 561610000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 535948000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1098024500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 462000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 462000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6083213000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6083213000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 315500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 151000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 562062000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6610381000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7172909500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 561610000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6619161000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7181237500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 315500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 151000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 562062000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6610381000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7172909500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 561610000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6619161000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7181237500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8706 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 854360 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 380193 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1246810 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 596039 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 596039 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 854358 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 380187 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1246802 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 596040 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 596040 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2901 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2901 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247610 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247610 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247621 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247621 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8706 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 854360 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 627803 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1494420 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 854358 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 627808 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1494423 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8706 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 854360 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 627803 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1494420 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 854358 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 627808 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1494423 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000845 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012406 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025929 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016414 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012412 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025932 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016419 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991038 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991038 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537874 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.537874 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537850 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.537850 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000845 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012406 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012412 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.227844 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.102814 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.102818 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000845 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012406 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012412 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.227844 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.102814 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.102818 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 63100 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 50333.333333 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53029.719785 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54221.850274 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53606.034693 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45620.402003 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45620.402003 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52962.089777 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54361.294249 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53638.048947 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160.695652 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160.695652 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45675.596735 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45675.596735 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 63100 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 50333.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53029.719785 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46213.190624 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 46684.040795 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52962.089777 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46274.248123 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 46736.417536 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 63100 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 50333.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53029.719785 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46213.190624 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 46684.040795 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52962.089777 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46274.248123 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 46736.417536 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -520,92 +505,92 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 57461 # number of writebacks -system.cpu.l2cache.writebacks::total 57461 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 57463 # number of writebacks +system.cpu.l2cache.writebacks::total 57463 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10599 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9858 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 20465 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10604 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9859 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 20471 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2875 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2875 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133183 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 133183 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10599 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143041 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 153648 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10604 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143042 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 153654 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10599 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143041 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 153648 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 253760 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 113756 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 430665051 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 411778800 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 842811367 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28850324 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28850324 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4437954325 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4437954325 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 253760 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 113756 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 430665051 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4849733125 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5280765692 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 253760 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 113756 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 430665051 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4849733125 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5280765692 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 209122550 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166688445815 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166897568365 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9173753597 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9173753597 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 209122550 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175862199412 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176071321962 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10604 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143042 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 153654 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 253755 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 113753 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 430132104 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 413197859 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 843697471 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28847322 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28847322 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4445123890 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4445123890 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 253755 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 113753 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 430132104 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4858321749 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5288821361 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 253755 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 113753 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 430132104 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4858321749 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5288821361 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 209116116 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166689052786 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166898168902 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9175171345 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9175171345 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 209116116 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175864224131 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176073340247 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012406 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025929 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016414 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025932 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016419 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991038 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991038 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537874 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537874 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537850 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537850 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012406 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227844 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.102814 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.102818 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012406 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227844 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.102814 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 50752 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 37918.666667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40632.611661 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41771.028606 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41183.062155 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10034.895304 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10034.895304 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33322.228250 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33322.228250 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 50752 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 37918.666667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40632.611661 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33904.496788 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34369.244585 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 50752 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37918.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40632.611661 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33904.496788 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34369.244585 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.102818 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 50751 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 37917.666667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40563.193512 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41910.727153 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41214.277319 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10033.851130 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10033.851130 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33376.060683 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33376.060683 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 50751 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 37917.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40563.193512 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33964.302436 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34420.329838 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 50751 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37917.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40563.193512 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33964.302436 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34420.329838 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -615,79 +600,79 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 627291 # number of replacements +system.cpu.dcache.replacements 627296 # number of replacements system.cpu.dcache.tagsinuse 511.912639 # Cycle average of tags in use -system.cpu.dcache.total_refs 23655046 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627803 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.679090 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 23655010 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 627808 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.678733 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 472186000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.912639 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999829 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999829 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13195134 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13195134 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9973055 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9973055 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236278 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236278 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 13195118 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13195118 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9973036 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9973036 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236277 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236277 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247678 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247678 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23168189 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23168189 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23168189 # number of overall hits -system.cpu.dcache.overall_hits::total 23168189 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368792 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368792 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250511 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250511 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11401 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11401 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 619303 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 619303 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 619303 # number of overall misses -system.cpu.dcache.overall_misses::total 619303 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5222508000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5222508000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8035214500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8035214500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155940000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 155940000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13257722500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13257722500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13257722500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13257722500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13563926 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13563926 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10223566 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10223566 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 23168154 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23168154 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23168154 # number of overall hits +system.cpu.dcache.overall_hits::total 23168154 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368785 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368785 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250522 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250522 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11402 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11402 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 619307 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 619307 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 619307 # number of overall misses +system.cpu.dcache.overall_misses::total 619307 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5224078000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5224078000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8042704500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8042704500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155711000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 155711000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13266782500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13266782500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13266782500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13266782500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13563903 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13563903 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10223558 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10223558 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247679 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247679 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247678 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247678 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23787492 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23787492 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23787492 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23787492 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 23787461 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23787461 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23787461 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23787461 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027189 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.027189 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046031 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046031 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024504 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024504 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046035 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046035 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.026035 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.026035 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.026035 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.026035 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14161.120632 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14161.120632 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32075.296095 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 32075.296095 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13677.747566 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13677.747566 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21407.489549 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21407.489549 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14165.646650 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14165.646650 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32103.785296 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 32103.785296 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13656.463778 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13656.463778 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21421.980536 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21421.980536 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21421.980536 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21421.980536 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -696,54 +681,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 596039 # number of writebacks -system.cpu.dcache.writebacks::total 596039 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368792 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368792 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250511 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250511 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11401 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11401 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619303 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619303 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619303 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619303 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4484924000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4484924000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7534192500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7534192500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 133138000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 133138000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12019116500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12019116500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12019116500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12019116500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182082004500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182082004500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708047000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708047000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200790051500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 200790051500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.writebacks::writebacks 596040 # number of writebacks +system.cpu.dcache.writebacks::total 596040 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368785 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368785 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250522 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250522 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11402 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11402 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 619307 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619307 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619307 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619307 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4486508000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4486508000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7541660500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7541660500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 132907000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 132907000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12028168500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12028168500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12028168500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12028168500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182082624500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182082624500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18709226000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18709226000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200791850500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 200791850500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027189 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027189 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046031 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046031 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024504 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024504 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046035 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046035 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12161.120632 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12161.120632 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30075.296095 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30075.296095 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.747566 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.747566 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12165.646650 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12165.646650 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30103.785296 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30103.785296 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11656.463778 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11656.463778 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19421.980536 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19421.980536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19421.980536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19421.980536 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -765,10 +750,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1199398748332 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1199398748332 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1199377224257 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1199377224257 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 9d3d17a68..8816091ac 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu sim_ticks 2332810256000 # Number of ticks simulated final_tick 2332810256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1011951 # Simulator instruction rate (inst/s) -host_op_rate 1301307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39078665084 # Simulator tick rate (ticks/s) -host_mem_usage 435224 # Number of bytes of host memory used -host_seconds 59.70 # Real time elapsed on the host +host_inst_rate 685945 # Simulator instruction rate (inst/s) +host_op_rate 882083 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26489224850 # Simulator tick rate (ticks/s) +host_mem_usage 391216 # Number of bytes of host memory used +host_seconds 88.07 # Real time elapsed on the host sim_insts 60408639 # Number of instructions simulated sim_ops 77681819 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory @@ -113,26 +113,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 0 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -165,7 +152,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -198,7 +184,6 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 4cde41f9a..fb87772ef 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.112041 # Nu sim_ticks 5112040970500 # Number of ticks simulated final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1816388 # Simulator instruction rate (inst/s) -host_op_rate 3719186 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46471341970 # Simulator tick rate (ticks/s) -host_mem_usage 582576 # Number of bytes of host memory used -host_seconds 110.00 # Real time elapsed on the host +host_inst_rate 1074050 # Simulator instruction rate (inst/s) +host_op_rate 2199194 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27479001055 # Simulator tick rate (ticks/s) +host_mem_usage 583620 # Number of bytes of host memory used +host_seconds 186.03 # Real time elapsed on the host sim_insts 199810242 # Number of instructions simulated sim_ops 409125913 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory @@ -97,26 +97,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 0 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -149,7 +136,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -182,7 +168,6 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index da7af1088..38cfd80e2 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,13 +4,13 @@ sim_seconds 5.195162 # Nu sim_ticks 5195162021000 # Number of ticks simulated final_tick 5195162021000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 973985 # Simulator instruction rate (inst/s) -host_op_rate 1877578 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39447094407 # Simulator tick rate (ticks/s) -host_mem_usage 612564 # Number of bytes of host memory used -host_seconds 131.70 # Real time elapsed on the host -sim_insts 128273348 # Number of instructions simulated -sim_ops 247275973 # Number of ops (including micro ops) simulated +host_inst_rate 926995 # Simulator instruction rate (inst/s) +host_op_rate 1786992 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37543942770 # Simulator tick rate (ticks/s) +host_mem_usage 611560 # Number of bytes of host memory used +host_seconds 138.38 # Real time elapsed on the host +sim_insts 128273323 # Number of instructions simulated +sim_ops 247275942 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2861312 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory @@ -48,7 +48,7 @@ system.physmem.bw_total::cpu.data 1734722 # To system.physmem.bw_total::total 4007716 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 198400 # Total number of read requests seen system.physmem.writeReqs 126924 # Total number of write requests seen -system.physmem.cpureqs 331611 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 327581 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 12697600 # Total number of bytes read from memory system.physmem.bytesWritten 8123136 # Total number of bytes written to memory system.physmem.bytesConsumedRd 12697600 # bytesRead derated as per pkt->getSize() @@ -97,44 +97,31 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 198400 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 127557 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 1624 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 155111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8768 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6671 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2070 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2020 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1315 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1213 # What read queue length does an incoming req see +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 126924 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 155117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8774 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3415 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2249 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2071 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2021 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1212 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 1130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1043 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1042 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 972 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 971 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1084 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 505 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 37 # What read queue length does an incoming req see @@ -149,16 +136,15 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4520 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 5322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5512 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 5519 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 5518 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 5518 # What write queue length does an incoming req see @@ -173,24 +159,23 @@ system.physmem.wrQLenPdf::19 5518 # Wh system.physmem.wrQLenPdf::20 5518 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5518 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 999 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4076582985 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7872522985 # Sum of mem lat for all requests +system.physmem.wrQLenPdf::26 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see +system.physmem.totQLat 4073325250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7869155250 # Sum of mem lat for all requests system.physmem.totBusLat 991710000 # Total cycles spent in databus access -system.physmem.totBankLat 2804230000 # Total cycles spent in bank access -system.physmem.avgQLat 20553.30 # Average queueing delay per request -system.physmem.avgBankLat 14138.36 # Average bank access latency per request +system.physmem.totBankLat 2804120000 # Total cycles spent in bank access +system.physmem.avgQLat 20536.88 # Average queueing delay per request +system.physmem.avgBankLat 14137.80 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 39691.66 # Average memory access latency +system.physmem.avgMemAccLat 39674.68 # Average memory access latency system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s @@ -199,10 +184,10 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 12.66 # Average write queue length over time -system.physmem.readRowHits 175587 # Number of row buffer hits during reads -system.physmem.writeRowHits 94819 # Number of row buffer hits during writes +system.physmem.readRowHits 175586 # Number of row buffer hits during reads +system.physmem.writeRowHits 94818 # Number of row buffer hits during writes system.physmem.readRowHitRate 88.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.71 # Row buffer hit rate for writes +system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes system.physmem.avgGap 15969193.66 # Average gap between requests system.iocache.replacements 47509 # number of replacements system.iocache.tagsinuse 0.124742 # Cycle average of tags in use @@ -223,12 +208,12 @@ system.iocache.overall_misses::pc.south_bridge.ide 47564 system.iocache.overall_misses::total 47564 # number of overall misses system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 139479932 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 139479932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10701739160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10701739160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10841219092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10841219092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10841219092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10841219092 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10699969160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10699969160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10839449092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10839449092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10839449092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10839449092 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) @@ -247,17 +232,17 @@ system.iocache.overall_miss_rate::pc.south_bridge.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165260.582938 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 165260.582938 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229061.197774 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 229061.197774 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227929.086957 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 227929.086957 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227929.086957 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 227929.086957 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 173428 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229023.312500 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 229023.312500 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227891.873938 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 227891.873938 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227891.873938 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 227891.873938 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 173195 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16211 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16181 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.698168 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.703603 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -271,14 +256,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47564 system.iocache.demand_mshr_misses::total 47564 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95570991 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 95570991 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8270938224 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8270938224 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8366509215 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8366509215 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8366509215 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8366509215 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95570962 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 95570962 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8269165315 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8269165315 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8364736277 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8364736277 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8364736277 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8364736277 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -287,14 +272,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113235.771327 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 113235.771327 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177032.068151 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 177032.068151 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175900.033954 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 175900.033954 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175900.033954 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 175900.033954 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113235.736967 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 113235.736967 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176994.120612 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 176994.120612 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175862.759167 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 175862.759167 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175862.759167 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 175862.759167 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -311,72 +296,72 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.cpu.numCycles 10390324042 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128273348 # Number of instructions committed -system.cpu.committedOps 247275973 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232011682 # Number of integer alu accesses +system.cpu.committedInsts 128273323 # Number of instructions committed +system.cpu.committedOps 247275942 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232011652 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 23157367 # number of instructions that are conditional controls -system.cpu.num_int_insts 232011682 # number of integer instructions +system.cpu.num_int_insts 232011652 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 567056120 # number of times the integer registers were read -system.cpu.num_int_register_writes 293242224 # number of times the integer registers were written +system.cpu.num_int_register_reads 567056066 # number of times the integer registers were read +system.cpu.num_int_register_writes 293242220 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 22232138 # number of memory refs -system.cpu.num_load_insts 13871783 # Number of load instructions -system.cpu.num_store_insts 8360355 # Number of store instructions -system.cpu.num_idle_cycles 9789668776.998116 # Number of idle cycles -system.cpu.num_busy_cycles 600655265.001884 # Number of busy cycles +system.cpu.num_mem_refs 22232130 # number of memory refs +system.cpu.num_load_insts 13871776 # Number of load instructions +system.cpu.num_store_insts 8360354 # Number of store instructions +system.cpu.num_idle_cycles 9789674914.998116 # Number of idle cycles +system.cpu.num_busy_cycles 600649127.001884 # Number of busy cycles system.cpu.not_idle_fraction 0.057809 # Percentage of non-idle cycles system.cpu.idle_fraction 0.942191 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 791521 # number of replacements +system.cpu.icache.replacements 791510 # number of replacements system.cpu.icache.tagsinuse 510.376104 # Cycle average of tags in use -system.cpu.icache.total_refs 144497694 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 792033 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 182.438982 # Average number of references to valid blocks. +system.cpu.icache.total_refs 144497671 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 792022 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 182.441486 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 159800886000 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 510.376104 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144497694 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144497694 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144497694 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144497694 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144497694 # number of overall hits -system.cpu.icache.overall_hits::total 144497694 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 792040 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 792040 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 792040 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 792040 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 792040 # number of overall misses -system.cpu.icache.overall_misses::total 792040 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 10957638500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 10957638500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 10957638500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 10957638500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 10957638500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 10957638500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145289734 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145289734 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145289734 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145289734 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145289734 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145289734 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144497671 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144497671 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144497671 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144497671 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144497671 # number of overall hits +system.cpu.icache.overall_hits::total 144497671 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 792029 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 792029 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 792029 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 792029 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 792029 # number of overall misses +system.cpu.icache.overall_misses::total 792029 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 10955241500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 10955241500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 10955241500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 10955241500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 10955241500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 10955241500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145289700 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145289700 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145289700 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145289700 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145289700 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145289700 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005451 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.005451 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.005451 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.005451 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.005451 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.005451 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13834.703424 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13834.703424 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13834.703424 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13834.703424 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13834.703424 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13834.703424 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13831.869161 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13831.869161 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13831.869161 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13831.869161 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13831.869161 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13831.869161 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -385,30 +370,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792040 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 792040 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 792040 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 792040 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 792040 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 792040 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9373558500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9373558500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9373558500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9373558500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9373558500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9373558500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792029 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 792029 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 792029 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 792029 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 792029 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 792029 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9371183500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9371183500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9371183500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9371183500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9371183500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9371183500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005451 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.005451 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.005451 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11834.703424 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11834.703424 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11834.703424 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11834.703424 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11834.703424 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11834.703424 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11831.869161 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11831.869161 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11831.869161 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11831.869161 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11831.869161 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11831.869161 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.replacements 3425 # number of replacements system.cpu.itb_walker_cache.tagsinuse 3.077882 # Cycle average of tags in use @@ -494,51 +479,51 @@ system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7860.975041 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7860.975041 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7538 # number of replacements +system.cpu.dtb_walker_cache.replacements 7540 # number of replacements system.cpu.dtb_walker_cache.tagsinuse 5.062515 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13179 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7552 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.745101 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.total_refs 13178 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7554 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.744506 # Average number of references to valid blocks. system.cpu.dtb_walker_cache.warmup_cycle 5159123845000 # Cycle when the warmup percentage was hit. system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.062515 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.316407 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.occ_percent::total 0.316407 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13181 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13181 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13181 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13181 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13181 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13181 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8725 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8725 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8725 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8725 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8725 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8725 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92081500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92081500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92081500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 92081500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92081500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 92081500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13180 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13180 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13180 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13180 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13180 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13180 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8726 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8726 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8726 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8726 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8726 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8726 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92094500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92094500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92094500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 92094500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92094500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 92094500 # number of overall miss cycles system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21906 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.ReadReq_accesses::total 21906 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21906 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.demand_accesses::total 21906 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21906 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::total 21906 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398293 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398293 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398293 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398293 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398293 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398293 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10553.753582 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10553.753582 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10553.753582 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10553.753582 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10553.753582 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10553.753582 # average overall miss latency +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398338 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398338 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398338 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398338 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398338 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398338 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10554.033922 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10554.033922 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10554.033922 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10554.033922 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10554.033922 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10554.033922 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -547,74 +532,74 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2712 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2712 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8725 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8725 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8725 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8725 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8725 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8725 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74631500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74631500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74631500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74631500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74631500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74631500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398293 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398293 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398293 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398293 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398293 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398293 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8553.753582 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8553.753582 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8553.753582 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8553.753582 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8553.753582 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8553.753582 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2713 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2713 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8726 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8726 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8726 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8726 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8726 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8726 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74642500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74642500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74642500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74642500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74642500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74642500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398338 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398338 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398338 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398338 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398338 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398338 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8554.033922 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8554.033922 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8554.033922 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1618787 # number of replacements +system.cpu.dcache.replacements 1618785 # number of replacements system.cpu.dcache.tagsinuse 511.997766 # Cycle average of tags in use -system.cpu.dcache.total_refs 20025899 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1619299 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.367017 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 20025893 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1619297 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.367029 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 39012000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.997766 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11988264 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11988264 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8035473 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8035473 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20023737 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20023737 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20023737 # number of overall hits -system.cpu.dcache.overall_hits::total 20023737 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1306607 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1306607 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 314888 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 314888 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1621495 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1621495 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1621495 # number of overall misses -system.cpu.dcache.overall_misses::total 1621495 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18344083000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18344083000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8556368000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8556368000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26900451000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26900451000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26900451000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26900451000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13294871 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13294871 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8350361 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8350361 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21645232 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21645232 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21645232 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21645232 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11988262 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11988262 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8035470 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8035470 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20023732 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20023732 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20023732 # number of overall hits +system.cpu.dcache.overall_hits::total 20023732 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1306602 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1306602 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 314890 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 314890 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1621492 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1621492 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1621492 # number of overall misses +system.cpu.dcache.overall_misses::total 1621492 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18343104000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18343104000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8556691000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8556691000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26899795000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26899795000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26899795000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26899795000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13294864 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13294864 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8350360 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8350360 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21645224 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21645224 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21645224 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21645224 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098279 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.098279 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037710 # miss rate for WriteReq accesses @@ -623,14 +608,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.074912 system.cpu.dcache.demand_miss_rate::total 0.074912 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074912 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.074912 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14039.480119 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14039.480119 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27172.734433 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27172.734433 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16589.906845 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16589.906845 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16589.906845 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16589.906845 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14038.784573 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14038.784573 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27173.587602 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27173.587602 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16589.532973 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16589.532973 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16589.532973 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16589.532973 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -639,24 +624,24 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1536049 # number of writebacks -system.cpu.dcache.writebacks::total 1536049 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1306607 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1306607 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314888 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 314888 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1621495 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1621495 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1621495 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1621495 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15730869000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15730869000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7926592000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7926592000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23657461000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23657461000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23657461000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23657461000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1536047 # number of writebacks +system.cpu.dcache.writebacks::total 1536047 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1306602 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1306602 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314890 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 314890 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1621492 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1621492 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1621492 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1621492 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15729900000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15729900000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7926911000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7926911000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23656811000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23656811000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23656811000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23656811000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94145949000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94145949000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467832500 # number of WriteReq MSHR uncacheable cycles @@ -671,14 +656,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074912 system.cpu.dcache.demand_mshr_miss_rate::total 0.074912 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074912 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074912 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12039.480119 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12039.480119 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25172.734433 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25172.734433 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14589.906845 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14589.906845 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14589.906845 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14589.906845 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12038.784573 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12038.784573 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25173.587602 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25173.587602 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14589.532973 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14589.532973 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14589.532973 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14589.532973 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -687,43 +672,43 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 86864 # number of replacements -system.cpu.l2cache.tagsinuse 64770.429000 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3484731 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 64770.428925 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3484716 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 151631 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.981653 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 22.981554 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 50336.267441 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 50336.266909 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.007172 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140366 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3358.135857 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 11075.878163 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3358.136526 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 11075.877952 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.768070 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.051241 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.169004 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.988318 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6346 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6347 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2754 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 779155 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1277466 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2065721 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1539402 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1539402 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 779144 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1277462 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2065707 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1539401 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1539401 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 293 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 293 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 199364 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 199364 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6346 # number of demand (read+write) hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 199367 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 199367 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6347 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 2754 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 779155 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1476830 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2265085 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6346 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.inst 779144 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1476829 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2265074 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6347 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 2754 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 779155 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1476830 # number of overall hits -system.cpu.l2cache.overall_hits::total 2265085 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 779144 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1476829 # number of overall hits +system.cpu.l2cache.overall_hits::total 2265074 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 12872 # number of ReadReq misses @@ -745,44 +730,44 @@ system.cpu.l2cache.overall_misses::cpu.data 141743 # system.cpu.l2cache.overall_misses::total 154621 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 68500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 789955500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1648844500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2439213500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 787701500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1647921500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2436036500 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16174500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 16174500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5583075000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5583075000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5583363000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5583363000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 68500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 345000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 789955500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7231919500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8022288500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 787701500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7231284500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8019399500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 68500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 345000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 789955500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7231919500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8022288500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6347 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_miss_latency::cpu.inst 787701500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7231284500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8019399500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6348 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2759 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 792027 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1305851 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2106984 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1539402 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1539402 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 792016 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1305847 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2106970 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1539401 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1539401 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1657 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1657 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 312722 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 312722 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6347 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 312725 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 312725 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6348 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 2759 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 792027 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1618573 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2419706 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6347 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 792016 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1618572 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2419695 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6348 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 2759 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 792027 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1618573 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2419706 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 792016 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1618572 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2419695 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000158 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001812 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016252 # miss rate for ReadReq accesses @@ -790,8 +775,8 @@ system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021737 system.cpu.l2cache.ReadReq_miss_rate::total 0.019584 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823174 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823174 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362488 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.362488 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362485 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.362485 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000158 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001812 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016252 # miss rate for demand accesses @@ -804,23 +789,23 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.087573 system.cpu.l2cache.overall_miss_rate::total 0.063901 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 68500 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61370.066812 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58088.585521 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 59113.818675 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61194.958048 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58056.068346 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 59036.824758 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11858.137830 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11858.137830 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49251.706981 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49251.706981 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49254.247605 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49254.247605 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 68500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61370.066812 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51021.352024 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51883.563682 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61194.958048 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51016.872085 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51864.879285 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 68500 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61370.066812 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51021.352024 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51883.563682 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61194.958048 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51016.872085 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51864.879285 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -850,25 +835,25 @@ system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 system.cpu.l2cache.overall_mshr_misses::cpu.inst 12872 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141743 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 154621 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 56252 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 281260 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 630045573 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1296264296 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1926647381 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 56251 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 281255 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 627778857 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1295316957 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1923433320 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14542846 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14542846 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4190240726 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4190240726 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 56252 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 281260 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 630045573 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5486505022 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6116888107 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 56252 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 281260 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 630045573 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5486505022 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6116888107 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4190411275 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4190411275 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 281255 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 627778857 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5485728232 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6113844595 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 56251 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 281255 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 627778857 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5485728232 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6113844595 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86591175500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86591175500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305021500 # number of WriteReq MSHR uncacheable cycles @@ -882,8 +867,8 @@ system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021737 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019584 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823174 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823174 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362488 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362488 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362485 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362485 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for demand accesses @@ -894,25 +879,25 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001812 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087573 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.063901 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56252 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48946.983608 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45667.229029 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46691.888156 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56251 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48770.886964 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45633.854395 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46613.996074 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10661.910557 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10661.910557 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36964.667037 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36964.667037 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56252 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48946.983608 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38707.414278 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39560.526106 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56252 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48946.983608 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38707.414278 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39560.526106 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36966.171554 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36966.171554 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48770.886964 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38701.934007 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39540.842415 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48770.886964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38701.934007 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39540.842415 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index c8eb78d93..ac7e3035a 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.200409 # Nu sim_ticks 200409293000 # Number of ticks simulated final_tick 4321201686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 19440889 # Simulator instruction rate (inst/s) -host_op_rate 19440880 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7408936081 # Simulator tick rate (ticks/s) -host_mem_usage 472492 # Number of bytes of host memory used -host_seconds 27.05 # Real time elapsed on the host +host_inst_rate 11931696 # Simulator instruction rate (inst/s) +host_op_rate 11931689 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4547176905 # Simulator tick rate (ticks/s) +host_mem_usage 472520 # Number of bytes of host memory used +host_seconds 44.07 # Real time elapsed on the host sim_insts 525869186 # Number of instructions simulated sim_ops 525869186 # Number of ops (including micro ops) simulated testsys.physmem.bytes_read::cpu.inst 81048564 # Number of bytes read from this memory @@ -91,26 +91,13 @@ testsys.physmem.readPktSize::3 0 # Ca testsys.physmem.readPktSize::4 0 # Categorize read packet sizes testsys.physmem.readPktSize::5 0 # Categorize read packet sizes testsys.physmem.readPktSize::6 0 # Categorize read packet sizes -testsys.physmem.readPktSize::7 0 # Categorize read packet sizes -testsys.physmem.readPktSize::8 0 # Categorize read packet sizes -testsys.physmem.writePktSize::0 0 # categorize write packet sizes -testsys.physmem.writePktSize::1 0 # categorize write packet sizes -testsys.physmem.writePktSize::2 0 # categorize write packet sizes -testsys.physmem.writePktSize::3 0 # categorize write packet sizes -testsys.physmem.writePktSize::4 0 # categorize write packet sizes -testsys.physmem.writePktSize::5 0 # categorize write packet sizes -testsys.physmem.writePktSize::6 0 # categorize write packet sizes -testsys.physmem.writePktSize::7 0 # categorize write packet sizes -testsys.physmem.writePktSize::8 0 # categorize write packet sizes -testsys.physmem.neitherpktsize::0 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::1 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::2 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::3 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::4 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::5 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::6 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::7 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::8 0 # categorize neither packet sizes +testsys.physmem.writePktSize::0 0 # Categorize write packet sizes +testsys.physmem.writePktSize::1 0 # Categorize write packet sizes +testsys.physmem.writePktSize::2 0 # Categorize write packet sizes +testsys.physmem.writePktSize::3 0 # Categorize write packet sizes +testsys.physmem.writePktSize::4 0 # Categorize write packet sizes +testsys.physmem.writePktSize::5 0 # Categorize write packet sizes +testsys.physmem.writePktSize::6 0 # Categorize write packet sizes testsys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see testsys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see testsys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -143,7 +130,6 @@ testsys.physmem.rdQLenPdf::28 0 # Wh testsys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see testsys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see testsys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see testsys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see testsys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see testsys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -176,7 +162,6 @@ testsys.physmem.wrQLenPdf::28 0 # Wh testsys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see testsys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see testsys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see testsys.physmem.totQLat 0 # Total cycles spent in queuing delays testsys.physmem.totMemAccLat 0 # Sum of mem lat for all requests testsys.physmem.totBusLat 0 # Total cycles spent in databus access @@ -462,26 +447,13 @@ drivesys.physmem.readPktSize::3 0 # Ca drivesys.physmem.readPktSize::4 0 # Categorize read packet sizes drivesys.physmem.readPktSize::5 0 # Categorize read packet sizes drivesys.physmem.readPktSize::6 0 # Categorize read packet sizes -drivesys.physmem.readPktSize::7 0 # Categorize read packet sizes -drivesys.physmem.readPktSize::8 0 # Categorize read packet sizes -drivesys.physmem.writePktSize::0 0 # categorize write packet sizes -drivesys.physmem.writePktSize::1 0 # categorize write packet sizes -drivesys.physmem.writePktSize::2 0 # categorize write packet sizes -drivesys.physmem.writePktSize::3 0 # categorize write packet sizes -drivesys.physmem.writePktSize::4 0 # categorize write packet sizes -drivesys.physmem.writePktSize::5 0 # categorize write packet sizes -drivesys.physmem.writePktSize::6 0 # categorize write packet sizes -drivesys.physmem.writePktSize::7 0 # categorize write packet sizes -drivesys.physmem.writePktSize::8 0 # categorize write packet sizes -drivesys.physmem.neitherpktsize::0 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::1 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::2 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::3 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::4 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::5 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::6 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::7 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::8 0 # categorize neither packet sizes +drivesys.physmem.writePktSize::0 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::1 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::2 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::3 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::4 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::5 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::6 0 # Categorize write packet sizes drivesys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see drivesys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see drivesys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -514,7 +486,6 @@ drivesys.physmem.rdQLenPdf::28 0 # Wh drivesys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see drivesys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see drivesys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see drivesys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see drivesys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see drivesys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -547,7 +518,6 @@ drivesys.physmem.wrQLenPdf::28 0 # Wh drivesys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see drivesys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see drivesys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see drivesys.physmem.totQLat 0 # Total cycles spent in queuing delays drivesys.physmem.totMemAccLat 0 # Sum of mem lat for all requests drivesys.physmem.totBusLat 0 # Total cycles spent in databus access @@ -751,11 +721,11 @@ sim_seconds 0.000407 # Nu sim_ticks 407365500 # Number of ticks simulated final_tick 4321609052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 12024534237 # Simulator instruction rate (inst/s) -host_op_rate 12021051237 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9308365303 # Simulator tick rate (ticks/s) -host_mem_usage 472492 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 6212406894 # Simulator instruction rate (inst/s) +host_op_rate 6210790807 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4809282801 # Simulator tick rate (ticks/s) +host_mem_usage 472520 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 525940622 # Number of instructions simulated sim_ops 525940622 # Number of ops (including micro ops) simulated testsys.physmem.bytes_read::cpu.inst 141136 # Number of bytes read from this memory @@ -835,26 +805,13 @@ testsys.physmem.readPktSize::3 0 # Ca testsys.physmem.readPktSize::4 0 # Categorize read packet sizes testsys.physmem.readPktSize::5 0 # Categorize read packet sizes testsys.physmem.readPktSize::6 0 # Categorize read packet sizes -testsys.physmem.readPktSize::7 0 # Categorize read packet sizes -testsys.physmem.readPktSize::8 0 # Categorize read packet sizes -testsys.physmem.writePktSize::0 0 # categorize write packet sizes -testsys.physmem.writePktSize::1 0 # categorize write packet sizes -testsys.physmem.writePktSize::2 0 # categorize write packet sizes -testsys.physmem.writePktSize::3 0 # categorize write packet sizes -testsys.physmem.writePktSize::4 0 # categorize write packet sizes -testsys.physmem.writePktSize::5 0 # categorize write packet sizes -testsys.physmem.writePktSize::6 0 # categorize write packet sizes -testsys.physmem.writePktSize::7 0 # categorize write packet sizes -testsys.physmem.writePktSize::8 0 # categorize write packet sizes -testsys.physmem.neitherpktsize::0 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::1 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::2 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::3 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::4 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::5 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::6 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::7 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::8 0 # categorize neither packet sizes +testsys.physmem.writePktSize::0 0 # Categorize write packet sizes +testsys.physmem.writePktSize::1 0 # Categorize write packet sizes +testsys.physmem.writePktSize::2 0 # Categorize write packet sizes +testsys.physmem.writePktSize::3 0 # Categorize write packet sizes +testsys.physmem.writePktSize::4 0 # Categorize write packet sizes +testsys.physmem.writePktSize::5 0 # Categorize write packet sizes +testsys.physmem.writePktSize::6 0 # Categorize write packet sizes testsys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see testsys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see testsys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -887,7 +844,6 @@ testsys.physmem.rdQLenPdf::28 0 # Wh testsys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see testsys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see testsys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see testsys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see testsys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see testsys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -920,7 +876,6 @@ testsys.physmem.wrQLenPdf::28 0 # Wh testsys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see testsys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see testsys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see testsys.physmem.totQLat 0 # Total cycles spent in queuing delays testsys.physmem.totMemAccLat 0 # Sum of mem lat for all requests testsys.physmem.totBusLat 0 # Total cycles spent in databus access @@ -1157,26 +1112,13 @@ drivesys.physmem.readPktSize::3 0 # Ca drivesys.physmem.readPktSize::4 0 # Categorize read packet sizes drivesys.physmem.readPktSize::5 0 # Categorize read packet sizes drivesys.physmem.readPktSize::6 0 # Categorize read packet sizes -drivesys.physmem.readPktSize::7 0 # Categorize read packet sizes -drivesys.physmem.readPktSize::8 0 # Categorize read packet sizes -drivesys.physmem.writePktSize::0 0 # categorize write packet sizes -drivesys.physmem.writePktSize::1 0 # categorize write packet sizes -drivesys.physmem.writePktSize::2 0 # categorize write packet sizes -drivesys.physmem.writePktSize::3 0 # categorize write packet sizes -drivesys.physmem.writePktSize::4 0 # categorize write packet sizes -drivesys.physmem.writePktSize::5 0 # categorize write packet sizes -drivesys.physmem.writePktSize::6 0 # categorize write packet sizes -drivesys.physmem.writePktSize::7 0 # categorize write packet sizes -drivesys.physmem.writePktSize::8 0 # categorize write packet sizes -drivesys.physmem.neitherpktsize::0 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::1 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::2 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::3 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::4 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::5 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::6 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::7 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::8 0 # categorize neither packet sizes +drivesys.physmem.writePktSize::0 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::1 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::2 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::3 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::4 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::5 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::6 0 # Categorize write packet sizes drivesys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see drivesys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see drivesys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -1209,7 +1151,6 @@ drivesys.physmem.rdQLenPdf::28 0 # Wh drivesys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see drivesys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see drivesys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see drivesys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see drivesys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see drivesys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -1242,7 +1183,6 @@ drivesys.physmem.wrQLenPdf::28 0 # Wh drivesys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see drivesys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see drivesys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see drivesys.physmem.totQLat 0 # Total cycles spent in queuing delays drivesys.physmem.totMemAccLat 0 # Sum of mem lat for all requests drivesys.physmem.totBusLat 0 # Total cycles spent in databus access diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 9e62381ba..a38dae954 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 19476000 # Number of ticks simulated final_tick 19476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 78389 # Simulator instruction rate (inst/s) -host_op_rate 78368 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 238789679 # Simulator tick rate (ticks/s) -host_mem_usage 223680 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 1322 # Simulator instruction rate (inst/s) +host_op_rate 1322 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4028719 # Simulator tick rate (ticks/s) +host_mem_usage 223696 # Number of bytes of host memory used +host_seconds 4.83 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 469 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2628216 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13374466 # Sum of mem lat for all requests +system.physmem.totQLat 2627750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13374000 # Sum of mem lat for all requests system.physmem.totBusLat 2345000 # Total cycles spent in databus access system.physmem.totBankLat 8401250 # Total cycles spent in bank access -system.physmem.avgQLat 5603.87 # Average queueing delay per request +system.physmem.avgQLat 5602.88 # Average queueing delay per request system.physmem.avgBankLat 17913.11 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28516.99 # Average memory access latency +system.physmem.avgMemAccLat 28515.99 # Average memory access latency system.physmem.avgRdBW 1537.89 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1537.89 # Average consumed read bandwidth in MB/s @@ -372,13 +357,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52524.834437 system.cpu.icache.overall_avg_mshr_miss_latency::total 52524.834437 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 199.973805 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 199.973821 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 143.049582 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.924223 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 143.049595 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.924226 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004366 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001737 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006103 # Average percentage of cache occupancy @@ -462,17 +447,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11816499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4177366 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15993865 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2666348 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2666348 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11816499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6843714 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18660213 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11816499 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6843714 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18660213 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11816250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4177308 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15993558 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2666299 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2666299 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11816250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6843607 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18659857 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11816250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6843607 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18659857 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -484,17 +469,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39257.471761 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43972.273684 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40388.547980 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36525.315068 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36525.315068 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39257.471761 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40736.392857 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39787.234542 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39257.471761 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40736.392857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39787.234542 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39256.644518 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43971.663158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40387.772727 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36524.643836 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36524.643836 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39256.644518 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40735.755952 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39786.475480 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39256.644518 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40735.755952 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39786.475480 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 104.433203 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index d7bf6a6b9..8b0cd4f27 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16030500 # Number of ticks simulated -final_tick 16030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16039500 # Number of ticks simulated +final_tick 16039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76258 # Simulator instruction rate (inst/s) -host_op_rate 76239 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 191753794 # Simulator tick rate (ticks/s) -host_mem_usage 225728 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 1336 # Simulator instruction rate (inst/s) +host_op_rate 1336 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3362323 # Simulator tick rate (ticks/s) +host_mem_usage 225744 # Number of bytes of host memory used +host_seconds 4.77 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19968 # Nu system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory system.physmem.num_reads::total 486 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1245625526 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 694675774 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1940301301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1245625526 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1245625526 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1245625526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 694675774 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1940301301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1244926587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 694285981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1939212569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1244926587 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1244926587 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1244926587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 694285981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1939212569 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 486 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 15817000 # Total gap between requests +system.physmem.totGap 15803000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 486 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 247 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,28 +149,27 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2909986 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13644986 # Sum of mem lat for all requests +system.physmem.totQLat 2921750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13656750 # Sum of mem lat for all requests system.physmem.totBusLat 2430000 # Total cycles spent in databus access system.physmem.totBankLat 8305000 # Total cycles spent in bank access -system.physmem.avgQLat 5987.63 # Average queueing delay per request +system.physmem.avgQLat 6011.83 # Average queueing delay per request system.physmem.avgBankLat 17088.48 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28076.10 # Average memory access latency -system.physmem.avgRdBW 1940.30 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28100.31 # Average memory access latency +system.physmem.avgRdBW 1939.21 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1940.30 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1939.21 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 15.16 # Data bus utilization in percentage +system.physmem.busUtil 15.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.85 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 396 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 32545.27 # Average gap between requests +system.physmem.avgGap 32516.46 # Average gap between requests system.cpu.branchPred.lookups 2896 # Number of BP lookups system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 513 # Number of conditional branches incorrect @@ -227,7 +212,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 32062 # number of cpu cycles simulated +system.cpu.numCycles 32080 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 8352 # Number of cycles fetch is stalled on an Icache miss @@ -258,8 +243,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 14509 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.090325 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.515470 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.090274 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.515181 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 9308 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1148 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2753 # Number of cycles decode is running @@ -384,7 +369,7 @@ system.cpu.iq.FU_type_0::MemWrite 1140 10.55% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 10806 # Type of FU issued -system.cpu.iq.rate 0.337034 # Inst issue rate +system.cpu.iq.rate 0.336845 # Inst issue rate system.cpu.iq.fu_busy_cnt 118 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010920 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 36268 # Number of integer instruction queue reads @@ -428,13 +413,13 @@ system.cpu.iew.exec_nop 86 # nu system.cpu.iew.exec_refs 3233 # number of memory reference insts executed system.cpu.iew.exec_branches 1613 # Number of branches executed system.cpu.iew.exec_stores 1101 # Number of stores executed -system.cpu.iew.exec_rate 0.316699 # Inst execution rate +system.cpu.iew.exec_rate 0.316521 # Inst execution rate system.cpu.iew.wb_sent 9857 # cumulative count of insts sent to commit system.cpu.iew.wb_count 9710 # cumulative count of insts written-back system.cpu.iew.wb_producers 5134 # num instructions producing a value system.cpu.iew.wb_consumers 6919 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.302851 # insts written-back per cycle +system.cpu.iew.wb_rate 0.302681 # insts written-back per cycle system.cpu.iew.wb_fanout 0.742015 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 6741 # The number of squashed insts skipped by commit @@ -472,14 +457,14 @@ system.cpu.commit.bw_limited 0 # nu system.cpu.rob.rob_reads 25928 # The number of ROB reads system.cpu.rob.rob_writes 27481 # The number of ROB writes system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17553 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 17571 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 5.031701 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.031701 # CPI: Total CPI of All Threads -system.cpu.ipc 0.198740 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.198740 # IPC: Total IPC of All Threads +system.cpu.cpi 5.034526 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.034526 # CPI: Total CPI of All Threads +system.cpu.ipc 0.198628 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.198628 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 12888 # number of integer regfile reads system.cpu.int_regfile_writes 7343 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads @@ -487,14 +472,14 @@ system.cpu.fp_regfile_writes 2 # nu system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 159.192237 # Cycle average of tags in use +system.cpu.icache.tagsinuse 159.281471 # Cycle average of tags in use system.cpu.icache.total_refs 1869 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5.971246 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 159.192237 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.077731 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.077731 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 159.281471 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.077774 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.077774 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1869 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1869 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1869 # number of demand (read+write) hits @@ -507,12 +492,12 @@ system.cpu.icache.demand_misses::cpu.inst 480 # n system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses system.cpu.icache.overall_misses::total 480 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 22202500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 22202500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 22202500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 22202500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 22202500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 22202500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22197500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22197500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22197500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22197500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22197500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22197500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2349 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2349 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2349 # number of demand (read+write) accesses @@ -525,12 +510,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.204342 system.cpu.icache.demand_miss_rate::total 0.204342 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.204342 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.204342 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46255.208333 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46255.208333 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46255.208333 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46255.208333 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46255.208333 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46255.208333 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46244.791667 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46244.791667 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46244.791667 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46244.791667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46244.791667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46244.791667 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -551,36 +536,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 313 system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16102000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16102000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16102000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16102000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16102000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16102000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16111000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16111000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16111000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16111000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16111000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16111000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133248 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.133248 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.133248 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51444.089457 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51444.089457 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51444.089457 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51444.089457 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51444.089457 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51444.089457 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51472.843450 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51472.843450 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51472.843450 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51472.843450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51472.843450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51472.843450 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 219.643453 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 219.754912 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002421 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 159.327355 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 60.316098 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004862 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 159.415983 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 60.338929 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004865 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006703 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006706 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -598,17 +583,17 @@ system.cpu.l2cache.demand_misses::total 486 # nu system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses system.cpu.l2cache.overall_misses::total 486 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15777000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15786000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6080500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21857500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21866500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3687500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3687500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15777000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15786000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 9768000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25545000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15777000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 25554000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15786000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 9768000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25545000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 25554000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 313 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 414 # number of ReadReq accesses(hits+misses) @@ -631,17 +616,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997947 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50567.307692 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50596.153846 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60202.970297 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52923.728814 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52945.520581 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50513.698630 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50513.698630 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50567.307692 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50596.153846 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52561.728395 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50567.307692 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52580.246914 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50596.153846 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52561.728395 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52580.246914 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -661,17 +646,17 @@ system.cpu.l2cache.demand_mshr_misses::total 486 system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11907990 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4848832 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16756822 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2795812 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2795812 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11907990 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7644644 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19552634 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11907990 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7644644 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19552634 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11916495 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4848791 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16765286 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2795781 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2795781 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11916495 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7644572 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19561067 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11916495 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7644572 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19561067 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997585 # mshr miss rate for ReadReq accesses @@ -683,27 +668,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38166.634615 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48008.237624 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40573.418886 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38298.794521 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38298.794521 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38166.634615 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43934.735632 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40231.757202 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38166.634615 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.735632 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40231.757202 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38193.894231 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48007.831683 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40593.912833 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38298.369863 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38298.369863 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38193.894231 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40249.109053 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38193.894231 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40249.109053 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 107.713176 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 107.750370 # Cycle average of tags in use system.cpu.dcache.total_refs 2262 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 107.713176 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026297 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026297 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 107.750370 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026306 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026306 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1756 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1756 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 6b89534e6..c84a7ed5c 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000009 # Nu sim_ticks 9350000 # Number of ticks simulated final_tick 9350000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146 # Simulator instruction rate (inst/s) -host_op_rate 146 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 570039 # Simulator tick rate (ticks/s) -host_mem_usage 224412 # Number of bytes of host memory used -host_seconds 16.40 # Real time elapsed on the host +host_inst_rate 55287 # Simulator instruction rate (inst/s) +host_op_rate 55271 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 216439769 # Simulator tick rate (ticks/s) +host_mem_usage 224436 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 272 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 148 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 87 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1329022 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7872772 # Sum of mem lat for all requests +system.physmem.totQLat 1328750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7872500 # Sum of mem lat for all requests system.physmem.totBusLat 1360000 # Total cycles spent in databus access system.physmem.totBankLat 5183750 # Total cycles spent in bank access -system.physmem.avgQLat 4886.11 # Average queueing delay per request +system.physmem.avgQLat 4885.11 # Average queueing delay per request system.physmem.avgBankLat 19057.90 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28944.01 # Average memory access latency +system.physmem.avgMemAccLat 28943.01 # Average memory access latency system.physmem.avgRdBW 1861.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1861.82 # Average consumed read bandwidth in MB/s @@ -571,13 +556,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51481.278075 system.cpu.icache.overall_avg_mshr_miss_latency::total 51481.278075 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 119.099628 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 119.099647 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 248 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 91.174739 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 27.924890 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 91.174754 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 27.924893 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.002782 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000852 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.003635 # Average percentage of cache occupancy @@ -655,17 +640,17 @@ system.cpu.l2cache.demand_mshr_misses::total 272 system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7118288 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2838816 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9957104 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1114024 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1114024 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7118288 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3952840 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11071128 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7118288 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3952840 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11071128 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7118144 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2838783 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9956927 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1114012 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1114012 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7118144 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3952795 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11070939 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7118144 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3952795 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11070939 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -677,17 +662,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38065.711230 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46537.967213 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40149.612903 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46417.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46417.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38065.711230 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46504 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40702.676471 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38065.711230 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46504 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40702.676471 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38064.941176 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46537.426230 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40148.899194 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46417.166667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46417.166667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38064.941176 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46503.470588 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40701.981618 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38064.941176 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46503.470588 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40701.981618 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 44.507812 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 80cf199ee..ed4523776 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000014 # Nu sim_ticks 13709000 # Number of ticks simulated final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 51480 # Simulator instruction rate (inst/s) -host_op_rate 64222 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 153638426 # Simulator tick rate (ticks/s) -host_mem_usage 239936 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 31817 # Simulator instruction rate (inst/s) +host_op_rate 39697 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 94976589 # Simulator tick rate (ticks/s) +host_mem_usage 239960 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 394 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2508144 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11751894 # Sum of mem lat for all requests +system.physmem.totQLat 2507750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11751500 # Sum of mem lat for all requests system.physmem.totBusLat 1970000 # Total cycles spent in databus access system.physmem.totBankLat 7273750 # Total cycles spent in bank access -system.physmem.avgQLat 6365.85 # Average queueing delay per request +system.physmem.avgQLat 6364.85 # Average queueing delay per request system.physmem.avgBankLat 18461.29 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29827.14 # Average memory access latency +system.physmem.avgMemAccLat 29826.14 # Average memory access latency system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s @@ -624,13 +609,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110 system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.063220 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 185.063238 # Cycle average of tags in use system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.360527 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.702693 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 138.360542 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.702695 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy @@ -723,17 +708,17 @@ system.cpu.l2cache.demand_mshr_misses::total 394 system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10736168 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756318 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492486 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896792 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896792 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10736168 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653110 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16389278 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10736168 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653110 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16389278 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10735959 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756284 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492243 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896771 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896771 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10735959 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653055 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16389014 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10735959 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653055 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16389014 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses @@ -745,17 +730,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39471.205882 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46374.296296 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41055.201133 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46263.219512 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46263.219512 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39470.437500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46373.876543 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41054.512748 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46262.707317 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46262.707317 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 13489057c..ef2f22c88 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000014 # Nu sim_ticks 13709000 # Number of ticks simulated final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58002 # Simulator instruction rate (inst/s) -host_op_rate 72354 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 173086159 # Simulator tick rate (ticks/s) -host_mem_usage 238920 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 36221 # Simulator instruction rate (inst/s) +host_op_rate 45190 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 108117571 # Simulator tick rate (ticks/s) +host_mem_usage 238932 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 394 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2508144 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11751894 # Sum of mem lat for all requests +system.physmem.totQLat 2507750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11751500 # Sum of mem lat for all requests system.physmem.totBusLat 1970000 # Total cycles spent in databus access system.physmem.totBankLat 7273750 # Total cycles spent in bank access -system.physmem.avgQLat 6365.85 # Average queueing delay per request +system.physmem.avgQLat 6364.85 # Average queueing delay per request system.physmem.avgBankLat 18461.29 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29827.14 # Average memory access latency +system.physmem.avgMemAccLat 29826.14 # Average memory access latency system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s @@ -579,13 +564,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110 system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.063220 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 185.063238 # Cycle average of tags in use system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.360527 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.702693 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 138.360542 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.702695 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy @@ -678,17 +663,17 @@ system.cpu.l2cache.demand_mshr_misses::total 394 system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10736168 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756318 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492486 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896792 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896792 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10736168 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653110 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16389278 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10736168 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653110 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16389278 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10735959 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756284 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492243 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896771 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896771 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10735959 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653055 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16389014 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10735959 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653055 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16389014 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses @@ -700,17 +685,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39471.205882 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46374.296296 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41055.201133 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46263.219512 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46263.219512 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39470.437500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46373.876543 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41054.512748 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46262.707317 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46262.707317 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 4baa76c40..d65cf38dc 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 19339000 # Number of ticks simulated final_tick 19339000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 100636 # Simulator instruction rate (inst/s) -host_op_rate 100592 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 334460805 # Simulator tick rate (ticks/s) -host_mem_usage 224316 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 54855 # Simulator instruction rate (inst/s) +host_op_rate 54842 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 182382541 # Simulator tick rate (ticks/s) +host_mem_usage 224336 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 455 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 293 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2650454 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13959204 # Sum of mem lat for all requests +system.physmem.totQLat 2650000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13958750 # Sum of mem lat for all requests system.physmem.totBusLat 2275000 # Total cycles spent in databus access system.physmem.totBankLat 9033750 # Total cycles spent in bank access -system.physmem.avgQLat 5825.17 # Average queueing delay per request +system.physmem.avgQLat 5824.18 # Average queueing delay per request system.physmem.avgBankLat 19854.40 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30679.57 # Average memory access latency +system.physmem.avgMemAccLat 30678.57 # Average memory access latency system.physmem.avgRdBW 1505.77 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1505.77 # Average consumed read bandwidth in MB/s @@ -358,13 +343,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54322.884013 system.cpu.icache.overall_avg_mshr_miss_latency::total 54322.884013 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 206.866516 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 206.866533 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 151.045976 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 55.820540 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 151.045990 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.820543 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001704 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006313 # Average percentage of cache occupancy @@ -448,17 +433,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13055529 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4090608 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17146137 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1925076 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1925076 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13055529 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6015684 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19071213 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13055529 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6015684 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19071213 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13055265 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4090554 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17145819 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1925038 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1925038 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13055265 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6015592 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19070857 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13055265 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6015592 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19070857 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -470,17 +455,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41184.634069 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47018.482759 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42440.933168 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37746.588235 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37746.588235 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41184.634069 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43591.913043 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41914.753846 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41184.634069 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43591.913043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41914.753846 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41183.801262 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47017.862069 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42440.146040 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37745.843137 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37745.843137 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41183.801262 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43591.246377 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41913.971429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41183.801262 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43591.246377 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41913.971429 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 89.917113 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 7feba62df..13fbe689c 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 17026500 # Number of ticks simulated final_tick 17026500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76348 # Simulator instruction rate (inst/s) -host_op_rate 76319 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 251939378 # Simulator tick rate (ticks/s) -host_mem_usage 226380 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 44899 # Simulator instruction rate (inst/s) +host_op_rate 44889 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 148205995 # Simulator tick rate (ticks/s) +host_mem_usage 226388 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 478 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 253 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2863474 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 14617224 # Sum of mem lat for all requests +system.physmem.totQLat 2863000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 14616750 # Sum of mem lat for all requests system.physmem.totBusLat 2390000 # Total cycles spent in databus access system.physmem.totBankLat 9363750 # Total cycles spent in bank access -system.physmem.avgQLat 5990.53 # Average queueing delay per request +system.physmem.avgQLat 5989.54 # Average queueing delay per request system.physmem.avgBankLat 19589.44 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30579.97 # Average memory access latency +system.physmem.avgMemAccLat 30578.97 # Average memory access latency system.physmem.avgRdBW 1796.73 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1796.73 # Average consumed read bandwidth in MB/s @@ -556,13 +541,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52572.271386 system.cpu.icache.overall_avg_mshr_miss_latency::total 52572.271386 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 222.426618 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 222.426637 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 427 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.007026 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 164.638321 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 57.788297 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 164.638337 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 57.788300 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.005024 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006788 # Average percentage of cache occupancy @@ -646,17 +631,17 @@ system.cpu.l2cache.demand_mshr_misses::total 478 system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 478 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13273303 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4804087 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18077390 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2032056 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2032056 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13273303 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6836143 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20109446 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13273303 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6836143 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20109446 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13273027 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4804044 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18077071 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2032028 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2032028 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13273027 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6836072 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20109099 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13273027 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6836072 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20109099 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993023 # mshr miss rate for ReadReq accesses @@ -668,17 +653,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993763 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39503.877976 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52792.164835 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42335.807963 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39844.235294 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39844.235294 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39503.877976 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48141.852113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42069.970711 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39503.877976 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48141.852113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42069.970711 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39503.056548 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52791.692308 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42335.060890 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39843.686275 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39843.686275 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39503.056548 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48141.352113 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42069.244770 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39503.056548 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48141.352113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42069.244770 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 91.642501 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index ccc0289be..69396a815 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000015 # Nu sim_ticks 14724500 # Number of ticks simulated final_tick 14724500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87376 # Simulator instruction rate (inst/s) -host_op_rate 87343 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 221965921 # Simulator tick rate (ticks/s) -host_mem_usage 222644 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 62176 # Simulator instruction rate (inst/s) +host_op_rate 62167 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 158021685 # Simulator tick rate (ticks/s) +host_mem_usage 222660 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 446 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 232 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 147 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2286195 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12779945 # Sum of mem lat for all requests +system.physmem.totQLat 2285750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12779500 # Sum of mem lat for all requests system.physmem.totBusLat 2230000 # Total cycles spent in databus access system.physmem.totBankLat 8263750 # Total cycles spent in bank access -system.physmem.avgQLat 5126.00 # Average queueing delay per request +system.physmem.avgQLat 5125.00 # Average queueing delay per request system.physmem.avgBankLat 18528.59 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28654.59 # Average memory access latency +system.physmem.avgMemAccLat 28653.59 # Average memory access latency system.physmem.avgRdBW 1938.54 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1938.54 # Average consumed read bandwidth in MB/s @@ -553,13 +538,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50659.544160 system.cpu.icache.overall_avg_mshr_miss_latency::total 50659.544160 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 198.145802 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 198.145822 # Cycle average of tags in use system.cpu.l2cache.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.017544 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 166.786148 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.359654 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 166.786167 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.359655 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.005090 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000957 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006047 # Average percentage of cache occupancy @@ -646,17 +631,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13081037 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2509304 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15590341 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2332794 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2332794 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13081037 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4842098 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17923135 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13081037 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4842098 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17923135 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13080769 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2509277 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15590046 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2332772 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2332772 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13080769 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4842049 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17922818 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13080769 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4842049 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17922818 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses @@ -668,17 +653,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37916.049275 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46468.592593 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39073.536341 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49633.914894 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49633.914894 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37916.049275 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47941.564356 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40186.401345 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37916.049275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47941.564356 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40186.401345 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37915.272464 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46468.092593 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39072.796992 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49633.446809 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49633.446809 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37915.272464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47941.079208 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40185.690583 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37915.272464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47941.079208 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40185.690583 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 63.324462 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index a586f3039..d53327dbb 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 16783500 # Number of ticks simulated final_tick 16783500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84096 # Simulator instruction rate (inst/s) -host_op_rate 84062 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 264753473 # Simulator tick rate (ticks/s) -host_mem_usage 230292 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 48421 # Simulator instruction rate (inst/s) +host_op_rate 48416 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 152524495 # Simulator tick rate (ticks/s) +host_mem_usage 230316 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 423 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2673172 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12996922 # Sum of mem lat for all requests +system.physmem.totQLat 2672750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12996500 # Sum of mem lat for all requests system.physmem.totBusLat 2115000 # Total cycles spent in databus access system.physmem.totBankLat 8208750 # Total cycles spent in bank access -system.physmem.avgQLat 6319.56 # Average queueing delay per request +system.physmem.avgQLat 6318.56 # Average queueing delay per request system.physmem.avgBankLat 19406.03 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30725.58 # Average memory access latency +system.physmem.avgMemAccLat 30724.59 # Average memory access latency system.physmem.avgRdBW 1613.01 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1613.01 # Average consumed read bandwidth in MB/s @@ -340,13 +325,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 167.397199 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 167.397215 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 140.660988 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.736211 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 140.661002 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.736213 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004293 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000816 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005109 # Average percentage of cache occupancy @@ -433,17 +418,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11527456 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2665331 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14192787 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3719824 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3719824 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11527456 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6385155 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17912611 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11527456 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6385155 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17912611 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11527228 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2665291 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14192519 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3719787 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3719787 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11527228 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6385078 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17912306 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11527228 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6385078 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17912306 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -455,17 +440,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39887.391003 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50289.264151 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41499.377193 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45923.753086 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45923.753086 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39887.391003 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47650.410448 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42346.598109 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39887.391003 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47650.410448 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42346.598109 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39886.602076 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50288.509434 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41498.593567 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45923.296296 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45923.296296 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39886.602076 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47649.835821 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42345.877069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39886.602076 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47649.835821 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42345.877069 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 84.137936 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index b6a3a3279..03f9c34cb 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000015 # Nu sim_ticks 15468000 # Number of ticks simulated final_tick 15468000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31666 # Simulator instruction rate (inst/s) -host_op_rate 57357 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 91020367 # Simulator tick rate (ticks/s) -host_mem_usage 241544 # Number of bytes of host memory used +host_inst_rate 31901 # Simulator instruction rate (inst/s) +host_op_rate 57781 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 91692634 # Simulator tick rate (ticks/s) +host_mem_usage 241568 # Number of bytes of host memory used host_seconds 0.17 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9746 # Number of ops (including micro ops) simulated @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 451 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 231 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1899951 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13161201 # Sum of mem lat for all requests +system.physmem.totQLat 1899500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13160750 # Sum of mem lat for all requests system.physmem.totBusLat 2255000 # Total cycles spent in databus access system.physmem.totBankLat 9006250 # Total cycles spent in bank access -system.physmem.avgQLat 4212.75 # Average queueing delay per request +system.physmem.avgQLat 4211.75 # Average queueing delay per request system.physmem.avgBankLat 19969.51 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29182.26 # Average memory access latency +system.physmem.avgMemAccLat 29181.26 # Average memory access latency system.physmem.avgRdBW 1857.77 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1857.77 # Average consumed read bandwidth in MB/s @@ -536,13 +521,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53148.026316 system.cpu.icache.overall_avg_mshr_miss_latency::total 53148.026316 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 177.982441 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 177.982459 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 144.961595 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 33.020847 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 144.961610 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 33.020849 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004424 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005432 # Average percentage of cache occupancy @@ -626,17 +611,17 @@ system.cpu.l2cache.demand_mshr_misses::total 451 system.cpu.l2cache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12092212 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3030082 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15122294 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3058112 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3058112 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12092212 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6088194 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18180406 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12092212 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6088194 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18180406 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12091981 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3030041 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15122022 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3058056 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3058056 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12091981 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6088097 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18180078 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12091981 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6088097 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18180078 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997340 # mshr miss rate for ReadReq accesses @@ -648,17 +633,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997788 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39908.290429 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42084.472222 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40326.117333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40238.315789 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40238.315789 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39908.290429 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41136.445946 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40311.321508 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39908.290429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41136.445946 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40311.321508 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39907.528053 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42083.902778 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40325.392000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40237.578947 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40237.578947 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39907.528053 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41135.790541 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40310.594235 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39907.528053 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41135.790541 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40310.594235 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 83.496642 # Cycle average of tags in use diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 329680740..8505308fc 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu sim_ticks 24473000 # Number of ticks simulated final_tick 24473000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4068 # Simulator instruction rate (inst/s) -host_op_rate 4068 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7811345 # Simulator tick rate (ticks/s) -host_mem_usage 226312 # Number of bytes of host memory used -host_seconds 3.13 # Real time elapsed on the host +host_inst_rate 87264 # Simulator instruction rate (inst/s) +host_op_rate 87257 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 167537445 # Simulator tick rate (ticks/s) +host_mem_usage 226344 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39808 # Number of bytes read from this memory @@ -78,29 +78,16 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 970 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 253 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 86 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 29 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 22646466 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 53470216 # Sum of mem lat for all requests +system.physmem.totQLat 22645500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 53469250 # Sum of mem lat for all requests system.physmem.totBusLat 4850000 # Total cycles spent in databus access system.physmem.totBankLat 25973750 # Total cycles spent in bank access -system.physmem.avgQLat 23346.87 # Average queueing delay per request +system.physmem.avgQLat 23345.88 # Average queueing delay per request system.physmem.avgBankLat 26777.06 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 55123.93 # Average memory access latency +system.physmem.avgMemAccLat 55122.94 # Average memory access latency system.physmem.avgRdBW 2536.67 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2536.67 # Average consumed read bandwidth in MB/s @@ -717,13 +702,13 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements system.cpu.l2cache.replacements::total 0 # number of replacements -system.cpu.l2cache.tagsinuse 407.828883 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 407.828902 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 824 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002427 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 293.011617 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 114.817266 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 293.011633 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 114.817269 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.008942 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.003504 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.012446 # Average percentage of cache occupancy @@ -807,17 +792,17 @@ system.cpu.l2cache.demand_mshr_misses::total 970 system.cpu.l2cache.overall_mshr_misses::cpu.inst 622 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 970 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40142034 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15600631 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55742665 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10339864 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10339864 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40142034 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25940495 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 66082529 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40142034 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25940495 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 66082529 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40141642 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15600566 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55742208 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10339807 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10339807 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40141642 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25940373 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 66082015 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40141642 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25940373 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 66082015 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997579 # mshr miss rate for ReadReq accesses @@ -829,17 +814,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64537.032154 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77230.846535 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67648.865291 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70820.986301 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70820.986301 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64537.032154 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74541.652299 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68126.318557 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64537.032154 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74541.652299 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68126.318557 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64536.401929 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77230.524752 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67648.310680 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70820.595890 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70820.595890 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64536.401929 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74541.301724 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68125.788660 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64536.401929 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74541.301724 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68125.788660 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 3cd467a4b..7316b9759 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000023 # Nu sim_ticks 23146500 # Number of ticks simulated final_tick 23146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62448 # Simulator instruction rate (inst/s) -host_op_rate 62442 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 95315643 # Simulator tick rate (ticks/s) -host_mem_usage 230224 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host +host_inst_rate 95077 # Simulator instruction rate (inst/s) +host_op_rate 95070 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 145124480 # Simulator tick rate (ticks/s) +host_mem_usage 230244 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 436 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2156686 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12064186 # Sum of mem lat for all requests +system.physmem.totQLat 2156250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12063750 # Sum of mem lat for all requests system.physmem.totBusLat 2180000 # Total cycles spent in databus access system.physmem.totBankLat 7727500 # Total cycles spent in bank access -system.physmem.avgQLat 4946.53 # Average queueing delay per request +system.physmem.avgQLat 4945.53 # Average queueing delay per request system.physmem.avgBankLat 17723.62 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27670.15 # Average memory access latency +system.physmem.avgMemAccLat 27669.15 # Average memory access latency system.physmem.avgRdBW 1205.54 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1205.54 # Average consumed read bandwidth in MB/s @@ -340,13 +325,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49700.996678 system.cpu.icache.overall_avg_mshr_miss_latency::total 49700.996678 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 203.582900 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 203.582912 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005698 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 171.517590 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 32.065310 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 171.517600 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 32.065312 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.005234 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000979 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006213 # Average percentage of cache occupancy @@ -430,17 +415,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10987236 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2575826 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13563062 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3583070 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3583070 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10987236 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6158896 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17146132 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10987236 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6158896 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17146132 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10986993 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2575788 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13562781 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3583035 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3583035 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10986993 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6158823 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17145816 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10986993 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6158823 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17145816 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -452,17 +437,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36746.608696 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48600.490566 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38531.426136 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42153.764706 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42153.764706 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36746.608696 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44629.681159 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39236 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36746.608696 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44629.681159 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39236 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36745.795987 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48599.773585 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38530.627841 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42153.352941 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42153.352941 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36745.795987 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44629.152174 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39235.276888 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36745.795987 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44629.152174 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39235.276888 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 99.212064 # Cycle average of tags in use diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index cd86d7e47..eaa2ab26e 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000024 # Nu sim_ticks 23775500 # Number of ticks simulated final_tick 23775500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69212 # Simulator instruction rate (inst/s) -host_op_rate 69204 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 113962469 # Simulator tick rate (ticks/s) -host_mem_usage 232268 # Number of bytes of host memory used +host_inst_rate 69027 # Simulator instruction rate (inst/s) +host_op_rate 69023 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 113671122 # Simulator tick rate (ticks/s) +host_mem_usage 232284 # Number of bytes of host memory used host_seconds 0.21 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 483 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4632480 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15613730 # Sum of mem lat for all requests +system.physmem.totQLat 4632000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15613250 # Sum of mem lat for all requests system.physmem.totBusLat 2415000 # Total cycles spent in databus access system.physmem.totBankLat 8566250 # Total cycles spent in bank access -system.physmem.avgQLat 9591.06 # Average queueing delay per request +system.physmem.avgQLat 9590.06 # Average queueing delay per request system.physmem.avgBankLat 17735.51 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32326.56 # Average memory access latency +system.physmem.avgMemAccLat 32325.57 # Average memory access latency system.physmem.avgRdBW 1300.16 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1300.16 # Average consumed read bandwidth in MB/s @@ -533,13 +518,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52118.343195 system.cpu.icache.overall_avg_mshr_miss_latency::total 52118.343195 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 224.642209 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 224.642221 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 189.932225 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 34.709984 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 189.932236 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 34.709985 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.005796 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001059 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006856 # Average percentage of cache occupancy @@ -623,17 +608,17 @@ system.cpu.l2cache.demand_mshr_misses::total 483 system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13099526 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4042315 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17141841 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4145826 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4145826 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13099526 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8188141 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 21287667 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13099526 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8188141 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 21287667 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13099263 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4042283 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17141546 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4145788 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4145788 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13099263 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8188071 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21287334 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13099263 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8188071 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21287334 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses @@ -645,17 +630,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38986.684524 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63161.171875 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42854.602500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49949.710843 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49949.710843 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38986.684524 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55701.639456 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44073.844720 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38986.684524 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55701.639456 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44073.844720 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38985.901786 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63160.671875 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42853.865000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49949.253012 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49949.253012 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38985.901786 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55701.163265 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44073.155280 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38985.901786 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55701.163265 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44073.155280 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 99.563734 # Cycle average of tags in use diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 3dd8cecd5..3eb29c400 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000106 # Nu sim_ticks 105801500 # Number of ticks simulated final_tick 105801500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99938 # Simulator instruction rate (inst/s) -host_op_rate 99937 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10207562 # Simulator tick rate (ticks/s) -host_mem_usage 247464 # Number of bytes of host memory used -host_seconds 10.37 # Real time elapsed on the host +host_inst_rate 173787 # Simulator instruction rate (inst/s) +host_op_rate 173787 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17750545 # Simulator tick rate (ticks/s) +host_mem_usage 247480 # Number of bytes of host memory used +host_seconds 5.96 # Real time elapsed on the host sim_insts 1035849 # Number of instructions simulated sim_ops 1035849 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 22848 # Number of bytes read from this memory @@ -59,7 +59,7 @@ system.physmem.bw_total::cpu3.data 7863783 # To system.physmem.bw_total::total 399238196 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 661 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 978 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 732 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 42240 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 42240 # bytesRead derated as per pkt->getSize() @@ -108,26 +108,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 661 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 71 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 377 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 205 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see @@ -160,7 +147,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -193,15 +179,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4077160 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 20692160 # Sum of mem lat for all requests +system.physmem.totQLat 4076500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 20691500 # Sum of mem lat for all requests system.physmem.totBusLat 3305000 # Total cycles spent in databus access system.physmem.totBankLat 13310000 # Total cycles spent in bank access -system.physmem.avgQLat 6168.17 # Average queueing delay per request +system.physmem.avgQLat 6167.17 # Average queueing delay per request system.physmem.avgBankLat 20136.16 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31304.33 # Average memory access latency +system.physmem.avgMemAccLat 31303.33 # Average memory access latency system.physmem.avgRdBW 399.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 399.24 # Average consumed read bandwidth in MB/s @@ -2117,17 +2102,17 @@ system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9965.116279 system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9965.116279 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 425.230692 # Cycle average of tags in use +system.l2c.tagsinuse 425.230696 # Cycle average of tags in use system.l2c.total_refs 1445 # Total number of references to valid blocks. system.l2c.sampled_refs 527 # Sample count of references to valid blocks. system.l2c.avg_refs 2.741935 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.occ_blocks::writebacks 0.824596 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 289.832857 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 289.832859 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.data 59.073855 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 61.730806 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 61.730807 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.data 5.603647 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 4.388881 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 4.388882 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu2.data 0.760374 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu3.inst 2.293580 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu3.data 0.722095 # Average occupied blocks per requestor @@ -2409,43 +2394,43 @@ system.l2c.overall_mshr_misses::cpu2.data 13 # n system.l2c.overall_mshr_misses::cpu3.inst 3 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 661 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13753074 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3705088 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3257128 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 578261 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 230760 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 56252 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 86256 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.data 56252 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 21723071 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13752787 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3705044 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3257064 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 578256 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 230755 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 56251 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 86253 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.data 56251 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 21722661 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 184010 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 190518 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 161513 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 191511 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 727552 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4247116 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 838760 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 720020 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 607520 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 6413416 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 13753074 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 7952204 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 3257128 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1417021 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 230760 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 776272 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 86256 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 663772 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 28136487 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 13753074 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 7952204 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 3257128 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1417021 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 230760 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 776272 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 86256 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 663772 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 28136487 # number of overall MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4247058 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 838755 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 720010 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 607510 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 6413333 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 13752787 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 7952102 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3257064 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1417011 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 230755 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 776261 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 86253 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 663761 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 28135994 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 13752787 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 7952102 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 3257064 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1417011 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 230755 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 776261 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 86253 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 663761 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 28135994 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for ReadReq accesses @@ -2483,43 +2468,43 @@ system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.311792 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50068.756757 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82608.714286 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 38460 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56252 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 28752 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56252 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40986.926415 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50068.162162 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82608 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 28751 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40986.152830 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10222.777778 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.263158 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10094.562500 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10639.500000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10247.211268 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45182.085106 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64520 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60001.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50626.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 48957.374046 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47334.547619 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70851.050000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 38460 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59713.230769 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 28752 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51059.384615 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42566.546142 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47334.547619 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70851.050000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 38460 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59713.230769 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 28752 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51059.384615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42566.546142 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45181.468085 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64519.615385 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60000.833333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50625.833333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 48956.740458 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47333.940476 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70850.550000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 28751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51058.538462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42565.800303 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47333.940476 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70850.550000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 28751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51058.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42565.800303 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt index e7866c92f..adb4052b9 100644 --- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt +++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 29045358432 # Simulator tick rate (ticks/s) -host_mem_usage 222412 # Number of bytes of host memory used -host_seconds 3.44 # Real time elapsed on the host +host_tick_rate 31852968745 # Simulator tick rate (ticks/s) +host_mem_usage 226592 # Number of bytes of host memory used +host_seconds 3.14 # Real time elapsed on the host system.physmem.bytes_read::cpu 213337536 # Number of bytes read from this memory system.physmem.bytes_read::total 213337536 # Number of bytes read from this memory system.physmem.num_reads::cpu 3333399 # Number of read requests responded to by this memory @@ -66,37 +66,24 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 3333400 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 3200711 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 105371 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 4811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3757 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3749 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 3205 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 2146 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1076 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1074 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 546 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see @@ -118,7 +105,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -151,15 +137,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 6115686626 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 69505296626 # Sum of mem lat for all requests +system.physmem.totQLat 6112380100 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 69501990100 # Sum of mem lat for all requests system.physmem.totBusLat 16667000000 # Total cycles spent in databus access system.physmem.totBankLat 46722610000 # Total cycles spent in bank access -system.physmem.avgQLat 1834.67 # Average queueing delay per request +system.physmem.avgQLat 1833.68 # Average queueing delay per request system.physmem.avgBankLat 14016.50 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 20851.17 # Average memory access latency +system.physmem.avgMemAccLat 20850.18 # Average memory access latency system.physmem.avgRdBW 2133.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2133.38 # Average consumed read bandwidth in MB/s @@ -278,9 +263,9 @@ system.monitor.writeBandwidthHist::total 100 # Hi system.monitor.averageWriteBandwidth 0 # Average write bandwidth (bytes/s) system.monitor.totalWrittenBytes 0 # Number of bytes written system.monitor.readLatencyHist::samples 3333399 # Read request-response latency -system.monitor.readLatencyHist::mean 20879.051770 # Read request-response latency -system.monitor.readLatencyHist::gmean 19622.150808 # Read request-response latency -system.monitor.readLatencyHist::stdev 15688.008500 # Read request-response latency +system.monitor.readLatencyHist::mean 20878.092191 # Read request-response latency +system.monitor.readLatencyHist::gmean 19621.155070 # Read request-response latency +system.monitor.readLatencyHist::stdev 15688.085413 # Read request-response latency system.monitor.readLatencyHist::0-32767 3201881 96.05% 96.05% # Read request-response latency system.monitor.readLatencyHist::32768-65535 104731 3.14% 99.20% # Read request-response latency system.monitor.readLatencyHist::65536-98303 5355 0.16% 99.36% # Read request-response latency |