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-rw-r--r--util/cpt_upgraders/arm-miscreg-teehbr.py15
1 files changed, 15 insertions, 0 deletions
diff --git a/util/cpt_upgraders/arm-miscreg-teehbr.py b/util/cpt_upgraders/arm-miscreg-teehbr.py
new file mode 100644
index 000000000..70359ddfa
--- /dev/null
+++ b/util/cpt_upgraders/arm-miscreg-teehbr.py
@@ -0,0 +1,15 @@
+# Add the ARM MISCREG TEEHBR
+def upgrader(cpt):
+ if cpt.get('root','isa') == 'arm':
+ for sec in cpt.sections():
+ import re
+ # Search for all ISA sections
+ if re.search('.*sys.*\.cpu.*\.isa$', sec):
+ mr = cpt.get(sec, 'miscRegs').split()
+ if len(mr) == 161:
+ print "MISCREG_TEEHBR already seems to be inserted."
+ else:
+ mr.insert(51,0); # Add dummy value for MISCREG_TEEHBR
+ cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
+
+legacy_version = 8