summaryrefslogtreecommitdiff
path: root/util/tlm/examples/master_port/tlm.py
diff options
context:
space:
mode:
Diffstat (limited to 'util/tlm/examples/master_port/tlm.py')
-rw-r--r--util/tlm/examples/master_port/tlm.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/util/tlm/examples/master_port/tlm.py b/util/tlm/examples/master_port/tlm.py
index 13c4388a9..0b017a6d1 100644
--- a/util/tlm/examples/master_port/tlm.py
+++ b/util/tlm/examples/master_port/tlm.py
@@ -61,7 +61,7 @@ system.clk_domain = SrcClockDomain(clock = '1.5GHz',
# Create a external TLM port:
system.tlm = ExternalMaster()
system.tlm.port_type = "tlm_master"
-system.tlm.port_data = "memory"
+system.tlm.port_data = "transactor"
# Route the connections:
system.system_port = system.membus.slave