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Diffstat (limited to 'util/tlm/examples/slave_port/tlm.py')
| -rw-r--r-- | util/tlm/examples/slave_port/tlm.py | 78 |
1 files changed, 0 insertions, 78 deletions
diff --git a/util/tlm/examples/slave_port/tlm.py b/util/tlm/examples/slave_port/tlm.py deleted file mode 100644 index ed4db4047..000000000 --- a/util/tlm/examples/slave_port/tlm.py +++ /dev/null @@ -1,78 +0,0 @@ -# Copyright (c) 2015, University of Kaiserslautern -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Matthias Jung - -import m5 -from m5.objects import * - -# This configuration shows a simple setup of a TrafficGen (CPU) and an -# external TLM port for SystemC co-simulation -# -# Base System Architecture: -# +-------------+ +-----+ ^ -# | System Port | | CPU | | -# +-------+-----+ +--+--+ | -# | | | gem5 World -# | +----+ | (see this file) -# | | | -# +-------v------v-------+ | -# | Membus | v -# +----------------+-----+ External Port (see sc_slave_port.*) -# | ^ -# +---v---+ | TLM World -# | TLM | | (see sc_target.*) -# +-------+ v -# - -# Create a system with a Crossbar and a TrafficGenerator as CPU: -system = System() -system.membus = IOXBar(width = 16) -system.physmem = SimpleMemory() # This must be instanciated, even if not needed -system.cpu = TrafficGen(config_file = "tgen.cfg") -system.clk_domain = SrcClockDomain(clock = '1.5GHz', - voltage_domain = VoltageDomain(voltage = '1V')) - -# Create a external TLM port: -system.tlm = ExternalSlave() -system.tlm.addr_ranges = [AddrRange('512MB')] -system.tlm.port_type = "tlm_slave" -system.tlm.port_data = "transactor" - -# Route the connections: -system.cpu.port = system.membus.slave -system.system_port = system.membus.slave -system.membus.master = system.tlm.port - -# Start the simulation: -root = Root(full_system = False, system = system) -root.system.mem_mode = 'timing' -m5.instantiate() -m5.simulate() #Simulation time specified later on commandline |