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-rw-r--r--util/tlm/examples/slave_port/tlm.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/util/tlm/examples/slave_port/tlm.py b/util/tlm/examples/slave_port/tlm.py
index 9d6b26db1..ed4db4047 100644
--- a/util/tlm/examples/slave_port/tlm.py
+++ b/util/tlm/examples/slave_port/tlm.py
@@ -64,7 +64,7 @@ system.clk_domain = SrcClockDomain(clock = '1.5GHz',
system.tlm = ExternalSlave()
system.tlm.addr_ranges = [AddrRange('512MB')]
system.tlm.port_type = "tlm_slave"
-system.tlm.port_data = "memory"
+system.tlm.port_data = "transactor"
# Route the connections:
system.cpu.port = system.membus.slave