5 files changed, 20 insertions, 37 deletions

diff --git a/util/tlm/examples/master_port/main.cc b/util/tlm/examples/master_port/main.cc
index 588d81156..2fb1caeae 100644
--- a/util/tlm/examples/master_port/main.cc
+++ b/util/tlm/examples/master_port/main.cc
@@ -36,8 +36,8 @@
 #include <tlm>
 
 #include "cli_parser.hh"
+#include "master_transactor.hh"
 #include "report_handler.hh"
-#include "sc_master_port.hh"
 #include "sim_control.hh"
 #include "stats.hh"
 #include "traffic_generator.hh"
@@ -50,24 +50,16 @@ sc_main(int argc, char** argv)
 
     sc_core::sc_report_handler::set_handler(reportHandler);
 
-    Gem5SystemC::Gem5SimControl simControl("gem5",
-                                           parser.getConfigFile(),
-                                           parser.getSimulationEnd(),
-                                           parser.getDebugFlags());
+    Gem5SystemC::Gem5SimControl sim_control("gem5",
+                                            parser.getConfigFile(),
+                                            parser.getSimulationEnd(),
+                                            parser.getDebugFlags());
 
     TrafficGenerator trafficGenerator("traffic_generator");
+    Gem5SystemC::Gem5MasterTransactor transactor("transactor", "transactor");
 
-    tlm::tlm_target_socket<>* mem_port =
-      dynamic_cast<tlm::tlm_target_socket<>*>(
-        sc_core::sc_find_object("gem5.memory"));
-
-    if (mem_port) {
-        SC_REPORT_INFO("sc_main", "Port Found");
-        trafficGenerator.socket.bind(*mem_port);
-    } else {
-        SC_REPORT_FATAL("sc_main", "Port Not Found");
-        std::exit(EXIT_FAILURE);
-    }
+    trafficGenerator.socket.bind(transactor.socket);
+    transactor.sim_control.bind(sim_control);
 
     SC_REPORT_INFO("sc_main", "Start of Simulation");
 
diff --git a/util/tlm/examples/master_port/tlm.py b/util/tlm/examples/master_port/tlm.py
index 13c4388a9..0b017a6d1 100644
--- a/util/tlm/examples/master_port/tlm.py
+++ b/util/tlm/examples/master_port/tlm.py
@@ -61,7 +61,7 @@ system.clk_domain = SrcClockDomain(clock = '1.5GHz',
 # Create a external TLM port:
 system.tlm = ExternalMaster()
 system.tlm.port_type = "tlm_master"
-system.tlm.port_data = "memory"
+system.tlm.port_data = "transactor"
 
 # Route the connections:
 system.system_port = system.membus.slave
diff --git a/util/tlm/examples/slave_port/main.cc b/util/tlm/examples/slave_port/main.cc
index 9f1cadc8d..5f555aa32 100644
--- a/util/tlm/examples/slave_port/main.cc
+++ b/util/tlm/examples/slave_port/main.cc
@@ -50,6 +50,7 @@
 #include "report_handler.hh"
 #include "sc_target.hh"
 #include "sim_control.hh"
+#include "slave_transactor.hh"
 #include "stats.hh"
 
 int
@@ -60,31 +61,21 @@ sc_main(int argc, char **argv)
 
     sc_core::sc_report_handler::set_handler(reportHandler);
 
-    Gem5SystemC::Gem5SimControl simControl("gem5",
+    Gem5SystemC::Gem5SimControl sim_control("gem5",
                                            parser.getConfigFile(),
                                            parser.getSimulationEnd(),
                                            parser.getDebugFlags());
-    Target *memory;
 
     unsigned long long int memorySize = 512*1024*1024ULL;
 
-    tlm::tlm_initiator_socket <> *mem_port =
-        dynamic_cast<tlm::tlm_initiator_socket<> *>(
-                    sc_core::sc_find_object("gem5.memory")
-                );
+    Gem5SystemC::Gem5SlaveTransactor transactor("transactor", "transactor");
+    Target memory("memory",
+                  parser.getVerboseFlag(),
+                  memorySize,
+                  parser.getMemoryOffset());
 
-    if (mem_port) {
-        SC_REPORT_INFO("sc_main", "Port Found");
-        memory = new Target("memory",
-                            parser.getVerboseFlag(),
-                            memorySize,
-                            parser.getMemoryOffset());
-
-        memory->socket.bind(*mem_port);
-    } else {
-        SC_REPORT_FATAL("sc_main", "Port Not Found");
-        std::exit(EXIT_FAILURE);
-    }
+    memory.socket.bind(transactor.socket);
+    transactor.sim_control.bind(sim_control);
 
     SC_REPORT_INFO("sc_main", "Start of Simulation");
 
diff --git a/util/tlm/examples/slave_port/run_gem5.sh b/util/tlm/examples/slave_port/run_gem5.sh
index a4a0b8021..fd14689b9 100644
--- a/util/tlm/examples/slave_port/run_gem5.sh
+++ b/util/tlm/examples/slave_port/run_gem5.sh
@@ -37,7 +37,7 @@ BGre='\e[1;31m';
 echo -e "\n${BGre}Create gem5 Configuration${RCol}\n"
 
 ../../../../build/ARM/gem5.opt ../../../../configs/example/fs.py \
---tlm-memory=memory                                         \
+--tlm-memory=transactor                                     \
 --cpu-type=timing                                           \
 --num-cpu=1                                                 \
 --mem-type=SimpleMemory                                     \
diff --git a/util/tlm/examples/slave_port/tlm.py b/util/tlm/examples/slave_port/tlm.py
index 9d6b26db1..ed4db4047 100644
--- a/util/tlm/examples/slave_port/tlm.py
+++ b/util/tlm/examples/slave_port/tlm.py
@@ -64,7 +64,7 @@ system.clk_domain = SrcClockDomain(clock = '1.5GHz',
 system.tlm = ExternalSlave()
 system.tlm.addr_ranges = [AddrRange('512MB')]
 system.tlm.port_type = "tlm_slave"
-system.tlm.port_data = "memory"
+system.tlm.port_data = "transactor"
 
 # Route the connections:
 system.cpu.port = system.membus.slave