1 files changed, 62 insertions, 0 deletions
diff --git a/util/tlm/src/slave_transactor.cc b/util/tlm/src/slave_transactor.cc
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+++ b/util/tlm/src/slave_transactor.cc
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+/*
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Christian Menard
+ */
+
+#include "sc_slave_port.hh"
+#include "sim_control.hh"
+#include "slave_transactor.hh"
+
+namespace Gem5SystemC
+{
+
+Gem5SlaveTransactor::Gem5SlaveTransactor(sc_core::sc_module_name name,
+                                         const std::string& portName)
+    : sc_core::sc_module(name),
+      socket(portName.c_str()),
+      sim_control("sim_control"),
+      portName(portName)
+{
+    if (portName.empty()) {
+        SC_REPORT_ERROR(name, "No port name specified!\n");
+    }
+}
+
+void
+Gem5SlaveTransactor::before_end_of_elaboration()
+{
+    auto* port = sim_control->getSlavePort(portName);
+
+    port->bindToTransactor(this);
+}
+
+}