diff options
Diffstat (limited to 'util')
| -rw-r--r-- | util/tlm/examples/master_port/SConstruct | 77 | ||||
| -rw-r--r-- | util/tlm/examples/master_port/main.cc | 98 | ||||
| -rw-r--r-- | util/tlm/examples/master_port/tlm.py | 75 | ||||
| -rw-r--r-- | util/tlm/examples/master_port/traffic_generator.cc | 154 | ||||
| -rw-r--r-- | util/tlm/examples/master_port/traffic_generator.hh | 77 | ||||
| -rw-r--r-- | util/tlm/sc_master_port.cc | 362 | ||||
| -rw-r--r-- | util/tlm/sc_master_port.hh | 137 | ||||
| -rw-r--r-- | util/tlm/sim_control.cc | 2 |
8 files changed, 982 insertions, 0 deletions
diff --git a/util/tlm/examples/master_port/SConstruct b/util/tlm/examples/master_port/SConstruct new file mode 100644 index 000000000..8ca9959a0 --- /dev/null +++ b/util/tlm/examples/master_port/SConstruct @@ -0,0 +1,77 @@ +#!python + +# Copyright (c) 2016, Dresden University of Technology (TU Dresden) +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Christian Menard + +import os + +gem5_arch = 'ARM' +gem5_variant = 'opt' +#gem5_variant = 'debug' + +gem5_root = '#../../../..' + +target = 'gem5.' + gem5_variant + '.sc' + +env = Environment() + +# Import PKG_CONFIG_PATH from the external environment +if os.environ.has_key('PKG_CONFIG_PATH'): + env['ENV']['PKG_CONFIG_PATH'] = os.environ['PKG_CONFIG_PATH'] + +# search for SystemC +env.ParseConfig('pkg-config --cflags --libs systemc') + +# add include dirs +env.Append(CPPPATH=[gem5_root + '/build/' + gem5_arch, + gem5_root + '/util/systemc', + gem5_root + '/util/tlm']) + +env.Append(LIBS=['gem5_' + gem5_variant]) +env.Append(LIBPATH=[gem5_root + '/build/' + gem5_arch]) + +env.Append(CXXFLAGS=['-std=c++11', + '-DSC_INCLUDE_DYNAMIC_PROCESSES', + '-DTRACING_ON']) + +if gem5_variant == 'debug': + env.Append(CXXFLAGS=['-g', '-DDEBUG']) + +src_systemc = [gem5_root + '/util/systemc/sc_gem5_control.cc', + gem5_root + '/util/systemc/sc_logger.cc', + gem5_root + '/util/systemc/sc_module.cc', + gem5_root + '/util/systemc/stats.cc'] + +src_tlm = Glob(gem5_root + '/util/tlm/*.cc') +src_main = Glob('*.cc') + +main = env.Program(target, src_systemc + src_tlm + src_main) diff --git a/util/tlm/examples/master_port/main.cc b/util/tlm/examples/master_port/main.cc new file mode 100644 index 000000000..205e430ae --- /dev/null +++ b/util/tlm/examples/master_port/main.cc @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2016, Dresden University of Technology (TU Dresden) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Christian Menard + */ + +#include <systemc> +#include <tlm> + +#include "sc_master_port.hh" +#include "sim_control.hh" +#include "stats.hh" +#include "traffic_generator.hh" + +// Defining global string variable decalred in stats.hh +std::string filename; + +void +reportHandler(const sc_core::sc_report& report, + const sc_core::sc_actions& actions) +{ + uint64_t systemc_time = report.get_time().value(); + uint64_t gem5_time = curTick(); + + std::cerr << report.get_time(); + + if (gem5_time < systemc_time) { + std::cerr << " (<) "; + } else if (gem5_time > systemc_time) { + std::cerr << " (!) "; + } else { + std::cerr << " (=) "; + } + + std::cerr << ": " << report.get_msg_type() << ' ' << report.get_msg() + << '\n'; +} + +int +sc_main(int argc, char** argv) +{ + sc_core::sc_report_handler::set_handler(reportHandler); + + SimControl simControl("gem5", argc, argv); + TrafficGenerator trafficGenerator("traffic_generator"); + + filename = "m5out/stats-systemc.txt"; + + tlm::tlm_target_socket<>* mem_port = + dynamic_cast<tlm::tlm_target_socket<>*>( + sc_core::sc_find_object("gem5.memory")); + + if (mem_port) { + SC_REPORT_INFO("sc_main", "Port Found"); + trafficGenerator.socket.bind(*mem_port); + } else { + SC_REPORT_FATAL("sc_main", "Port Not Found"); + std::exit(EXIT_FAILURE); + } + + std::cout << "Starting sc_main" << std::endl; + + sc_core::sc_start(); // Run to end of simulation + + SC_REPORT_INFO("sc_main", "End of Simulation"); + + CxxConfig::statsDump(); + + return EXIT_SUCCESS; +} diff --git a/util/tlm/examples/master_port/tlm.py b/util/tlm/examples/master_port/tlm.py new file mode 100644 index 000000000..13c4388a9 --- /dev/null +++ b/util/tlm/examples/master_port/tlm.py @@ -0,0 +1,75 @@ +# +# Copyright (c) 2016, Dresden University of Technology (TU Dresden) +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Christian Menard +# + +import m5 +from m5.objects import * + +import os + +# Base System Architecture: +# +-----+ ^ +# | TLM | | TLM World +# +--+--+ | (see main.cc) +# | v +# +----------v-----------+ External Port (see sc_master_port.*) +# | Membus | ^ +# +----------+-----------+ | +# | | gem5 World +# +---v----+ | +# | Memory | | +# +--------+ v +# + +# Create a system with a Crossbar and a simple Memory: +system = System() +system.membus = IOXBar(width = 16) +system.physmem = SimpleMemory(range = AddrRange('512MB')) +system.clk_domain = SrcClockDomain(clock = '1.5GHz', + voltage_domain = VoltageDomain(voltage = '1V')) + +# Create a external TLM port: +system.tlm = ExternalMaster() +system.tlm.port_type = "tlm_master" +system.tlm.port_data = "memory" + +# Route the connections: +system.system_port = system.membus.slave +system.physmem.port = system.membus.master +system.tlm.port = system.membus.slave +system.mem_mode = 'timing' + +# Start the simulation: +root = Root(full_system = False, system = system) +m5.instantiate() +m5.simulate() diff --git a/util/tlm/examples/master_port/traffic_generator.cc b/util/tlm/examples/master_port/traffic_generator.cc new file mode 100644 index 000000000..33e94a813 --- /dev/null +++ b/util/tlm/examples/master_port/traffic_generator.cc @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2016, Dresden University of Technology (TU Dresden) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Christian Menard + */ + +#include "base/random.hh" +#include "traffic_generator.hh" + +TrafficGenerator::TrafficGenerator(sc_core::sc_module_name name) + : sc_core::sc_module(name), + requestInProgress(0), + peq(this, &TrafficGenerator::peq_cb) +{ + socket.register_nb_transport_bw(this, &TrafficGenerator::nb_transport_bw); + SC_THREAD(process); +} + +void +TrafficGenerator::process() +{ + auto rnd = Random(time(NULL)); + + unsigned const memSize = (1 << 10); // 512 MB + + while (true) { + + wait(sc_core::sc_time((double)rnd.random(1,100), sc_core::SC_NS)); + + auto trans = mm.allocate(); + trans->acquire(); + + std::string cmdStr; + if (rnd.random(0,1)) // Generate a write request? + { + cmdStr = "write"; + trans->set_command(tlm::TLM_WRITE_COMMAND); + dataBuffer = rnd.random(0,0xffff); + } else { + cmdStr = "read"; + trans->set_command(tlm::TLM_READ_COMMAND); + } + + trans->set_data_ptr(reinterpret_cast<unsigned char*>(&dataBuffer)); + trans->set_address(rnd.random(0, (int)(memSize-1))); + trans->set_data_length(4); + trans->set_streaming_width(4); + trans->set_byte_enable_ptr(0); + trans->set_dmi_allowed(0); + trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); + + // honor the BEGIN_REQ/END_REQ exclusion rule + if (requestInProgress) + sc_core::wait(endRequestEvent); + + std::stringstream ss; + ss << "Send " << cmdStr << " request @0x" << std::hex + << trans->get_address(); + SC_REPORT_INFO("Traffic Generator", ss.str().c_str()); + + // send the request + requestInProgress = trans; + tlm::tlm_phase phase = tlm::BEGIN_REQ; + auto delay = sc_core::SC_ZERO_TIME; + + auto status = socket->nb_transport_fw(*trans, phase, delay); + + // Check status + if (status == tlm::TLM_UPDATED) { + peq.notify(*trans, phase, delay); + } else if (status == tlm::TLM_COMPLETED) { + requestInProgress = 0; + checkTransaction(*trans); + SC_REPORT_INFO("Traffic Generator", "request completed"); + trans->release(); + } + } +} + +void +TrafficGenerator::peq_cb(tlm::tlm_generic_payload& trans, + const tlm::tlm_phase& phase) +{ + if (phase == tlm::END_REQ || + (&trans == requestInProgress && phase == tlm::BEGIN_RESP)) { + // The end of the BEGIN_REQ phase + requestInProgress = 0; + endRequestEvent.notify(); + } else if (phase == tlm::BEGIN_REQ || phase == tlm::END_RESP) + SC_REPORT_FATAL("TLM-2", + "Illegal transaction phase received by initiator"); + + if (phase == tlm::BEGIN_RESP) { + checkTransaction(trans); + SC_REPORT_INFO("Traffic Generator", "received response"); + + // Send end response + tlm::tlm_phase fw_phase = tlm::END_RESP; + + // stress the retry mechanism by deferring the response + auto delay = sc_core::sc_time(5.0, sc_core::SC_NS); + socket->nb_transport_fw(trans, fw_phase, delay); + trans.release(); + } +} + +void +TrafficGenerator::checkTransaction(tlm::tlm_generic_payload& trans) +{ + if (trans.is_response_error()) { + std::stringstream ss; + ss << "Transaction returned with error, response status = %s" + << trans.get_response_string(); + SC_REPORT_ERROR("TLM-2", ss.str().c_str()); + } +} + +tlm::tlm_sync_enum +TrafficGenerator::nb_transport_bw(tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, + sc_core::sc_time& delay) +{ + trans.acquire(); + peq.notify(trans, phase, delay); + return tlm::TLM_ACCEPTED; +} diff --git a/util/tlm/examples/master_port/traffic_generator.hh b/util/tlm/examples/master_port/traffic_generator.hh new file mode 100644 index 000000000..212d363ca --- /dev/null +++ b/util/tlm/examples/master_port/traffic_generator.hh @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2016, Dresden University of Technology (TU Dresden) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Christian Menard + */ + +#ifndef __TRAFFIC_GENERATOR_HH__ +#define __TRAFFIC_GENERATOR_HH__ + +#include <tlm_utils/peq_with_cb_and_phase.h> +#include <tlm_utils/simple_initiator_socket.h> + +#include <systemc> +#include <tlm> + +#include "sc_mm.hh" + +class TrafficGenerator : public sc_core::sc_module +{ + private: + Gem5SystemC::MemoryManager mm; + + tlm::tlm_generic_payload* requestInProgress; + + uint32_t dataBuffer; + + sc_core::sc_event endRequestEvent; + + tlm_utils::peq_with_cb_and_phase<TrafficGenerator> peq; + + public: + tlm_utils::simple_initiator_socket<TrafficGenerator> socket; + + SC_HAS_PROCESS(TrafficGenerator); + + TrafficGenerator(sc_core::sc_module_name name); + + void process(); + + void peq_cb(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase); + + void checkTransaction(tlm::tlm_generic_payload& trans); + + virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, + sc_core::sc_time& delay); +}; + +#endif diff --git a/util/tlm/sc_master_port.cc b/util/tlm/sc_master_port.cc new file mode 100644 index 000000000..06fab51a2 --- /dev/null +++ b/util/tlm/sc_master_port.cc @@ -0,0 +1,362 @@ +/* + * Copyright (c) 2016, Dresden University of Technology (TU Dresden) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Christian Menard + */ + +#include <sstream> + +#include "params/ExternalMaster.hh" +#include "sc_master_port.hh" +#include "sim/system.hh" + +namespace Gem5SystemC +{ + +PacketPtr +SCMasterPort::generatePacket(tlm::tlm_generic_payload& trans) +{ + Request::Flags flags; + auto req = new Request(trans.get_address(), trans.get_data_length(), flags, + owner.masterId); + + MemCmd cmd; + + switch (trans.get_command()) { + case tlm::TLM_READ_COMMAND: + cmd = MemCmd::ReadReq; + break; + case tlm::TLM_WRITE_COMMAND: + cmd = MemCmd::WriteReq; + break; + default: + SC_REPORT_FATAL("SCMasterPort", + "received transaction with unsupported command"); + } + + /* + * Allocate a new Packet. The packet will be deleted when it returns from + * the gem5 world as a response. + */ + auto pkt = new Packet(req, cmd); + pkt->dataStatic(trans.get_data_ptr()); + + return pkt; +} + +void +SCMasterPort::destroyPacket(PacketPtr pkt) +{ + delete pkt; +} + +SCMasterPort::SCMasterPort(const std::string& name_, + const std::string& systemc_name, + ExternalMaster& owner_, + Module& module) + : ExternalMaster::Port(name_, owner_), + tSocket(systemc_name.c_str()), + peq(this, &SCMasterPort::peq_cb), + waitForRetry(false), + pendingRequest(nullptr), + needToSendRetry(false), + responseInProgress(false), + module(module) +{ + auto system = + dynamic_cast<const ExternalMasterParams*>(owner_.params())->system; + + /* + * Register the TLM non-blocking interface when using gem5 Timing mode and + * the TLM blocking interface when using the gem5 Atomic mode. + * Then the magic (TM) in simple_target_socket automatically transforms + * non-blocking in blocking transactions and vice versa. + * + * NOTE: The mode may change during execution. + */ + if (system->isTimingMode()) { + SC_REPORT_INFO("SCMasterPort", "register non-blocking interface"); + tSocket.register_nb_transport_fw(this, + &SCMasterPort::nb_transport_fw); + } else if (system->isAtomicMode()) { + SC_REPORT_INFO("SCMasterPort", "register blocking interface"); + tSocket.register_b_transport(this, &SCMasterPort::b_transport); + } else { + panic("gem5 operates neither in Timing nor in Atomic mode"); + } + + tSocket.register_transport_dbg(this, &SCMasterPort::transport_dbg); +} + +void +SCMasterPort::checkTransaction(tlm::tlm_generic_payload& trans) +{ + if (trans.is_response_error()) { + std::stringstream ss; + ss << "Transaction returned with error, response status = " + << trans.get_response_string(); + SC_REPORT_ERROR("TLM-2", ss.str().c_str()); + } +} + +tlm::tlm_sync_enum +SCMasterPort::nb_transport_fw(tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, sc_core::sc_time& delay) +{ + uint64_t adr = trans.get_address(); + unsigned len = trans.get_data_length(); + unsigned char* byteEnable = trans.get_byte_enable_ptr(); + unsigned width = trans.get_streaming_width(); + + // check the transaction attributes for unsupported features ... + if (byteEnable != 0) { + trans.set_response_status(tlm::TLM_BYTE_ENABLE_ERROR_RESPONSE); + return tlm::TLM_COMPLETED; + } + if (width < len) { // is this a burst request? + trans.set_response_status(tlm::TLM_BURST_ERROR_RESPONSE); + return tlm::TLM_COMPLETED; + } + + // ... and queue the valid transaction + peq.notify(trans, phase, delay); + return tlm::TLM_ACCEPTED; +} + +void +SCMasterPort::peq_cb(tlm::tlm_generic_payload& trans, + const tlm::tlm_phase& phase) +{ + // catch up with SystemC time + module.catchup(); + assert(curTick() == sc_core::sc_time_stamp().value()); + + switch (phase) { + case tlm::BEGIN_REQ: + handleBeginReq(trans); + break; + case tlm::END_RESP: + handleEndResp(trans); + break; + default: + panic("unimplemented phase in callback"); + } + + // the functions called above may have scheduled gem5 events + // -> notify the event loop handler + module.notify(); +} + +void +SCMasterPort::handleBeginReq(tlm::tlm_generic_payload& trans) +{ + sc_assert(!waitForRetry); + sc_assert(pendingRequest == nullptr); + + trans.acquire(); + auto pkt = generatePacket(trans); + + auto tlmSenderState = new TlmSenderState(trans); + pkt->pushSenderState(tlmSenderState); + + if (sendTimingReq(pkt)) { // port is free -> send END_REQ immediately + sendEndReq(trans); + } else { // port is blocked -> wait for retry before sending END_REQ + waitForRetry = true; + pendingRequest = &trans; + } +} + +void +SCMasterPort::handleEndResp(tlm::tlm_generic_payload& trans) +{ + sc_assert(responseInProgress); + + responseInProgress = false; + + checkTransaction(trans); + + if (needToSendRetry) { + sendRetryResp(); + needToSendRetry = false; + } +} + +void +SCMasterPort::sendEndReq(tlm::tlm_generic_payload& trans) +{ + tlm::tlm_phase phase = tlm::END_REQ; + auto delay = sc_core::SC_ZERO_TIME; + + auto status = tSocket->nb_transport_bw(trans, phase, delay); + panic_if(status != tlm::TLM_ACCEPTED, + "Unexpected status after sending END_REQ"); +} + +void +SCMasterPort::b_transport(tlm::tlm_generic_payload& trans, + sc_core::sc_time& t) +{ + auto pkt = generatePacket(trans); + + // send an atomic request to gem5 + Tick ticks = sendAtomic(pkt); + panic_if(!pkt->isResponse(), "Packet sending failed!\n"); + + // one tick is a pico second + auto delay = + sc_core::sc_time((double)(ticks / SimClock::Int::ps), sc_core::SC_PS); + + // update time + t += delay; + + destroyPacket(pkt); + + trans.set_response_status(tlm::TLM_OK_RESPONSE); +} + +unsigned int +SCMasterPort::transport_dbg(tlm::tlm_generic_payload& trans) +{ + auto pkt = generatePacket(trans); + + sendFunctional(pkt); + + destroyPacket(pkt); + + return trans.get_data_length(); +} + +bool +SCMasterPort::get_direct_mem_ptr(tlm::tlm_generic_payload& trans, + tlm::tlm_dmi& dmi_data) +{ + return false; +} + +bool +SCMasterPort::recvTimingResp(PacketPtr pkt) +{ + // exclusion rule + // We need to Wait for END_RESP before sending next BEGIN_RESP + if (responseInProgress) { + sc_assert(!needToSendRetry); + needToSendRetry = true; + return false; + } + + sc_assert(pkt->isResponse()); + + // pay for annotaded transport delays + auto delay = + sc_core::sc_time::from_value(pkt->payloadDelay + pkt->headerDelay); + + auto tlmSenderState = dynamic_cast<TlmSenderState*>(pkt->popSenderState()); + auto& trans = tlmSenderState->trans; + + // clean up + delete tlmSenderState; + destroyPacket(pkt); + + sendBeginResp(trans, delay); + trans.release(); + + return true; +} + +void +SCMasterPort::sendBeginResp(tlm::tlm_generic_payload& trans, + sc_core::sc_time& delay) +{ + tlm::tlm_phase phase = tlm::BEGIN_RESP; + + trans.set_response_status(tlm::TLM_OK_RESPONSE); + + auto status = tSocket->nb_transport_bw(trans, phase, delay); + + if (status == tlm::TLM_COMPLETED || + status == tlm::TLM_UPDATED && phase == tlm::END_RESP) { + // transaction completed -> no need to wait for tlm::END_RESP + responseInProgress = false; + } else if (status == tlm::TLM_ACCEPTED) { + // we need to wait for tlm::END_RESP + responseInProgress = true; + } else { + panic("Unexpected status after sending BEGIN_RESP"); + } +} + +void +SCMasterPort::recvReqRetry() +{ + sc_assert(waitForRetry); + sc_assert(pendingRequest != nullptr); + + auto& trans = *pendingRequest; + + waitForRetry = false; + pendingRequest = nullptr; + + // retry + handleBeginReq(trans); +} + +void +SCMasterPort::recvRangeChange() +{ + SC_REPORT_WARNING("SCMasterPort", + "received address range change but ignored it"); +} + +class SCMasterPortHandler : public ExternalMaster::Handler +{ + Module& module; + + public: + SCMasterPortHandler(Module& module) : module(module) {} + + ExternalMaster::Port* getExternalPort(const std::string& name, + ExternalMaster& owner, + const std::string& port_data) + { + // This will make a new initiatiator port + return new SCMasterPort(name, port_data, owner, module); + } +}; + +void +SCMasterPort::registerPortHandler(Module& module) +{ + ExternalMaster::registerHandler("tlm_master", + new SCMasterPortHandler(module)); +} + +} // namespace Gem5SystemC diff --git a/util/tlm/sc_master_port.hh b/util/tlm/sc_master_port.hh new file mode 100644 index 000000000..f2ac1580e --- /dev/null +++ b/util/tlm/sc_master_port.hh @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2016, Dresden University of Technology (TU Dresden) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Christian Menard + */ + +#ifndef __SC_MASTER_PORT_HH__ +#define __SC_MASTER_PORT_HH__ + +#include <tlm_utils/peq_with_cb_and_phase.h> +#include <tlm_utils/simple_target_socket.h> + +#include <tlm> + +#include <mem/external_master.hh> +#include <sc_module.hh> +#include <sc_peq.hh> + +namespace Gem5SystemC +{ + +/** + * This is a gem5 master port that translates TLM transactions to gem5 packets. + * + * Upon receiving a TLM transaction (b_transport, nb_transport_fw, + * dbg_transport) the port generates a gem5 packet and initializes the packet + * with information from the transaction payload. The original TLM payload is + * added as a sender state to the gem5 packet. This way the payload can be + * restored when the response packet arrives at the port. + * + * If gem5 operates in atomic mode, the master port registers the TLM blocking + * interface and automatically translates non-blocking requests to blocking. + * If gem5 operates in timing mode, the transactor registers the non-blocking + * interface. Then, the transactor automatically translated blocking requests. + * It is assumed that the mode (atomic/timing) does not change during + * execution. + */ +class SCMasterPort : public ExternalMaster::Port +{ + private: + struct TlmSenderState : public Packet::SenderState + { + tlm::tlm_generic_payload& trans; + TlmSenderState(tlm::tlm_generic_payload& trans) + : trans(trans) + { + } + }; + + tlm_utils::peq_with_cb_and_phase<SCMasterPort> peq; + + bool waitForRetry; + tlm::tlm_generic_payload* pendingRequest; + + bool needToSendRetry; + + bool responseInProgress; + + // Keep a reference to the gem5 SystemC module + Module& module; + + public: + tlm_utils::simple_target_socket<SCMasterPort> tSocket; + + protected: + // payload event call back + void peq_cb(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase); + + // The TLM target interface + tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, + sc_core::sc_time& t); + void b_transport(tlm::tlm_generic_payload& trans, sc_core::sc_time& t); + unsigned int transport_dbg(tlm::tlm_generic_payload& trans); + bool get_direct_mem_ptr(tlm::tlm_generic_payload& trans, + tlm::tlm_dmi& dmi_data); + + // Gem5 SCMasterPort interface + bool recvTimingResp(PacketPtr pkt); + void recvReqRetry(); + void recvRangeChange(); + + public: + SCMasterPort(const std::string& name_, + const std::string& systemc_name, + ExternalMaster& owner_, + Module& module); + + static void registerPortHandler(Module& module); + + friend PayloadEvent<SCMasterPort>; + + private: + void sendEndReq(tlm::tlm_generic_payload& trans); + void sendBeginResp(tlm::tlm_generic_payload& trans, + sc_core::sc_time& delay); + + void handleBeginReq(tlm::tlm_generic_payload& trans); + void handleEndResp(tlm::tlm_generic_payload& trans); + + PacketPtr generatePacket(tlm::tlm_generic_payload& trans); + void destroyPacket(PacketPtr pkt); + + void checkTransaction(tlm::tlm_generic_payload& trans); +}; + +} + +#endif diff --git a/util/tlm/sim_control.cc b/util/tlm/sim_control.cc index ef04c6bbd..2423f1fb6 100644 --- a/util/tlm/sim_control.cc +++ b/util/tlm/sim_control.cc @@ -46,6 +46,7 @@ #include <systemc> #include <tlm> +#include "sc_master_port.hh" #include "sc_slave_port.hh" #include "sim/cxx_config_ini.hh" #include "sim/init_signals.hh" @@ -90,6 +91,7 @@ SimControl::SimControl(sc_core::sc_module_name name, int argc_, char** argv_) cxxConfigInit(); Gem5SystemC::SCSlavePort::registerPortHandler(); + Gem5SystemC::SCMasterPort::registerPortHandler(*this); Trace::setDebugLogger(&logger); |