diff options
Diffstat (limited to 'util')
| -rw-r--r-- | util/systemc/main.cc | 9 | ||||
| -rw-r--r-- | util/systemc/stats.cc | 86 | ||||
| -rw-r--r-- | util/systemc/stats.hh | 4 | ||||
| -rw-r--r-- | util/tlm/README | 23 | ||||
| -rw-r--r-- | util/tlm/main.cc | 8 | ||||
| -rw-r--r-- | util/tlm/tlm_elastic.py | 123 |
6 files changed, 231 insertions, 22 deletions
diff --git a/util/systemc/main.cc b/util/systemc/main.cc index 75a77853b..c9fbd48a0 100644 --- a/util/systemc/main.cc +++ b/util/systemc/main.cc @@ -74,6 +74,9 @@ #include "sc_module.hh" #include "stats.hh" +// Defining global string variable decalred in stats.hh +std::string filename; + void usage(const std::string &prog_name) { @@ -289,7 +292,7 @@ void SimControl::run() std::cerr << "Waiting for " << wait_period << "ps for" " SystemC to catch up to gem5\n"; - wait(sc_core::sc_time(wait_period, sc_core::SC_PS)); + wait(sc_core::sc_time::from_value(wait_period)); } config_manager->loadState(*checkpoint); @@ -383,7 +386,11 @@ sc_main(int argc, char **argv) { SimControl sim_control("gem5", argc, argv); + filename = "m5out/stats-systemc.txt"; + sc_core::sc_start(); + CxxConfig::statsDump(); + return EXIT_SUCCESS; } diff --git a/util/systemc/stats.cc b/util/systemc/stats.cc index ef5d9b5d3..54d149474 100644 --- a/util/systemc/stats.cc +++ b/util/systemc/stats.cc @@ -35,6 +35,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Andrew Bardsley + * Matthias Jung + * Abdul Mutaal Ahmad */ /** @@ -45,7 +47,9 @@ * Register with: Stats::registerHandlers(statsReset, statsDump) */ +#include "base/output.hh" #include "base/statistics.hh" +#include "base/stats/text.hh" #include "stats.hh" namespace CxxConfig @@ -56,45 +60,76 @@ void statsPrepare() std::list<Stats::Info *> stats = Stats::statsList(); /* gather_stats -> prepare */ - for (auto i = stats.begin(); i != stats.end(); ++i) - (*i)->prepare(); + for (auto i = stats.begin(); i != stats.end(); ++i){ + Stats::Info *stat = *i; + Stats::VectorInfo *vector = dynamic_cast<Stats::VectorInfo *>(stat); + if (vector){ + (dynamic_cast<Stats::VectorInfo *>(*i))->prepare(); + } + else { + (*i)->prepare(); + } + + } } void statsDump() { - std::cerr << "Stats dump\n"; + bool desc = true; + Stats::Output *output = Stats::initText(filename, desc); Stats::processDumpQueue(); std::list<Stats::Info *> stats = Stats::statsList(); + statsEnable(); statsPrepare(); + output->begin(); /* gather_stats -> convert_value */ for (auto i = stats.begin(); i != stats.end(); ++i) { Stats::Info *stat = *i; - Stats::ScalarInfo *scalar = dynamic_cast<Stats::ScalarInfo *>(stat); + const Stats::ScalarInfo *scalar = dynamic_cast<Stats::ScalarInfo + *>(stat); Stats::VectorInfo *vector = dynamic_cast<Stats::VectorInfo *>(stat); - - if (scalar) { - std::cerr << "SCALAR " << stat->name << ' ' - << scalar->value() << '\n'; - } else if (vector) { - Stats::VResult results = vector->value(); - - unsigned int index = 0; - for (auto e = results.begin(); e != results.end(); ++e) { - std::cerr << "VECTOR " << stat->name << '[' << index - << "] " << (*e) << '\n'; - index++; + const Stats::Vector2dInfo *vector2d = dynamic_cast<Stats::Vector2dInfo + *>(vector); + const Stats::DistInfo *dist = dynamic_cast<Stats::DistInfo *>(stat); + const Stats::VectorDistInfo *vectordist = + dynamic_cast<Stats::VectorDistInfo *>(stat); + const Stats::SparseHistInfo *sparse = + dynamic_cast<Stats::SparseHistInfo *>(stat); + const Stats::InfoProxy <Stats::Vector2d,Stats::Vector2dInfo> *info = + dynamic_cast<Stats::InfoProxy + <Stats::Vector2d,Stats::Vector2dInfo>*>(stat); + + if (vector) { + const Stats::FormulaInfo *formula = dynamic_cast<Stats::FormulaInfo + *>(vector); + if (formula){ + output->visit(*formula); + } else { + const Stats::VectorInfo *vector1 = vector; + output->visit(*vector1); } - std::cerr << "VTOTAL " << stat->name << ' ' - << vector->total() << '\n'; + } else if (vector2d) { + output->visit(*vector2d); + } else if (info){ + output->visit(*info); + } else if (vectordist){ + output->visit(*vectordist); + } else if (dist) { + output->visit(*dist); + } else if (sparse) { + output->visit(*sparse); + } else if (scalar) { + output->visit(*scalar); } else { - std::cerr << "?????? " << stat->name << '\n'; + warn("Stat not dumped: %s\n", stat->name); } } + output->end(); } void statsReset() @@ -108,8 +143,17 @@ void statsEnable() { std::list<Stats::Info *> stats = Stats::statsList(); - for (auto i = stats.begin(); i != stats.end(); ++i) - (*i)->enable(); + for (auto i = stats.begin(); i != stats.end(); ++i){ + Stats::Info *stat = *i; + Stats::VectorInfo *vector = dynamic_cast<Stats::VectorInfo *>(stat); + if (vector){ + (dynamic_cast<Stats::VectorInfo *>(*i))->enable(); + } + else { + (*i)->enable(); + } + + } } } diff --git a/util/systemc/stats.hh b/util/systemc/stats.hh index 360cb6293..9dac960ee 100644 --- a/util/systemc/stats.hh +++ b/util/systemc/stats.hh @@ -35,6 +35,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Andrew Bardsley + * Matthias Jung + * Abdul Mutaal Ahmad */ /** @@ -48,6 +50,8 @@ #ifndef __UTIL_CXX_CONFIG_STATS_H__ #define __UTIL_CXX_CONFIG_STATS_H__ +extern std::string filename; + namespace CxxConfig { diff --git a/util/tlm/README b/util/tlm/README index 126705296..fc620f145 100644 --- a/util/tlm/README +++ b/util/tlm/README @@ -94,3 +94,26 @@ The parameter -o specifies the begining of the memory region (0x80000000). The system should boot now. For conveniance a run_gem5.sh file holds all those commands + + +III. Elastic Trace Setup +======================== + +Elastic traces can also be replayed into the SystemC world. +For more information on elastic traces please refer to: + + - http://www.gem5.org/TraceCPU + + - Exploring System Performance using Elastic Traces: + Fast, Accurate and Portable + R. Jagtap, S. Diestelhorst, A. Hansson, M. Jung, N. Wehn. + IEEE International Conference on Embedded Computer Systems Architectures + Modeling and Simulation (SAMOS), July, 2016, Samos Island, Greece. + +Similar to I. the simulation can be set up with this command: + +> ../../build/ARM/gem5.opt ./tlm_elastic.py + +Then: + +> ./gem5.opt.sc m5out/config.ini diff --git a/util/tlm/main.cc b/util/tlm/main.cc index c06565603..bf442e02b 100644 --- a/util/tlm/main.cc +++ b/util/tlm/main.cc @@ -30,6 +30,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Matthias Jung + * Abdul Mutaal Ahmad */ /** @@ -67,6 +68,9 @@ #include "sim/system.hh" #include "stats.hh" +// Defining global string variable decalred in stats.hh +std::string filename; + void usage(const std::string &prog_name) { std::cerr << "Usage: " << prog_name << ( @@ -296,6 +300,8 @@ sc_main(int argc, char **argv) SimControl sim_control("gem5", argc, argv); Target *memory; + filename = "m5out/stats-tlm.txt"; + tlm::tlm_initiator_socket <> *mem_port = dynamic_cast<tlm::tlm_initiator_socket<> *>( sc_core::sc_find_object("gem5.memory") @@ -319,5 +325,7 @@ sc_main(int argc, char **argv) SC_REPORT_INFO("sc_main", "End of Simulation"); + CxxConfig::statsDump(); + return EXIT_SUCCESS; } diff --git a/util/tlm/tlm_elastic.py b/util/tlm/tlm_elastic.py new file mode 100644 index 000000000..3de0670c0 --- /dev/null +++ b/util/tlm/tlm_elastic.py @@ -0,0 +1,123 @@ +# Copyright (c) 2016, University of Kaiserslautern +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Matthias Jung + +import m5 +import optparse + +from m5.objects import * +from m5.util import addToPath, fatal + +addToPath('../../configs/common/') + +from Caches import * + +# This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU) +# and an external TLM port for SystemC co-simulation. +# +# We assume a DRAM size of 512MB and L1 cache sizes of 32KB. +# +# Base System Architecture: +# +# +-----------+ ^ +# +-------------+ | eTraceCPU | | +# | System Port | +-----+-----+ | +# +------+------+ | $D1 | $I1 | | +# | +--+--+--+--+ | +# | | | | gem5 World +# | | | | (see this file) +# | | | | +# +------v------------v-----v--+ | +# | Membus | v +# +----------------+-----------+ External Port (see sc_port.*) +# | ^ +# +---v---+ | TLM World +# | TLM | | (see sc_target.*) +# +-------+ v +# +# +# Create a system with a Crossbar and an Elastic Trace Player as CPU: + +# Setup System: +system = System(cpu=TraceCPU(cpu_id=0), + mem_mode='timing', + mem_ranges = [AddrRange('512MB')], + cache_line_size = 64) + +# Create a top-level voltage domain: +system.voltage_domain = VoltageDomain() + +# Create a source clock for the system. This is used as the clock period for +# xbar and memory: +system.clk_domain = SrcClockDomain(clock = '1GHz', + voltage_domain = system.voltage_domain) + +# Create a CPU voltage domain: +system.cpu_voltage_domain = VoltageDomain() + +# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock +# is actually used only by the caches connected to the CPU: +system.cpu_clk_domain = SrcClockDomain(clock = '1GHz', + voltage_domain = system.cpu_voltage_domain) + +# Setup CPU and its L1 caches: +system.cpu.createInterruptController() +system.cpu.icache = L1_ICache(size="32kB") +system.cpu.dcache = L1_DCache(size="32kB") +system.cpu.icache.cpu_side = system.cpu.icache_port +system.cpu.dcache.cpu_side = system.cpu.dcache_port + +# Assign input trace files to the eTraceCPU: +system.cpu.instTraceFile="system.cpu.traceListener.inst.gz" +system.cpu.dataTraceFile="system.cpu.traceListener.data.gz" + +# Setting up L1 BUS: +system.membus = IOXBar(width = 16) +system.physmem = SimpleMemory() # This must be instantiated, even if not needed + +# Create a external TLM port: +system.tlm = ExternalSlave() +system.tlm.addr_ranges = [AddrRange('512MB')] +system.tlm.port_type = "tlm" +system.tlm.port_data = "memory" + +# Connect everything: +system.membus = SystemXBar() +system.system_port = system.membus.slave +system.cpu.icache.mem_side = system.membus.slave +system.cpu.dcache.mem_side = system.membus.slave +system.membus.master = system.tlm.port + +# Start the simulation: +root = Root(full_system = False, system = system) +root.system.mem_mode = 'timing' +m5.instantiate() +m5.simulate() #Simulation time specified later on commandline |