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AgeCommit message (Expand)Author
2018-07-25cpu: Warn when (un)serializing a traffic generatorGiacomo Travaglini
2018-07-25cpu: Allow creation of traffic gen from generic SimObjectsGiacomo Travaglini
2018-07-25mem-cache: TempCacheBlk allocates and destroys its own dataRobert Kovacsics
2018-07-24systemc: Flesh out the sc_port implementation slightly.Gabe Black
2018-07-24systemc: Stub out the predefined channels.Gabe Black
2018-07-24systemc: Add systemc and systemc.h header files.Gabe Black
2018-07-24systemc: Stub out the sc_spawn related classes and functions.Gabe Black
2018-07-24systemc: Stub out the sc_process_handle class.Gabe Black
2018-07-24systemc: Seperate the "external" header interface.Gabe Black
2018-07-24systemc: Stub out the sc_module class and related functions.Gabe Black
2018-07-24systemc: Add a stubbed out implementation of the sc_sensitive class.Gabe Black
2018-07-24systemc: Add a stub implementation for sc_attr related classes.Gabe Black
2018-07-24cpu-o3: Missing freeing the heads of DepGraph in IQ squashingHanhwi Jang
2018-07-23systemc: Add a stubbed out sc_event_finder class.Gabe Black
2018-07-23systemc: Implement a stub version of the sc_prim class.Gabe Black
2018-07-23systemc: Add stubbed out versions of sc_port and sc_export.Gabe Black
2018-07-23systemc: Add stubbed out versions of sc_event and related classes.Gabe Black
2018-07-23systemc: Add stubbed out versions of the sc_time functions.Gabe Black
2018-07-23systemc: Add the sc_nbdefs.hh header from Accellera.Gabe Black
2018-07-23systemc: Add a stub version of the sc_interface class.Gabe Black
2018-07-23systemc: Hook up sc_main.Gabe Black
2018-07-23systemc: Partially implement the sc_module_name class.Gabe Black
2018-07-23mem: Rename Packet::checkFunctional to trySatisfyFunctionalRobert Kovacsics
2018-07-20mem: Removed "using namespace std;" from src/mem/packet.ccRobert Kovacsics
2018-07-19mem: Fix off-by-one error in checkFunctional, and simplify itRobert Kovacsics
2018-07-19mem-cache: Typo in comment: 'proceed' -> 'precede'Robert Kovacsics
2018-07-17dev, arm: accept and ignore writes to GIC APRn registersCiro Santilli
2018-07-16systemc: Add a stub kernel SimObject.Gabe Black
2018-07-16systemc: Add a stubbed out sc_object class.Gabe Black
2018-07-16arch-arm: Introduce ARMv8.1 Virtual Timer System RegistersGiacomo Travaglini
2018-07-16arch-arm: Introduce RAS System RegistersGiacomo Travaglini
2018-07-13configs: Update the DRAM sweep script to use PyTrafficGenAndreas Sandberg
2018-07-13cpu: Add a Python-enabled traffic generatorAndreas Sandberg
2018-07-13cpu: Support trace termination in BaseTrafficGenAndreas Sandberg
2018-07-13cpu: Unify error handling for address generatorsAndreas Sandberg
2018-07-13cpu: Split the traffic generator into two classesAndreas Sandberg
2018-07-10misc: Fix BaseCPU doxygenJason Lowe-Power
2018-07-09arch-riscv: enable rudimentary fs simulationRobert
2018-07-09arch-riscv: Fix the srlw and srliw instructions.Austin Harris
2018-06-29base: Add a M5_PUBLIC and M5_LOCAL attribute macroAndreas Sandberg
2018-06-28python: Fix call bug in @cxxMethod when override is TrueAndreas Sandberg
2018-06-28cpu: Remove reduntant protobuf includesAndreas Sandberg
2018-06-28python: Fixup incorrect syntax in PyBind argument handlerAndreas Sandberg
2018-06-28mem: Add a memory delay simulatorAndreas Sandberg
2018-06-28arch-arm: Fix incorrect t{0,1}sz field in TTBCRAndreas Sandberg
2018-06-28base: Add an asymmetrical Coroutine classGiacomo Travaglini
2018-06-26gpu-compute: Remove unneeded Request::setVirt callAlexandru Dutu
2018-06-26python: Add support for multiplying proxies to compatible ParamNikos Nikoleris
2018-06-26scons: Generalize building binaries.Gabe Black
2018-06-25syscall_emul: adding symlink system callMatt Sinclair
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