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2015-06-25ruby: message: remove a data member added by mistakeNilay Vaish
I (Nilay) had mistakenly added a data member to the Message class in revision c1694b4032a6. The data member is being removed.
2015-06-25Ruby: Remove assert in RubyPort retry list logicJason Power
Remove the assert when adding a port to the RubyPort retry list. Instead of asserting, just ignore the added port, since it's already on the list. Without this patch, Ruby+detailed fails for even the simplest tests
2015-06-21base: Add a warn_if macroAndreas Sandberg
Add a warn if macro that is analogous to the panic_if and fatal_if.
2015-06-21arm: Cleanup arch headers to remove dma_device.hh dependencyAndreas Sandberg
Break the dependency on dma_device.hh by forward-declaring DmaPort in the relevant header.
2015-06-09mem: Add check for express snoop in packet destructorAli Jafri
Snoop packets share the request pointer with the originating packets. We need to ensure that the snoop packet destruction does not delete the request. Snoops are used for reads, invalidations, HardPFReqs, Writebacks and CleansEvicts. Reads, invalidations, and HardPFReqs need a response so their snoops do not delete the request. For Writebacks and CleanEvicts we need to check explicitly for whethere the current packet is an express snoop, in whcih case do not delete the request.
2015-06-09mem: Fix snoop packet data allocation bugAndreas Hansson
This patch fixes an issue where the snoop packet did not properly forward the data pointer in case of static data.
2015-06-09arm: Delete debug print in initialization of hardware threadRune Holm
There seems to have been a debug print left in when the original ARMv8 support was merged in. This printout is performed every time you initialize a hardware thread, and it prints raw pointers, so it always causes diffs in the regression. This patch removes the debug print.
2015-06-09arm: Fix typo in ldrsh instruction nameRune Holm
ldrsh was typoed as hdrsh, which is a bit annoying when printing instructions. This patch fixes it.
2015-06-09base: Reset CircleBuf size on flush()Andreas Sandberg
The flush() method in CircleBuf resets the state of the circular buffer, but fails to set size to zero. This obviously confuses code that tries to determine the amount of data in the buffer. Set the size to zero on flush.
2015-06-09dev, arm: Include PIO size in AmbaDmaDevice constructorAndreas Sandberg
Make it possible to specify the size of the PIO space for an AMBA DMA device. Maintain backwards compatibility and default to zero.
2015-06-09scons: Allow GNU assembler version strings with hyphenAndreas Hansson
Make scons a bit more forgiving when determining the GNU assembler version.
2015-06-07ruby: Fix MESI consistency bugMarco Elver
Fixes missed forward eviction to CPU. With the O3CPU this can lead to load-load reordering, as the LQ is never notified of the invalidate. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-06-07mem: Add HMC Timing ParametersMatthias Jung
A single HMC-2500 x32 model based on: [1] DRAMSpec: a high-level DRAM bank modelling tool developed at the University of Kaiserslautern. This high level tool uses RC (resistance-capacitance) and CV (capacitance-voltage) models to estimate the DRAM bank latency and power numbers. [2] A Logic-base Interconnect for Supporting Near Memory Computation in the Hybrid Memory Cube (E. Azarkhish et. al) Assumed for the HMC model is a 30 nm technology node. The modelled HMC consists of a 4 Gbit part with 4 layers connected with TSVs. Each layer has 16 vaults and each vault consists of 2 banks per layer. In order to be able to use the same controller used for 2D DRAM generations for HMC, the following analogy is done: Channel (DDR) => Vault (HMC) device_size (DDR) => size of a single layer in a vault ranks per channel (DDR) => number of layers banks per rank (DDR) => banks per layer devices per rank (DDR) => devices per layer ( 1 for HMC). The parameters for which no input is available are inherited from the DDR3 configuration.
2015-06-07arch: fix build under MacOSXRuslan Bukin ext:(%2C%20Zhang%20Guoye)
put O_DIRECT under ifdefs -- this fixes build for MacOSX. Also use correct class for arm64 openFlagTable. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-05-30mem: addr_mapper: restore old address if request not sentChristoph Pfister
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-06-01sim, arm: add checkpoint upgrader for d02b45a5Curtis Dunham
The insertion of CONTEXTIDR_EL2 in the ARM miscellaneous registers obsoletes old checkpoints.
2015-06-01kvm, arm: Add support for aarch64Andreas Sandberg
This changeset adds support for aarch64 in kvm. The CPU module supports both checkpointing and online CPU model switching as long as no devices are simulated by the host kernel. It currently has the following limitations: * The system register based generic timer can only be simulated by the host kernel. Workaround: Use a memory mapped timer instead to simulate the timer in gem5. * Simulating devices (e.g., the generic timer) in the host kernel requires that the host kernel also simulates the GIC. * ID registers in the host and in gem5 must match for switching between simulated CPUs and KVM. This is particularly important for ID registers describing memory system capabilities (e.g., ASID size, physical address size). * Switching between a virtualized CPU and a simulated CPU is currently not supported if in-kernel device emulation is used. This could be worked around by adding support for switching to the gem5 (e.g., the KvmGic) side of the device models. A simpler workaround is to avoid in-kernel device models altogether.
2015-06-01kvm, arm, dev: Add an in-kernel GIC implementationAndreas Sandberg
This changeset adds a GIC implementation that uses the kernel's built-in support for simulating the interrupt controller. Since there is currently no support for state transfer between gem5 and the kernel, the device model does not support serialization and CPU switching (which would require switching to a gem5-simulated GIC).
2015-06-01kvm: Handle inst events at the current instruction countAndreas Sandberg
There are cases (particularly when attaching GDB) when instruction events are scheduled at the current instruction tick. This used to trigger an assertion error in kvm. This changeset adds a check for this condition and forces KVM to do a quick entry that completes any pending IO operations, but does not execute any new instructions, before servicing the event. We could check if we need to enter KVM at all, but forcing a quick entry is makes the code slightly cleaner and does not hurt correctness (performance is hardly an issue in these cases).
2015-06-01kvm, arm: Move ARM-specific files to arch/arm/kvm/Andreas Sandberg
This changeset moves the ARM-specific KVM CPU implementation to arch/arm/kvm/. This change is expected to keep the source tree somewhat cleaner as we start adding support for ARMv8 and KVM in-kernel interrupt controller simulation. --HG-- rename : src/cpu/kvm/ArmKvmCPU.py => src/arch/arm/kvm/ArmKvmCPU.py rename : src/cpu/kvm/arm_cpu.cc => src/arch/arm/kvm/arm_cpu.cc rename : src/cpu/kvm/arm_cpu.hh => src/arch/arm/kvm/arm_cpu.hh
2015-05-26arm: implement the CONTEXTIDR_EL2 system reg.Curtis Dunham
2015-05-26arm, stats: Update stats to reflect reduction in misc reg readsAndreas Hansson
2015-05-26arm: Make address translation faster with better cachingNathanael Premillieu
This patch adds better caching of the sys regs for AArch64, thus avoiding unnecessary calls to tc->readMiscReg(MISCREG_CPSR) in the non-faulting case.
2015-05-26base: Allow multiple interleaved rangesAndreas Hansson
This patch changes how the address range calculates intersection such that a system can have a number of non-overlapping interleaved ranges without complaining. Without this patch we end up with a panic.
2015-05-26stats: Update MinorCPU regressions after accounting fixAndreas Hansson
2015-05-26cpu: Fix a bug in counting issued instructions in MinorCPUAndrew Bardsley
The MinorCPU would count bubbles in Execute::issue as part of the num_insts_issued and so sometimes reach the instruction issue limit incorrectly. Fixed by checking for a bubble in one new place.
2015-05-26arm: Implement some missing syscalls (SE mode)Giacomo Gabrielli
Adding a few syscalls that were previously considered unimplemented.
2015-05-26ruby: Deprecation warning for RubyMemoryControlAndreas Hansson
A step towards removing RubyMemoryControl and shift users to DRAMCtrl. The latter is faster, more representative, very versatile, and is integrated with power models.
2015-05-23arm, stats: Update stats to reflect changes to generic timerAndreas Sandberg
The addition of a virtual timer affects stats in minor and o3.
2015-05-23arm, dev: Add support for a memory mapped generic timerAndreas Sandberg
There are cases when we don't want to use a system register mapped generic timer, but can't use the SP804. For example, when using KVM on aarch64, we want to intercept accesses to the generic timer, but can't do so if it is using the system register interface. In such cases, we need to use a memory-mapped generic timer. This changeset adds a device model that implements the memory mapped generic timer interface. The current implementation only supports a single frame (i.e., one virtual timer and one physical timer).
2015-05-23arm: Get rid of pointless have_generic_timer paramAndreas Sandberg
The ArmSystem class has a parameter to indicate whether it is configured to use the generic timer extension or not. This parameter doesn't affect any feature flags in the current implementation and is therefore completely unnecessary. In fact, we usually don't set it even if a system has a generic timer. If we ever need to check if there is a generic timer present, we should just request a pointer and check if it is non-null instead.
2015-05-23dev, arm: Add virtual timers to the generic timer modelAndreas Sandberg
The generic timer model currently does not support virtual counters. Virtual and physical counters both tick with the same frequency. However, virtual timers allow a hypervisor to set an offset that is subtracted from the counter when it is read. This enables the hypervisor to present a time base that ticks with virtual time in the VM (i.e., doesn't tick when the VM isn't running). Modern Linux kernels generally assume that virtual counters exist and try to use them by default.
2015-05-23dev, arm: Refactor and clean up the generic timer modelAndreas Sandberg
This changeset cleans up the generic timer a bit and moves most of the register juggling from the ISA code into a separate class in the same source file as the rest of the generic timer. It also removes the assumption that there is always 8 or fewer CPUs in the system. Instead of having a fixed limit, we now instantiate per-core timers as they are requested. This is all in preparation for other patches that add support for virtual timers and a memory mapped interface.
2015-05-23kvm: Fix dumping code for large registersAndreas Sandberg
The register dumping code in kvm tries to print the bytes in large registers (128 bits and larger) instead of printing them as hex. This changeset fixes that.
2015-05-23kvm, x86: Guard x86-specific APIs in KvmVMAndreas Sandberg
Protect x86-specific APIs in KvmVM with compile-time guards to avoid breaking ARM builds.
2015-05-23build: Don't test for KVM xsave support on ARMAndreas Sandberg
The current build tests for KVM unconditionally check for xsave support. This obviously never works on ARM since xsave is x86-specific. This changeset refactors the build tests probing for KVM support and moves the xsave test to an x86-specific section of is_isa_kvm_compatible().
2015-05-23arm: Workaround incorrect HDLCD register order in kernelAndreas Sandberg
Some versions of the kernel incorrectly swap the red and blue color select registers. This changeset adds a workaround for that by swapping them when instantiating a PixelConverter.
2015-05-23base: Redesign internal frame buffer handlingAndreas Sandberg
Currently, frame buffer handling in gem5 is quite ad hoc. In practice, we pass around naked pointers to raw pixel data and expect consumers to convert frame buffers using the (broken) VideoConverter. This changeset completely redesigns the way we handle frame buffers internally. In summary, it fixes several color conversion bugs, adds support for more color formats (e.g., big endian), and makes the code base easier to follow. In the new world, gem5 always represents pixel data using the Pixel struct when pixels need to be passed between different classes (e.g., a display controller and the VNC server). Producers of entire frames (e.g., display controllers) should use the FrameBuffer class to represent a frame. Frame producers are expected to create one instance of the FrameBuffer class in their constructors and register it with its consumers once. Consumers are expected to check the dimensions of the frame buffer when they consume it. Conversion between the external representation and the internal representation is supported for all common "true color" RGB formats of up to 32-bit color depth. The external pixel representation is expected to be between 1 and 4 bytes in either big endian or little endian. Color channels are assumed to be contiguous ranges of bits within each pixel word. The external pixel value is scaled to an 8-bit internal representation using a floating multiplication to map it to the entire 8-bit range.
2015-05-23base: Clean up bitmap generation codeAndreas Sandberg
The bitmap generation code is hard to follow and incorrectly uses the size of an enum member to calculate the size of a pixel. This changeset cleans up the code and adds some documentation.
2015-05-19ruby: Fix RubySystem warm-up and cool-down scopeJoel Hestness
The processes of warming up and cooling down Ruby caches are simulation-wide processes, not just RubySystem instance-specific processes. Thus, the warm-up and cool-down variables should be globally visible to any Ruby components participating in either process. Make these variables static members and track the warm-up and cool-down processes as appropriate. This patch also has two side benefits: 1) It removes references to the RubySystem g_system_ptr, which are problematic for allowing multiple RubySystem instances in a single simulation. Warmup and cooldown variables being static (global) reduces the need for instance-specific dereferences through the RubySystem. 2) From the AbstractController, it removes local RubySystem pointers, which are used inconsistently with other uses of the RubySystem: 11 other uses reference the RubySystem with the g_system_ptr. Only sequencers have local pointers.
2015-05-15arm: Identify table-walker requestsAndreas Hansson
This patch ensures all page-table walks are flagged as such.
2015-05-15misc: Appease gcc 5.1Andreas Hansson
Three minor issues are resolved: 1. Apparently gcc 5.1 does not like negation of booleans followed by bitwise AND. 2. Somehow the compiler also gets confused and warns about NoopMachInst being unused (removing it causes compilation errors though). Most likely a compiler bug. 3. There seems to be a number of instances where loop unrolling causes false positives for the array-bounds check. For now, switch to std::array. Potentially we could disable the warning for newer gcc versions, but switching to std::array is probably a good move in any case.
2015-05-15sim: Don't clear the active CPU vector in System::initStateAndreas Sandberg
The system class currently clears the vector of active CPUs in initState(). CPUs are added to the list by registerThreadContext() which is called from BaseCPU::init(). This obviously breaks when the System object is initialized after the CPUs. This changeset removes the offending clear() call since the list will be empty after it has been instantiated anyway.
2015-05-15config: Use null memory for DRAM sweep scriptAndreas Hansson
Do not waste time when we do not care about the data.
2015-05-15config: Add new MemConfig options to DRAM sweep scriptWendy Elsasser
Update script to match current MemConfig options with external_memory_system option set to 0.
2015-05-05syscall_emul: fix warn_once behaviorSteve Reinhardt
The current ignoreWarnOnceFunc doesn't really work as expected, since it will only generate one warning total, for whichever "warn-once" syscall is invoked first. This patch fixes that behavior by keeping a "warned" flag in the SyscallDesc object, allowing suitably flagged syscalls to warn exactly once per syscall.
2015-05-05stats, arm: Update stats for missing FPEXC.EN checkAndreas Hansson
Only one regression is affected.
2015-05-05arm: Add missing FPEXC.EN checkAndreas Hansson
Add a missing check to ensure that exceptions are generated properly.
2015-05-05arm: enable DCZVA by default in SE modeGiacomo Gabrielli
2015-05-05stats: Update stats to reflect cache changesAndreas Hansson