summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2019-11-04mem-cache: Modify compressor to appease newer compilersDaniel R. Carvalho
The type of the local unique_ptr variable was different from the return type. In C++11 because of such difference, a copy-ellision would not be possible, and that required the use of a std::move. In C++14 the restriction of same types being required was removed, so std::move would not be needed anymore. With the addition of the -Wredundant-move warning in newer compilers, having the std::move on the return became an issue, breaking compilation. Change-Id: I45d18dfc500bb5db5fe360814feb91853c735a19 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22403 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-11-04mem-cache: Implement a perfect compressorDaniel R. Carvalho
Implement a perfect compressor that always manages to compresses data exactly to its maximum allowed compression ratio. This allows tracking a compression upper bound. Change-Id: Ibc68bf2dc84b75207795d5ba6304b9ed6dbeae8f Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21160 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Make BDI a multi compressorDaniel R. Carvalho
BDI is a compressor containing multiple sub-compressors. Change-Id: I98411e2ef9dcc2182801a172dfc59ed7a8ee7dd4 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21159 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Implement a multi compressorDaniel R. Carvalho
Implement a compressor that contains multiple sub-compressors and choses the one that provides the best compression results for each compression. Change-Id: I758cf67c84bd85edbea16b2a07b2068b00454461 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21158 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-04mem-cache: Implement BDI sub-compressorsDaniel R. Carvalho
Implement sub-compressors of BDI as public compressors so that they can be used separately. Change-Id: I710e35f39f4abb82fd02fd33b1b86a3f214c12cb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21157 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Implement a repeated values compressorDaniel R. Carvalho
The repeated values compressor can only compress data composed solely repeated instances of the same value. Change-Id: If2c4f47ad4af492d202ec2017e30ba52ee67e307 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21156 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Implement a zero compressorDaniel R. Carvalho
The zero compressor can only compress data composed solely of zero bits. Change-Id: I8b359c03776a8748abd144a178bda944b5a1b766 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21155 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Implement FPC-D cache compressionDaniel R. Carvalho
Implementation of Frequent Pattern Compression with limited Dictionary support (FPC-D) cache compressor, as described in "Opportunistic Compression for Direct-Mapped DRAM Caches", by Alameldeen et al. Change-Id: I26cc1646f95400b6a006f89754f6b2952f5b4aeb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21154 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-02arch,cpu: Move endianness conversion of inst bytes into the ISA.Gabe Black
It doesn't matter if the bytes are converted before or after they're fed into the decoder. The ISA already knows what endianness to use implicitly, and this frees the CPU which doesn't from having to worry about it. Change-Id: Id6574ee81bbf4f032c1d7b2901a664f2bd014fbc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22343 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-01mem: Delete the packet accessors which use guest endianness.Gabe Black
These accessors create an extra dependency on the guest OS, and can be avoided. Now that all their uses have been removed, they aren't needed any more. Change-Id: I466c07fef99bce2d7964c07a7ac3dd398691378b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13465 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-11-01arch-x86: Fix FLDCW_P and FNSTCW_P to use rip.seanzw
FLDCW_P and FNSTCW_P should use rip to compute address. Change-Id: Ide7327e243d42bdd8791e43773385b2a79d45418 Signed-off-by: Zhengrong Wang <seanzw@ucla.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22483 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-01tests: add squashfs make to m5-exitCiro Santilli
An ARM squashfs rootfs that runs m5 exit can be generated for example with: make ARCH=arm_A64 CROSS_COMPILE=aarch64-linux-gnu- squashfs The existing Makefile.x86 was not used as a basis because we would like to provide a setup that allows users to use their own compilers if they wish, without requiring dockcross. Change-Id: I19c54cf0575b405f191f45aaf1e4a05c3f2e69ae Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22223 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-01arch-arm: generic method for getting an ArmSystemAdrian Herrera
This patch provides a generic method for casting a System object into an ArmSystem object. This is specially useful in dev-arm, since devices by default obtain a generic System reference which needs to be casted to use ArmSystem-specific functionality. Change-Id: Ib100002413cb48cd93772dcf38f13be65badd1d3 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22426 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-01dev-arm: Add SMMUv3 to VExpress_GEM5_V*Giacomo Travaglini
The VExpress_GEM5_V* Platforms will now optionally make use of the SMMUv3. In order to attach a devices to it, a user must simply use the attachSmmu method, making sure the device it is not part of the _on_chip_devices(). Change-Id: Ib819eb50d43dba1f5e5d1a1f7159ac4fbaccff6e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21559 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-01config: Add --kernel-cmd option in fs_bigLITTLE.pyChun-Chen TK Hsu
Allow users to specify their custom Linux kernel command. Change-Id: I1e88523c918369ea5dd86c088eca82471663e76a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20900 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-11-01config: Add --mem-size option in fs_bigLITTLE.pyChun-Chen TK Hsu
Allow users to specify system memory size. Change-Id: I1e0c099dc08d04f71b406d8cc86850f68b6048cb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20899 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-31fastmodel: Add CortexA76x[234] models.Gabe Black
These use the parameterization added in earlier commits. Change-Id: Id7b99b97894f8fc1f1e5cc34e3e5d32146fed1c7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21505 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-31fastmodel: Enable auto bridging and use it to simplify CortexA76x1.Gabe Black
This lets us avoid having to set up bridges for all the different interrupt signals coming out of the CPU. When we have more cores, like in the x2, x3, and x4 versions of the CPU, we won't have to have a set of bridges for each set of signals, and can connect them all to external ports using array notation, keeping everything simple, concise, and maintainable. Change-Id: I1a5f707073868516e93c106dc17d105409de668a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21504 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-31fastmodel: Templatize the xn versions of the CortexA76.Gabe Black
This will make it a lot easier and more succinct to define the x2-x4 versions of that CPU. Change-Id: I951cd3af4419c62892c57968e729fd11c0e4a59e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21503 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-31cpu-o3,tests: add page boundary access testBrandon Potter
The O3 model supports unaligned accesses across page boundaries. This changeset provides a stress test for the feature. Other benchmarks exercise it, but their coverage is spotty. This test does nothing else except poke bytes which straddle page boundaries. Change-Id: Ic20c2862bcb7af7be091030c12916ba499db10c7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22303 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-31mem-cache: Fix missing header in associative setDaniel R. Carvalho
Add missing intmath header to AssociativeSet, so that isPowerOf2 can be used. error: there are no arguments to 'isPowerOf2' that depend on a template parameter, so a declaration of 'isPowerOf2' must be available Change-Id: Ib2b194f9e71284ee439786bdb76d99858e57e2f5 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22444 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-31mem-ruby: Fixed pipeline squashes caused by aliased requestsJoe Gross
This patch was created by Bihn Pham during his internship at AMD. This patch fixes a very significant performance bug when using the O3 CPU model and Ruby. The issue was Ruby returned false when it received a request to the same address that already has an outstanding request or when the memory is blocked. As a result, O3 unnecessary squashed the pipeline and re-executed instructions. This fix merges readRequestTable and writeRequestTable in Sequencer into a single request table that keeps track of all requests and allows multiple outstanding requests to the same address. This prevents O3 from squashing the pipeline. Change-Id: If934d57b4736861e342de0ab18be4feec464273d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21219 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-31configs: Add baremetal.py example scriptGiacomo Travaglini
Change-Id: I7a4818836decbf743f6c9b1f2e5361a43fca2d10 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21799 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-31cpu-o3: bugfix for partial faults in x86Brandon Potter
The c58cb8c9 changeset broke some code related to checking consistency model guarantees (found in X86 benchmarks). This changeset adds some documentation to the code and obviates the problem. Change-Id: Ied9c6b0b1d237538efe4beb2f97ef76248ce2746 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22283 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2019-10-31ext: Fix undefined-behavior bug in bitshiftSamuel Grayson
If a small number or zero is passed in, fp64_exp could be very negative (-1000 for example). The intent of the line is to evaluate to zero in these cases, but what it actually did was bitshift right by 1000, which is undefined behavior (according to ubsan) that so happens to result in 0 on GCC/most architectures. This commit changes the code to check for cases where the bitshift is larger than the width of the integer. Change-Id: I8de4bd8ad170f0321d54689460de449b7f8fb60a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21859 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-31alpha: Convert htog and gtoh to htole and letoh.Gabe Black
When within the Alpha arch, we know the guest endianness already. Change-Id: Iee22a33451a06c6e6a5c7d1e8c71f0b00e98ae3f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22367 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-10-30arch,sim: Make copyStringArray take an explicit endianness.Gabe Black
Change-Id: I5cf4291b19dd2d2bdbbf145ad8e00994fabf5547 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22366 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30kern: When dumping dmesg, detect the byte order dynamically.Gabe Black
The dmesg dumper has access to the system object and so has access to the getGuestByteOrder accessor. Use that instead of TheISA to determine the byte order. Change-Id: I4df7b1bcd807aaced1d7dc8d2030123e2d4d1d2b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22365 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30sim: Use the system and OS to get endianness.Gabe Black
This converts the syscall implementations to either use the OS::byteOrder constant or, if that's not available, the system's getGuestByteOrder() accessor, to determine the byte order, instead of relying on TheISA to provide the correct accessor. Change-Id: Idf7b02ee8d73990224ceac9a5efaec91a5ebf79f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22364 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30arch: Make endianness a property of the OS class syscalls can consume.Gabe Black
That way the syscall implementations won't have to find the right endianness to use on their own, typically by referring to TheISA. Change-Id: I186b2f419d5dbee72cc9b5abce7356f3143f0c83 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22363 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30dev: Make the virtio devices track endianness explicitly.Gabe Black
These classes now track what endianness they're supposed to use explicitly, initially set by the getGuestByteOrder accessor on the system object. In the future, if the endianness depends on the version of the VirtIO spec as the comment suggest, it will be easier to dynamically set the endianness in the various structures based on the version being used, Since there isn't anything special about the virt IO versions of these converters other than their types, and since the endianness conversion infrastructure can be taught how to convert new types, the code was switched over to using the standard htog and gtoh but with the explicit byte order provided. This also gets rid of the final use of TheISA in the dev directory. Change-Id: I9345e3295eb27fc5eb87e8ce0d8d424ad1e75d2d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22273 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30sim: Add a getGuestByteOrder accessor to the system class.Gabe Black
This goes along with the existing getPageBytes, etc., accessors, and paves the way for this to be a parameter of the System class. Change-Id: Ibfe2d591185d23beccdd5bbff1092dc07b1278ac Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22272 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30misc: Update MAINTAINERS fileJason Lowe-Power
Add systemc tag and add Bobby as a tests maintainer. Change-Id: Idc890365387f7e99543067d2e02ce0caadf785df Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22304 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30fastmodel: Refactor the CortexA76x1 model for MP support.Gabe Black
This change inverts the relationship between the fast model and gem5 CPUs, and factors out the parts of the CortexA76x1 which are per core vs. per cluster. Change-Id: I33eacc2461f08c7fd1784936b230e96c768c0e79 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21501 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30dev: Adding support for large BARPouya Fotouhi
During PCI setup, this patch checks if a Base Address Register (BAR) is used as a large BAR (64 bits rather than 32), and return proper address range. The order which updates are done is decided by kernel, so this patch implements both cases (writing lower or upper bits first). Bit 2 in a BAR indicates a 64-bit decoder (10X to be more exact, 11X is reserved). The addresses in BARAddrs are full addresses and are set to zero for BAR providing upper 32 bits to avoid conflicts in addr ranges reported. Change-Id: I93303d36ac83dab9ed6837c81e77c9dfb778f409 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22082 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30base: Name segments after their indexGiacomo Travaglini
Current loader is performing a linear scan of the section table for every segment in the elf since it is naming every segment after the sections it contains. With this patch we are just naming segments after their index. This is in any case how they are referenced when a readelf --segments command is issued on the elf file. Change-Id: I599400fcdfc0b80ac64632aba36781bd876777f0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21999 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30cpu-o3: Fix handling of some mem. order violationsGiacomo Gabrielli
This patch fixes the handling of memory order violations due to snoops targeting out-of-order loads: the re-execution triggered in these cases is achieved by raising a ReExec fault, but such a fault was not handled correctly after the code changes introduced in changeset 46da8fb. Change-Id: I2abe161a90468412f56cb28dcc92729326cba1cd Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21819 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Timothy Hayes <timothy.hayes@arm.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-30dev: Remove TheISA from ns_gige.cc.Gabe Black
It was not being used there. Change-Id: Ib39cfb52553e0556f7a6ad616e1029c74fa90e1f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22271 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-30dev: Stop including config/the_isa.hh unnecessarily.Gabe Black
This file was included in a few files which didn't use TheISA. Change-Id: Ib296b88dc6cfe9d487ee31cf385bb872d2cffaf2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22270 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-30dev: Get PageBytes from the system in the ARM generic timer.Gabe Black
These will ultimately by ArmISA::PageBytes, but this is more consistent with other devices which don't know what ISA they're part of. Change-Id: Iac13d5010564512207ed009377a771ee5949eff3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22269 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-30dev: Get PageBytes from the system in the ide_disk model.Gabe Black
This avoids having to use TheISA::. Change-Id: I020860ab343f9b6fafbcb0e23479d0b64f094512 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22268 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-30dev: Remove using namespace std and TheISA from ide_disk.cc.Gabe Black
Neither was necessary since either that namespace wasn't used, or was used explicitly when referenced. Change-Id: I96d2791c09250255e7e65d47cbb6f65eb4fcb3ba Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22267 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-30fastmodel: Helper function to setup FastModels for simulationChun-Chen TK Hsu
This function sets up ARM license, simulation name, and minimum synchronize latency in FastModels. This function should be called once per simulation. Change-Id: Ic3408955aaff9f8b4e2b72d2f2b0da97b41bfc3f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22183 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30arm: Get rid of using namespace std and TheISA in realview.cc.Gabe Black
Neither was actually used by the nearly empty file. Change-Id: Ief1b77b18c8c616511bf9870e1667439a42dfcbd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22266 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30dev: Remove SINIC_VTOPHYS and related code.Gabe Black
The code in this #ifdef isn't turned on by anything, and either has or likely will bitrot, especially since there are no tests to even determine manually if the code they guard works. They are also preceeded by panics which say that the code they guard is known not to work now anyway. This change also gets rid of TheISA in that file since the only reason it was around was for vtophys in the guarded code. Change-Id: I59fd8974d0dd3d7ab0d5a8ccfa6a446d2da41eb0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22265 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30alpha: Remove TheISA from the Alpha devices.Gabe Black
These are the from the various bits of the tsunami platform. They primarily consisted of "using TheISA" which could be replaced with using AlphaISA or removed altogether (I went with the later), and use of TheISA:: which I replaced with AlphaISA::. Change-Id: Ic52577c65241a92a3f1ae318a19431f8faa50a66 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22264 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30x86: Remove TheISA from x86 devices.Gabe Black
This was really only in the PC platform class. Change-Id: I5365d965ea335a7c45be9f80706a875b19ed0417 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22263 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30sparc: Create a helper functions to install firmware images.Gabe Black
The first function handles the repetitive process of creating an ObjectFile for a particular purpose and checking if that was successful. The second conditionally offsets the images in case they were, for instance, loaded from an ELF file which already had them in the right place. It offsets them so that their entry point (which will be zero for raw images) lines up with the appropriate entry address (which will be at the start of raw images). This is more correct in more cases, and also removes a lot of redundancy. There's still a lot of redundancy in the code which sets up the symbol tables, but there are some irregularities which make that harder to wrap in a helper function. Change-Id: I2fee8b2175faff284ff9e007307f7769043497a1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21469 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Add a repeated value pattern to compressorsDaniel R. Carvalho
The repeated value pattern checks if values are composed of multiple instances of the same value. If successful, the bits of the repeated value are included only once in the compressed data. Change-Id: Ia7045b4e33a91fd8d712fe1ca689f7f8cb4e5feb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21153 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Inform unused bits instead of bytes in compressor patternDaniel R. Carvalho
Increase pattern precision by giving the number of unmatched bits instead of bytes. Change-Id: I5efbe9c31672cc973b4c89c741cdc8cc28d26285 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21152 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 08:41:22 +0000