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2007-04-03Made the "data" field of store queue entries into a character array. It's ↵Gabe Black
sized to match an IntReg which was what it used to be, but we might want to make it something architecture independent. All data is now endian converted before entering the store queue entries which simplifies store to load forwarding in "trans endian" simulations, and makes twin memory ops work. src/cpu/o3/lsq_unit.hh: src/cpu/o3/lsq_unit_impl.hh: fixed twin memory operations. --HG-- extra : convert_revision : 8fb97f98e285cd22413e06e146fa82392ac2a590
2007-04-03Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemAli Saidi
into zizzer.eecs.umich.edu:/tmp/newmem.1449b --HG-- extra : convert_revision : 05021f4884de7af769df9f9c4416c483baa9c2fe
2007-04-03fixed sttw instruction changes execution trace a bitAli Saidi
--HG-- extra : convert_revision : 4bebe6f9acedfd29dfe02f16d4ddb551a2fc7290
2007-04-03Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : 7be8ebe55a7b11552d78701520f93aa86db1e501
2007-04-03A batch of changes and fixes. Macroops are now generated automatically, ↵Gabe Black
multiops do alot more of what they're supposed to (excluding memory operands), and microops are slightly more implemented. --HG-- extra : convert_revision : 518059f47e11df50aa450d4a322ef2ac069c99c9
2007-04-03Zero out ModRM if the byte isn't there, and fix some displacement size stuff.Gabe Black
--HG-- extra : convert_revision : f43abf33a223a665b30098c63011fb162200d5e6
2007-04-02Remove/comment out DPRINTFs that were causing a segfault.Kevin Lim
The removed ones were unnecessary. The commented out ones could be useful in the future, should this problem get fixed. See flyspray task #243. src/cpu/o3/commit_impl.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/lsq_impl.hh: src/cpu/o3/lsq_unit_impl.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/rob_impl.hh: Remove/comment out DPRINTFs that were causing a segfault. --HG-- extra : convert_revision : b5aeda1c6300dfde5e0a3e9b8c4c5f6fa00b9862
2007-04-02Fix up SPARC's CPU builder to match changes to Alpha's CPU builder.Kevin Lim
--HG-- extra : convert_revision : ec2a739f1da07f0922c772e6998017995115ce80
2007-03-30Update refs for recent changes.Kevin Lim
--HG-- extra : convert_revision : 30a02eec4d83c4e1708ed0a4e2b5faea88fe8e03
2007-03-29Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 2f7f50f4ad31f741c0c67db96e49d30ca078fc94
2007-03-29make serialization at least seem to workAli Saidi
--HG-- extra : convert_revision : cbfdb64f9a204670b8dd0294c74a17044b9f330c
2007-03-29Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : e6a6c65cb0f8df9af82daa3eebd989c4211edfb0
2007-03-29Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemGabe Black
into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-mcf --HG-- extra : convert_revision : f2c3503e8893b957330cf3791748a45800ea5a82
2007-03-29Added SPARC_SE simple timing twolf regression.Gabe Black
--HG-- extra : convert_revision : 289aadd4bc762a5a9e7a82ee15196ebdea2521e5
2007-03-29Added a SPARC_SE simple timing mcf regression.Gabe Black
--HG-- extra : convert_revision : d8fea11c37bd3f0b5f5e8880c92b711892ee8125
2007-03-29get rid of CWP bounds warning...Ali Saidi
--HG-- extra : convert_revision : 74df09341c091c2d6ca9b46c6a3521f22b48acf4
2007-03-29add to instruction test sttw instructionAli Saidi
--HG-- extra : convert_revision : 16efbe12e609a909a589505ad6c473eb44c38f9c
2007-03-29Made the MultiOp format do a little more. It now sets up single microop ↵Gabe Black
instructions to return an instance of the right class. The code to decode register numbers and generate loads and stores still needs to be added. Also, a syntax for specifying operands as sources, destinations, or both needs to be established. Multipl microop instructions are also not handled, pending real macroop generation support. --HG-- extra : convert_revision : 1a0a4b36afce8255e23e3cdd7a85c1392dda5f72
2007-03-29Add a microcode assembler. A microcode "program" is a series of statements. ↵Gabe Black
Each statement has an optional label at the beginning, a capitilized microcode class name which is roughly equivalent to a mnemonic in a regular ISA, and then an optional series of operands seperated by white space. The operands are either a decimal constant, a label, or a code fragment surrounded by non nested {}s. Labels are a letter or underscore followed by letters, underscores, or digits. The syntax for describing code segments might need to be changed if a need arrises to have {}s in the code itself. --HG-- extra : convert_revision : 8e5cfdd1a3c9a7e3731fdf6acd615ee82ac2b9b7
2007-03-29Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemGabe Black
into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-vortex --HG-- extra : convert_revision : 709766f1a1a2347c92d4f508e38b9602c1030717
2007-03-29Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemGabe Black
into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-vortex --HG-- extra : convert_revision : 7efa5fe80ef75155685b93453e967a1115318b9d
2007-03-29Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemGabe Black
into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-gzip --HG-- extra : convert_revision : 39cf24fe19cd48306baef1ef147a3f4738d0fe8a
2007-03-29Added SPARC_SE simple timing vortex regression.Gabe Black
--HG-- extra : convert_revision : 12a2fc0b43cfa72747c1ef24d124979e43b166c7
2007-03-29Added SPARC_SE simple timing gzip regression.Gabe Black
--HG-- extra : convert_revision : 3d5f5f991c9b0c1c07499a2013119240cae5870f
2007-03-29Override addPrivateSplitL1Caches function in order to automatically set the ↵Kevin Lim
tgts_per_mshr of the caches to 20. This is needed otherwise things will potentially lock up when using the O3CPU because the caches can run out of targets, and then not respond. Remove this hack once the caches eventually get fixed. --HG-- extra : convert_revision : 8c61ac1b6182f57ebbe3bcfeddb5a4f4334d7bc0
2007-03-29Update code so that the O3 CPU can handle not initially having anything ↵Kevin Lim
hooked up to its ports. This fixes the segfault Ali recently found when using sampling. src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: Update code so that the O3 CPU can handle not initially having anything hooked up to its ports. --HG-- extra : convert_revision : 04bcef44e754735d821509ebd69b0ef9c8ef8e2c
2007-03-29Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : 849b63ae1300e240082da19dfeb283cdeeb80aef
2007-03-29Fidget with the syntax of the MultiOp format in anticipation of making it ↵Gabe Black
actually work. --HG-- extra : convert_revision : f62a1f035cc11677df8eb5a839ca1247d819fab3
2007-03-29Add code to generate register and immediate based integer op microop classes.Gabe Black
--HG-- extra : convert_revision : 718f941da74dd3b4557cd21e1772879ac21aa9c6
2007-03-29Allow "let" blocks to add code to the output files.Gabe Black
--HG-- extra : convert_revision : 0ffddb2b40dccbf2a3790464c843cfc1b43eaa02
2007-03-28Call compare and Swap on the target, not the response.Ron Dreslinski
--HG-- extra : convert_revision : 522805fe2c9abaa5ba0d9262ad98f841d90f6452
2007-03-27some more fixes... non-tso stuff seems to workAli Saidi
--HG-- extra : convert_revision : da604d20443376d04826397d0aaff0bdd744053b
2007-03-27Merge zizzer:/bk/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head --HG-- extra : convert_revision : 45b64b1564f0e4958d8441455f87b2b185324d55
2007-03-27First Pass At Cmp/Swap in cachesRon Dreslinski
--HG-- extra : convert_revision : 211bfb7c6a59e9e120dae1600d4754baaf231332
2007-03-26Instead of creating a new python process to run traceflags.py,Nathan Binkert
just directly exec the file and generate the flags --HG-- extra : convert_revision : d648ca7348404ded5337db327adafccbd2ae40c8
2007-03-26Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 4b60e96e8dc9c69842514e29925ec1931597ddb4
2007-03-26first bit of life from the intel gigabit modelAli Saidi
--HG-- extra : convert_revision : d8944a53f6b585df21651c4e624518d5c49a7837
2007-03-25Update stats for changes.Kevin Lim
--HG-- extra : convert_revision : a24c4cd7e2fcd732f5da5679f0c0fbf205f22815
2007-03-24Update for new trace data behavior.Kevin Lim
--HG-- extra : convert_revision : c3df20c5187614febc4cc9f4d4c68bfecfba1ea7
2007-03-24Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2 --HG-- extra : convert_revision : f3d193dd1e0b82c496d8224f014123b7cb028c02
2007-03-24Added a SPARC_SE simple atomic regression for the mcf benchmark.Gabe Black
--HG-- extra : convert_revision : 2284e41c03659db8fc8f284f7d9b587a3708fadf
2007-03-23Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zower.eecs.umich.edu:/home/gblack/m5/newmem-o3-spec --HG-- extra : convert_revision : 6b1c8025d29f3e8f90906805dd51a5d523d56004
2007-03-23Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2 src/cpu/base_dyn_inst.hh: Hand merge. Line is no longer needed because it's handled in the ISA. --HG-- extra : convert_revision : 0be4067aa38759a5631c6940f0167d48fde2b680
2007-03-23Make hardware loads/stores serializing; they need to avoid certain ↵Kevin Lim
out-of-order interactions in the 21264. --HG-- extra : convert_revision : d83940af7d0e8efe891d574ac42c6d70d179e2b1
2007-03-23Updates for commit.Kevin Lim
1. Move interrupt handling to a separate function to clean up main commit() function a bit. Also gate the function call off properly based on whether or not there are outstanding interrupts, and the system is not in PAL mode. 2. Better handling of updating instruction's status bits. Instructions are not marked "atCommit" until other stages view it (pushed off to IEW/IQ), and they have been properly handled (faults). 3. Don't consider the ROB "empty" for the purpose of other stages until the ROB is empty, all stores have written back, and there was no store commits this cycle. The last is necessary in case a store committed, in which case it would look like all stores have written back but in actuality have not. src/cpu/o3/commit.hh: Slightly modify how interrupts are handled. Also include some extra bools to keep track of state properly. src/cpu/o3/commit_impl.hh: Slightly modify how interrupts are handled. Also include some extra bools to keep track of state. General correctness updates, most specifically for when commit broadcasts to other stages that the ROB is empty. --HG-- extra : convert_revision : 682ec6ccf4ee6ed0c8a030ceaba1c90a3619d102
2007-03-233 memory system fixes:Kevin Lim
1. Update packet's flags properly when a snoop happens 2. Don't allow accesses to read a block's data if the block has outstanding MSHRs. This avoids a RAW hazard in MP systems that the memory system was not detecting properly earlier (a write required a block to upgrade, and while the upgrade was outstanding, a read came along and read old data). 3. Update MSHR's request upon a response being handled. If the MSHR has more targets than it can respond to in one cycle, then its request must be properly updated to the new head of the targets list. src/mem/bus.cc: Update packet's flags properly upon snoop. src/mem/cache/cache_impl.hh: Be sure to not allow accesses to a block with outstanding MSHRs. src/mem/cache/miss/miss_queue.cc: Update MSHR's request upon a response being handled. --HG-- extra : convert_revision : 76a9abc610ca3f1904f075ad21637148a41982d6
2007-03-23Handle status bits a little better, as well as non-speculative instructions.Kevin Lim
src/cpu/o3/iew_impl.hh: Allow for slightly more flexible handling of non-speculative instructions. They can be other classes now, such as loads or stores. Also be sure to clear the state associated with squashes that are not used. i.e. if a squash due to a memory ordering violation happens on the same cycle as an older branch squashing, clear the state associated with the memory ordering violation. Lastly don't consider uncached loads to officially be "at commit" until IEW receives the signal back from commit about the load. src/cpu/o3/inst_queue_impl.hh: Don't consider non-speculative instructions to be "at commit" until the IQ has received a signal from commit about the instruction. This prevents non-speculative instructions from being issued too early. src/cpu/o3/mem_dep_unit_impl.hh: Clear instruction's ability to issue if it's replayed. --HG-- extra : convert_revision : d69dae878a30821222885485f4dee87170d56eb3
2007-03-23Two fixes:Kevin Lim
1. Requests are handled more properly now. They assume the memory system takes control of the request upon sending out an access. 2. load-load ordering is maintained. src/cpu/base_dyn_inst.hh: Update how requests are handled. The BaseDynInst should not be able to hold a pointer to the request because the request becomes owned by the memory system once it is sent out. Also include some functions to allow certain status bits to be cleared. src/cpu/base_dyn_inst_impl.hh: Update how requests are handled. The BaseDynInst should not be able to hold a pointer to the request because the request becomes owned by the memory system once it is sent out. src/cpu/o3/fetch_impl.hh: General correctness fixes. retryPkt is not necessarily always set, so handle it properly. Also consider the cache unblocked only when recvRetry is called. src/cpu/o3/lsq_unit.hh: Handle requests a little more correctly. Now that the requests aren't pointed to by the DynInst, be sure to delete the request if it's not being used by the memory system. Also be sure to not store-load forward from an uncacheable store. src/cpu/o3/lsq_unit_impl.hh: Check to make sure load-load ordering was maintained. Also handle requests a little more correctly. --HG-- extra : convert_revision : e86bead2886d02443cf77bf7a7a1492845e1690f
2007-03-23Set progress_interval in terms of CPU cycles.Kevin Lim
--HG-- extra : convert_revision : 76b0918276cb613eb314ab1479b5ffdb31f31dee
2007-03-23A couple of minor fixes.Kevin Lim
1. Set CPU ID in all modes for the O3 CPU. 2. Use nextCycle() function to prevent phase drift in O3 CPU. 3. Remove assertion in rename map that is no longer true. src/cpu/o3/alpha/cpu_builder.cc: Allow for CPU id in all modes, not just full system. Also include a parameter that was left out by accident. src/cpu/o3/alpha/cpu_impl.hh: Set the CPU ID properly. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: Use nextCycle() function so that the CPU does not get out of phase when starting up from quiesces. src/cpu/o3/rename_map.cc: Remove assertion that is no longer true. tests/configs/o3-timing.py: Set CPU's id to 0. --HG-- extra : convert_revision : 2b69c19adfce2adcc2d1939e89d702bd6674d5d5
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