gem5 - gem5

Age	Commit message (Expand)	Author
2013-06-03	dev: Clean up MC146818 register (A & B) handling	Andreas Sandberg
2013-05-30	stats: Update the stats to reflect bus and memory changes	Andreas Hansson
2013-05-30	mem: More descriptive DRAM config names	Andreas Hansson
2013-05-30	mem: Add bytes per activate DRAM controller stat	Andreas Hansson
2013-05-30	mem: Add static latency to the DRAM controller	Andreas Hansson
2013-05-30	mem: Spring cleaning of MSHR and MSHRQueue	Andreas Hansson
2013-05-30	mem: Fix MSHR print format	Andreas Hansson
2013-05-30	cpu: Prune the stale TraceCPU	Andreas Hansson
2013-05-30	cpu: Check that minimum TrafficGen period is less than max period	Sascha Bischoff
2013-05-30	cpu: Fix bug when reading in TrafficGen state transitions	Sascha Bischoff
2013-05-30	cpu: Add request elasticity to the traffic generator	Andreas Hansson
2013-05-30	cpu: Block traffic generator when requests have to retry	Andreas Hansson
2013-05-30	cpu: Move traffic generator sending out of generator states	Andreas Hansson
2013-05-30	cpu: Fold together the StateGraph and the TrafficGen	Andreas Hansson
2013-05-30	mem: Make returning snoop responses occupy response layer	Andreas Hansson
2013-05-30	mem: Make the buses multi layered	Andreas Hansson
2013-05-30	mem: Separate the two snoop response cases in the bus	Andreas Hansson
2013-05-30	mem: Tidy up a few variables in the bus	Andreas Hansson
2013-05-30	mem: Add basic stats to the buses	Uri Wiener
2013-05-30	mem: Use unordered set in bus request tracking	Andreas Hansson
2013-05-30	mem: Check for waiting state in bus draining	Andreas Hansson
2013-05-30	mem: Add a LPDDR3-1600 configuration	Andreas Hansson
2013-05-30	mem: Adapt the LPDDR2 to match a single x32 channel	Andreas Hansson
2013-05-30	mem: Avoid explicitly zeroing the memory backing store	Andreas Hansson
2013-05-30	util: Auto generate the packet proto definitions	Andreas Hansson
2013-05-30	base: Avoid size limitation on protobuf coded streams	Andreas Hansson
2013-05-30	cpu: Make hash struct instead of class to please clang	Andreas Hansson
2013-05-21	ruby: slicc: fix error msg in TypeFieldMemberAST.py	Malek Musleh
2013-05-21	x86, regressions: updates stats	Nilay Vaish
2013-05-21	x86: Squash outstanding walks when instructions are squashed.	Gedare Bloom
2013-05-21	x86: mark instructions for being function call/return	Nilay Vaish
2013-05-21	x86: add op class for int and fp microops in isa description	Nilay Vaish
2013-05-21	stats: updates statistics for ruby regressions	Nilay Vaish
2013-05-21	ruby: moesi hammer: cosmetic changes	Nilay Vaish
2013-05-21	ruby: mesi cmp directory: cosmetic changes	Nilay Vaish
2013-05-21	ruby: moesi cmp token: cosmetic changes	Nilay Vaish
2013-05-21	ruby: moesi cmp directory: cosmetic changes	Nilay Vaish
2013-05-21	configs: ruby: pass the option use_map to directory controller	Nilay Vaish
2013-05-21	ruby: add stats to .sm files, remove cache profiler	Nilay Vaish ext:(%2C%20Malek%20Musleh%20%3Cmalek.musleh%40gmail.com%3E)
2013-05-14	cpu: remove local/globalHistoryBits params from branch pred	Anthony Gutierrez
2013-05-14	kvm: Add support for disabling coalesced MMIO	Andreas Sandberg
2013-05-14	kvm: Dump state before panic in KVM exit handlers	Andreas Sandberg
2013-05-14	kvm: Fix the memory interface used by KVM	Andreas Sandberg
2013-05-14	arm: Add support for the m5fail pseudo-op	Andreas Sandberg
2013-05-14	arm: Fix compilation error in m5 utility	Andreas Sandberg
2013-05-07	arm: Make libm5 a dependency of the m5 utility	Andreas Sandberg
2013-05-02	kvm: Add a stat counting number of instructions executed	Andreas Sandberg
2013-05-02	kvm: Add checkpoint debug print	Andreas Sandberg
2013-05-02	kvm: Make MMIO requests uncacheable	Andreas Sandberg
2013-05-02	sim: Add support for m5fail in pseudoInst()	Andreas Sandberg