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2019-11-20system-arm: gitignore the aarch64 bootloader object filesCiro Santilli
Change-Id: I0cb494fb82c557cfce553bc925ea89a8220e4c16 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22826 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-20system-arm: ignore .gen directory that contains DTS filesCiro Santilli
Those files are removed by default because they are intermediary, but it is possible to explicitly build them with an explicit target: make .gen/armv7_gem5_v1_1cpu.dts Change-Id: Id86968fbb2f2b95ce71109de5a0cb8039a048a27 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22825 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-20system-arm: Use dts include instead of cpp in ARM DTBsBertrand Marquis
Change-Id: I342691a42e84dfe53659a7acb3b8db04e52e3002 Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22824 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-20system-arm: Rework boot loader makefile to be more genericBertrand Marquis
add all, clean and install rules use variables for CROSS_COMPILE, CC, LD, DESTDIR use generic rules to produce objects and link Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com> [ciro.santilli@arm.com: Also add BUILDDIR and to allow fully out-of-tree builds.] Signed-off-by: Ciro Santilli <ciro.santilli@arm.com> Change-Id: Id84bc6a8e5dde409b6fb968925ca268376730196 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22823 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-20tests, base: Added GTests for base/intmath.ccBobby R. Bruce
Testing intmath.hh and intmath.cc. Here is the list of the functions that are tested. intmath.isPowerOf2, intmath.power, intmath.floorLog2, intmath.ceilLog2, intmath.divCeil, intmath.roundUp, intmath.roundDown. Other functions are not tested, because they are not currently used and are dead code. Change-Id: I150ac1b5cead93c6698a8c9e9cec80bd87ef181a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22081 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Mahyar Samani <msamani@ucdavis.edu> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-11-20tests, base: Removed dead code from base/intmathMahyar Samani
The below list of functions were dead code and are now deleted. intmath.prevPrime, intmath.isPrime, intmath.leastSigBit, intmath.floorPow2, intmath.ceilPow2, intmath.isHex, intmath.isOct, intmath.isDec, intmath.hex2Int. The source file intmath.cc is now effectively useless and deleted. Change-Id: I28e4350056b8d03e02fecd5c7f7f9c62bc2df7ce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22584 Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com>
2019-11-18arch: Get rid of the (Big|Little)EndianGuest namespaces.Gabe Black
These namespaces were used to set up an environment/context where there was an implicit guest namespace. This is an issue when there may be multiple guest endiannesses which might be different. In cases where we don't know what the guest endianness is, we can't rely on it being an implicit part of our context since that would be ambiguous. In cases where we do know, for instance in ISA specific code, we can just use the endianness specific version that's appropriate for that context. This also (somewhat) removes the assumption that there is a single endianness that applies for a particular ISA. Practically speaking this assumption will probably still stand though, since there would likely be a non-trivial performance penalty to apply a configurable endianness instead of a fixed one the compiler can optomize/remove. Change-Id: I2dff338b58726d724f387388efe32d9233885680 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22374 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18arch: Make and use endian specific versions of the mem helpers.Gabe Black
Rather than using TheISA to pick an endian conversion function, we can have a version defined for big and little endian and call the right one from the ISA code. Change-Id: I5014504968952e21abff3c5f6cbe58ca24233f33 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22373 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18arch-arm: R/W interface to AArch32 HCR2 misc regAdrian Herrera
This patch implements read/write interfaces to HCR2 AArch32 register, which is mapped to the upper 32 bits of HCR_EL2. Change-Id: I996023f3ad8233457d19de8a506ebcf106409165 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22832 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18mem-cache: Initialize all members of `QueuedPrefetcher::DeferredPacket`.Isaac Sánchez Barrera
Members `tc` and `ongoingTranslation` were uninitialized in the constructor for `QueuedPrefetcher::DeferredPacket`. If `ongoingTranslation` is not initialized to `false` by default, some translation requests from queued prefetchers are not properly handled and executions are nondeterministic. Change-Id: Ia278f9e74847d6b847984d47f6a45643bae57794 Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22844 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18mem-cache: Fix destructor of `BasePrefetcher::PrefetchInfo`.Isaac Sánchez Barrera
The destructor of `BasePrefetcher::PrefetchInfo` was calling `delete` for a dynamically-allocated array. Changed to `delete[]` to remove potential undefined behaviour. Change-Id: I6f531bfb6fb7108f1d3e743ae0384d80173e15ef Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22843 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18arch-arm: Fix short descriptors cacheability during table walksGiacomo Travaglini
This implies checking for the SCTLR.C bit TTBR1.IRGN0 bits. Change-Id: I341faf85692ce2d2b4afd30a2f4aabac0e133192 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22724 Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18arch-arm: Fix long descriptors cacheability during table walksGiacomo Travaglini
Prior to this patch table walks were always cacheable unless cacheability was globally disabled by SCTLR.C being 0. Arm allows to select the memory attributes of table walks via the TCR registers. For example the TCR.IRGN0 bits: Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1. IRGN0 Meaning 0b00 Normal memory, Inner Non-cacheable. 0b01 Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable. 0b10 Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable. 0b11 Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable. Note: we check IRGNx bits (Inner Shareable domain) instead of ORGNx (Outer Shareable domain) since in gem5 we consider everything as Inner Shareable. Change-Id: If472c218040029c9d165b056a052f522d48d4a82 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22723 Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-16tests: Added GTests for byteswap.hhBobby R. Bruce
In addition to the test, "#include base/logging.hh" was added to the "byteswap.hh". It is is required to compile the header. Added tests ByteswapTest.swap_byte64, ByteswapTest.swap_byte32, ByteswapTest.swap_byte16, ByteswapTest.swap_byte, ByteswapTest.htog, and ByteswapTest.gtoh. The file byteswap.hh is mostly templates. Added test for BigEndianGuest and LittleEndianGuest namespaces. Change-Id: I8870a55594ed439fe9e1fb333384f73261d1b1b8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22080 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-14tests: Specify a non-default root folder for regressionsGiacomo Travaglini
The new testlib library is looking for regressions walking from a root folder. This by default points to the tests dir. Since all regressions are supposed to live in the tests/gem5 subdir, the patch is assigning the gem5 subdir as a root directory. This will prevent the example garbage to be printed in the ci framework: Exception thrown while loading "/tmpfs/src/git/jenkins-gem5-prod/tests/long/fs/10.linux-boot/test.py" Ignoring all tests in this file. Exception thrown while loading "/tmpfs/src/git/jenkins-gem5-prod/tests/long/fs/80.solaris-boot/test.py" Ignoring all tests in this file. [...] Change-Id: Ia12c6bbeda4ceac71ccd38156ab1e3bb98b05c89 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22726 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-14tests, base: Removed ambiguity from base/intmath.hhMahyar Samani
The function intmath.leastSigBit is ambiguous given its name. It does not return the value of the least significant bit, or the position of the least significant set bit, but instead 2 to the power of the position of the least significant set bit. It has thereby been removed and the function intmath.isPowerOf2 has been refactored to not require intmath.leastSigBit. Change-Id: I22479c666cdd059865b8c73b70b5388f98a4584d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22583 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-14arch-arm: Refactor code to check if gic is GicV2Chun-Chen TK Hsu
Refactor code to use cpu_addr only when gic is GicV2 since cpu_addr is only meanful to GicV2. Test: Boot Android P successfully with the following command: M5_PATH=$PWD/fs_files ./build/ARM/gem5.opt ./configs/example/arm/fs_bigLITTLE.py --dtb $PWD/fs_files/binaries/armv8_gem5_v2_1cpu.dtb --kernel $PWD/fs_files/binaries/vmlinux --disk $PWD/fs_files/disks/disk.img --kernel-init "/init" --cpu-type fastmodel --machine-type VExpressFastmodel --big-cpu-clock "2GHz" --big-cpus 1 --little-cpus 0 --mem-size 8GB --kernel-cmd "earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=8GB root=/dev/vda1 init=/init androidboot.hardware=gem5 qemu=1 qemu.gles=2 android.bootanim=0 vmalloc=640MB android.early.fstab=/fstab.gem5 androidboot.selinux=permissive audit=0 cma=128M" Change-Id: Iedd1388f292685c25f1effcd2e14b3db8899dff9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21339 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-11-14config: Add fastmodel cluster in fs_bigLITTLE.pyChun-Chen TK Hsu
One can create a system with ARM FastModels CPU and GICv3 with --cpu-type fastmodel --machine-type VExpressFastmodel options. Currently the FastmodelCluster only supports one CPU. Change-Id: I2e985f08f9df01a703e21441c6f9bc1fbae4a222 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20901 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-14fastmodel: Add VExpressFastmodel platformChun-Chen TK Hsu
A VExpress based platform with FastModelGIC as interrupt controller. Change-Id: I5ef6d04573d271225d7b39c110e93350a290c371 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21359 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-13arm: Replace most htog and gtoh with htole and letoh.Gabe Black
We already know what endianness to use when with ARM. In places where a ISA was being supplied through an argument, those were left as htog or gtoh. Change-Id: Iff01e8b09a061d9a72e657cdd4570836e0da933f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22372 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-13arch-arm: fix routeToHyp for AArch64 in faultsAdrian Herrera
This patch fixes several bugs in Fault classes "routeToHyp" member function by which mode checking was not taking into account AArch64 execution state. For the particular case of SVC calls from NS EL0, this prevented a correct routing to EL2 when HCR_EL2.TGE was set. Change-Id: I5815fe6dcf4501f52bf92f61687ef6d6ef950e52 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22725 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
2019-11-13tests: Added GTests for base/chunk_generator.hhBobby R. Bruce
Change-Id: Ic6ededfc7fed1f91a75e48a0933e61b4670e5af1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21679 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-13fastmodel: Implement reading vector registers with readVecReg.Gabe Black
The n other flavors of vector reading functions and all the vector writing functions are not implemented currently. Change-Id: I0c25c3ba47c7e4072da3d28596f44f6073b6f609 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22117 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-11-13tests: Added GTests for base/types.ccBobby R. Bruce
Change-Id: I9515735efdd452a9f8c98f37f4ec2c27120929f5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21659 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-12tests,base: Added GTests for base/condcodes.hhBobby R. Bruce
The documentation for the "findParity" and "findCarry" functions in base/condcodes.hh has been enhanced to better explain their behavior. Change-Id: I9ba3bf68eb56529a3030e965ec21e41d2dacfad6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21639 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-12tests: Using super in arm_generic whenever possibleGiacomo Travaglini
This exclude the case where multiple inheritance is used. Change-Id: Id1a46ca5c6c526a1a29a2cff7b00d7e3b6a79273 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22685 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-12tests: Using super for calling superclass __init__Giacomo Travaglini
Change-Id: I19906db9ce1b9ffb4107b47fe2bc64a8e005e776 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22684 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-12tests: Remove Noncoherent cache from regressionsGiacomo Travaglini
Change-Id: I1d499477acec09fd0b36e3b7c2f5eecee737bd93 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22683 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-11arch-arm: Fix TarmacParser handling of 64bit LD/STGiacomo Travaglini
The TarmacParser was assuming 32 bit accesses only. This was creating a mismatch when parsing a trace with 64 bit accesses. E.g. In clk IT (18) 002001f4 f8008441 O EL3h_s : STR x1,[x2],#8 clk MW8 00201008:000000201008 00000000_40000401 Only the 32 MSBs were checked (00000000) Change-Id: I51e803b53efe953edcd9378f6c9481c04932331e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21562 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-11arch-arm: Provide SVE support to the TarmacTracerGiacomo Travaglini
Change-Id: I86ff5f49a0c0aa126d53076964f208716e70aacb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21561 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-11arch-arm: Provide SVE support to the TarmacParserGiacomo Gabrielli
This patch is providing SVE support to the tarmac parser, so that it is recognizing Vector & Predicate entries. Change-Id: I268e621cffa05644d3f1d80170b067aacaa2d5ea Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21560 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07arm: Set the number of FloatRegs to zero.Gabe Black
ARM no longer uses the floating point register file and uses the vector registers instead. This avoids checkpointing a bunch of unused registers, making it hard to tell where floating point instructions are keeping their values, etc. Change-Id: I23145ba750f1dd9ff5b815395e073c410120840d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22524 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07tests,base: Added GTests for base/match.ccBobby R. Bruce
In order to aid testing the method "match.getExpressions()" has been added. Change-Id: I11acf9bed286ee2809dfa3d05ef573dea85eb786 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22503 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07cpu: Fix a bug in getCurrentInstCount in the checker CPU.Gabe Black
An earlier change accidentally left out the actualTC-> prefix in the getCurrentInstCount method which was supposed to delegate the call to another thread context. Without that, it just called itself and would infinitely recurse. This bug was pointed out in email by Robert Henry. Change-Id: Ibf1fee6b48ff87790309c6d435bd76fa95c6cab9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22623 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07power: Replace gtoh and htog with betoh and htobe.Gabe Black
We already know what endianness to use when within power. Change-Id: Id4ced279d21c56855307a5a8da51654101a13786 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22371 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07x86: Replace htog and gtoh with htole and letoh.Gabe Black
We already know what endianness to use from within x86. Change-Id: Ie92568efe8b23fbb7d9edad55fef09c6302cbe62 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22370 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07mips: Replace gtoh and htog with letoh and htole.Gabe Black
We already know what endianness to use from within MIPS. Change-Id: Ic4cd295a7a66c4c8ef55ebcf976fe6637567391f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22369 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07sparc: Replace htog and gtoh with htobe and betoh.Gabe Black
We know what endianness to use when we're implicitly working with SPARC. Change-Id: I85eaac1da087a8086b9450b762a52323f2498e2e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22368 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07systemc: Remove boost dependency caused by tlmHoa Nguyen
This commit replaces the tlm header file, which caused the boost dependency. Change-Id: Ie4b1af71202522d8139e9a861144863097188072 Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22624 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07fastmodel: Plumb the ITB and DTB through the IRIS thread context.Gabe Black
These might be necessary to, for instance, translate virtual addresses. A custom TLB which uses the IRIS API will be written which can be substituted in for the normal ARM TLB. Change-Id: Ic44822db6692ca3a4ca13875b2260b08547a24da Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22116 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-11-06fastmodel: Implement inst count events in the IRIS thread contexts.Gabe Black
These use the IRIS stepping API. Change-Id: Ib45744cb0928fece664187e4df6b25b064b19f0e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22115 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-06arch-arm: Simplify AMO code generation templatesNikos Nikoleris
This change simplifies the isa template for the atomic memory operation (AMO). Previously the flow had unecessary if statements that ended up breaking build using clang, due to variables that could seemingly be used before they were unitialized. Change-Id: I1b46dfd5f1e90377245c4f649c08b6532b507b9c Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22603 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-06cpu: Use std::array for registers in SimpleThread.Gabe Black
If the number of one of the register types is zero (useful on ARM in the near future), memset will complain that it's given the length of the array without multiplying by the size of the array elements. This is a false positive since the length of the array and the number of elements are both zero. To avoid that warning/error and to simplify and update the SimpleThread class slightly, this change replaces the C style arrays with std::array. Change-Id: Ifedd081a1940a578765c4d585e623236008ace67 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22523 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-05arch-arm: Annotate original address in CMOsGiacomo Travaglini
This is needed when a CMO triggers an exception (e.g. DataAbort) In that case the faulting address should be the one encoded in the instruction rather than the cacheline address: According to armarm: If a memory fault that sets FAR_EL1 is generated from a data cache maintenance or other DC instruction, FAR_EL1[63:0] holds the address specified in the register argument of the instruction. Change-Id: I6d0dadbef6e70db57438b01a76c5def3bdd2d974 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22443 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-05mem-ruby: Reset Ruby Sequencer Outstanding Requests statsPolydoros Petrakis
Change-Id: I14b106e0eb7abd9c14badeedf35d6d1c9f198f98 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22446 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-05dev-arm: optional instantiation of GICv3 ITSAdrian Herrera
GICv3 ITS is an optional component of GICv3. The previous behaviour was for a stub ITS to be created by default, which resulted in a crash for use cases where a GICv3 with no ITS is required. This patch removes the instantiation of the ITS by default and adds checks for its presence both in initialization and device tree generation code. Change-Id: Id424924c8c1152d512aaa2837de4aa60329ec234 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22423 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-04mem-cache: Modify compressor to appease newer compilersDaniel R. Carvalho
The type of the local unique_ptr variable was different from the return type. In C++11 because of such difference, a copy-ellision would not be possible, and that required the use of a std::move. In C++14 the restriction of same types being required was removed, so std::move would not be needed anymore. With the addition of the -Wredundant-move warning in newer compilers, having the std::move on the return became an issue, breaking compilation. Change-Id: I45d18dfc500bb5db5fe360814feb91853c735a19 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22403 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-11-04mem-cache: Implement a perfect compressorDaniel R. Carvalho
Implement a perfect compressor that always manages to compresses data exactly to its maximum allowed compression ratio. This allows tracking a compression upper bound. Change-Id: Ibc68bf2dc84b75207795d5ba6304b9ed6dbeae8f Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21160 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Make BDI a multi compressorDaniel R. Carvalho
BDI is a compressor containing multiple sub-compressors. Change-Id: I98411e2ef9dcc2182801a172dfc59ed7a8ee7dd4 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21159 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Implement a multi compressorDaniel R. Carvalho
Implement a compressor that contains multiple sub-compressors and choses the one that provides the best compression results for each compression. Change-Id: I758cf67c84bd85edbea16b2a07b2068b00454461 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21158 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 18:01:31 +0000