gem5 - gem5

Age	Commit message (Expand)	Author
2012-11-02	mips: Remove unused Python file	Andreas Sandberg
2012-11-02	dev: Add missing inline declarations	Andreas Sandberg
2012-11-02	base: Add missing header file to addr_range.hh.	Andreas Sandberg
2012-10-09	m5: Expose m5 pseudo-instructions to C/C++ via a static library	James Clarkson
2012-11-02	ARM: dump stats and process info on context switches	Dam Sunwoo
2012-11-02	base: Fix a few incorrectly handled print format cases	Chander Sudanthi
2012-11-02	base: split out the VncServer into a VncInput and Server classes	Chander Sudanthi
2012-11-02	ISA: generic Linux thread info support	Dam Sunwoo
2012-11-02	sim: Fix as issue where exit events on instr queues are used after freed.	Ali Saidi
2012-11-02	o3: Fix a couple of issues with the local predictor.	Mrinmoy Ghosh
2012-11-02	Partly revert [4f54b0f229b5] and move draining to m5.changeToTiming	Andreas Sandberg
2012-10-31	mem: Fix typo in port comments	Andreas Hansson
2012-10-31	stats: Update stats for fixed simple-atomic-mp config	Andreas Hansson
2012-10-31	config: Fix a typo in the simple-atomic-mp configuration	Andreas Hansson
2012-10-30	stats: Update stats for unified cache configuration	Andreas Hansson
2012-10-30	config: Unify caches used in regressions and adjust L2 MSHRs	Andreas Hansson
2012-10-27	regressions: update stats for ruby fs test	Nilay Vaish
2012-10-27	ruby: set the is_icache param for caches	Malek Musleh
2012-10-27	Ruby: Use block size in configuring directory bits in address	Jason Power ext:(%2C%20Joel%20Hestness%20%3Chestness%40cs.wisc.edu%3E)
2012-10-26	config: Add a check for fastmem only used with Atomic CPU	Andreas Hansson
2012-10-26	config: Remove unused mem_size in fs.py	Andreas Hansson
2012-10-26	config: Fix the cache class naming in regression scripts	Andreas Hansson
2012-10-25	stats: Update the stats to reflect the 1GHz default system clock	Andreas Hansson
2012-10-25	dev: Make default clock more reasonable for system and devices	Andreas Hansson
2012-10-25	stats: Update stats to reflect use of SimpleDRAM	Andreas Hansson
2012-10-25	config: Use SimpleDRAM in full-system, and with o3 and inorder	Andreas Hansson
2012-10-25	config: Use shared cache config for regressions	Andreas Hansson
2012-10-25	arm: Use table walker clock that is inherited from CPU	Andreas Hansson
2012-10-23	stats: Update stats for DMA port send	Andreas Hansson
2012-10-23	dev: Remove zero-time loop in DMA timing send	Andreas Hansson
2012-10-23	stats: Update t1000 stats to match recent changes	Andreas Hansson
2012-10-18	ruby: functional access updates to network test protocol	Nilay Vaish
2012-10-16	regressions: update stats for eio tests	Nilay Vaish
2012-10-15	regressions: update stats due to change to ruby memory system	Nilay Vaish
2012-10-15	ruby: improved support for functional accesses	Nilay Vaish
2012-10-15	memtest: move check on outstanding requests	Nilay Vaish
2012-10-15	ruby: register multiple memory controllers	Nilay Vaish
2012-10-15	ruby: remove AbstractMemOrCache	Nilay Vaish
2012-10-15	ruby: allow function definition in slicc structs	Nilay Vaish
2012-10-15	ruby banked array: do away with event scheduling	Nilay Vaish
2012-10-15	ruby: reset timing after cache warm up	Nilay Vaish
2012-10-15	Mem: Fix incorrect logic in bus blocksize check	Andreas Hansson
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-10-15	Mem: Separate the host and guest views of memory backing store	Andreas Hansson
2012-10-15	Checkpoint: Make system serialize call children	Andreas Hansson
2012-10-15	Mem: Use deque instead of list for bus retries	Andreas Hansson
2012-10-15	Fix: Address a few minor issues identified by cppcheck	Andreas Hansson
2012-10-15	Stats: Update stats for cache timings in cycles	Andreas Hansson
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-10-15	Stats: Update memtest stats after setting clock	Andreas Hansson