gem5 - gem5

Age	Commit message (Expand)	Author
2013-01-07	mem: Add interleaving bits to the address ranges	Andreas Hansson
2013-01-07	config: Traverse lists when visiting children in all proxy	Andreas Hansson
2013-01-07	base: Simplify the AddrRangeMap by removing unused code	Andreas Hansson
2013-01-07	config: Do not use hardcoded physmem in fs script	Andreas Hansson
2013-01-07	mem: Tidy up bus addr range debug messages	Andreas Hansson
2013-01-07	mem: Skip address mapper range checks to allow more flexibility	Andreas Hansson
2013-01-07	base: Encapsulate the underlying fields in AddrRange	Andreas Hansson
2013-01-07	mem: Remove the joining of neighbouring ranges	Andreas Hansson
2013-01-07	cpu: Share the send functionality between traffic generators	Andreas Hansson
2013-01-07	cpu: Add support for protobuf input for the trace generator	Andreas Hansson
2013-01-07	tests: Add support for skipping tests, skip EIO tests if not enabled	Andreas Sandberg
2013-01-07	cpu: Encapsulate traffic generator input in a stream	Andreas Hansson
2013-01-07	base: Add wrapped protobuf input stream	Andreas Hansson
2013-01-07	mem: Add tracing support in the communication monitor	Andreas Hansson
2013-01-07	base: Add wrapped protobuf output streams	Andreas Hansson
2013-01-07	scons: Add support for google protobuf building	Andreas Hansson
2013-01-07	arm: Fix DMA event handling bug in the PL111 model	Andreas Sandberg
2013-01-07	dev: Fix the Pl111 timings by separating pixel and DMA clock	Andreas Hansson
2013-01-07	stats: Update DRAM regression stats to match new config	Andreas Hansson
2013-01-07	config: Reduce DRAM controller regression traffic rate	Andreas Hansson
2013-01-07	cpu: Fix the traffic gen read percentage	Andreas Hansson
2013-01-07	mem: Add sanity check to packet queue size	Andreas Hansson
2013-01-07	ruby: Fix missing cxx_header in Switch	Andreas Hansson
2013-01-07	scons: Fix libelf linking errors when using clang/llvm	Andreas Hansson
2013-01-07	config: Replace second keyboard with a mouse.	Chris Emmons
2013-01-07	mem: Fix a bug in the memory serialization file naming	Andreas Hansson
2013-01-07	arm: Make ID registers ISA parameters	Andreas Sandberg
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
2013-01-07	o3: Fix issue with LLSC ordering and speculation	Ali Saidi
2013-01-07	cpu: rename the misleading inSyscall to noSquashFromTC	Ali Saidi
2013-01-07	tests: Always specify memory mode in every test system.	Ali Saidi
2013-01-07	tests: Create base classes to encapsulate common test configurations	Andreas Sandberg
2013-01-07	cache: add note about where conflicts are handled	Ali Saidi
2013-01-04	regressions: stats update due to decoder changes	Nilay Vaish
2013-01-04	Decoder: Remove the thread context get/set from the decoder.	Gabe Black
2013-01-04	X86: Move address based decode caching in front of the predecoder.	Gabe Black
2013-01-04	SPARC: Keep a copy of the current ASI in the decoder.	Gabe Black
2013-01-04	ARM: Keep a copy of the fpscr len and stride fields in the decoder.	Gabe Black
2012-12-30	x86 regressions: stats update due to new x87 instructions	Nilay Vaish
2012-12-30	x86: implement x87 fp instruction fnstsw	Nilay Vaish
2012-12-30	x86: implement x87 fp instruction fsincos	Nilay Vaish
2012-12-12	arm regressions: updates to config.ini, terminal files	Nilay Vaish
2012-12-12	arm: set uopSet_uop as conditional or unconditional control	Nathanael Premillieu
2012-12-12	arm: set movret_uop as conditional or unconditional control	Nathanael Premillieu
2012-12-11	regressions: stats update due to stats from ruby prefetcher	Nilay Vaish
2012-12-11	ruby: add support for prefetching to MESI protocol	Nilay Vaish
2012-12-11	ruby: modify the directed tester to read/write streams	Nilay Vaish
2012-12-11	ruby: change slicc to allow for constructor args	Nilay Vaish
2012-12-11	ruby: add a prefetcher	Nilay Vaish
2012-12-11	ruby: add functions for computing next stride/page address	Nilay Vaish