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AgeCommit message (Expand)Author
2008-03-17Update long regression stats for semi-recent cache changes.Steve Reinhardt
2008-03-17Fix a few Packet memory leaks.Steve Reinhardt
2008-03-17Restructure bus timing calcs to cope with pkt being deleted by target.Steve Reinhardt
2008-03-15Fix subtle cache bug where read could return stale dataSteve Reinhardt
2008-03-15Simpoints: Fix regression bug/Don't set process.simpoint, if simpoint doesn't...Ali Saidi
2008-03-06MergeGabe Black
2008-03-06X86: Refine the local APIC.Gabe Black
2008-03-06O3CPU: Don't call dumpInsts if DEBUG is not definedVilas Sridharan
2008-03-01X86: Don't map the local APIC into the physical address space in SE mode.Gabe Black
2008-02-29Added tag m5_2.0_beta4 for changeset cad8c2b5d2ecAli Saidi
2008-02-29Added tag m5_2.0_beta5 for changeset fb826c79a385Ali Saidi
2008-02-29Error out if -s is used without --caches (instead of saying you must specify aLisa Hsu
2008-02-29Configs: Make sure options don't conflictAli Saidi
2008-02-28Configs: Fix some bugs we introduced in the simpoints codeAli Saidi
2008-02-27Automated merge with ssh://daystrom.m5sim.org//repo/m5Steve Reinhardt
2008-02-27Update outputs for quick tests to reflect fixed cache stats.Steve Reinhardt
2008-02-27Add comments in code to describe bug conditions.Korey Sewell
2008-02-27Fix Load/Store Queue squashing after a SMT thread is removed but ensuringKorey Sewell
2008-02-27Fix offset in removeThread() function so that float registers start freeing upKorey Sewell
2008-02-26Revamp cache timing access mshr check to make stats sane again.Steve Reinhardt
2008-02-27Configs: Make using Simpoints easier with some config files that support them...Rick Strong
2008-02-26X86: Put in initial implementation of the local APIC.Gabe Black
2008-02-26X86: Implement the INVLPG instruction and the TIA microop.Gabe Black
2008-02-26TLB: Make a TLB base class and put a virtual demapPage function in it.Gabe Black
2008-02-26X86: Get PCI config space to work, and adjust address space prefix numbering ...Gabe Black
2008-02-26Cache: better comments particularly regarding writeback situation.Steve Reinhardt
2008-02-26Update make release, README, and RELEASE_NOTES for b5Ali Saidi
2008-02-26Bus: Update the stats for the recent bus fix.Gabe Black
2008-02-26Bus: Fix the bus timing to be more realistic.Gabe Black
2008-02-22add instruction count fast forwaing and max instruction optionsVilas Sridharan
2008-02-19Added ARM_SE as a build option.Stephen Hines
2008-02-16Update stats for new writeback behavior.Steve Reinhardt
2008-02-16Make L2+ caches allocate new block for writeback missesSteve Reinhardt
2008-02-16Update stats for some unknown minor x86 changesSteve Reinhardt
2008-02-14CPU: move the PC Events code to a place where the code won't be executed mult...Ali Saidi
2008-02-14Configs: Change Simulation.py to return a subclass of the CPU models rather t...Ali Saidi
2008-02-11Update copyright datesAli Saidi
2008-02-11Automated merge with file:/home/stever/hg/m5-origSteve Reinhardt
2008-02-11EXTRAS now points to src instead of needing 'src' subdir.Steve Reinhardt
2008-02-11Wait to set BUILD_DIR until *after* env is copied.Steve Reinhardt
2008-02-10Bus: Only update port cache when there is an item to update it with.Nicolas Zea
2008-02-10IGbE: Fix a couple of bugs.Ali Saidi
2008-02-10Fix #include lines for renamed cache files.Steve Reinhardt
2008-02-10Rename cache files for brevity and consistency with rest of tree.Steve Reinhardt
2008-02-06Make the Event::description() a const functionStephen Hines
2008-02-05Add base ARM code to M5Stephen Hines
2008-02-05Cleaned up os.path imports a bit.Steve Reinhardt
2008-02-05Make EXTRAS work for SConsopts too.Steve Reinhardt
2008-01-23X86: Put an SMBios/DMI table in memory.Gabe Black
2008-01-23X86: Optomize the bit scanning instruction microassembly a little. More can b...Gabe Black
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