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2011-09-19MIPS, faults: Update how the PC is set.Gabe Black
2011-09-19MIPS: Get rid of skipFaultInstruction and setRestartAddress.Gabe Black
Neither of these functions were used.
2011-09-19MIPS: Use inheritance to consolidate class definitions.Gabe Black
2011-09-19MIPS: Always compile in setExceptionState, including in SE mode.Gabe Black
Also fix the newly exposed and preexisting compile errors. This code hasn't been exposed in a while, and it's not up to date with the rest of gem5.
2011-09-19MIPS: Consolidate TLB related faults.Gabe Black
Pass in a bool to indicate if the fault is from a store instead of having two different classes. The classes were also misleadingly named since loads are also processed by the DTB but should return ITB faults since they aren't stores. The TLB may be returning the wrong fault in this case, but I haven't looked at it closely.
2011-09-19MIPS: Get rid of the unused "count" field in FaultVals.Gabe Black
2011-09-19MIPS: Move the genMachineCheckFault function near MachineCheckFault.Gabe Black
Since they're so closely linked, they should be next to each other in the file.
2011-09-19MIPS: Consolidate the two AddressErrorFault variants.Gabe Black
2011-09-19Faults: Get rid of the unused isAlignmentFault and isMachineCheckFault.Gabe Black
These functions aren't called anywhere and are probably only theoretically useful.
2011-09-19MIPS: Get rid of cruft in the fault classes.Gabe Black
Get rid of Fault classes left over from when this file was copied from Alpha, and rename ArithmeticOverflowFault to be IntegerOverflowFault and get rid of the old IntegerOverflowFault stub. The Integer version is what's actually in the manual, but the Arithmetic version had the implementation.
2011-09-19MIPS: Add constructors to the fault classes.Gabe Black
2011-09-19MIPS: Use the CRTP to streamline the Fault class definitions.Gabe Black
CRTP stands for the curiously recurring template pattern.
2011-09-19SPARC: Remove #if FULL_SYSTEMs from the ISA description.Gabe Black
2011-09-19MIPS: Get rid of #if style config checks in the ISA description.Gabe Black
2011-09-19MIPS: Guard SystemCallFault::invoke consistently.Gabe Black
Make sure it's declared iff it's also defined.
2011-09-19MIPS: Get rid of the unused (and partially defined) CacheError fault.Gabe Black
2011-09-19Endianness: Make it easier to check the compiled in guest endianness.Gabe Black
It was technically possible but clumsy to determine what endianness a guest was configured with using the state in byteswap.hh. This change makes that information available more directly. Also get rid of unused (and mildly redundant) ByteOrderDiffers constant.
2011-09-19Alpha: Get rid of some #if FULL_SYSTEMs in the Alpha ISA description.Gabe Black
The remaining ones are more complicated and may require adjustments in other parts of the simulator.
2011-09-19PseudoInst: Make all the pseudo insts available in SE and FS.Gabe Black
2011-09-19X86: Don't use "#if FULL_SYSTEM" in the X86 ISA description.Gabe Black
The decoder now checks the value of FULL_SYSTEM in a switch statement to decide whether to return a real syscall instruction or one that triggers syscall emulation (or a panic in FS mode). The switch statement should devolve into an if, and also should be optimized out since it's based on constant input.
2011-09-19Syscall: Make the syscall function available in both SE and FS modes.Gabe Black
In FS mode the syscall function will panic, but the interface will be consistent and code which calls syscall can be compiled in. This will allow, for instance, instructions that use syscall to be built unconditionally but then not returned by the decoder.
2011-09-19PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts.Gabe Black
2011-09-18Pseudoinst: Add an initParam pseudo inst function.Gabe Black
2011-09-17MIPS: Fix regressions testsAli Saidi
2011-09-13IGbE: Clean up debug printing and proprly account for copied bytes.Ali Saidi
Some DPRINTFs were printing uninitalized values because the DPRINTFs were always being printed even when the features they were printing weren't being used. This change moves the DPRINTFs into the appropriate if blocks and initializes the state variables correctly. There also is a case where the offset into the packet could be calculated incorrectly during a DMA that is fixed.
2011-09-13ARM: update TLB to set request packet ASID fieldDaniel Johnson
2011-09-13Mem: Allow ASID to be set after request is created.Daniel Johnson
2011-09-13CP15 c15: enable execution with accesses to c15 registersChander Sudanthi
Previously, coprocessor accesses to CP15 c15 would fault. This patch enables accesses but prints out a warning, as the registers are not implemented.
2011-09-13ARM: Implement numcpus bits in L2CTLR register.Daniel Johnson
2011-09-13Prefetch: Don't prefetch if address is in the write queue.Ali Saidi
Check that we're not currently writing back an address the prefetcher is trying to prefetch before issuing it. We previously checked the mshrQueue and the cache itself, but forgot to check the writeBuffer. This fixes a memory corrucption issue with an L2 prefetcher.
2011-09-13gem5ops: Implement Java JNI for gem5OpsPrakash Ramrakhyani
These ops allow gem5 ops to be called from within java programs like the following: import jni.gem5Op; public class HelloWorld { public static void main(String[] args) { gem5Op gem5 = new gem5Op(); System.out.println("Rpns0:" + gem5.rpns()); System.out.println("Rpns1:" + gem5.rpns()); } static { System.loadLibrary("gem5OpJni"); } } When building you need to make sure classpath include gem5OpJni.jar: javac -classpath $CLASSPATH:/path/to/gem5OpJni.jar HelloWorld.java and when running you need to make sure both the java and library path are set: java -classpath $CLASSPATH:/path/to/gem5OpJni.jar -Djava.library.path=/path/to/libgem5OpJni.so HelloWorld
2011-09-13O3: Update stats for new ordering fix.Ali Saidi
2011-09-13LSQ: Only trigger a memory violation with a load/load if the value changes.Ali Saidi
Only create a memory ordering violation when the value could have changed between two subsequent loads, instead of just when loads go out-of-order to the same address. While not very common in the case of Alpha, with an architecture with a hardware table walker this can happen reasonably frequently beacuse a translation will miss and start a table walk and before the CPU re-schedules the faulting instruction another one will pass it to the same address (or cache block depending on the dendency checking). This patch has been tested with a couple of self-checking hand crafted programs to stress ordering between two cores. The performance improvement on SPEC benchmarks can be substantial (2-10%).
2011-09-10MIPS: Implement gem5/src/arch/mips/remote_gdb.cc.Deyuan Guo
So a mips-cross-gdb can connect with gem5(MIPS_SE), and do some remote debugging. Testing: Build gem5 for MIPS_SE and make gem5 wait at beginning: modify "rgdb_wait = -1" to "rgdb_wait = 0" in src/sim/system.cc; scons build/MIPS_SE/gem5.opt CPU_MODELS=O3CPU ---- Build GDB-7.3 mips-cross: ./configure --target=mips-linux-gnu --prefix=xxx/gdb-7.3-install/ make make install ---- Run: ./build/MIPS_SE/gem5.opt configs/example/se.py --detailed --caches ./mips-linux-gnu-gdb xxx/gem5/tests/test-progs/hello/bin/mips/linux/hello (gdb) target remote :7000 (gdb) info registers (gdb) disassemble (gdb) si (gdb) break main (gdb) c (gdb) quit Testing done.
2011-09-10PseudoInst: Add compiler guards to pseudo_inst.hh.Gabe Black
2011-09-09StaticInst: Merge StaticInst and StaticInstBase.Gabe Black
Having two StaticInst classes, one nominally ISA dependent and the other ISA dependent, has not been historically useful and makes the StaticInst class more complicated that it needs to be. This change merges StaticInstBase into StaticInst.
2011-09-09Decode: Pull instruction decoding out of the StaticInst class into its own.Gabe Black
This change pulls the instruction decoding machinery (including caches) out of the StaticInst class and puts it into its own class. This has a few intrinsic benefits. First, the StaticInst code, which has gotten to be quite large, gets simpler. Second, the code that handles decode caching is now separated out into its own component and can be looked at in isolation, making it easier to understand. I took the opportunity to restructure the code a bit which will hopefully also help. Beyond that, this change also lays some ground work for each ISA to have its own, potentially stateful decode object. We'd be able to include less contextualizing information in the ExtMachInst objects since that context would be applied at the decoder. Also, the decoder could "know" ahead of time that all the instructions it's going to see are going to be, for instance, 64 bit mode, and it will have one less thing to check when it decodes them. Because the decode caching mechanism has been separated out, it's now possible to have multiple caches which correspond to different types of decoding context. Having one cache for each element of the cross product of different configurations may become prohibitive, so it may be desirable to clear out the cache when relatively static state changes and not to have one for each setting. Because the decode function is no longer universally accessible as a static member of the StaticInst class, a new function was added to the ThreadContexts that returns the applicable decode object.
2011-09-09MIPS: Update MIPS stats for cleaned up operand checks.Gabe Black
2011-09-09Stack: Tidy up some comments, a warning, and make stack extension consistent.Gabe Black
Do some minor cleanup of some recently added comments, a warning, and change other instances of stack extension to be like what's now being done for x86.
2011-09-08ISA parser: Don't look for operands in strings.Gabe Black
2011-09-08ISA parser: Match /* */ and // style comments.Gabe Black
Comments should not be scanned for operands, and we should look for both /* */ style and // style.
2011-09-05X86: Make sure instruction flags are set properly even on 32 bit machines.Gabe Black
The way flag bits were being set for microops in x86 ended up implicitly calling the bitset constructor which was truncating flags beyond the width of an unsigned long. This change sets the bits in chunks which are always small enough to avoid being truncated. On 64 bit machines this should reduce to be the same as before, and on 32 bit machines it should work properly and not be unreasonably inefficient.
2011-09-05X86,TLB: Make sure the "delayedResponse" variable is always set.Gabe Black
When an instruction is translated in the x86 TLB, a variable called delayedResponse is passed back and forth which tracks whether a translation could be completed immediately, or if there's going to be callback that will finish things up. If a read was to the internal memory space, memory mapped registers used to implement things like MSRs, the function hadn't yet gotten to where delayedResponse was set to false, it's default. That meant that the value was never set, and the TLB could start waiting for a callback that would never come. This change simply moves the assignment to above where control can divert to translateInt().
2011-09-02TLB: comments and a helpful warning.Lisa Hsu
Nothing big here, but when you have an address that is not in the page table request to be allocated, if it falls outside of the maximum stack range all you get is a page fault and you don't know why. Add a little warn() to explain it a bit. Also add some comments and alter logic a little so that you don't totally ignore the return value of checkAndAllocNextPage().
2011-09-01Fix build for gcc-4.2 opt/fastLisa Hsu
Even though the code is safe, compiler flags a warning here, which are treated as errors for fast/opt. I know it's redundant but it has no side effects and fixes the compile.
2011-09-01Functional Accesses: Update states to support Broadcast/Snooping protocols.Lisa Hsu
In the current implementation of Functional Accesses, it's very hard to implement broadcast or snooping protocols where the memory has no idea if it has exclusive access to a cache block or not. Without this knowledge, making sure the RW vs. RO permissions are right are next to impossible. So we add a new state called Backing_Store to enable the conveyance that this is the backup storage for a block, so that it can be written if it is the only possibly RW block in the system, or written even if there is another RW block in the system, without causing problems. Also, a small change to actually set the m_name field for each Controller so that debugging can be easier. Now you can access a controller's name just by controller->getName().
2011-08-29SLICC: Pass arguments by referenceNilay Vaish
Arguments to functions were being passed by value. This patch changes SLICC so that arguments are passed by reference.
2011-08-29Ruby: Remove some unused codeNilay Vaish
2011-08-26Ruby: Eliminate modulo op for computing set size.Nilay Vaish
2011-08-19ARM: Add some MP regressions and clean up the disk images and kernels a bitAli Saidi