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AgeCommit message (Expand)Author
2014-09-03arm: Mark v7 cbz instructions as direct branchesMitch Hayenga
2014-09-03cpu: Fix cache blocked load behavior in o3 cpuMitch Hayenga
2014-09-03cpu: Fix o3 quiesce fetch bugMitch Hayenga
2014-09-03cpu: Fix SMT scheduling issue with the O3 cpuMitch Hayenga
2014-09-03cpu: Fix incorrect speculative branch predictor behaviorMitch Hayenga
2014-09-03cpu: Add a fetch queue to the o3 cpuMitch Hayenga
2014-09-03cpu: Fix o3 front-end pipeline interlock behaviorMitch Hayenga
2014-09-03cpu: Change writeback modeling for outstanding instructionsMitch Hayenga
2014-09-03arch: Properly guess OpClass from optional StaticInst flagsMitch Hayenga
2014-09-03cache: Fix handling of LL/SC requests under contentionGeoffrey Blake
2014-05-27arm: support 16kb vm granulesCurtis Dunham
2014-09-03mem: Add utility script to plot DRAM efficiency sweepAndreas Hansson
2014-09-03mem: Packet queue clean upAndreas Hansson
2014-09-03dev: Avoid invalid sized reads in PL390 with DPRINTF enabledMitch Hayenga
2014-09-03sim: Fix checkpoint restore for TickedAndrew Bardsley
2014-09-03arch, cpu: Factor out the ExecContext into a proper base classAndreas Sandberg
2014-09-03arch: Cleanup unused ISA traits constantsAndreas Hansson
2014-09-03config: Change parsing of Addr so hex values work from scriptsMitch Hayenga
2014-09-03arm: Fix ExtMachInst hash operator underlying typeAndreas Hansson
2014-09-01stats: updates due to recent ruby and x86 changesNilay Vaish
2014-09-01ruby: remove typedef of Index as int64Nilay Vaish
2014-09-01x86: set op class of two fp instructionsNilay Vaish
2014-09-01ruby: PerfectSwitch: moves code to a per vnet helper functionNilay Vaish
2014-09-01ruby: message buffers: significant changesNilay Vaish
2014-09-01build opts: add MI_example to NULL ISANilay Vaish
2014-09-01mem: change the namespace Message to ProtoMessageNilay Vaish
2014-09-01ruby: slicc: change the way configurable members are specifiedNilay Vaish
2014-09-01ruby: slicc: improve the grammarNilay Vaish
2014-09-01ruby: mesi three level: slight naming changes.Nilay Vaish
2014-09-01ruby: slicc: donot prefix machine name to variablesNilay Vaish
2014-09-01ruby: remove unused toString() from AbstractControllerNilay Vaish
2014-09-01ruby: network: move getNumNodes() to base classNilay Vaish
2014-09-01ruby: eliminate type TimeNilay Vaish
2014-09-01ruby: move files from ruby/system to ruby/structuresNilay Vaish
2014-09-01ruby: Fixes clock domains in configuration filesEmilio Castillo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2014-08-28mem: adding architectural page table support for SE modeAlexandru
2014-04-01mem: adding a multi-level page table classAlexandru
2014-08-26Added tag stable_2014_08_26 for changeset cb2e6950956dNilay Vaish
2014-08-26mem: Fix DRAMSim2 cycle check when restoring from checkpointAndreas Hansson
2014-08-26base: Add const to intmath and be more flexible with typingAndreas Hansson
2014-08-26style: Add support for a style ignore list and ignore ext/Andreas Sandberg
2014-08-26style: Fixup strange semantics in hg m5styleAndreas Sandberg
2014-08-26base: Replace the internal varargs stuff with C++11 constructsAndreas Sandberg
2014-08-26base: Add compiler macros for C++11 final/overrideAndreas Sandberg
2014-08-26mips: Fix RLIMIT_RSS namingMitch Hayenga
2014-08-26base: Add a static assert to check bit union rangesAndreas Sandberg
2014-08-26sparc: Fixup bit ordering in the PSTATE bit unionAndreas Sandberg
2014-08-26mem: Update DRAM controller commentsAndreas Hansson
2014-08-26mem: Fix address interleaving bug in DRAM controllerAndreas Hansson
2014-02-05sim: bump checkpoint version for multiple event queuesCurtis Dunham
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