summaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2019-02-08sim, kern: support FUTEX_CMP_REQUEUEMoyang Wang
2019-02-08sim: handle the case when there're not enough HW thread contextsTuan Ta
2019-02-08riscv: fixed syscall return valueTuan Ta
2019-02-08cpu: fix how branching is handled when a thread is suspended in MinorCPUTuan Ta
2019-02-08cpu: stop scheduling suspended threads in all stages of MinorCPUTuan Ta
2019-02-08riscv: ignore nanosleep syscallTuan Ta
2019-02-08sim,cpu: make exit_group halt all threads in a groupTuan Ta
2019-02-08arch-riscv: initialize RISC-V's thread pointer register in clone syscallTuan Ta
2019-02-08sim,kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET opsTuan Ta
2019-02-08cpu: fixed how O3 CPU executes an exit system callTuan Ta
2019-02-08arch-arm: Fix Virtual interrupts in AArch64Giacomo Travaglini
2019-02-08arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30Giacomo Travaglini
2019-02-08arch-arm: Allow ArmPPI usage for PMUGiacomo Travaglini
2019-02-08arch-arm: Fix initialization of PMU countersRuben Ayrapetyan
2019-02-07configs, arch-arm: Using AddrRange for Realview mem_regionsGiacomo Travaglini
2019-02-07configs: Unifiy interpretation of Realview mem_regionsGiacomo Travaglini
2019-02-07arch-riscv: Enable support for riscv 32-bit in SE mode.Austin Harris
2019-02-06riscv: remove NonSpeculative flag from fence instTuan Ta
2019-02-06cpu: fix how a thread starts up in MinorCPUTuan Ta
2019-02-06arch-riscv: Initialize interrupt maskTuan Ta
2019-02-06scons: fix unused auto-generated blob variable in clangCiro Santilli
2019-02-06sim: added missed macro definition on MacOSAndrea Mondelli
2019-02-05misc: added missing override specifierAndrea Mondelli
2019-02-05cpu: Made the Loop Predictor a SimObjectJavier Bueno
2019-02-05cpu: Made TAGE a SimObject that can be used by other predictorsJairo Balart
2019-02-05riscv: Get rid of ISA specific register types in Interrupts.Austin Harris
2019-02-01mem-cache: Updated version of the Signature Path PrefetcherJavier Bueno
2019-02-01dev, arm: Removed contextId variableAnouk Van Laer
2019-02-01cpu, arch: Replace the CCReg type with RegVal.Gabe Black
2019-01-31python: Remove getCode() type workaroundAndreas Sandberg
2019-01-31sim: Prepare C++ side for Python 3Andreas Sandberg
2019-01-31tests: Add a helper to run external scriptsAndreas Sandberg
2019-01-31tests: Don't override tick rate in Ruby testsAndreas Sandberg
2019-01-31power: Get rid of some ISA specific register types.Gabe Black
2019-01-31null: Get rid of some register type definitions.Gabe Black
2019-01-31mips: Stop using architecture specific register types.Gabe Black
2019-01-31alpha: Stop using architecture specific register types.Gabe Black
2019-01-31x86: Stop using/defining some ISA specific register types.Gabe Black
2019-01-31riscv: Get rid of some ISA specific register types.Gabe Black
2019-01-31arch: cpu: Rename *FloatRegBits* to *FloatReg*.Gabe Black
2019-01-30arch,cpu: Add vector predicate registersGiacomo Gabrielli
2019-01-30configs: Enable DTB autogeneration in starter_fs.pyGiacomo Travaglini
2019-01-30arch-arm, configs: Create single instance of DTB autogenerationGiacomo Travaglini
2019-01-28tests: fix arm regression due to kernel not foundCiro Santilli
2019-01-25configs: fs.py remove --generate-dtb and enable it by defaultCiro Santilli
2019-01-25configs, arch-arm: don't search for default DTB and kernelCiro Santilli
2019-01-25arch-arm: Remove floatReg operand typeGiacomo Travaglini
2019-01-25arch-arm: Use VecElem instead of FloatReg for FP instructionGiacomo Travaglini
2019-01-25arch: Fix VecElem Operand generation in ISA parserGiacomo Travaglini
2019-01-25cpu, arch, arch-arm: Wire unused VecElem code in the O3 modelGiacomo Travaglini
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-06 09:55:47 +0000