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AgeCommit message (Expand)Author
2015-08-14ruby: add accessor functions to SLICC def of MachineIDNilay Vaish
2015-08-14ruby: simple network: refactor codeNilay Vaish
2015-08-14ruby: profiler: provide the number of vnets through ruby systemNilay Vaish
2015-08-14ruby: directory memory: drop unused variable.Nilay Vaish
2015-08-14ruby: slicc: remove a stray line in StateMachine.pyNilay Vaish
2015-08-14ruby: garnet: flexible: refactor flitNilay Vaish
2015-08-14ruby: DataBlock: adds a commentNilay Vaish
2015-08-14ruby: remove random seedNilay Vaish
2015-08-14ruby: SubBlock: refactor codeNilay Vaish
2015-08-14ruby: cache recorder: move check on block size to RubySystem.Nilay Vaish
2015-08-14ruby: abstract controller: mark some variables as constNilay Vaish
2015-08-14ruby: simple network: store Switch* in PerfectSwitch and ThrottleNilay Vaish
2015-08-14ruby: remove unused functionalRead() function.Nilay Vaish
2015-08-14ruby: perfect switch: refactor codeNilay Vaish
2015-08-14ruby: cache memory: drop {try,test}CacheAccess functionsNilay Vaish
2015-08-14ruby: call setMRU from L1 controllers, not from sequencerNilay Vaish
2015-08-14ruby: adds set and way indices to AbstractCacheEntryNilay Vaish
2015-08-14ruby: eliminate type uint64 and int64Nilay Vaish
2015-08-14ruby: slicc: use default argument valueNilay Vaish
2015-08-14ruby: slicc: avoid duplicate code for function argument checkNilay Vaish
2015-08-14ruby: drop the [] notation for lookup function.Nilay Vaish
2015-08-14ruby: handle llsc accesses through CacheEntry, not CacheMemoryNilay Vaish
2015-08-14stats: updates to ruby fs regression testNilay Vaish
2015-08-14ruby: replace Address by AddrNilay Vaish
2015-08-14ruby: rename variables Addr to addrNilay Vaish
2015-08-14stats: Bump for MessageBuffer, cache latency changesJoel Hestness
2015-08-14ruby: Protocol changes for SimObject MessageBuffersJoel Hestness
2015-08-14ruby: Expose MessageBuffers as SimObjectsJoel Hestness
2015-08-14ruby: Change PerfectCacheMemory::lookup to return pointerJoel Hestness
2015-08-14ruby: Remove the RubyCache/CacheMemory latencyJoel Hestness
2015-08-11sim: clocked object: function for converting cycles to ticks.Nilay Vaish
2015-08-11ruby: drop some redundant includesNilay Vaish
2015-08-11ruby: slicc: allow mathematical operations on TicksNilay Vaish
2015-08-07sim: Flag EventQueue::getCurTick() as constAndreas Sandberg
2015-08-07stats: Update ARM stats to include programmable oscillatorsAndreas Sandberg
2015-08-07mem: Cleanup packet accessor methodsAndreas Sandberg
2015-08-07dev: Implement a simple display timing generatorAndreas Sandberg
2015-08-07arm: Add support for programmable oscillatorsAndreas Sandberg
2015-08-07dev: Add a simple DMA engine that can be used by devicesAndreas Sandberg
2015-08-07sim: Split ClockedObject to make it usable to non-SimObjectsAndreas Sandberg
2015-08-07base: Rewrite the CircleBuf to fix bugs and add serializationAndreas Sandberg
2015-08-07dev, x86: Fix serialization bug in the i8042 deviceAndreas Sandberg
2015-08-07dev: Make serialization in Sinic constantAndreas Sandberg
2015-08-07base: Declare a type for context IDsAndreas Sandberg
2015-08-07base: Use constexpr in CyclesAndreas Sandberg
2015-08-07mem: Remove extraneous acquire/release flags and attributesAndreas Hansson
2015-08-05sim: Fixup comments and constness in draining infrastructureAndreas Sandberg
2015-08-05mem: Fixup incorrect include guardsAndreas Sandberg
2015-08-05util: Enable DRAM sweep to print power and efficiencyAndreas Hansson
2015-08-05stats: Reflect current behaviourAndreas Hansson
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