| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2009-11-18 | ruby: Ruby debug print fixes. | Brad Beckmann | |
| 2009-11-18 | ruby: Ruby memtest python script. | Brad Beckmann | |
| 2009-11-17 | ARM: Begin implementing CP15 | Ali Saidi | |
| 2009-11-17 | ARM: Differentiate between LDM exception return and LDM user regs. | Ali Saidi | |
| 2009-11-17 | ARM: Boilerplate full-system code. | Ali Saidi | |
| --HG-- rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc rename : src/arch/sparc/system.cc => src/arch/arm/system.cc rename : src/arch/sparc/system.hh => src/arch/arm/system.hh rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh | |||
| 2009-11-16 | imported patch isa_fixes2.diff | Ali Saidi | |
| 2009-11-15 | ARM: Make the exception return form of ldm restore CPSR. | Gabe Black | |
| 2009-11-15 | ARM: Create a new type of load uop that restores spsr into cpsr. | Gabe Black | |
| 2009-11-14 | ARM: Check in the actual change from the last commit. | Gabe Black | |
| The last commit was somehow empty. This was what was supposed to go in it. | |||
| 2009-11-14 | ARM: Switch the immediate and register versions of msr. | Gabe Black | |
| These were accidently transposed. This change straightens them out. | |||
| 2009-11-14 | ARM: Fix up the implmentation of the msr instruction. | Gabe Black | |
| 2009-11-14 | ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits. | Gabe Black | |
| 2009-11-14 | ARM: Add a bitfield to indicate if an immediate should be used. | Gabe Black | |
| 2009-11-14 | ARM: Write some functions to write to the CPSR and SPSR for instructions. | Gabe Black | |
| 2009-11-14 | ARM: Fix up the implmentation of the mrs instruction. | Gabe Black | |
| 2009-11-14 | ARM: More accurately describe the effects of using the control operands. | Gabe Black | |
| 2009-11-14 | ARM: Hook up the moded versions of the SPSR. | Gabe Black | |
| These registers can be accessed directly, or through MISCREG_SPSR which will act as whichever SPSR is appropriate for the current mode. | |||
| 2009-11-14 | SE: Fix SE mode OS X compilation. | Ali Saidi | |
| 2009-11-14 | ARM: Move around decoder to properly decode CP15 | Ali Saidi | |
| 2009-11-11 | X86: add ULL to 1's being shifted in 64-bit values | Vince Weaver | |
| Some of the micro-ops weren't casting 1 to ULL before shifting, which can cause problems. On the perl makerand input this caused some values to be negative that shouldn't have been. The casts are done as ULL(1) instead of 1ULL to match others in the m5 code base. | |||
| 2009-11-10 | ARM: Fix some bugs in the ISA desc and fill out some instructions. | Gabe Black | |
| 2009-11-10 | Merge with the head. | Gabe Black | |
| 2009-11-10 | Mem: Eliminate the NO_FAULT request flag. | Gabe Black | |
| 2009-11-10 | ARM: Implement fault classes. | Gabe Black | |
| Implement some fault classes using the curriously recurring template pattern, similar to SPARCs. | |||
| 2009-11-10 | ARM: Fix the integer register indexes. | Gabe Black | |
| The PC indexes in the various register sets was defined in the section for unaliased registers which was throwing off the indexing. This moves those where they belong. Also, to make detecting accesses to the PC easier and because it's in the same place in all modes, the intRegForceUser function now passes it through as index 15. | |||
| 2009-11-10 | X86: Fix bugs in movd implementation. | Vince Weaver | |
| Unfortunately my implementation of the movd instruction had two bugs. In one case, when moving a 32-bit value into an xmm register, the lower half of the xmm register was not zero extended. The other case is that xmm was used instead of xmmlm as the source for a register move. My test case didn't notice this at first as it moved xmm0 to eax, which both have the same register number. | |||
| 2009-11-10 | X86: Remove double-cast in Cvtf2i micro-op | Vince Weaver | |
| This double cast led to rounding errors which caused some benchmarks to get the wrong values, most notably lucas which failed spectacularly due to CVTTSD2SI returning an off-by-one value. equake was also broken. | |||
| 2009-11-09 | syscall: missing initializer in getcwd call | Vince Weaver | |
| This one case was missed during the update to stack-based arguments. Without this fix, m5 will crash during a gwtcwd call, at least with X86. | |||
| 2009-11-08 | X86: Don't panic on faults on prefetches in SE mode. | Gabe Black | |
| 2009-11-08 | X86: Explain what really didn't work with unmapped addresses in SE mode. | Gabe Black | |
| 2009-11-08 | X86: Make x86 use PREFETCH instead of PF_EXCLUSIVE. | Gabe Black | |
| 2009-11-08 | automerge | Nathan Binkert | |
| 2009-11-08 | tests: update statistics for change caused by vsyscall support in x86 | Nathan Binkert | |
| Caused by a slight change in memory layout. | |||
| 2009-11-08 | scons: deal with generated .py files properly | Steve Reinhardt | |
| 2009-11-08 | ARM: Support forcing load/store multiple to use user registers. | Gabe Black | |
| 2009-11-08 | ARM: Simplify the load/store multiple generation code. | Gabe Black | |
| Specifically, get rid of the big switch statement so more cases can be handled. Enumerating all the possible settings doesn't scale well. Also do some minor style clean up. | |||
| 2009-11-08 | compile: wrap 64bit numbers with ULL() so 32bit compiles work | Nathan Binkert | |
| In the isa_parser, we need to check case statements. | |||
| 2009-11-08 | ARM: Split the condition codes out of the CPSR. | Gabe Black | |
| This allows those bits to be renamed while allowing the other fields to control the behavior of the processor. | |||
| 2009-11-08 | ARM: Add in more bits for the mon mode. | Gabe Black | |
| 2009-11-08 | ARM: Get rid of NumInternalProcRegs. | Gabe Black | |
| That constant is a carry over from Alpha and doesn't do anything in ARM. | |||
| 2009-11-08 | ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR. | Gabe Black | |
| 2009-11-08 | ARM: Get rid of the Raddr operand. | Gabe Black | |
| 2009-11-08 | ARM: Initialize processes in user mode. | Gabe Black | |
| I accidentally left in a change to test using int registers in system mode. This change reverts that. | |||
| 2009-11-08 | ARM: Implement the shadow registers using register flattening. | Gabe Black | |
| 2009-11-08 | ARM: Set up an intregs.hh for ARM. | Gabe Black | |
| Add constants for all the modes and registers, maps for aliasing, functions that use the maps and range check, and use a named constant instead of a magic number for the microcode register. | |||
| 2009-11-07 | ARM: Get rid of some unneeded register indexes. | Gabe Black | |
| 2009-11-04 | X86: Fix problem with movhps instruction | Vince Weaver | |
| This problem is like the one fixed with movhpd a few weeks ago. A +8 displacement is used to access memory when there should be none. This fix is needed for the perlbmk spec2k benchmark to run. | |||
| 2009-11-05 | slicc: tweak file enumeration for scons | Steve Reinhardt | |
| Right now .cc and .hh files are handled separately, but then they're just munged together at the end by scons, so it doesn't buy us anything. Might as well munge from the start since we'll eventually be adding generated Python files to the list too. | |||
| 2009-11-05 | slicc: whack some of Nate's leftover debug code | Steve Reinhardt | |
| 2009-11-04 | build: fix compile problems pointed out by gcc 4.4 | Nathan Binkert | |
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