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2019-10-30fastmodel: Refactor the CortexA76x1 model for MP support.Gabe Black
This change inverts the relationship between the fast model and gem5 CPUs, and factors out the parts of the CortexA76x1 which are per core vs. per cluster. Change-Id: I33eacc2461f08c7fd1784936b230e96c768c0e79 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21501 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30dev: Adding support for large BARPouya Fotouhi
During PCI setup, this patch checks if a Base Address Register (BAR) is used as a large BAR (64 bits rather than 32), and return proper address range. The order which updates are done is decided by kernel, so this patch implements both cases (writing lower or upper bits first). Bit 2 in a BAR indicates a 64-bit decoder (10X to be more exact, 11X is reserved). The addresses in BARAddrs are full addresses and are set to zero for BAR providing upper 32 bits to avoid conflicts in addr ranges reported. Change-Id: I93303d36ac83dab9ed6837c81e77c9dfb778f409 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22082 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30base: Name segments after their indexGiacomo Travaglini
Current loader is performing a linear scan of the section table for every segment in the elf since it is naming every segment after the sections it contains. With this patch we are just naming segments after their index. This is in any case how they are referenced when a readelf --segments command is issued on the elf file. Change-Id: I599400fcdfc0b80ac64632aba36781bd876777f0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21999 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30cpu-o3: Fix handling of some mem. order violationsGiacomo Gabrielli
This patch fixes the handling of memory order violations due to snoops targeting out-of-order loads: the re-execution triggered in these cases is achieved by raising a ReExec fault, but such a fault was not handled correctly after the code changes introduced in changeset 46da8fb. Change-Id: I2abe161a90468412f56cb28dcc92729326cba1cd Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21819 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Timothy Hayes <timothy.hayes@arm.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-30dev: Remove TheISA from ns_gige.cc.Gabe Black
It was not being used there. Change-Id: Ib39cfb52553e0556f7a6ad616e1029c74fa90e1f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22271 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-30dev: Stop including config/the_isa.hh unnecessarily.Gabe Black
This file was included in a few files which didn't use TheISA. Change-Id: Ib296b88dc6cfe9d487ee31cf385bb872d2cffaf2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22270 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-30dev: Get PageBytes from the system in the ARM generic timer.Gabe Black
These will ultimately by ArmISA::PageBytes, but this is more consistent with other devices which don't know what ISA they're part of. Change-Id: Iac13d5010564512207ed009377a771ee5949eff3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22269 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-30dev: Get PageBytes from the system in the ide_disk model.Gabe Black
This avoids having to use TheISA::. Change-Id: I020860ab343f9b6fafbcb0e23479d0b64f094512 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22268 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-30dev: Remove using namespace std and TheISA from ide_disk.cc.Gabe Black
Neither was necessary since either that namespace wasn't used, or was used explicitly when referenced. Change-Id: I96d2791c09250255e7e65d47cbb6f65eb4fcb3ba Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22267 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-30fastmodel: Helper function to setup FastModels for simulationChun-Chen TK Hsu
This function sets up ARM license, simulation name, and minimum synchronize latency in FastModels. This function should be called once per simulation. Change-Id: Ic3408955aaff9f8b4e2b72d2f2b0da97b41bfc3f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22183 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30arm: Get rid of using namespace std and TheISA in realview.cc.Gabe Black
Neither was actually used by the nearly empty file. Change-Id: Ief1b77b18c8c616511bf9870e1667439a42dfcbd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22266 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30dev: Remove SINIC_VTOPHYS and related code.Gabe Black
The code in this #ifdef isn't turned on by anything, and either has or likely will bitrot, especially since there are no tests to even determine manually if the code they guard works. They are also preceeded by panics which say that the code they guard is known not to work now anyway. This change also gets rid of TheISA in that file since the only reason it was around was for vtophys in the guarded code. Change-Id: I59fd8974d0dd3d7ab0d5a8ccfa6a446d2da41eb0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22265 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30alpha: Remove TheISA from the Alpha devices.Gabe Black
These are the from the various bits of the tsunami platform. They primarily consisted of "using TheISA" which could be replaced with using AlphaISA or removed altogether (I went with the later), and use of TheISA:: which I replaced with AlphaISA::. Change-Id: Ic52577c65241a92a3f1ae318a19431f8faa50a66 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22264 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30x86: Remove TheISA from x86 devices.Gabe Black
This was really only in the PC platform class. Change-Id: I5365d965ea335a7c45be9f80706a875b19ed0417 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22263 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30sparc: Create a helper functions to install firmware images.Gabe Black
The first function handles the repetitive process of creating an ObjectFile for a particular purpose and checking if that was successful. The second conditionally offsets the images in case they were, for instance, loaded from an ELF file which already had them in the right place. It offsets them so that their entry point (which will be zero for raw images) lines up with the appropriate entry address (which will be at the start of raw images). This is more correct in more cases, and also removes a lot of redundancy. There's still a lot of redundancy in the code which sets up the symbol tables, but there are some irregularities which make that harder to wrap in a helper function. Change-Id: I2fee8b2175faff284ff9e007307f7769043497a1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21469 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Add a repeated value pattern to compressorsDaniel R. Carvalho
The repeated value pattern checks if values are composed of multiple instances of the same value. If successful, the bits of the repeated value are included only once in the compressed data. Change-Id: Ia7045b4e33a91fd8d712fe1ca689f7f8cb4e5feb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21153 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Inform unused bits instead of bytes in compressor patternDaniel R. Carvalho
Increase pattern precision by giving the number of unmatched bits instead of bytes. Change-Id: I5efbe9c31672cc973b4c89c741cdc8cc28d26285 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21152 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Add a masked const value pattern to compressorsDaniel R. Carvalho
The masked pattern compares values to masked const non-dictionary values to determine whether these match. If successful, the bits that do not match must be added to the compressed data. Change-Id: I4c53568694dab916136fe384cb2ee10e554f7136 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21151 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Add a masked pattern to compressorsDaniel R. Carvalho
The masked pattern compares masked values to masked dictionary entries to determine whether these values match. If successful, the bits that do not match must be added to the compressed data. Change-Id: I4b1c8feb0faa99576382b54a73a20c353f965d2a Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21150 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Add an uncompressed pattern to compressorsDaniel R. Carvalho
The uncompressed pattern always stores the original data, and therefore it is always successful. All of the derived classes of the dictionary compressor must have this pattern as the last pattern of the pattern factory. Change-Id: I2a38fd56630d88ef8b918220dc4c2824a196a8a2 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21149 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Templatize DictionaryCompressorDaniel R. Carvalho
Templatize DictionaryCompressor so that the dictionary entries' sizes can be changed. Change-Id: I3d89e3c692a721cefcd7e3c55d2ccdefa425f614 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21148 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-10-29mem-cache: Factor out CPack's dictionary functionalityDaniel R. Carvalho
Factor out dictionary functionality of CPack, so that it can be used easily for other compressors. As a side effect, create an addToDictionary function to allow subclasses to chose how to handle insertion. Change-Id: I02fae4e98b02db5a40467ec470b71020d5e867cb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21147 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-10-29mem-cache: Use shouldAllocate() instead of CPack's decompress()Daniel R. Carvalho
Split decompression functionality using the proper function to determine if a dictionary entry should be allocated after decompression or not. Change-Id: I4995304f4c4508c03c9fc1685f04511622969556 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21146 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-10-29mem-cache: Limit compression sizeDaniel R. Carvalho
Add a threshold so that if the compressed size is greater than it, the compression is abandoned, and the data is considered uncompressible. Change-Id: Ic416195b06ec440a40263b75bd0f0383cde2ea6a Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21144 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-10-29mem-cache: Do not try to compress dataless packetsDaniel R. Carvalho
Fix filling blocks so that packets that do not contain data do not generate a compression attempt. This can happen, for example, with invalidation responses, which will trigger a packet data access assertion. Change-Id: I2a1e7983657f6e5e770b148ab62c9de9ac3986ac Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22164 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29ext: Remove non-source files from fputilsAndreas Sandberg
Remove the autoconf-based build system and GNU-style information files from fputils. After this change, we only keep the files we will need to integrate into gem5's main source tree. Change-Id: I2ddf1d07d9cb51bcd91fc63f1ae43c7f46129933 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22163 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-29mem: Fix DRAM controller to operate on its own address spaceNikos Nikoleris
Typically, a memory controller is assigned an address range of the form [start, end). This address range might be interleaved and therefore only a non-continuous subset of the addresses in the address range is handed by this controller. Prior to this patch, the DRAM controller was unaware of the interleaving and as a result the address range could affect the mapping of addresses to DRAM ranks, rows and columns. This patch changes the DRAM controller, to transform the input address to a continuous range of the form [0, size). As a result the DRAM controller always operates on a dense and continuous address range regardlesss of the system configuration. Change-Id: I7d273a630928421d1854658c9bb0ab34e9360851 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19328 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Avoid promotion of incompatible deferred targetsNikos Nikoleris
Often a request that hits on an MSHR has to be deferred as it can't be serviced by the current response. For example, a request that requires writable has to be deferred when the response is expected to bring in a read-only copy of the block. However, there are cases where the response, although not expected to do so, brings a writable copy and as a result we also service deferred targets. In such cases, we promote deferred targets up until the first that can't be serviced by the current response (e.g., cache maintainance operation). If the first deferred target is incompatible we don't promote any targets at all. Change-Id: Ib3e13be51120b7c0f0053b83b76bde03e1b7dd4e Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22127 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-29mem-cache: Fix MSHR whole line write trackingNikos Nikoleris
The MSHR keeps track of outstanding writes and services them as a whole line write whenever possible. To do this the outstanding writes have to be compatible (e.g., not strictly ordered). Prior to this change, due to this tracking mechanism, the MSHR would not service a WriteLineReq with flags that do not allow merging as a full line write even if it was the first target triggering an assertion. This changeset fixes this bug. Change-Id: I2cbf5ece0c108c1fcfe6855e8f194408d5ab8ce2 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22126 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-28configs: Update HPI to use ArmDTB and ArmITB.Gabe Black
Change-Id: I67693e9d79e89f151e30c585ad565deac53c77c1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22203 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-28configs: Fix undefined BaseCPUDaniel R. Carvalho
When using NULL ISA BaseCPU is undefined, and therefore the isinstance call generates a NameError. Change-Id: Ia4582606b775cdb20829966f8e312a333a55b6f3 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21959 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-28tests, base: Fixed incorrect implementation of StrTest.ToLower test.Bobby R. Bruce
Change-Id: I96672052f8c9da9d4f61ff0e8eed324032b1afac Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22123 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-28ext: Update fputils to rev 0721843Andreas Sandberg
This patch updates fputils to the latest revision (0721843) from the upstream repository (github.com/andysan/fputils). This effectively only updates the license of the library to match gem5's 3-clause BSD license. Change-Id: I46d8a5dfac2f4a95e66ee82a15288ac424d7df90 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22125 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25mips,riscv: Get rid of some Alpha cruft in these System classes.Gabe Black
The consolePanicEvent pointer and addConsoleFuncEvent template were inherited from Alpha and were not used (and probably make no sense) for MIPS or RISCV which (to my knowledge) don't have the idea of a "console" binary. Change-Id: I109b866a65f69c7334062f7304c7b18acc51d99d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21782 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-25cpu: Get rid of the nextInstEventCount method.Gabe Black
This was only used by the KVM CPU, and it has access to all it needs to figure out that value locally without requiring all the ThreadContexts to implement an equivalent function. Change-Id: I17a14ce669db2519edf129db761ebd8dc3bd4129 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22114 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Get rid of the serviceInstCountEvents method.Gabe Black
This was useful when transitioning away from the CPU based comInstEventQueue, but now that objects backing the ThreadContexts have access to the underlying comInstEventQueue and can manipulate it directly, they don't need to do so through a generic interface. Getting rid of this function narrows and simplifies the interface. Change-Id: I202d466d266551675ef6792d38c658d8a8f1cb8b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22113 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25fastmodel: Use getCurrentInstCount for totalInsts().Gabe Black
This had been using a custom totalInsts method on the iris ThreadContext, but since that's equivalent to what the totalInsts method does only through a different mechanism, we can drop that and use getCurrentInstCount instead. Change-Id: I058fec13e81f28285281e136635d53a2e849cb47 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22112 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25fastmodel: Implement getCurrentInstCount.Gabe Black
This uses the step counter the iris API provides. Change-Id: Ic916888fa256d0aa65042d3e6695d9bf4ba32c86 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22111 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Switch off of the CPU's comInstEventQueue.Gabe Black
This switches to letting the ThreadContexts use a thread based/local comInstEventQueue instead of falling back to the CPU's array. Because the implementation is no longer shared and it's not given where the comInstEventQueue (or other implementation) should be accessed, the default implementation has been removed. Also, because nobody is using the CPU's array of event queues, those have been removed. Change-Id: I515e6e00a2174067a928c33ef832bc5c840bdf7f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22110 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Access inst events through ThreadContext instead of the CPU.Gabe Black
Also delete the CPU interface. Change-Id: I62a6b0a9a303d672f4083bdedf393f9f6d07331f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22109 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Delegate comInstEventQueue methods to the ThreadContexts.Gabe Black
These then just use the comInstEventQueue array from the CPU, but soon they will actually be self contained and allow the thread context to use whatever mechanism it wants. Also, now that the thread contexts need to exist before instruction count based events can be scheduled, setting up max instruction based events needs to happen in init after the CPU subclasses have had a chance to set up the threadContexts vector. Change-Id: I34bb401633d277a60be74e30d5a478a149b972ea Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22108 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Make accesses to comInstEventQueue indirect through methods.Gabe Black
This lets us move the event queue itself around, or change how those services are provided. Change-Id: Ie36665b353cf9788968f253cf281a854a6eff4f4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22107 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu,sim: Delegate PCEvent scheduling from Systems to ThreadContexts.Gabe Black
The System keeps track of what events are live so new ThreadContexts can have the same set of events as the other ThreadContexts. Change-Id: Id22bfa0af7592a43d97be1564ca067b08ac1de7c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22106 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Make the ThreadContext a PCEventScope.Gabe Black
Both the thread and system's PCEventQueue are checked when appropriate. Change-Id: I16c371339c91a37b5641860d974e546a30e23e13 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22105 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu,sim: Get rid of a bunch of conditional compilation for PCEvents.Gabe Black
These can now be built without referring to anything in ThreadContext and so can be built even with the NULL ISA. This means the pcEventQueue can be unconditionally built into the System class. Even though the pcEventQueue is going away, this still makes it possible for System to be a PCEventScope unconditionally. Change-Id: Ia342bb7972b1b5ce95033176d72af4bfa343560f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22104 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Don't print the CPU name when a (Break|Panic)PCEvent happens.Gabe Black
This requires reaching into the threadcontext to access the CPU pointer, and also isn't all that useful since it's more important what event happened, not what CPU happened to be running the code at that time. Change-Id: I368707c804dff9bd349f3261bdcd08be55c5d04a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22103 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Pass the address to check into the PCEventQueue service method.Gabe Black
This prevents having to access it from within the ThreadContext. Change-Id: I34f5815a11201b8fc41871c18bdbbcd0f40305cf Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22102 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25sim: Make the System object a PCEventScope.Gabe Black
This abstracts away the raw PCEventQueue managed by the System. Change-Id: I04d773e6be90a891884a76841f15c3eecd5796ed Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Stop checking for PC changes when servicing a PCEventQueue.Gabe Black
First of all, this would arbitrarily skip events based on when they were encountered in the queue. Second, this is one of the three places where the ThreadContext is actually accessed in pc_event.cc. By removing this and the other uses, this file can be included even when using the NULL ISA, and a lot of #ifdefs can be removed. Change-Id: If81f5e9ff9d3f9833145fec0b6062b4bda8d2e47 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22100 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Create a PCEventScope class to abstract the scope of PCEvents.Gabe Black
This abstraction will allow scheduling PCEvents for a particular ThreadContext, all contexts on a CPU, all contexts in a system, etc., and delegates scheduling and removing events to each particular scope. Right now the PCEventQueue is the only implementor of the PCEventSCope interface. Change-Id: I8fb62931511136229915c2e19d36aae7ffdec9df Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22099 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-06 05:50:39 +0000