summaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2013-01-21scons: Disable protobuf if pkg-config and CheckLib failsAndreas Hansson
2013-01-19O3 IEW: Make incrWb and decrWb clearerJoel Hestness
2013-01-17ruby: remove calls to g_system_ptr->getTime()Nilay Vaish
2013-01-15x86 regressions: updates due to new instructions and cpuidNilay Vaish
2013-01-15x86 cpuid: enable clflushNilay Vaish
2013-01-15x86: implements fsin, fcos instructionsNilay Vaish
2013-01-15x86: implements emms instructionNilay Vaish
2013-01-15x86: implement fabs, fchs instructionsNilay Vaish
2013-01-14regressions: update stats due to changes in ruby obj hierarchyNilay Vaish
2013-01-14config: move ruby objects under ruby_system in obj hierarchyMalek Musleh
2013-01-14ruby sequencer: converts cycles to ticks in deadlock panic()Malek Musleh
2013-01-14Ruby: remove reference to g_system_ptr from class MessageNilay Vaish
2013-01-14Ruby: use ClockedObject in Consumer classNilay Vaish
2013-01-14scons: Address clang 3.2 compilation errorAndreas Hansson
2013-01-14stats: Bump failing x86 regression statsAndreas Hansson
2013-01-12base simple cpu: removes commented out code about cache opsNilay Vaish
2013-01-12x86: Changes to decoder, corrects 9376Nilay Vaish
2013-01-08config: Fix issue with changeset: a4739b6f799d.Ali Saidi
2013-01-08stats: update stats for previous six changesAli Saidi
2013-01-08util: add writefile to m5 util program for x86Lluís Vilanova
2013-01-08util: add m5_fail op.Lluís Vilanova
2013-01-08sim: Fix early termination in multi-core simulation under SE mode.Tao Zhang
2013-01-08arm: add access syscall for ARM SE modeMitch Hayenga
2013-01-08mem: Make LL/SC locks fine grainedMitch Hayenga
2013-01-08mem: Fix use-after-free bugMitch Hayenga
2013-01-07dev: Fix infinite recursion in DMA devicesAndreas Sandberg
2013-01-07util: Fix stack corruption in the m5 utilAndreas Sandberg
2013-01-07stats: Fix swig wrapping for Tick in statsSascha Bischoff
2013-01-07stats: update stats for previous changes.Ali Saidi
2013-01-07cpu: Unify the serialization code for all of the CPU modelsAndreas Sandberg
2013-01-07tests: Add CPU switching testsAndreas Sandberg
2013-01-07cpu: Flush TLBs on switchOut()Andreas Sandberg
2013-01-07mem: Fix guest corruption when caches handle uncacheable accessesAndreas Sandberg
2013-01-07cpu: Rewrite O3 draining to avoid stopping in microcodeAndreas Sandberg
2013-01-07cpu: Make sure that a drained atomic CPU isn't executing ucodeAndreas Sandberg
2013-01-07cpu: Make sure that a drained timing CPU isn't executing ucodeAndreas Sandberg
2013-01-07cpu: Fix broken thread context handoverAndreas Sandberg
2013-01-07cpu: Fix O3 LSQ debug dumping constness and formattingAndreas Sandberg
2013-01-07arm: Invalidate cached TLB configuration in drainResumeAndreas Sandberg
2013-01-07arm: Fix draining of the pagetable walker when squashingAndreas Sandberg
2013-01-07cpu: Fix broken squashAfter implementation in O3 CPUAndreas Sandberg
2013-01-07o3 cpu: Remove unused variablesAndreas Sandberg
2013-01-07tests: Update the ignore regexps to reflect the M5->gem5 name changeAndreas Sandberg
2013-01-07sim: Remove unused variablesAndreas Sandberg
2013-01-07cpu: Rename defer_registration->switched_outAndreas Sandberg
2013-01-07cpu: Remove unused params.hh header file in inorder CPUAndreas Sandberg
2013-01-07arm: Remove the register mapping hack used when copying TCsAndreas Sandberg
2013-01-07cpu: Introduce sanity checks when switching between CPUsAndreas Sandberg
2013-01-07cpu: Correctly call parent on switchOut() and takeOverFrom()Andreas Sandberg
2013-01-07cpu: Unify SimpleCPU and O3 CPU serialization codeAndreas Sandberg
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 15:29:15 +0000