summaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2014-06-21o3: make dispatch LSQ full check more selectiveBinh Pham
2014-06-21o3: split load & store queue full cases in renameBinh Pham
2014-06-10scons: Bump the compiler version to gcc 4.6 and clang 3.0Andreas Hansson
2014-06-09Util: Do not style check symlinksJoel Hestness
2014-06-09sim: More rigorous clocking commentsJoel Hestness
2014-06-04ext: Add a McPAT regression testerYasuko Eckert
2014-06-03ext: McPAT interface changes and fixesYasuko Eckert
2014-06-03ext: change McPAT to not force compile in 32-bit mode.Yasuko Eckert
2014-06-03ext: Redirect McPAT object filesYasuko Eckert
2014-05-31style: eliminate equality tests with true and falseSteve Reinhardt
2014-05-24stats: changes due to recent o3 patch.Nilay Vaish
2014-05-23stats: changes due to o3 cpu and ruby message buffer patchesNilay Vaish
2014-05-23ruby: slicc: remove unused ids DNUCA*Nilay Vaish
2014-05-23ruby: remove old protocol documentationNilay Vaish
2014-05-23ruby: message buffer: drop dequeue_getDelayCycles()Nilay Vaish
2014-05-23cpu: o3: remove stat totalCommittedInstsNilay Vaish
2014-05-15config: remove unecessary assignment of etherlink interfacesAnthony Gutierrez
2014-05-12syscall emulation: clean up & comment SyscallReturnSteve Reinhardt
2014-05-12tests: update t1000 & pc-switcheroo-full statsSteve Reinhardt
2014-05-10tests: update eio ref outputs for new statsSteve Reinhardt
2014-05-09stats: Bump stats for the fixes, and mostly DRAM controller changesAndreas Hansson
2014-05-09config: Bump DRAM sweep bus speed to match DDR4 configAndreas Hansson
2014-05-09tests: Reflect name change in DRAM testsAndreas Hansson
2014-05-09mem: Update DDR3 and DDR4 based on datasheetsAndreas Hansson
2014-05-09mem: Add DRAM cycle timeAndreas Hansson
2014-05-09mem: Simplify DRAM response schedulingAndreas Hansson
2014-05-09mem: Add precharge all (PREA) to the DRAM controllerAndreas Hansson
2014-05-09mem: Remove printing of DRAM paramsAndreas Hansson
2014-05-09mem: Add tRTP to the DRAM controllerAndreas Hansson
2014-05-09mem: Merge DRAM latency calculation and bank state updateAndreas Hansson
2014-05-09mem: Add tWR to DRAM activate and precharge constraintsAndreas Hansson
2014-05-09mem: Merge DRAM page-management calculationsAndreas Hansson
2014-05-09mem: Add DRAM power states to the controllerAndreas Hansson
2014-05-09mem: Ensure DRAM refresh respects timingsAndreas Hansson
2014-05-09mem: Make DRAM read/write switching less conservativeAndreas Hansson
2014-04-17arm: Make sure UndefinedInstructions are properly initializedAli Saidi
2014-04-17arm: allow DC instructions by default so SE mode worksAli Saidi
2014-04-17sim, arm: implement more of the at variety syscallsAli Saidi
2014-05-09cpu: Useful getters for ActivityRecorderAndrew Bardsley
2014-05-09cpu: Add flag name printing to StaticInstAndrew Bardsley
2014-05-09cpu: Timebuf const accessorsAndrew Bardsley
2014-05-09arm: Add branch flags onto macroopsAndrew Bardsley
2014-05-09cpu: Allow setWhen on trace objectsAndrew Bardsley
2014-05-09arm: add preliminary ISA splits for ARM archCurtis Dunham
2014-05-09arch: teach ISA parser how to split code across filesCurtis Dunham
2014-05-09config: Avoid generating a reference to myself for Parent.anyGeoffrey Blake
2014-05-09arch, arm: Preserve TLB bootUncacheability when switching CPUsGeoffrey Blake
2014-05-09cpu: add more instruction mix statisticsCurtis Dunham
2014-05-09mem: Squash prefetch requests from downstream cachesMitch Hayenga
2014-05-09stats: Method stats sourceStephan Diestelhorst
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 02:12:41 +0000