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2009-08-15Made servicing_atomic a counter and added started writes:Polina Dudnik
a function for setting the flag to indicate that the rmw_writes started issuing
2009-08-14Bug fix: indicate when writes started coming inPolina Dudnik
2009-08-14Merge with current branchPolina Dudnik
2009-08-14Added proc_id to CacheMsg for SMT.Polina Dudnik
Not yet necessary, but in case each of the threads is allowed to initiate an atomic, will come in handy
2009-08-14Multi-line RMW handlingPolina Dudnik
2009-08-14SMT atomics modifications:Polina Dudnik
don't allow enquing from other threads if servicing and atomic for a thread
2009-08-13Automated merge with ssh://hg@m5sim.org/m5Derek Hower
2009-08-13ruby: config bugfixDerek Hower
2009-08-11ruby/network data_msg_size bug fix with updated statsTushar Krishna
2009-08-11merged Tushar's bug fix with public repository changesBrad Beckmann
2009-08-09Automated merge with ssh://hg@m5sim.org/m5Derek Hower
2009-08-09protocol: added recycle actions to MOESI DMA eventsDerek Hower
2009-08-09X86: Update the stats on the ruby x86 regressions for the new CMOVcc ↵Gabe Black
implementation.
2009-08-09X86: Implement the CMPXCHG8B/CMPXCHG16B instruction.Gabe Black
2009-08-09X86: Don't clobber the original dividend when doing signed divide.Gabe Black
2009-08-09X86: Decode byte sized singed divide as byte sized.Gabe Black
2009-08-08X86: Update the stats for the slightly lengthened cmov.Gabe Black
2009-08-08X86: Make not taken conditional moves leave the destination alone. Adjust ↵Gabe Black
CMOVcc. The manuals from both AMD and Intel say that when writing to a 32 bit destination in 64 bit mode, the upper 32 bits of the register are filled with zeros. They also both say that the CMOV instructions leave their destination alone when their condition fails. Unfortunately, it seems that CMOV will zero extend its destination register whether or not it was supposed to actually do a move on both platforms. This seems to be the only case where this happens, but it would be hard to say for sure.
2009-08-07bug fix for data_msg_size in network/Network.ccTushar Krishna
2009-08-07X86: (Re)Implemented SHRD.Gabe Black
2009-08-07X86: Implement SHLD.Gabe Black
2009-08-07X86: Implement shift right/left double microops.Gabe Black
This is my best guess as far as what these should do. Other existing microops use implicit registers, mul1s and mul1u for instance, so this should be ok. The microop that loads the implicit DoubleBits register would fall into one of the microop slots for moving to/from special registers.
2009-08-07X86: Make the qaud width bswap instruction handle the fact that 32 bit ↵Gabe Black
operations zero extend.
2009-08-07X86: Use the right field when using legacy prefixes to distinguish instructions.Gabe Black
2009-08-07X86: Don't truncate the immediate parameter for the ENTER instruction.Gabe Black
2009-08-06X86: Adjust the various sizes used for the enter and leave instructions.Gabe Black
2009-08-06X86: Make scas compare its operands in the right order.Gabe Black
2009-08-06X86: Fix a copy/paste error for cmovnp.Gabe Black
2009-08-06fixed MOESI_CMP_directory bugDerek Hower
2009-08-06protocol: fixed MOESI_CMP_directory bugDerek Hower
2009-08-06ruby: better configuration assert messageDerek Hower
2009-08-05mergeDerek Hower
2009-08-05regression: updated statsDerek Hower
2009-08-05ruby: configuration supports multiple runs in same sessionDerek Hower
These changes allow to run Ruby-gems multiple times from the same ruby-lang script with different configurations
2009-08-05protocol: made MI_example dma mapping genericDerek Hower
2009-08-05Merge with head.Gabe Black
2009-08-05X86: Make conditional moves zero extend their 32 bit destinations always.Gabe Black
2009-08-05X86: Fix condition code setting for signed multiplies with negative results.Gabe Black
2009-08-05X86: Make the check for negative operands for sign multiply more direct.Gabe Black
2009-08-05X86: Make sure immediate values are truncated properly.Gabe Black
Register values will be "picked" which will assure they don't have junk beyond the part we're using. Immediate values don't go through a similar process, so we should truncate them explicitly.
2009-08-05X86: Use the new forced folding mechanism for the SAHF and LAHF instructions.Gabe Black
2009-08-05X86: Fix the indexing for ah in byte division instructions.Gabe Black
2009-08-05X86: Fix the indexing for ah in byte multiply instructions.Gabe Black
2009-08-05X86: Let microops force folding an index into the high byte of a register.Gabe Black
2009-08-05X86: Handle rotate left with carry instructions that go all the way around ↵Gabe Black
or more.
2009-08-05X86: Set the flags on rotate left with carry instructions.Gabe Black
2009-08-05X86: Handle rotate right with carry instructions that go all the way around ↵Gabe Black
or more.
2009-08-05X86: Fix the overflow bit for rotate right with carry.Gabe Black
2009-08-05X86: Fix the computation of the bottom part of rotate right with carry.Gabe Black
2009-08-05X86: Fix the computation of the upper part of rotate right with carry.Gabe Black