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2013-10-31arm: fix m5ops binary for ARM and add m5fail.Ali Saidi
Changes to make m5ops work under virtualization seemed to break them working with non-virtualized systems and the recently added m5 fail command makes the m5op binary not compile. For now remove the code for virtualization.
2013-10-31cpu: Fix O3 issuse with load+barrier instructions.Ali Saidi
Fix a problem in the O3 CPU for instructions that are both memory loads and memory barriers (e.g. load acquire) and to uncacheable memory. This combination can confuse the commit stage into commitng an instruction that hasn't executed and got it's value yet. At the same time refactor the code slightly to remove duplication between two of the cases.
2013-10-30ruby: set SenderMachine in messages of MOESI_CMP_directoryLluc Alvarez
This patch adds missing initializations of the SenderMachine field of out_msg's when thery are created in the L2 cache controller of the MOESI_CMP_directory coherence protocol. When an out_msg is created and this field is left uninitialized, it is set to the default value MachineType_NUM. This causes a panic in the MachineType_to_string function when gem5 is executed with the Ruby debug flag on and it tries to print the message. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-10-30ruby: Fixed a deadlock when restoring a checkpoint with garnetEmilio Castillo
This patch fixes a problem where in Garnet, the enqueue time in the VCallocator and the SWallocator which is of type Cycles was being stored inside a variable with int type. This lead to a known problem restoring checkpoints with garnet & the fixed pipeline enabled. That value was really big and didn't fit in the variable overflowing it, therefore some conditions on the VC allocation stage & the SW allocation stage were not met and the packets didn't advance through the network, leading to a deadlock panic right after the checkpoint was restored. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-10-17mem: De-virtualise interfaces in the CoherentBusStephan Diestelhorst
The CoherentBus eventually got virtual methods for its interface. The "virtuality" of the CoherentBus, however, comes already from the virtual interface of the bus' ports. There is no need to add another layer of virtual functions, here.
2013-10-17cpu: add consistent guarding to *_impl.hh files.Matt Horsnell
2013-10-17mem: Add PortID to QueuedMasterPort constructorSascha Bischoff
This patch adds the PortID to the QueuedMasterPort. This allows a PortID to be specified as it previously was set to the detault value of -1.
2013-10-17arm: Add a 'clear PPI' method to gic_pl390Matt Evans
The underlying assumption that all PPIs must be edge-triggered is strained when the architected timers and VGIC interfaces make level-behaviour observable. For example, a virtual timer interrupt 'goes away' when the hypervisor is entered and the vtimer is disabled; this requires a PPI to be de-activated. The new method simply clears the interrupt pending state.
2013-10-17config: Fix ommission of number base in ethernet address paramGeoffrey Blake
The ethernet address param tries to convert a hexadecimal string using int() in python, which defaults to base 10, need to specify base 16 in this case.
2013-10-17config: Fix for port references generated multiple timesGeoffrey Blake
SimObjects are expected to only generate one port reference per port belonging to them. There is a subtle bug with using "not" here as a VectorPort is seen as not having a reference if it is either None or empty as per Python docs sec 9.9 for Standard operators. Intended behavior is to only check if we have not created the reference.
2013-10-17dev: Add option to disable framebuffer .bmp dump in run folderDam Sunwoo
There is an option to enable/disable all framebuffer dumps, but the last frame always gets dumped in the run folder with no other way to disable it. These files can add up very quickly running many experiments. This patch adds an option to disable them. The default behavior remains unchanged.
2013-10-17cpu: Removing an unused variable in renameFaissal Sleiman
2013-10-17cpu: Change IEW DPRINTF to use IEW debug flagFaissal Sleiman
IEW DPRINTF uses Decode debug flag, which appears to be a copying error. This patch changes this to the IEW Debug flag.
2013-10-17cpu: Put in assertions to check for maximum supported LQ/SQ sizeFaissal Sleiman
LSQSenderState represents the LQ/SQ index using uint8_t, which supports up to 256 entries (including the sentinel entry). Sending packets to memory with a higher index than 255 truncates the index, such that the response matches the wrong entry. For instance, this can result in a deadlock if a store completion does not clear the head entry.
2013-10-17util: Streamline .apc project convertsion scriptDam Sunwoo
This Python script generates an ARM DS-5 Streamline .apc project based on gem5 run. To successfully convert, the gem5 runs needs to be run with the context-switch-based stats dump option enabled (The guest kernel also needs to be patched to allow gem5 interrogate its task information.) See help for more information.
2013-10-17arm: Accomodate function name changes in newer linux kernelsEric Van Hensbergen
2013-10-17arm: Fix a GIC mask register bugAli Saidi
This resulted in a kernel printk that said, "GIC CPU mask not found - kernel will fail to boot."
2013-10-17cpu: Fix O3 uncacheable load that is replayed but misses the TLBAli Saidi
This change fixes an issue in the O3 CPU where an uncachable instruction is attempted to be executed before it reaches the head of the ROB. It is determined to be uncacheable, and is replayed, but a PanicFault is attached to the instruction to make sure that it is properly executed before committing. If the TLB entry it was using is replaced in the interveaning time, the TLB returns a delayed translation when the load is replayed at the head of the ROB, however the LSQ code can't differntiate between the old fault and the new one. If the translation isn't complete it can't be faulting, so clear the fault.
2013-10-17mem: Make MemoryAccess flag more verboseAli Saidi
This patch extends the MemoryAccess debug flag to report who sent the requests and the cacheability.
2013-10-17build: Place proto output in the same directory, also for EXTRASAndreas Hansson
This patch changes the ProtoBuf builder such that the generated source and header is placed in the build directory of the proto file. This was previously not the case for the directories included as EXTRAS. To make this work, we also ensure that the build directory for the EXTRAS are added to the include path (which does not seem to automatically be the case).
2013-10-17arm, config: Fix a small issue with the dtb file being specifiedAli Saidi
2013-10-17config: Fix memtest example scriptAli Saidi
2013-10-17dev: Allow additional UART interrupts to be setAli Saidi
This patch allows setting a few additional interrupts for status changes that should never occur.
2013-10-17build: Enable color diagnostics in clang by preserving TERM.Stan Czerniawski
2013-10-16kvm: Fix latency calculation of IPR accessesAndreas Sandberg
When handling IPR accesses in doMMIOAccess, the KVM CPU used clockEdge() to convert between cycles and ticks. This is incorrect since doMMIOAccess is supposed to return a latency in ticks rather than when the access is done. This changeset fixes this issue by returning clockPeriod() * ipr_delay instead.
2013-10-16test: update statsSteve Reinhardt
Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
2013-10-15ruby: eliminate non-determinism from ruby.stats outputSteve Reinhardt
Get rid of non-deterministic "stats" in ruby.stats output such as time & date of run, elapsed & CPU time used, and memory usage. These values cause spurious miscomparisons when looking at output diffs (though they don't affect regressions, since the regressions pass/fail status currently ignores ruby.stats entirely). Most of this information is already captured in other places (time & date in stdout, elapsed time & mem usage in stats.txt), where the regression script is smart enough to filter it out. It seems easier to get rid of the redundant output rather than teaching the regression tester to ignore the same information in two different places.
2013-10-15scons: fix minor update-ref bug in regressionsSteve Reinhardt
In the unusual case that regressions are run with --update-ref when there is no existing regression output, scons gets confused because it depends on stats.txt to trigger the update, but it has no indication that running the test will generate the stats.txt file. (In the typical case where stats.txt already exists, scons doesn't care about where it came from.) It's easy to fix this just by adding the stats.txt file to the target list for the test action.
2013-10-15arch/x86: add support for explicit CC register fileYasuko Eckert
Convert condition code registers from being specialized ("pseudo") integer registers to using the recently added CC register class. Nilay Vaish also contributed to this patch.
2013-10-15cpu: add a condition-code register classYasuko Eckert
Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
2013-10-15cpu/o3: clean up rename map and free listSteve Reinhardt
Restructured rename map and free list to clean up some extraneous code and separate out common code that can be reused across different register classes (int and fp at this point). Both components now consist of a set of Simple* objects that are stand-alone rename map & free list for each class, plus a Unified* object that presents a unified interface across all register classes and then redirects accesses to the appropriate Simple* object as needed. Moved free list initialization to PhysRegFile to better isolate knowledge of physical register index mappings to that class (and remove the need to pass a number of parameters to the free list constructor). Causes a small change to these stats: cpu.rename.int_rename_lookups cpu.rename.fp_rename_lookups because they are now categorized on a per-operand basis rather than a per-instruction basis. That is, an instruction with mixed fp/int/misc operand types will have each operand categorized independently, where previously the lookup was categorized based on the instruction type.
2013-10-15cpu: rename *_DepTag constants to *_Reg_BaseSteve Reinhardt
Make these names more meaningful. Specifically, made these substitutions: s/FP_Base_DepTag/FP_Reg_Base/g; s/Ctrl_Base_DepTag/Misc_Reg_Base/g; s/Max_DepTag/Max_Reg_Index/g;
2013-10-15isa: clean up register constantsSteve Reinhardt
Clean up and add some consistency to the *_Base_DepTag constants as well as some related register constants: - Get rid of NumMiscArchRegs, TotalArchRegs, and TotalDataRegs since they're never used and not always defined - Set FP_Base_DepTag = NumIntRegs when possible (i.e., every case except x86) - Set Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs (this was true before, but wasn't always expressed that way) - Drastically reduce the number of arbitrary constants appearing in these calculations
2013-10-15cpu/o3: clean up scoreboard objectSteve Reinhardt
It had a bunch of fields (and associated constructor parameters) thet it didn't really use, and the array initialization was needlessly verbose. Also just hardwired the getReg() method to aleays return true for misc regs, rather than having an array of bits that we always kept marked as ready.
2013-10-15cpu/o3: clean up physical register fileSteve Reinhardt
No need for PhysRegFile to be a template class, or have a pointer back to the CPU. Also made some methods for checking the physical register type (int vs. float) based on the phys reg index, which will come in handy later.
2013-10-15cpu/inorder: merge register class enumsSteve Reinhardt
The previous patch introduced a RegClass enum to clean up register classification. The inorder model already had an equivalent enum (RegType) that was used internally. This patch replaces RegType with RegClass to get rid of the now-redundant code.
2013-10-15cpu: clean up architectural register classificationSteve Reinhardt
Move from a poorly documented scheme where the mapping of unified architectural register indices to register classes is hardcoded all over to one where there's an enum for the register classes and a function that encapsulates the mapping.
2013-10-15mem: Rename the ASI_BITS flag field in RequestAndreas Sandberg
ASI_BITS in the Request object were originally used to store a memory request's ASI on SPARC. This is not the case any more since other ISAs use the ASI bits to store architecture-dependent information. This changeset renames the ASI_BITS to ARCH_BITS which better describes their use. Additionally, the getAsi() accessor is renamed to getArchFlags().
2013-10-15mem: Use a flag instead of address bit 63 for generic IPRsAndreas Sandberg
Using address bit 63 to identify generic IPRs caused problems on SPARC, where IPRs are heavily used. This changeset redefines how generic IPRs are identified. Instead of using bit 63, we now use a separate flag (GENERIC_IPR) a memory request.
2013-10-14Added tag stable_2013_10_14 to the changeset 6a043adb1e8dNilay Vaish
2013-10-09config: correct example ruby scriptsNilay Vaish
A couple of recent changesets added/deleted/edited some variables that are needed for running the example ruby scripts. This changeset edits these scripts to bring them to a working state.
2013-10-09stats: Bump pc-simple-timing-ruby statsAndreas Hansson
This patch simply brings the stats for the pc-simple-timing-ruby regression up to date. The particular regression seems to give different results on different systems unfortunately, and this update reflects the current behaviour on zizzer.
2013-10-07config: set cwd for processes in se.pyNilay Vaish
2013-10-07x86: enables lstat and readlink syscallsNilay Vaish
2013-10-07base: Fix a potential race in PollQueue::setupAsyncIOAndreas Sandberg
There is a potential race between enabling asynchronous IO and selecting the target for the SIGIO signal. This changeset move the F_SETOWN call to before the F_SETFL call that enables SIGIO delivery. This ensures that signals are always sent to the correct process.
2013-10-03kvm: Service events in the instruction event queuesAndreas Sandberg
This changset adds calls to the service the instruction event queues that accidentally went missing from commit [0063c7dd18ec]. The original commit only included the code needed to schedule instruction stops from KVM and missed the functionality to actually service the events.
2013-10-02kvm: Only include KVM support for supported kernelsAndreas Hansson
This patch adds a check to ensure that the KVM API provided by the running kernel is what we are expecting.
2013-10-02ext: Fix fputils compiler flags to ensure ISO C99Andreas Hansson
The fp code relies on C99, and depending on gcc version, the default is to use c89. This patch adds -std=c99 when using gcc to ensure the code is compiled in ISO C99 mode.
2013-10-02stats: Update x86 stats after x87 fixesAndreas Sandberg
The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-01scons, kvm: Check for the presence of POSIX timersAndreas Sandberg
The kvm-based CPU module requires support for POSIX timers. This changeset adds a check for POSIX timers and ensures that gem5 is linked with librt if necessary. KVM support is disabled if POSIX timers are not supported by the host. This fixes a compilation issue for some glibc versions where clock_nanosleep and timer_create are in different libraries.