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AgeCommit message (Expand)Author
2014-01-31config: correct bug in x86 drive sys instantiationNilay Vaish
2014-01-30unittest: Fix build errorsOla Jeppsson
2014-01-29mem: Add additional tolerance to stride prefetcherMitch Hayenga
2014-01-29mem: Allowed tagged instruction prefetching in stride prefetcherMitch Hayenga
2014-01-29mem: prefetcher: add options, support for unaligned addressesMitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E)
2014-01-29cpu: fix bug when TrafficGen deschedules eventXiangyu Dong
2014-01-28arm: Enable umask syscall in SE modeMitch Hayenga
2014-01-28base: Fix race condition in the socket listen functionMitch Hayenga
2014-01-28mem: Remove redundant findVictim() input argumentAmin Farmahini
2014-01-28mem: Fixes a bug in simple_dram write mergingAmin Farmahini
2014-01-28x86: add a warning about the number of memory controllersNilay Vaish
2014-01-27x86: use lfpimm instead of limm for fptanNilay Vaish
2014-01-27x86: implements x87 add/sub instructionsNilay Vaish
2014-01-27x86: implements fxch instruction.Nilay Vaish
2014-01-27x86: correct error in emms instruction.Nilay Vaish
2014-01-27config: allow more than 3GB of memory for x86 simulationsNilay Vaish
2014-01-27stats: update sparc fs statsNilay Vaish
2014-01-27stats: update eio stats for recent changesSteve Reinhardt
2014-01-24stats: update stats for ARMv8 changesAli Saidi
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2014-01-24stats: update stats for cache occupancy and clock domain changesAli Saidi
2014-01-24arch: Make all register index flattening constAndreas Hansson
2014-01-24checker: CheckerCPU handling of MiscRegs was incorrectGeoffrey Blake
2014-01-24arch, cpu: Add support for flattening misc register indexes.Ali Saidi
2014-01-24cpu: Add support for Memory+Barrier instruction types in O3 cpu.Giacomo Gabrielli
2014-01-24cpu: Add support for instructions that zero cache lines.Ali Saidi
2014-01-24cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...Ali Saidi
2014-01-24mem: Add flag to request if it was generated by a page table walkGiacomo Gabrielli
2014-01-24mem: Add support for a security bit in the memory systemGiacomo Gabrielli
2014-01-24sim: Add openat/fstatat syscalls and fix mremapChris Adeniyi-Jones
2014-01-24mem: Remove explict cast from memhelper.Ali Saidi
2014-01-24Cache: Collect very basic stats on tag and data accessesTimothy M. Jones
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
2014-01-24base: add support for probe points and common probesMatt Horsnell
2014-01-24sim: Expose the current voltage for each object as a statAndreas Hansson
2014-01-24sim: Expose the current clock period as a statAndreas Hansson
2014-01-24mem: track per-request latencies and access depths in the cache hierarchyMatt Horsnell
2014-01-24config: Make the Clock a Tick parameter like Latency/FrequencyAndreas Hansson
2014-01-24x86: Fix memory leak in table walkerAndreas Hansson
2014-01-24cpu: Relax check on squashed non-speculative instructionsAndreas Hansson
2014-01-24util: updated Streamline flow to support ARM DS-5 v5.17 protocolDam Sunwoo
2014-01-24cpu: remove faulty simpoint basic block inst count assertionDam Sunwoo
2014-01-17ruby: remove unused label no_vectorNilay Vaish
2014-01-10stats: updates due to changes to rubyNilay Vaish
2014-01-10ruby: move all statistics to stats.txt, eliminate ruby.statsNilay Vaish
2014-01-10stats: add function for adding two histogramsNilay Vaish
2014-01-09ruby: fix bug introduced to revision 8523754f8885Nilay Vaish
2014-01-08ruby: slicc: remove variable 'addr' used in calls to doTransitionNilay Vaish
2014-01-04ruby: add a three level MESI protocol.Nilay Vaish
2014-01-04ruby: rename MESI_CMP_directory to MESI_Two_LevelNilay Vaish
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