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AgeCommit message (Collapse)Author
2011-02-23MOESI_hammer: cache probe address clean upBrad Beckmann
2011-02-23ruby: cleaned up access permission enumBrad Beckmann
2011-02-23ruby: removed unsupported protocol filesBrad Beckmann
2011-02-23inorder: add 00.gzip and 60.bzip2 regression testsKorey Sewell
2011-02-23inorder: InstSeqNum bugKorey Sewell
Because int and not InstSeqNum was used in a couple of places, you can overflow the int type and thus get wierd bugs when the sequence number is negative (or some wierd value)
2011-02-23inorder: dyn inst initializationKorey Sewell
remove constructors that werent being used (it just gets confusing) use initialization list for all the variables instead of relying on initVars() function
2011-02-23inorder: cache packet handlingKorey Sewell
-use a pointer to CacheReqPacket instead of PacketPtr so correct destructors get called on packet deletion - make sure to delete the packet if the cache blocks the sendTiming request or for some reason we dont use the packet - dont overwrite memory requests since in the worst case an instruction will be replaying a request so no need to keep allocating a new request - we dont use retryPkt so delete it - fetch code was split out already, so just assert that this is a memory reference inst. and that the staticInst is available
2011-02-23ARM: Update regression tests for preceeding changes.Ali Saidi
2011-02-23Mem: Print out memory when access > 8 bytesAli Saidi
2011-02-23ARM: Set ITSTATE correctly after FlushPipeAli Saidi
2011-02-23ARM: This panic can be hit during misspeculation so it can't exist.Ali Saidi
2011-02-23ARM: Bad interworking warn way to noisy when running real code w/misspeculation.Ali Saidi
2011-02-23O3: When a prefetch causes a fault, don't record it in the instAli Saidi
2011-02-23ARM: NEON instruction templates modified to set the predicate flag to false ↵Giacomo Gabrielli
when needed.
2011-02-23O3: If there is an outstanding table walk don't let the inst queue sleep.Ali Saidi
If there is an outstanding table walk and no other activity in the CPU it can go to sleep and never wake up. This change makes the instruction queue always active if the CPU is waiting for a store to translate. If Gabe changes the way this code works then the below should be removed as indicated by the todo.
2011-02-23ARM: Squash state on FPSCR stride or len write.Ali Saidi
2011-02-23ARM: Mark store conditionals as such.Matt Horsnell
2011-02-23ARM: Do something for ISB, DSB, DMBAli Saidi
2011-02-23ARM: Fix bug that let two table walks occur in parallel.Ali Saidi
2011-02-23Includes: Don't include isa_traits.hh and use the TheISA namespace unless ↵Ali Saidi
really needed.
2011-02-23ARM: Make Noop actually decode to a noop and set it's instflags.Ali Saidi
2011-02-23O3: Fix bug when a squash occurs right before TLB miss returns.Ali Saidi
In this case we need to throw away the TLB miss, not assume it was the one we were waiting for.
2011-02-23ARM: Delete OABI syscall handling.Ali Saidi
We only support EABI binaries, so there is no reason to support OABI syscalls. The loader detects OABI calls and fatal() so there is no reason to even check here.
2011-02-23CLCD: Fix some serialization bugs with the clcd controller.Ali Saidi
2011-02-23ARM: Clarifies creation of Linux and baremetal ARM systems.Ali Saidi
makeArmSystem creates both bare-metal and Linux systems more cleanly. machine_type was never optional though listed as an optional argument; a system such as "RealView_PBX" must now be explicitly specified. Now that it is a required argument, the placement of the arguments has changed slightly requiring some changes to calls that create ARM systems.
2011-02-23ARM: Add support for read of 100MHz clock in system controller.Ali Saidi
2011-02-23ARM: Reset simulation statistics when pref counters are reset.Ali Saidi
The ARM performance counters are not currently supported by the model. This patch interprets a 'reset performance counters' command to mean 'reset the simulator statistics' instead.
2011-02-23ARM: Adds dummy support for a L2 latency miscreg.Ali Saidi
2011-02-23configs: cache: add cache line size optionKorey Sewell
2011-02-23configs: set default cache paramsKorey Sewell
It's confusing (especially to new users), when you are setting some standard parameters (as defined in Options.py) and they aren't reflected in the simulations so we might as well link the settings in CacheConfig.py to those in Options.py
2011-02-23ruby: extend dprintfs for RubyGenerated TraceFlagKorey Sewell
"executing" isnt a very descriptive debug message and in going through the output you get multiple messages that say "executing" but nothing to help you parse through the code/execution. So instead, at least print out the name of the action that is taking place in these functions.
2011-02-23ruby: cleaning up RubyQueue and RubyNetwork dprintfsKorey Sewell
Overall, continue to progress Ruby debug messages to more of the normal M5 debug message style - add a name() to the Ruby Throttle & PerfectSwitch objects so that the debug output isn't littered w/"global:" everywhere. - clean up messages that print over multiple lines when possible - clean up duplicate prints in the message buffer
2011-02-22m5: merged in hammer fixBrad Beckmann
2011-02-19Ruby: Machine Type missing in MOESI CMP directory protocolNilay Vaish
In certain actions of the L1 cache controller, while creating an outgoing message, the machine type was not being set. This results in a segmentation fault when trace is collected. Joseph Pusudesris provided his patch for fixing this issue.
2011-02-19Ruby: clean MOESI CMP directory protocolNilay Vaish
The L1 cache controller file contains references to foo and goo queues, which are not in use at all. These have been removed.
2011-02-18m5: merge inorder/release-notes/make_release changesKorey Sewell
2011-02-18inorder: regr-update: reduce dynamic mem. use to speedup simsKorey Sewell
previous changesets took a closer look at memory mgmt in the inorder model and sought to avoid dynamic memory mgmt (for access to pipeline resources) as much as possible. For the regressions that were run, the sims are about 2x speedup from changeset 7726 which is the last change since the recent commits in Feb. (note: these regressions now are 4-issue CPUs instead of just 1-issue)
2011-02-18inorder: add names and slot #s to res. dprintsKorey Sewell
2011-02-18inorder: ignore nops in execution unitKorey Sewell
2011-02-18inorder: update graduation unitKorey Sewell
make sure instructions are able to commit before writing back to the RF do not commit more than 1 non-speculative instruction per cycle
2011-02-18inorder: recognize isSerializeAfter flagKorey Sewell
keep track of when an instruction needs the execution behind it to be serialized. Without this, in SE Mode instructions can execute behind a system call exit().
2011-02-18inorder: update default thread size(=1)Korey Sewell
a lot of structures get allocated based off that MaxThreads parameter so this is an effort to not abuse it
2011-02-18inorder: don't overuse getLatency()Korey Sewell
resources don't need to call getLatency because the latency is already a member in the class. If there is some type of special case where different instructions impose a different latency inside a resource then we can revisit this and add getLatency() back in
2011-02-18inorder: update max. resource bandwidthsKorey Sewell
each resource has a certain # of requests it can take per cycle. update the #s here to be more realistic based off of the pipeline width and if the resource needs to be accessed on multiple cycles
2011-02-18inorder: cleanup in destructorsKorey Sewell
cleanup hanging pointers and other cruft in the destructors
2011-02-18inorder: fix cache/fetch unit memory leaksKorey Sewell
--- need to delete the cache request's data on clearRequest() now that we are recycling requests --- fetch unit needs to deallocate the fetch buffer blocks when they are replaced or squashed.
2011-02-18inorder: remove events for zero-cycle resourcesKorey Sewell
if a resource has a zero cycle latency (e.g. RegFile write), then dont allocate an event for it to use
2011-02-18inorder: update pipeline interface for handling finished resource reqsKorey Sewell
formerly, to free up bandwidth in a resource, we could just change the pointer in that resource but at the same time the pipeline stages had visibility to see what happened to a resource request. Now that we are recycling these requests (to avoid too much dynamic allocation), we can't throw away the request too early or the pipeline stage gets bad information. Instead, mark when a request is done with the resource all together and then let the pipeline stage call back to the resource that it's time to free up the bandwidth for more instructions *** inteface notes *** - When an instruction completes and is done in a resource for that cycle, call done() - When an instruction fails and is done with a resource for that cycle, call done(false) - When an instruction completes, but isnt finished with a resource, call completed() - When an instruction fails, but isnt finished with a resource, call completed(false) * * * inorder: tlbmiss wakeup bug fix
2011-02-18inorder: remove request map, use request vectorKorey Sewell
take away all instances of reqMap in the code and make all references use the built-in request vectors inside of each resource. The request map was dynamically allocating a request per instruction. The request vector just allocates N number of requests during instantiation and then the surrounding code is fixed up to reuse those N requests *** setRequest() and clearRequest() are the new accessors needed to define a new request in a resource
2011-02-18inorder: add valid bit for resource requestsKorey Sewell
this will allow us to reuse resource requests within a resource instead of always dynamically allocating
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