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2020-01-17mem-cache: Add more compression statsDaniel R. Carvalho
Add stats to calculate the total number of compressions, decompressions and the average compression size, in number of bits. Change-Id: I5eb563856c1ff54216e1edcd2886332b7481cbfe Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22609 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2020-01-17mem-cache: Factor out multiple block evictionDaniel R. Carvalho
Create a function to try to evict multiple blocks while checking for transient state. Change-Id: I6a879fa5e793cd92c4bdf4a258a133de4c865012 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22607 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2020-01-17configs: MESI_Three_level python parametersTimothy Hayes
Allow specifying the L0 cache parameters via command line in MESI_Three_Level. Change-Id: Ie2a7f74790ed4c81c408857eccc2b439c60627f5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24255 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-17misc: add Arm build_opts for MESI_Three_Level and MOESI_hammerTimothy Hayes
Change-Id: I0d1c5671efdd3cb2041805ab615cdff76d3a5e8a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24254 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2020-01-16util: Add fastmodel in valid tag listChun-Chen TK Hsu
The "fastmodel" tag has been used since 2019-08-22 so it should be an valid tag in commit header. Change-Id: I0032deaabc94e5896851da9afc28e1b1a699fed3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23923 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-16arm: A couple small fixes for the arm64 bootloader makefile.Gabe Black
First, remove a deprecated flag that gcc no longer recognizes. Second, disable suffix based implicit makefile rules. These, in combination with the %.o: boot.S rule, were tricking make into deleting it's own makefile. How, you might ask? make wants to update its makefile, since that's a thing it does automatically. This is useful if you, for instance, have computed header dependencies. make decides it can make a file called "makefile" from a file called "makefile.o" by doing a linking step. make decides it can make makefile.o from boot.S from the %.o: boot.S rule, which it does. It then attempts to link makefile.o into makefile, but that fails because it lacks a "main" function since it's using a built in rule which doesn't know not to expect main. The makefile is clobbered in the process. make then deletes makefile.o because it was an implicit target, eliminating all the evidence. Change-Id: Ib0dfc333dc554caf5772dd8468dba6ba821f98ac Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24329 Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-15tests: Renaming tests to include dash between wordsBobby R. Bruce
In `gem/hello_se/test_hello_se.py`, test suites were being generated with no space between the word "test" and the test name. A dash has now been added to make this a more readable. Change-Id: I9d115a5941cc28af5476175fcbf2bd6940920291 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23025 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2020-01-15tests: Migrated old quick/se/00.hello testsBobby R. Bruce
Migrated old quick/se/00.hello tests over to the new testing frame work (i.e., that executed via `./tests/main.py run`). These fail, so they are currently being ignored. These tests now pull from the http://dist.gem5.org cloud storage. Change-Id: Iff94cce53655bc629a3deb1e11d8d194824751d4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23024 Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2020-01-15arch-arm: ELIsInHost, check VHE and SecEL2Adrian Herrera
This patch modifies ELIsInHost to correctly check for VHE and Secure EL2 implementation. Change-Id: I947dddfc6761794493fef3d59b3b35754d07ed6b Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24046 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-15arch-arm: Virtualization Host Extensions checkingAdrian Herrera
This patch adds Armv8.1-VHE checking. This is based on the bit ID_AA64MMFR1_EL1.VH being 0b1. Change-Id: Ia3f278c63fe1b5448a686db87a46853fc8b6bea5 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24045 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-14system-arm: bigLITTLE with VExpress_GEM5_V2 in dtbAdrian Herrera
This patch adds targets in the device tree Makefile for using bigLITTLE DTS with VExpress_GEM5_V2 platform. Change-Id: I7a424a36c78a24b96224526aa112ac5d060f790b Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24083 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-14mem-garnet: Use smart pointers for CrossbarSwitch's membersDaniel R. Carvalho
Use smart pointers for the pointers managed by CrossbarSwitch. Change-Id: I71958c72cde5981d730aa3f68bba0ffbe4c2506f Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24244 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-14x86: Stop clearing RAX for BIST in initCPU.Gabe Black
This doesn't actually change any behavior since RAX was being zeroed anyway, but since we don't and almost certainly never will have a BIST and the BIST is optional even in real hardware, we can drop it and simplify initCPU a little further. This reduces x86's initCPU function to just an invocation of InitInterrupt's invoke. Change-Id: I56b1aae2c1a738ef7ffabcf648dd7d0fb819d4e0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24187 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2020-01-14x86: Move local APIC initialization out of initCPU.Gabe Black
The APIC can (and probably should) set its version register on its own. Also it already configures its CPUID register when associated with a CPU and doesn't need initCPU to do that. Change-Id: I4611563668d197c48caf2f23fcde9ec2ec101fe7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24186 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2020-01-14x86: Move miscreg initialization to the ISA class.Gabe Black
The initCPU function was setting a lot of values to zero or other initial values, but that's something the ISA object can do as part of its clear() method. This gets rid of a lot of code that was individually zeroing registers, and also centralizes responsibility for those registers in the ISA. Change-Id: Iafcffd3f9329c39f77009b38b1696f91c36c117e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24185 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-13configs: Remove check for kernel in fs.py.Gabe Black
It is *not* true that a kernel is required in FS mode. For example, in SPARC, gem5 is set up to run actual system firmware which will load a kernel from the disk image. Other systems can run in a bare metal mode where they also have no kernel. If a configuration requires a kernel, it should check for it in C++ where there context lives, not globally in fs.py. Change-Id: Ib094c29474c248f866bd08d4f975648a2c707a19 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24284 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-13sim: Add a dumpSimcall mechanism to GuestABI.Gabe Black
This dumps a signature for a simcall as if it was going to be invoked, and can be used for debugging. Change-Id: I6262b94ad4186bac8dc5a1469e9bb3b8ae9d34e1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23460 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-13sim: Add a unit test for the GuestABI mechanism.Gabe Black
Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I76934d94b4c61570a4ca603388012c65280e2b7c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23197 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-13sim: Implement a varargs like mechanism for GuestABI system.Gabe Black
This will let a function called with a GuestABI emulate the ... mechanism available in C. To make that possible without the functions knowing anything about the ABI and to follow C++'s (sensible) templating and virtual function rules, you have to tell VarArgs what types you might want to extract from it, unlike the pure ... varargs style mechanism. Also unlike ..., there is no mechanism in place to force the varargs to appear last in the argument list. It will pick up the progress through the arguments at the point it's reached, and will ignore any later arguments. It would be possible to be more rigorous about this by changing the callFrom templates, but the overhead in complexity is probably not worth it. Also, retrieving arguments through a VarArgs happens live, meaning at the point that the argument is asked for. If the ThreadContext or memory the argument lives in is modified before that point, the retrieved value will reflect that modification and not what the function was originally called with. Care should be taken so that this doesn't cause corrupted arguments. Finally, this mechansim (and the Guest ABI mechanism in general) is complex and should have tests written for it. That should be possible since ThreadContext is forward declared and so the test can say it works however it wants or even ignore it completely. If that changes in the future, we may need a mock ThreadContext implementation. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I37484b50a3e8c0d259d9590e32fecbb5f76670c1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23195 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-13systemc: keep SC_CONCAT* macroEarl Ou
Call of TLM_DECLARE_EXTENDED_PHASE requires SC_CONCAT* macros. This change keeps those macros to avoid compile errors. Change-Id: I573c4c126a350ef1a752d1c50658e7d9cedaaeae Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24123 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-11arch: Make the generic micropc enabled PCState set nupc to 1.Gabe Black
The default constructor of the micropc enabled generic PCState class set the next micropc to 0, when the non-default constructor and at least the x86 initCPU utility function set it to 1. This makes more sense since either the micropc doesn't matter as a concept if the instruction isn't microcoded, or, unless redirected by a micropc branch, you're going to want to execute the next microop and not just repeat the first one. Change-Id: I418ea986a071453563c4c8aad4fc4eb4f7beb641 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24184 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-10dev-arm: VExpress_GEM5_Base, fix daughterboard referenceAdrian Herrera
VExpress_GEM5_Base states that its memory map is based on CoreTile Express A15x2 A7x3, while the model used for the Daughterboard Configuration Controller (DCC) is based on Coretile Express A15x2. These two daughterboard specifications differ in both on-chip memory map and DCC clocks as of the TRMs. This patch makes the reference consistent to Coretile Express A15x2 and adds several non-confidential references to aid in understanding the platform and adding new peripherals. Change-Id: Ia55e7362bdc9ed6509f8eff4cbd7eb38e538d774 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24203 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-09tests,base: Added GTest for base/socket.ccBobby R. Bruce
It should be noted that some features of this class have not been fully tested due to interaction with system-calls. Change-Id: I8315188327e022ac4c98aa9ce4bd38243266ab17 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23984 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-09tests: Updated gtest/logging.cc to print log rather than fail.Bobby R. Bruce
Previously the `GTestExitLogger.log` function utilized GTest's `ADD_FAILURE_AT` macro. This meant, whenever `GTestExitLogger.log` were called, the calling test would be fail. This is problematic when trying to test code we expect to fail (i.e., when testing the error handling code is working correctly). Therefore, the `log` function now writes to stderr. The `GTestExitLogger` class is used by the `panic` and `fatal` loggers when running GTests. Instead of callnig `exit(1)` they throw a GTest exception, which can be captured in a test using `EXPECT_ANY_THROW(expection_thrower())`. Catching and verifying error logs can be done via: ``` testing::internal::CaptureStderr(); /* * "exception_thrower()" is a method we'd expect to call `fatal` or * `panic`, and therefore exit the simulation with a non-zero exit * code. When running via GTest, an exception is thrown instead. */ EXPECT_ANY_THROW(exception_thrower()); EXPECT_EQ("<error message>", testing::internal::GetCapturedStderr())); ``` Change-Id: I84a5f86bc573668d3dd5b40f626b43108dddb8e9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23983 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-09base: Include some required headers in amo.hh.Gabe Black
amo.hh was using several non-default definitions including std::function, uint8_t, and std::array without including any headers at all, and instead apparently relying on those having already been brought in by an earlier include. This change adds those includes explicitly. Change-Id: I92166ff581e74bd705e10fd4fa454df179ae1a97 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24183 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-09base, gpu-compute: Move gpu AMOs into the generic headerGiacomo Travaglini
Change-Id: I10d8aeaae83c232141ddd2fd21ee43bed8712539 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23565 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-08tests: Added functionality to allow the ignoring of test suitesBobby R. Bruce
Previously, when `tests/main.py run` was executed all the tests found were run. It is now necessary to ignore some test suites as they fail. Therefore, `gem5/suite.py` has been updated to read from `gem5/.testignore` (if present). This file contains a list of all the test suites which are to be ignored. Change-Id: I699ea662b701d82199980084261496f24b13d340 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23023 Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-08arch, base: Move arm AtomicOpFunctor into the generic headerGiacomo Travaglini
These AtomicGenericxOp functors are not arm specific: They just define a set of different functors depending on the number of operands they are using. Change-Id: Ida75066823c7718aee05717194cdb8225b700c5d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23564 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-08base: Move AtomicOpFunctors to a dedicated headerGiacomo Travaglini
src/base/types.hh file definition is: /** * @file * Defines global host-dependent types: * Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t. */ I feel AtomicOpFunctor doesn't fall in this cathegory so I am moving those into a dedicated header: base/amo.hh Change-Id: I8f05fb0944c03e4053cfaf2ffe65cac803df1d93 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23563 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-08scons: Add '-Wl,--as-needed' to default LINKFLAGSYu-hsin Wang
In current build flow, EXTRAS flag is evaluated before building gem5 tools and binaries. Such that, unneeded libraries may be linked into gem5 binaries. Adding '-Wl,--as-needed' can fix this problem also shrinks binaries. Change-Id: Ifb001786a66b0dd9b29865e39a5740313002f250 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24003 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-07arch,sim: Promote the m5ops_base param to the System base class.Gabe Black
This mechanism is shared between ARM and x86, even if x86 has a typical address range it choses to use. By moving this to the base class, it's now possible for anybody to find out where the m5 ops are, and no ISA specific assumptions need to be made. Because the x86 address is well known, it's set in the x86 System subclass as the default. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: Ifdb9f5cd1ce38b3c4dafa7566c50f245f14cf790 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23180 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-07cpu: Disable O3CPU value forwarding with write strobesGabor Dozsa
https://gem5-review.googlesource.com/c/public/gem5/+/19173 did the same for MinorCPU Change-Id: I22d631a3d2032570f6e84b0f5eb018d1f84414ef Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23952 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-07cpu: Use enums for O3CPU store value forwardingGabor Dozsa
This is aligning with MinorCPU, where an enum is tagging a Full, Partial and No address coverage. Change-Id: I0e0ba9b88c6f08c04430859e88135c61c56e6884 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23951 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-07system-arm: GICv2/GICv3 have different Distributor addressesGiacomo Travaglini
https://gem5-review.googlesource.com/c/public/gem5/+/22823 didn't take into consideration that GICv3's Distributor is placed at a different address than GICv2's one. This is reflected by the value in VExpress_GEM5_V2 and in the FDT in system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi Change-Id: Ie7661d4e9d3db0c5fe9eb9cea3a24a5e7c266676 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Adrian Herrera <adrian.herrera@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23953 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-07system-arm: Rename ARM bootloader sourceGiacomo Travaglini
The AArch32 assembly source has been renamed from simple.S to boot.S, and the Makefile has been renamed to makefile (lowercase) to match the AArch64 convention Change-Id: Ia4581fe0223c156460edcc558622b5d7962258dc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Adrian Herrera <adrian.herrera@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23949 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-07system-arm: Rename ARM bootloader directoriesGiacomo Travaglini
The patch is renaming: system/arm/simple_bootloader -> system/arm/bootloader/arm system/arm/aarch64_bootloader -> system/arm/bootloader/arm64 Change-Id: Ia7380be3914e277624060f1c96361a0f16dbea9d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Adrian Herrera <adrian.herrera@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23948 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-07misc: Reflect changes of arm bootloader nameAdrian Herrera
With https://gem5-review.googlesource.com/c/public/gem5/+/22687 the VExpress_GEM5_Base platform is changing the required bootloader name by removing the _emm suffix. While this had been changed in the prebuilt binaries in gem5.org, it hadn't in the bootloader makefiles or in other utility functions. The patch is not completely removing the _emm bootloaders since those are still used by VExpress_EMM and VExpress_EMM64 platforms. Change-Id: Iea3148eab313ab06cf2e74660e11708e1a22ce5f Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Adrian Herrera <adrian.herrera@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23947 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-07scons: Cleanup code that enables asan and ubsanNikos Nikoleris
Change-Id: Ie29efc99067dac051536bb099a89f29c940192ec Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23883 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-07mem-cache: Forward snoops when the cache is not respondingNikos Nikoleris
When the MSHR is handling a request that will make the block dirty the current cache commits respond. When that's not the case the cache should forward any snoops. This CL fixes MSHR::handleSnoop() to implement this behavior. Change-Id: I207e3ca4968fd9528fd4cdbfb3eb95f470b4744d Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23668 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2020-01-07mem-cache: Ensure that responses get data from the right sourceNikos Nikoleris
This CL makes sure that we use the right source for data for responses after a response from the cache below. Change-Id: I7329f3e6bcb7ce2054e912eb9dea48c9d169d45a Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23667 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-07systemc: fix gem5_to_tlm bridgeEarl Ou
The original implementation doesn't set trans and phase correctly when scheduling PayloadEvent, and causes unexpected behavior after the event started. This change fixes the wrong event triggering by directly applying tlm_utils::peq instead of creating another one. Change-Id: I207567b57f4b49c3c4ebe117d624e5cc9915c12a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23823 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-07fastmodel: Implement the vecPredReg accessor functions.Gabe Black
Change-Id: Iaf6f7d8d1db427bfd486e4bd43f67cc006751873 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23789 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2020-01-07arch,sim: Stop decoding the pseudo inst subfunc value.Gabe Black
This isn't used by anything any more. The func field is left in place to ensure compatability, but there's no reason to decode a value nobody is going to use. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I85fcd0e4a362551c29af6bff350d99af86050415 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23179 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2020-01-06arch,sim: Use the guest ABI mechanism with pseudo instructions.Gabe Black
Right now, there are only two places which call the pseudoInst function directly, the ARM KVM CPU and the generic mmapped IPR. These two callers currently use the generic "PseudoInstABI" which is just a wrapper around the existing getArgument function. In the future, this getArgument function will be disolved, and the PseudoInstABI will be defined for each ABI. Since it currently mimics the Linux ABI since gem5 can only handle one ABI at a time right now, this implementation will probably be shared by linux system calls, except that the pseudo inst implementation will eat return values since those are returned through other means when the pseudo inst is based on magic address ranges. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: Ied97e4a968795158873e492289a1058c8e4e411b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23178 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-06arch-arm: Semihosting, specify files root dirAdrian Herrera
This patch adds an option to "ArmSemihosting" which allows for specifying an optional search path for host files. Previously, behaviour was fixed to search in the directory from where the gem5 binary was run from. Change-Id: I57b932b38d022f132af78857104633d7bfdd1442 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23903 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-06dev-arm: Fix SMMUv3 walkMasks in page table opsMichiel van Tol
The masks did not include the high bits above the active addressing bits. This could cause overlapping issues when using high addresses. (Translated with TTBR1) Change-Id: Ib705558aac456c1b3f069e1bd3ccdd9229a1c1d2 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23764 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-06dev-arm: Fix SMMUv3 16KB next-level table address maskingGiacomo Travaglini
The next-level table address for a granule size of 16KB is retrieved from the 47:14 bits of the current table descriptor (instead of 47:12, which is the valid masking for a 4KB granule) Change-Id: I570138a34003dc034d8e67dc1209316157d57205 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel van Tol <michiel.vantol@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23763 Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-06dev-arm: GICv3, handle GICR_ICFGR0 WI behaviourAdrian Herrera
Architecture states write accesses to GICR_ICFGR0 are WI. This patch implements handling of this behaviour instead of crashing as an invalid offset. This is required to support certain software behaviour. Change-Id: I1f8c57838566c360d243a925306ec35c64a920b2 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24063 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-06mem-cache: Avoid write merging if there are reads in betweenNikos Nikoleris
This CL reworks the logic in the MSHR to make sure we do not coalesce requests unless there is a series of write requests for the whole cache block without any other incompatible requests (e.g., read) in between. Change-Id: I0b3195858fb33ef85d7aae27376506057dd53ea7 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23666 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-06configs-arm: enable PMU instantiation in CpuClusterAdrian Herrera
This patch adds a new method to the CpuCluster object which allows passing the PMU interrupt numbers and events to record for each core. This lets users create CPU clusters with PMUs. Change-Id: Id49fd0aee50f49e4c6fca95e4ee673da3dca73cd Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22848 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-12 21:33:14 +0000