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AgeCommit message (Expand)Author
2012-04-28Garnet: Correct computation of link utilizationNilay Vaish
2012-04-26util/regress: Add the missing comma in the list of buildsNilay Vaish
2012-04-25Regression: Add a test for x86 timing full system ruby simulationNilay Vaish
2012-04-25Ruby: Remove extra statements from SequencerNilay Vaish
2012-04-25MEM: Use base class Master/SlavePort pointers in the busAndreas Hansson
2012-04-25MEM: Add the PortId type and a corresponding id field to PortAndreas Hansson
2012-04-25clang/gcc: Use STL hash function for int64_t and uint64_tAndreas Hansson
2012-04-24X86: Update stats for the slightly changed TLB behavior.Gabe Black
2012-04-24X86: Clear out duplicate TLB entries when adding a new one.Gabe Black
2012-04-23ISA: Put parser generated files in a "generated" directory.Gabe Black
2012-04-23scons: update minimum SWIG version to 1.3.34Steve Reinhardt
2012-04-22base: Include cassert in trie.hh.Gabe Black
2012-04-21X86: Report an error if there's no kernel object, don't blindly use it.Gabe Black
2012-04-17SE Config: Changed se.py to support multithreaded modeJayneel Gandhi
2012-04-16Config: Add command line options for disk image and memory sizeJayneel Gandhi
2012-04-15CPU: Tidy up some formatting and a DPRINTF in the simple CPU base class.Gabe Black
2012-04-15X86: Fix a tiny typo in the load/store microop constructor.Gabe Black
2012-04-14X86: Use the AddrTrie class to implement the TLB.Gabe Black
2012-04-14sim: Update some comments in trie.hh that were meant to go in the last change.Gabe Black
2012-04-14sim: A trie data structure specifically to speed up paging lookups.Gabe Black
2012-04-14Ruby: Use MasterPort base-class pointers where possibleAndreas Hansson
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-04-14Regression: Add ANSI colours to highlight test statusAndreas Hansson
2012-04-14clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6Andreas Hansson
2012-04-13SCons: restore Werror option in src/SConscriptSteve Reinhardt
2012-04-12Stats: Update with use of std::map for ordered iteration in RubyAndreas Hansson
2012-04-12Ruby: Ensure order-dependent iteration uses an ordered mapAndreas Hansson
2012-04-09tests: Fix building unit tests.Gabe Black
2012-04-06rubytest: remove spurious printfBrad Beckmann
2012-04-06regress: ruby random tester and hammer stats updatesBrad Beckmann
2012-04-06ruby: set SimpleTiming as the default cpuBrad Beckmann
2012-04-06slicc: Controllers attached to Sequencers no longer have to be named L1Cache.Lisa Hsu
2012-04-06sim-ruby: checkpointing fixes and dependent eventq improvementsBrad Beckmann
2012-04-06slicc: fixed error message when the type has no inheritanceBrad Beckmann
2012-04-06MOESI_hammer: tbe allocation and dependent wakeup fixesBrad Beckmann
2012-04-06python: added __nonzero__ function to SimObject Bool paramsBrad Beckmann
2012-04-06MOESI_hammer: fixed bug with single cpu + flushes, then modified the regressi...Brad Beckmann
2012-04-06rubytest: seperated read and write ports.Brad Beckmann
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-04-05NetworkTest: remove unnecessary memory allocationTushar Krishna
2012-04-05Config: corrects the way Ruby attaches to the DMA portsNilay Vaish
2012-04-05Ruby: Fix the example configurations option parsingAndreas Hansson
2012-04-05Python: Make the All proxy traverse SimObject children as wellAndreas Hansson
2012-04-03Atomic: Remove the physmem_port and access memory directlyAndreas Hansson
2012-03-31X86: Fix address size handling so real mode works properly.Gabe Black
2012-03-30MEM: Remove legacy DRAM in preparation for memory updatesAndreas Hansson
2012-03-30Ruby: Remove the physMemPort and instead access memory directlyAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-30CPU: Unify initMemProxies across CPUs and simulation modesAndreas Hansson