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AgeCommit message (Expand)Author
2012-02-24Ruby: Simplify tester ports by not using SimpleTimingPortAndreas Hansson
2012-02-24MEM: Move all read/write blob functions from Port to PortProxyAndreas Hansson
2012-02-24MEM: Make port proxies use references rather than pointersAndreas Hansson
2012-02-24MEM: Move port creation to the memory object(s) constructionAndreas Hansson
2012-02-24CPU: Round-two unifying instr/data CPU ports across modelsAndreas Hansson
2012-02-24MEM: Fatal when no port can be found for an addressAndreas Hansson
2012-02-20SimObject: make get_config_as_dict() tolerate undefined paramsSteve Reinhardt
2012-02-14MEM: Fix residual bus ports and make them master/slaveAndreas Hansson
2012-02-14Script: Fix the scripts that use the num_cpus cache parameterAndreas Hansson
2012-02-14MEM: Fix master/slave ports in Ruby and non-regression scriptsAndreas Hansson
2012-02-13bp: fix up stats for changes to branch predictorAli Saidi
2012-02-13BPred: Fix RAS to handle predicated call/return instructions.Mrinmoy Ghosh
2012-02-13BP: Fix several Branch Predictor issues.Mrinmoy Ghosh
2012-02-13MEM: Explicit ports and Python binding on CopyEngineAndreas Hansson
2012-02-13MEM: Pass the ports from Python to C++ using the Swig paramsAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-02-12tests: fix diff-out script for op/inst stat changes.Ali Saidi
2012-02-12X86: open flags: Another patch from Vince WeaverGabe Black
2012-02-12configs: fix minor config bugs posted on the mailing listAli Saidi
2012-02-12stats: update stats for insts/ops and master id changesAli Saidi
2012-02-12cpu: add separate stats for insts/ops both globally and per cpu modelAnthony Gutierrez
2012-02-12mem: fix cache stats to use request ids correctlyDam Sunwoo
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-02-12prefetcher: Make prefetcher a sim object instead of it being a parameter on c...Mrinmoy Ghosh
2012-02-12Regressions: Update stats due to change in MESI protocolNilay Vaish
2012-02-11SPARC: Make PSTATE and HPSTATE a BitUnion.Gabe Black
2012-02-10Ruby: Remove isTagPresent() calls from Sequencer.ccNilay Vaish
2012-02-10MESI: Add queues for stalled requestsNilay Vaish
2012-02-10sim/system: initialize the pagePtr variableNilay Vaish
2012-02-10Regressions: Update stats due to O3 CPU changesNilay Vaish
2012-02-10O3 CPU: Improve handling of delayed commit flagNilay Vaish
2012-02-10O3 CPU: Strengthen condition for handling interruptsNilay Vaish
2012-02-10O3 CPU: Provide the squashing instructionNilay Vaish
2012-02-10O3 Fetch: Check if PC is pointing to Microcode ROMNilay Vaish
2012-02-10SE/FS: Record the system pointer all the time for the simple CPU.Gabe Black
2012-02-09MEM: Remove onRetryList from BusPort and rely on retryListAndreas Hansson
2012-02-07Checker: Access workload element 0 only if there is an element 0.Gabe Black
2012-02-07Faults: Turn off arch/faults.hhGabe Black
2012-02-07m5=>gem5: Make the regression script build gem5.* instead of m5.*Gabe Black
2012-02-05X86: Rename the bridge which allows commnication back to the local APICs.Gabe Black
2012-02-05Regressions: Fix the regress script when "all" is used.Gabe Black
2012-02-03System: Forgot to qrefresh with my last change.Gabe Black
2012-02-02System: Fix the check which detects running out of physical memory.Gabe Black
2012-02-02Regression: Update the regress script after SE/FS mergeAndreas Hansson
2012-02-01configs: More fixes for the memory system updatesAli Saidi
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2012-01-31MEM: Remove the otherPort from the cache portsAndreas Hansson
2012-01-31Thread: Use inherited baseCpu rather than cpu in SimpleThreadAndreas Hansson
2012-01-31util: implements "writefile" gem5 op to export file from guest to host filesy...Dam Sunwoo