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2012-11-02ruby: reset and dump stats along with reset of the systemHamid Reza Khaleghzadeh ext:(%2C%20Lluc%20Alvarez%20%3Clluc.alvarez%40bsc.es%3E%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
This patch adds support to ruby so that the statistics maintained by ruby are reset/dumped when the statistics for the rest of the system are reset/dumped. For resetting the statistics, ruby now provides the resetStats() function that a sim object can provide. As a consequence, the clearStats() function has been removed from RubySystem. For dumping stats, Ruby now adds a callback event to the dumpStatsQueue. The exit callback that ruby used to add earlier is being removed. Created by: Hamid Reza Khaleghzadeh. Improved by: Lluc Alvarez, Nilay Vaish Committed by: Nilay Vaish
2012-11-02mem: fix use after free issue in memories until 4-phase work complete.Ali Saidi
2012-11-02update stats for preceeding changesAli Saidi
2012-11-02mem: Add support for writing back and flushing cachesAndreas Sandberg
This patch adds support for the following optional drain methods in the classical memory system's cache model: memWriteback() - Write back all dirty cache lines to memory using functional accesses. memInvalidate() - Invalidate all cache lines. Dirty cache lines are lost unless a writeback is requested. Since memWriteback() is called when checkpointing systems, this patch adds support for checkpointing systems with caches. The serialization code now checks whether there are any dirty lines in the cache. If there are dirty lines in the cache, the checkpoint is flagged as bad and a warning is printed.
2012-11-02sim: Add drain methods to request additional cleanup operationsAndreas Sandberg
This patch adds the following two methods to the Drainable base class: memWriteback() - Write back all dirty cache lines to memory using functional accesses. memInvalidate() - Invalidate memory system buffers. Dirty data won't be written back. Specifying calling memWriteback() after draining will allow us to checkpoint systems with caches. memInvalidate() can be used to drop memory system buffers in preparation for switching to an accelerated CPU model that bypasses the gem5 memory system (e.g., hardware virtualized CPUs). Note: This patch only adds the methods to Drainable, the code for flushing the TLB and the cache is committed separately.
2012-11-02sim: Add SWIG interface for SerializableAndreas Sandberg
This changeset adds a SWIG interface for the Serializable class, which fixes a warning when compiling the SWIG interface for the event queue. Currently, the only method exported is the name() method.
2012-11-02python: Rename doDrain()->drain() and make it do the right thingAndreas Sandberg
There is no point in exporting the old drain() method in Simulate.py. It should only be used internally by doDrain(). This patch moves the old drain() method into doDrain() and renames doDrain() to drain().
2012-11-02sim: Reuse the code to change memory mode.Andreas Sandberg
changeToAtomic and changeToTiming both do essentially the same thing, they check the type of their input argument, drain the system, and switch to the desired memory mode. This patch moves all of that code to a separate method (changeMemoryMode) and calls that from both changeToAtomic and changeToTiming.
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
This patch moves the draining interface from SimObject to a separate class that can be used by any object needing draining. However, objects not visible to the Python code (i.e., objects not deriving from SimObject) still depend on their parents informing them when to drain. This patch also gets rid of the CountedDrainEvent (which isn't really an event) and replaces it with a DrainManager.
2012-11-02cpu: O3 add a header declaring the DerivO3CPUAndreas Sandberg
SWIG needs a complete declaration of all wrapped objects. This patch adds a header file with the DerivO3CPU class and includes it in the SWIG interface. --HG-- rename : src/cpu/o3/cpu_builder.cc => src/cpu/o3/deriv.cc
2012-11-02cpu: Add header files for checker CPUsAndreas Sandberg
In order to create reliable SWIG wrappers, we need to include the declaration of the wrapped class in the SWIG file. Previously, we didn't expose the declaration of checker CPUs. This patch adds header files for such CPUs and include them in the SWIG wrapper. --HG-- rename : src/cpu/dummy_checker_builder.cc => src/cpu/dummy_checker.cc rename : src/cpu/o3/checker_builder.cc => src/cpu/o3/checker.cc
2012-11-02dev: Fix ethernet device inheritance structureAndreas Sandberg
The Python wrappers and the C++ should have the same object structure. If this is not the case, bad things will happen when the SWIG wrappers cast between an object and any of its base classes. This was not the case for NSGigE and Sinic devices. This patch makes NSGigE and Sinic inherit from the new EtherDevBase class, which in turn inherits from EtherDevice. As a bonus, this removes some duplicated statistics from the Sinic device.
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
When casting objects in the generated SWIG interfaces, SWIG uses classical C-style casts ( (Foo *)bar; ). In some cases, this can degenerate into the equivalent of a reinterpret_cast (mainly if only a forward declaration of the type is available). This usually works for most compilers, but it is known to break if multiple inheritance is used anywhere in the object hierarchy. This patch introduces the cxx_header attribute to Python SimObject definitions, which should be used to specify a header to include in the SWIG interface. The header should include the declaration of the wrapped object. We currently don't enforce header the use of the header attribute, but a warning will be generated for objects that do not use it.
2012-11-02pci: Make Python wrapper cast to the right typeAndreas Sandberg
The PCI base class is PciDev and not PciDevice, which is used by the Python world. Make sure this is reflected in the wrapper code.
2012-11-02mips: Remove unused Python fileAndreas Sandberg
Remove BISystem.py, BareIronMipsSystem is already implemented in MipsSystem.py.
2012-11-02dev: Add missing inline declarationsAndreas Sandberg
2012-11-02base: Add missing header file to addr_range.hh.Andreas Sandberg
2012-10-09m5: Expose m5 pseudo-instructions to C/C++ via a static libraryJames Clarkson
Updated the util/m5/Makefile.arm so that m5op_arm.S is used to create a static library - libm5.a. Allowing users to insert m5 psuedo-instructions into their applications for fine-grained checkpointing, switching cpus or dumping statistics. e.g. #include <m5op.h> void foo(){ ... m5_reset_stats(<delay>,<period>) m5_work_begin(<workid>,<threadid>); ... m5_work_end(<workid>,<threadid>); m5_dump_stats(<delay>,<period>); }
2012-11-02ARM: dump stats and process info on context switchesDam Sunwoo
This patch enables dumping statistics and Linux process information on context switch boundaries (__switch_to() calls) that are used for Streamline integration (a graphical statistics viewer from ARM).
2012-11-02base: Fix a few incorrectly handled print format casesChander Sudanthi
This patch ensures cases like %0.6u, %06f, and %.6u are processed correctly. The case like %06f is ambiguous and was made to match printf. Also, this patch removes the goto statement in cprintf.cc in favor of a function call.
2012-11-02base: split out the VncServer into a VncInput and Server classesChander Sudanthi
This patch adds a VncInput base class which VncServer inherits from. Another class can implement the same interface and be used instead of the VncServer, for example a class that replays Vnc traffic. --HG-- rename : src/base/vnc/VncServer.py => src/base/vnc/Vnc.py rename : src/base/vnc/vncserver.cc => src/base/vnc/vncinput.cc rename : src/base/vnc/vncserver.hh => src/base/vnc/vncinput.hh
2012-11-02ISA: generic Linux thread info supportDam Sunwoo
This patch takes the Linux thread info support scattered across different ISA implementations (currently in ARM, ALPHA, and MIPS), and unifies them into a single file. Adds a few more helper functions to read out TGID, mm, etc. ISA-specific information (e.g., ALPHA PCBB register) is now moved to the corresponding isa_traits.hh files.
2012-11-02sim: Fix as issue where exit events on instr queues are used after freed.Ali Saidi
2012-11-02o3: Fix a couple of issues with the local predictor.Mrinmoy Ghosh
Fix some issues with the local predictor and the way it's indexed.
2012-11-02Partly revert [4f54b0f229b5] and move draining to m5.changeToTimingAndreas Sandberg
Changeset 4f54b0f229b5 removed the call to doDrain in changeToTiming based on the assumption that the system does not need draining when running in atomic mode. This is a false assumption since at least the System class requires the system to be drained before it allows switching of memory modes. This patch reverts that part of the changeset.
2012-10-31mem: Fix typo in port commentsAndreas Hansson
This patch merely fixes a few typos in the port comments.
2012-10-31stats: Update stats for fixed simple-atomic-mp configAndreas Hansson
This patch updates the stats for the regressions that were affected by the typo in the simple-atomic-mp configuration.
2012-10-31config: Fix a typo in the simple-atomic-mp configurationAndreas Hansson
This patch fixes a minor typo that managed to sneak into the simple-atomic-mp regression configuration.
2012-10-30stats: Update stats for unified cache configurationAndreas Hansson
This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30config: Unify caches used in regressions and adjust L2 MSHRsAndreas Hansson
This patch unified the L1 and L2 caches used throughout the regressions instead of declaring different, but very similar, configurations in the different scripts. The patch also changes the default L2 configuration to match what it used to be for the fs and se scripts (until the last patch that updated the regressions to also make use of the cache config). The MSHRs and targets per MSHR are now set to a more realistic default of 20 and 12, respectively. As a result of both the aforementioned changes, many of the regression stats are changed. A follow-on patch will bump the stats.
2012-10-27regressions: update stats for ruby fs testNilay Vaish
2012-10-27ruby: set the is_icache param for cachesMalek Musleh
This patch sets the is_icache param for the L1 caches used in the MESI and the MOESI CMP directory protocols.
2012-10-27Ruby: Use block size in configuring directory bits in addressJason Power ext:(%2C%20Joel%20Hestness%20%3Chestness%40cs.wisc.edu%3E)
This patch replaces hard coded values used in Ruby's configuration files for setting directory bits with values based on the block size in use.
2012-10-26config: Add a check for fastmem only used with Atomic CPUAndreas Hansson
This patch adds an additional check to ensure that the fastmem option is only used if the system is using the Atomic CPU.
2012-10-26config: Remove unused mem_size in fs.pyAndreas Hansson
This patch removes a segment of dead code that is never used.
2012-10-26config: Fix the cache class naming in regression scriptsAndreas Hansson
This patch unifies the naming of the default L1 and L2 caches in the regression configs to be in line with what is used in the se and fs scripts.
2012-10-25stats: Update the stats to reflect the 1GHz default system clockAndreas Hansson
This patch updates the stats to reflect the change in the default system clock from 1 THz to 1GHz. The changes are due to the DMA devices now injecting requests at a lower pace.
2012-10-25dev: Make default clock more reasonable for system and devicesAndreas Hansson
This patch changes the default system clock from 1THz to 1GHz. This clock is used by all modules that do not override the default (parent clock), and primarily affects the IO subsystem. Every DMA device uses its clock to schedule the next transfer, and the change will thus cause this inter-transfer delay to be longer. The default clock of the bus is removed, as the clock inherited from the system provides exactly the same value. A follow-on patch will bump the stats.
2012-10-25stats: Update stats to reflect use of SimpleDRAMAndreas Hansson
This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25config: Use SimpleDRAM in full-system, and with o3 and inorderAndreas Hansson
This patch favours using SimpleDRAM with the default timing instead of SimpleMemory for all regressions that involve the o3 or inorder CPU, or are full system (in other words, where the actual performance of the memory is important for the overall performance). Moving forward, the solution for FSConfig and the users of fs.py and se.py is probably something similar to what we use to choose the CPU type. I envision a few pre-set configurations SimpleLPDDR2, SimpleDDR3, etc that can be choosen by a dram_type option. Feedback on this part is welcome. This patch changes plenty stats and adds all the DRAM controller related stats. A follow-on patch updates the relevant statistics. The total run-time for the entire regression goes up with ~5% with this patch due to the added complexity of the SimpleDRAM model. This is a concious trade-off to ensure that the model is properly tested.
2012-10-25config: Use shared cache config for regressionsAndreas Hansson
This patch uses the common L1, L2 and IOCache configuration for the regressions that all share the same cache parameters. There are a few regressions that use a slightly different configuration (memtest, o3-timing=mp, simple-atomic-mp and simple-timing-mp), and the latter are not changed in this patch. They will be updated in a future patch. The common cache configurations are changed to match the ones used in the regressions, and are slightly changed with respect to what they were. Hopefully this means we can converge on a common base configuration, used both in the normal user configurations and regressions. As only regressions that shared the same cache configuration are updated, no regressions are affected.
2012-10-25arm: Use table walker clock that is inherited from CPUAndreas Hansson
This patch simplifies the scheduling of the next walk for the ARM table walker. Previously it used the CPU clock, but as the table walker inherits the clock from the CPU, it is cleaner to simply use its own clock (which is the same).
2012-10-23stats: Update stats for DMA port sendAndreas Hansson
This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23dev: Remove zero-time loop in DMA timing sendAndreas Hansson
This patch removes the zero-time loop used to send items from the DMA port transmit list. Instead of having a loop, the DMA port now uses an event to schedule sending of a single packet. Ultimately this patch serves to ease the transition to a blocking 4-phase handshake. A follow-on patch will update the regression statistics.
2012-10-23stats: Update t1000 stats to match recent changesAndreas Hansson
This patch brings the t1000 stats up to date.
2012-10-18ruby: functional access updates to network test protocolNilay Vaish
I had forgotten to change the network test protocol while making changes to ruby for supporting functional accesses. This patch updates the protocol so that it can compile correctly.
2012-10-16regressions: update stats for eio testsNilay Vaish
2012-10-15regressions: update stats due to change to ruby memory systemNilay Vaish
2012-10-15ruby: improved support for functional accessesNilay Vaish
This patch adds support to different entities in the ruby memory system for more reliable functional read/write accesses. Only the simple network has been augmented as of now. Later on Garnet will also support functional accesses. The patch adds functional access code to all the different types of messages that protocols can send around. These messages are functionally accessed by going through the buffers maintained by the network entities. The patch also rectifies some of the bugs found in coherence protocols while testing the patch. With this patch applied, functional writes always succeed. But functional reads can still fail.
2012-10-15memtest: move check on outstanding requestsNilay Vaish
The Memtest tester allows for only one request to be outstanding for a particular physical address. The check has been written separately for reads and writes. This patch moves the check earlier than its current position so that it need not be written separately for reads and writes.
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