| Age | Commit message (Expand) | Author |
|---|
| 2017-09-26 | sim: Add a set_parent to NullSimObject which does nothing. | Gabe Black |
| 2017-09-25 | mem: Fill the new packet ID fields with master IDs when tracing packets. | Gabe Black |
| 2017-09-25 | mem: Add a "map" of packet IDs to strings in probe traces. | Gabe Black |
| 2017-09-25 | mem: Trace the request master ID in the MemTraceProbe. | Gabe Black |
| 2017-09-25 | mem: Record the request master ID in the PacketInfo structure. | Gabe Black |
| 2017-09-25 | dev, virtio: Improvements to diod process handling | Anouk Van Laer |
| 2017-09-21 | alpha: Move some initialization logic from loadState into unserialize. | Gabe Black |
| 2017-09-21 | sim: Stop using loadState in the Root SimObject. | Gabe Black |
| 2017-09-20 | kvm: arm: Get rid of functions which just wrap the subclasses version. | Gabe Black |
| 2017-09-11 | tlm: Don't set SystemC time resolution | Matthias Jung |
| 2017-09-11 | stats: Move the swpipl function into the Alpha kernel stats. | Gabe Black |
| 2017-09-11 | stats: Get rid of some kernel stats related cruft. | Gabe Black |
| 2017-09-06 | cpu: Fix bi-mode branch predictor thresholds | Rico Amslinger |
| 2017-09-01 | cpu-minor: Fix for addr range coverage calculation | Pau Cabre |
| 2017-08-31 | scons: bump required python version to 2.7 to support pybind11 | Paul Rosenfeld |
| 2017-08-30 | arch-arm: Only increment SW PMU counters on writes to PMSWINC | Jose Marinho |
| 2017-08-30 | arch-arm: Add missing override keywords in fault.hh | Andreas Sandberg |
| 2017-08-30 | arch-x86: Add missing override in the X86 TLB | Andreas Sandberg |
| 2017-08-30 | arch-sparc: Add a FaultVals instantiation for VecDisabled | Andreas Sandberg |
| 2017-08-30 | arch-alpha: Add missing overrides | Andreas Sandberg |
| 2017-08-30 | python: Make GlobalExitEvent.getCode() return an int | Andreas Sandberg |
| 2017-08-30 | cpu-o3: fix data pkt initialization for split load | Matthias Hille |
| 2017-08-28 | x86: Use the new CondInst format for moves to/from control registers. | Gabe Black |
| 2017-08-28 | x86: Add a "CondInst" format for conditionally decoded instructions. | Gabe Black |
| 2017-08-12 | dev: Fix an IDE error check. | Gabe Black |
| 2017-08-08 | mem-cache: Delete squashed HWPrefetches | Pau Cabre |
| 2017-08-03 | configs, arm: Fix incorrect use of mem_range in bL example | Andreas Sandberg |
| 2017-08-03 | arm, config: Fix CPU names in ARM example configs | Andreas Sandberg |
| 2017-08-02 | base: Give more information when setting up asynchronous IO fails. | Gabe Black |
| 2017-08-01 | misc: git ignore file udpated | Éder F. Zulian |
| 2017-08-01 | style: Add shared gem5 headers to the style checker | Andreas Sandberg |
| 2017-08-01 | util: Move m5op.h to the shared include directory | Andreas Sandberg |
| 2017-08-01 | util, m5: Use consistent naming for m5op C symbols | Andreas Sandberg |
| 2017-08-01 | arch-arm: Use named constants for m5op instructions | Andreas Sandberg |
| 2017-08-01 | sim: Use named constants for pseudo ops | Andreas Sandberg |
| 2017-08-01 | util: Move the m5ops.h file to a shared directory | Andreas Sandberg |
| 2017-08-01 | kvm, arm: Switch to the device EQ when accessing ISA devices | Andreas Sandberg |
| 2017-08-01 | kvm: Add a helper method to access device event queues | Andreas Sandberg |
| 2017-08-01 | cpu, kvm: Fix deadlock issue when resuming a drained system | Andreas Sandberg |
| 2017-08-01 | arch-arm: Switch to DTOnly as the default machine type | Andreas Sandberg |
| 2017-07-28 | config: Discover CPU timing models based on target ISA | Andreas Sandberg |
| 2017-07-27 | config, arm: SE configuration for the ARM starter kit | Gabor Dozsa |
| 2017-07-27 | config, arm: FS configuration for the ARM starter kit | Gabor Dozsa |
| 2017-07-27 | config, arm: Add a high-performance in order timing model | Ashkan Tousi |
| 2017-07-27 | config: Change mem_range attribute naming in ARM SimpleSystem | Gabor Dozsa |
| 2017-07-25 | tests: Fix path for module imports in ARM system configs | Nikos Nikoleris |
| 2017-07-25 | configs,sim-se: fix se.py multi-cpu multi-cmd issue | Pau Cabre |
| 2017-07-20 | sim: Prevent segfault in the wakeCpu m5op if id is invalid | Jose Marinho |
| 2017-07-19 | cpu: Add missing rename of vector registers in the O3 CPU | Rekai Gonzalez-Alberquilla |
| 2017-07-17 | cpu,o3: Fixed checkpointing bug occuring in the o3 CPU | Anouk Van Laer |
