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AgeCommit message (Expand)Author
2012-07-02gcc: Fix warnings for gcc 4.7 and clang 3.1Andreas Hansson
2012-06-29Cache: Fix the LRU policy for classic memory hierarchyLena Olson
2012-06-29Bus: enable non/coherent buses sub-classesUri Wiener
2012-06-29Mem: fix master id assertion in cache_impl.hhDam Sunwoo
2012-06-29Style: Make style.py's invalid warning print which file caused the infraction.Matt Evans
2012-06-29Mem: Fix a livelock resulting in LLSC/locked memory access implementation.Matt Evans
2012-06-29Stats: Update stats for RAS and LRU fixes.Ali Saidi
2012-06-29O3: Track if the RAS has been pushed or not to pop the RAS if neccessary.Nathanael Premillieu
2012-06-29ARM: Fix identification of one RAS pop instruction.Ali Saidi
2012-06-29Cache: Only invalidate a line in the cache when an uncacheable write is seen.Ali Saidi
2012-06-29ARM: Update version of linux we claim to be to 3.0.0.Ali Saidi
2012-06-29ARM: Fix issue with predicted next pc being wrong because of advance() ordering.Ali Saidi
2012-06-27ARM: Fix address range issue with VExpress EMMAli Saidi
2012-06-20swig: Use SWIG from environment when determining versionAndreas Hansson
2012-06-18Build: Point to the appropriate tcmalloc packageAndreas Hansson
2012-06-11configs: add run scripts for ics/gb versions of android and bbenchAnthony Gutierrez
2012-06-11ARM: implement the ProcessInfo methodsAnthony Gutierrez
2012-06-11scons: Make compiler version error more verbose and easier to debug.Ali Saidi
2012-06-11Regression: Fix some bugs in simple-timing-mp-ruby.py.Marc Orr
2012-06-08Timing CPU: Remove a redundant port pointerAndreas Hansson
2012-06-08Power: Fix MaxMiscDestRegs which was set to zeroAndreas Hansson
2012-06-07X86 TLB: Add a missing = signNilay Vaish
2012-06-07mem: Delay deleting of incoming packets by one call.Ali Saidi
2012-06-07X86 TLB: Fix for gcc 4.4.3Jayneel Gandhi
2012-06-07Config: call to setWorkCountOptions() for all ISAsNilay Vaish
2012-06-07Config: Remove setMipsOptionsNilay Vaish
2012-06-07Config: changes to a couple of error msgsNilay Vaish
2012-06-05cpu: Don't init simple and inorder CPUs if they are defered.Anthony Gutierrez
2012-06-05ISA: Back-out NoopMachInst as a StaticInstPtr change.Ali Saidi
2012-06-05cpt: update some comments in the checkpoint migration scriptAli Saidi
2012-06-05all: Update stats for memory per master and total fix.Ali Saidi
2012-06-05stats: when applying an operation to two vectors sum the components first.William Wang
2012-06-05Mem: add per-master stats to physmemDam Sunwoo
2012-06-05ARM: Add PCIe support to VExpress_EMM model and remove deprecated ELTGeoffrey Blake
2012-06-05ARM: removed extra white spaceChander Sudanthi
2012-06-05ARM: Fix MPIDR and MIDR register implementation.Chander Sudanthi
2012-06-05ARM: PS2 encoding fixChander Sudanthi
2012-06-05sim: Provide a framework for detecting out of data checkpoints and migrating ...Ali Saidi
2012-06-05stats: Add stats unittest for total calculations.Ali Saidi
2012-06-05O3: Clean up the O3 structures and try to pack them a bit better.Ali Saidi
2012-06-05sim: Add support for tcmalloc if it's installed and available.Ali Saidi
2012-06-05sim: Remove FastAllocAli Saidi
2012-06-05ARM: Fix over-eager assert in gic.Ali Saidi
2012-06-05stats: Provide a mechanism to get a callback when stats are dumped.Mitchell Hayenga
2012-06-05ARM: Fix compilation on ARM after Gabe's change.Ali Saidi
2012-06-04ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.Gabe Black
2012-06-04X86: Update stats for the CPUID change.Gabe Black
2012-06-04X86: Ensure that the CPUID instruction always writes its outputs.Gabe Black
2012-06-04X86: Ensure that the decoder's internal ExtMachInst is completely initialized.Gabe Black
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson