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2018-05-29arch-arm: Remove unusued MISCREG_A64_UNIMPLGiacomo Travaglini
In case the decoder fails to find a suitable MiscReg during a MSR/MRS in AArch64, MISCREG_UNKNOWN is used, so there is no need for an extra MISCREG_A64_UNIMPL register. Change-Id: I7c709fc554e554b39d765dffb7ceb90e33b7c15f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10503 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-05-29arch-arm: MPIDR.MT = 1 in a multithreaded systemGiacomo Travaglini
MPIDR.MT Indicates whether the lowest level of affinity consists of logical PEs that are implemented using a multithreading type approach Change-Id: Ia5e6e65577729c7826227c4574ce690f76454edc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10502 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-05-29arch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation definedGiacomo Travaglini
In the AArch64 ISA, S3_<op1>_<Cn>_<Cm>_<op2> refers to a pool of implementation defined registers, provided that reg numbers are in the following range: <op1> is in the range 0 - 7 <CRn> can take the values 11, 15 <CRm> is in the range 0 - 15 <op2> is in the range 0 - 7 Change-Id: I7edd013e5cea4887f5e4c5a81f4835b7de93bd50 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10501 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-05-29cpu: Avoid unnecessary dynamic_pointer_cast in atomic modelGiacomo Travaglini
In the atomic model a dynamic_pointer_cast is performed at every tick to check if the fault is a SyscallRetryFault. This was happening even when there was no generated fault. Change-Id: I7f4afeffffdf4f988230e05286602d8d9a919c6c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10101 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-05-29arch-arm: Implement ARMv8.1 TTBR1_EL2 registerGiacomo Travaglini
This patch implements the ARMv8.1 TTBR1_EL2 register, which is used for getting the translation table base address when a Host Operating System is running at EL2. (HCR_EL2.E2H = 1) Change-Id: Ic0ab351cae3fd64855eda7c18c8757da0d7b8663 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10382 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-05-29arch-arm: Add E2H bit to HCR_EL2 System registerGiacomo Travaglini
This patch adds the EL2 Host bit to the HCR_EL2 register. Enables a configuration where a Host Operating System is running in EL2, and the Host Operating System's applications are running in EL0. Change-Id: I92d21ed9f8958c58f135dca1b6a97460ba4c02f9 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10381 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-05-24x86: Add op classes to the MediaOps.Gabe Black
The ISA parser had been assuming these microops were all FloatAddOp which is usually not correct. Change-Id: Ic54881d16f16b50c3d6a8c74b94bff9ae3b1f43e Reviewed-on: https://gem5-review.googlesource.com/10541 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Tariq Azmy <tariqslayer01@gmail.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-05-18mem: Add support for more flexible DRAM timing and topologiesWendy Elsasser
This patch has 2 main aspects: 1) Add new parameter to adjust write-to-write delay 2) Enable support of more than 64 banks per controller Changes for new parameter: Incorporated a new parameter, tCCD_L_WR, which defaults to tCCD_L. This parameter can be used to set a unique delay between writes and between reads. To incorporate this parameter in the controller, modified the DRAMCtrl class to have separate variables for read and write column delays. Used these variables to account for tRTW, tWTR, tBURST, tCCD_L, and tCS as well as the new tCCD_L_WR parameter. Changes to support more than 64 banks: Modified the logic selecting the next command (reorderQueue and minBankPrep functions). Replaced the unint64_t variables with a vector of uint32_t elements. There is a uint32_t element defined per ranks to allow up to 32 banks per rank. This will automatically scale with ranks without issue. Change will allow analysis of memory sub-systems beyond the current landscape. Change-Id: I0ce466efed58276f843ad90e9ecc0ece6c37d646 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10103 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-18mem: Optimize self-refresh entryWendy Elsasser
Self-refresh is entered during a refresh event, when the rank was previously in a precharge power-down state. The original code would enter self-refresh after a refresh was issued. The device subsequently will issue a refresh on self-refresh entry. On self-refresh exit, the controller will issue another refresh command. Devices require at least one additional refresh to be issued between self-refresh exit and re-entry. This ensures that enough refreshes occur in the case when the device narrowly missed a refresh on self-refresh exit. To minimize the number of refresh operations and still maintain the device requirement, the current logic does the following: 1) The controller will still enter self-refresh from a refresh event, when the previous state was precharge power-down. However, the refresh itself will be bypassed and the controller will immediately issue a self-refresh entry. 2) On a self-refresh exit, the controller will immediately issue a refresh command (per the original logic). This ensures the devices requirements are met and is a convenient way to kick off the command state machine. Change-Id: I1c4b0dcbfa3bdafd755f3ccd65e267fcd700c491 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10102 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-17mem-cache: Move reference count stats update to blk invalidationNikos Nikoleris
The tags in the cache keep track of the number of references to the blocks as well as the average number of references between an insertion and the next invalidation. Previously the stats where updated only on block insertion and invalidations were ignored. This changes moves the update of the counters to the block invalidation function. Change-Id: Ie7672c13813ec278a65232694024d2e5e17c4612 Reviewed-on: https://gem5-review.googlesource.com/10428 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-05-17mem-cache: Remove isTouched field from the CacheBlkNikos Nikoleris
At the moment isTouched is used in the warm-up detection mechanism but it keeps track of the same information as isValid(). This change removes it and substitutes its use by isValid(). Change-Id: I611ddf2fa4562ae3b3b2ed2fb74d26abd2e5ec62 Reviewed-on: https://gem5-review.googlesource.com/10427 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-05-17mem-cache: Move replacements stat to the base cache classNikos Nikoleris
Change-Id: I25dbcfcddfe1c422a76eb1af3f726c1360d8d110 Reviewed-on: https://gem5-review.googlesource.com/10426 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-05-17base: Add M5 flag for [[nodiscard]] attributeNikos Nikoleris
This change adds the M5_NODISCARD keyword to allow use of the [[nodiscard]] attribute with compilers that support C++17. Currently, C++17 is not a requirement and therefore the M5_NODISCARD has not effect and does not break compilation for older compilers. Change-Id: Ifc5c8f34764da3c7291066dcb2ff908c97738c3d Reviewed-on: https://gem5-review.googlesource.com/10441 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-05-17mem-cache: Simplify writeback for the tempBlock in recvTimingRespNikos Nikoleris
When we use the tempBlock to fill-in, we have to write it back and invalidate it at the end of current transaction. This patch simplifies the writeback flow by treating it as a regular writeback. Change-Id: I257be7bbff211e2832ad001a4e991daf67704485 Reviewed-on: https://gem5-review.googlesource.com/10421 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-16arch-arm: Fix semihosting arg count for SYS_GET_CMDLINEAndreas Sandberg
SYS_GET_CMDLINE was declared as having 1 parameter when it is really supposed to have two parameters. Change-Id: Ia364abb4b34834f4d5e598b5adee9585e0815ac8 Reported-by: Steve Capper <steve.capper@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10022 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-05-16arch-arm: Add support for semihosting STDIO redirectionAndreas Sandberg
The Arm Semihosting layer currently assumes that the guest application shares STDIO with gem5. This makes it hard to distinguish application output from gem5's output and makes it impossible to redirect STDIN when running in interactive mode. Add support for custom STDIO redirection when instantiating the Semihosting model. Change-Id: I3411a6b9bfb008ffc3087d8837f59be72bd1e8ae Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10021 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-05-16style: fix amd license and style issuesTony Gutierrez
Change-Id: I26136fb49f743c4a597f8021cfd27f78897267b5 Reviewed-on: https://gem5-review.googlesource.com/10463 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-05-15gpu-compute: Cleanup the scheduler a bitTony Gutierrez
Change-Id: If2c626544f208e15c91be975dee9253126862ced Reviewed-on: https://gem5-review.googlesource.com/10222 Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-05-12arch-riscv: Update CSR implementationsAlec Roelke
This patch updates the CSRs to match the RISC-V privileged specification version 1.10. As interrupts, faults, and privilege levels are not yet supported, there are no meaninful side effects that are implemented. Performance counters are also not yet implemented, as they do not have specifications. Currently they act as cycle counters. Note that this implementation trusts software to use the registers properly. Access protection, readability, and writeability of registers based on privilege will come in a future patch. Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a Reviewed-on: https://gem5-review.googlesource.com/7441 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2018-05-09sim: Remove trailing dot when assigning a master's nameGiacomo Travaglini
This patch fixes the master's name allocation in the system. The error was occurring when a submaster was not specified in getMasterId: a trailing separation dot was still added to the master's name. Change-Id: I0e67900f6fdd36a61900453b55219fc7007d1b05 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10301 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-05-09base, dev: Fix port message for vnc and terminalAndreas Sandberg
When running gem5, the simulator outputs the following message to describe the ports used by the VNC server and ther terminal: Listening for system connection on port 5900 Listening for system connection on port 3456 The code used to extract the basename ('terminal' or 'vncserver') and print that instead of system. However, this doesn't seem to work any more. Change the code to output the full object name instead. Change-Id: Ib27f66a5f8ba64c7a875b4e2f26a2e2ff48db8f3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10026 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-05-08arch-x86, arch-power: fix calls to bits and insertBitsMatt Sinclair
The bits and insertBits assume the first bit is the larger bit and the last bit is the smaller bit. This commit fixes several X86 and Power calls to these functions that incorrectly assumed that first was the smaller bit. Change-Id: I2b5354d1b9ca66e3436c4a72042416a6ce6dec01 Reviewed-on: https://gem5-review.googlesource.com/10241 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-05-08mem-cache: Create block insertion functionDaniel R. Carvalho
Create a block insertion function to be used when inserting blocks. This resets the number of references to 1 (the insertion is taken into account), sets the insertion tick, and set secure state. Change-Id: Ifc34cbbd1c125207ce47912d188809221c7a157e Reviewed-on: https://gem5-review.googlesource.com/9824 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-08arch-arm: Map ID_x_EL1 registers to AArch32 versionGiacomo Travaglini
AArch64 ID_x_EL1 registers map to AArch32 ID_x counterparts. Those registers must be initialized even when the highest Exception Level is using AArch64. Change-Id: Iccc9b6f631f5fac288116eb1ef2ad1d30c03de7b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10361 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-05-08dev: Add support for a simple debug UARTAndreas Sandberg
Add a simple memory-mapped device that forwards writes to a serial devices and treats reads as reads from the device. Unlike real UART models, this one doesn't support interrupts. This is useful to implement various debug devices that exist in many systems. Change-Id: I1e4300e4d3b70825a15d03f47d4e026941f9066c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10025 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-05-04scons: Fix --with-ubsan/asan compilation flagsGiacomo Travaglini
SConstruct was using an undefined env variable; this patch uses the main Environment variable. Change-Id: I30ab6b4bbfa6d9a71a30fb33406a799bfb476821 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10181 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-05-03mem-ruby: Consistent dprintf formats for issue outcomesBrad Beckmann
Change-Id: I053fc42f0d5f678f8e3434b53a0f09e00fc3e345 Reviewed-on: https://gem5-review.googlesource.com/10221 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-05-03arch-x86: Enable fstatfs for x86_64Tony Gutierrez
Change-Id: Ic871f852c4892f2228f0d9bb3cc5cb66887d9736 Reviewed-on: https://gem5-review.googlesource.com/10201 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-05-03mem-cache: Create Second-Chance replacement policyDaniel R. Carvalho
Implementation of a Second-Chance replacement policy. Similar to FIFO, but every block is given a second chance if it has been touched. Change-Id: Id4d52b698d0045a4914a4d848fdf9c3c00a28508 Reviewed-on: https://gem5-review.googlesource.com/9441 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-03mem-cache: ReplacementPolicy specific replacement dataDaniel R. Carvalho
Replacement data is specific for each replacement policy, and thus should be instantiated differently by each policy. Touch() and reset() do not need to be aware of CacheBlk, as they only update its ReplacementData. Invalidate() makes replacement policies independent of cache blocks, by removing the awareness of the valid state. An inheritable base ReplaceableEntry class was created to allow usage of replacement policies with any table-like structure. Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b Reviewed-on: https://gem5-review.googlesource.com/9421 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-02arch-x86: implement movntps/movntpd SSE instsSteve Reinhardt
These are non-temporal packed SSE stores. Change-Id: I526cd6551b38d6d35010bc6173f23d017106b466 Reviewed-on: https://gem5-review.googlesource.com/9861 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-05-02x86: Add a ld/st microop flag for marking an access uncacheable.Gabe Black
This percolates down to the memory request object which will have its "UNCACHEABLE" flag set. Change-Id: Ie73f4249bfcd57f45a473f220d0988856715a9ce Reviewed-on: https://gem5-review.googlesource.com/9881 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-05-02arch-x86: Enable the umask system callTony Gutierrez
Change-Id: I309beb1604657e8d1807ac90458709df57f0f819 Reviewed-on: https://gem5-review.googlesource.com/10161 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-04-27sim,cpu,mem,arch: Introduced MasterInfo data structureGiacomo Travaglini
With this patch a gem5 System will store more info about its Masters. While it was previously keeping track of the Master name and Master ID only, it is now adding a per-Master pointer to the SimObject related to the Master. This will make it possible for a client to query a System for a Master using either the master's name or the master's pointer. Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9781 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-26mem-cache: Use block iteration in BaseSetAssocDaniel R. Carvalho
Use block iteration instead of numSets and assoc in print(), cleanupRefs() and computeStats(). This makes these functions rely solely on what they are used for: printing and calculating stats of blocks. With the addition of Sectors an extra indirection level is added, and thus these functions would be skipping blocks. Change-Id: I0006f82736cce02ba3e501ffafe9236f748daf32 Reviewed-on: https://gem5-review.googlesource.com/10143 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-20docs: Fix power model doxygenJason Lowe-Power
Change-Id: I0a9a30bc4a89411e0f1dd897f0d1f05f20790b50 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/9981 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-04-19mem-cache: Use findBlock in FALRU's block accessDaniel R. Carvalho
An access must perform a block search, which is done by findBlock. The tagHash is indexed by tags, so use extractTag instead of re- implementing its functionality. Change-Id: Ib5abacbc65cddf0f2d7e4440eb5355b56998a585 Reviewed-on: https://gem5-review.googlesource.com/10082 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-04-19mem-cache: Use secure flag in FALRU's findBlockDaniel R. Carvalho
FALRU's findBlock() must use the secure flag to assure proper functionality. Change-Id: I54e9fbd3c9093b3e8043c4c6c850b74a8f1f5ec0 Reviewed-on: https://gem5-review.googlesource.com/10081 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-19arch-arm: Add ARMv8.1 TTBR1_EL2 registerGiacomo Travaglini
This patch adds ARMv8.1 TTBR1_EL2 register into the decodeAArch64SysReg table, but stil leaving it unimplemented (Accessing it through MSR/MRS causes an exception) Change-Id: I463b86cc544233aa1ee5b2fcba689d6b9f2a874b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10063 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-19arch-arm: Fix Unknown Instruction disassembleGiacomo Travaglini
Do not print the entire ExtMachInst when disassembling an Unknown Instruction. Change-Id: Icd5908ec0fa430090165b2426372bdeb43c2a155 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10062 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-19arch-arm: Change disassemble when MSR to UNKNOWN registerGiacomo Travaglini
This patch changes the fault being thrown when MSR/MRS to an unknown Misc register in AArch64. While previously the instruction was decoded as an Unknown instruction (hence not printing any information), it is now decoded as a FailUnimplemented and the unrecognized System register numbers (CRn, op0...) are printed. Change-Id: I205ff7adcde5934231c77e8d2250db69a34581fc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10061 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-18mem-cache: Create NRU Replacement PolicyDaniel R. Carvalho
Implementation of a Not Recently Used replacement policy. Change-Id: I24ab3a6f1db6dcb756b869cfebb5c4bc544170e8 Reviewed-on: https://gem5-review.googlesource.com/9001 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-18arch-arm: Fix masking in CPACR_EL1Chuan Zhu
Some bits in CPACR_EL1 are RES0 but not RAZ/WI. For instance, bit CPACR_EL1[31] is RES0 but should be made stateful, since it allows programing of CPACR.ASEDIS. Therefore the masking of CPACR_EL1 is removed. Change-Id: If1fa3fa1e06bc38495b8afce2c635f3ddf76ce32 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10046 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-18arch-arm: Mask out unsupported trapped exception handling bitsChuan Zhu
Floating-point trapped exception handlings are not currently supported in gem5, therefore the corresponding bits are RAZ/WI in FCPR. Change-Id: Ica43af62d5f3bbc095e8dd872f0bd365231a5b5f Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10045 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-18arch-arm: Fix FPEXC32_EL2 to FPEXC mappingChuan Zhu
The mapping between MISCREG_FPEXC32_EL2 and MISCREG_FPEXC was missing, this patch adds the mapping. Change-Id: I2e7fa0456b73662ff9f950deb5c7e648a1bdd9ca Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10043 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-18arch-arm: Adding MiscReg Priv (EL1) global flagGiacomo Travaglini
This patch introduces a single global flag for setting RW access permission at EL1 level, in either secure and non-secure mode. Change-Id: I35df66a73349044ca996b5c04c5a2476f3a7abdf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10042 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-18arch-arm: Correct masking of cp10 and cp11 in CPACRChuan Zhu
This patch fixes the masking of cp10 and cp11 in CPACR according to NSACR.cp10 / NSACR.cp11 by adding the condition "in Non-secure state, if EL3 is implemented and is using AArch32...", which is specified in ARM ARM. Change-Id: Id00e7bf04d6a985e27dbf1028677da0746b79924 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10044 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-18arch-arm: Using explicit invalidation in TLBGiacomo Travaglini
When setting TLB related MiscRegs, using explicit TLB regs invalidation rather than implicit switch-case fallthrough Change-Id: Ia1a7358b6d54dda3811be1c5ce5d676f8c518c4d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10041 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-18mem-cache: Revamp multiple size tracking for FALRU cachesNikos Nikoleris
This change fixes a few bugs and refactors the mechanism by which caches that use the FALRU tags can output statistics for multiple cache sizes ranging from the minimum cache of interest up to the actual configured cache size. Change-Id: Ibea029cf275a8c068c26eceeb06c761fc53aede2 Reviewed-on: https://gem5-review.googlesource.com/9826 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-18dev, arm: Cleanup Pl050 interrupt handlingAndreas Sandberg
Add support for TX interrupts and cleanup existing RX interrupt handling. Change-Id: If2e5b0c0cc6fbeb2dce09e7e9d935647516b2c47 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9769
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 06:28:14 +0000