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2014-03-01ruby: profiler: statically allocate stats variableNilay Vaish
Couple of users observed segmentation fault when the simulator tries to register the statistical variable m_IncompleteTimes. It seems that there is some problem with the initialization of these variables when allocated in the constructor.
2014-02-24stats: updates due to c0db268f811bNilay Vaish
2014-02-24ruby: correct errors in changeset 4eec7bdde5b0Nilay Vaish
Couple of errors were discovered in 4eec7bdde5b0 which necessitated this patch. Firstly, we create interrupt controllers in the se mode, but no piobus was being created. RubyPort, which earlier used to ignore range changes now forwards those to the piobus. The lack of piobus resulted in segmentation fault. This patch creates a piobus even in se mode. It is not created only when some tester is running. Secondly, I had missed out on modifying port connections for other coherence protocols.
2014-02-23stats: updates due to changes to ruby pio access handlingNilay Vaish
2014-02-23ruby: route all packets through ruby portNilay Vaish
Currently, the interrupt controller in x86 is connected to the io bus directly. Therefore the packets between the io devices and the interrupt controller do not go through ruby. This patch changes ruby port so that these packets arrive at the ruby port first, which then routes them to their destination. Note that the patch does not make these packets go through the ruby network. That would happen in a subsequent patch.
2014-02-23ruby: Simplify RubyPort flow control and routingAndreas Hansson
This patch simplfies the retry logic in the RubyPort, avoiding redundant attributes, and enforcing more stringent checks on the interactions with the normal ports. The patch also simplifies the routing done by the RubyPort, using the port identifiers instead of a heavy-weight sender state. The patch also fixes a bug in the sending of responses from PIO ports. Previously these responses bypassed the queue in the queued port, and ignored the return value, potentially leading to response packets being lost. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-02-23config: topologies: slight code refactorNilay Vaish
2014-02-23ruby: message buffer: refactor codeNilay Vaish
Code in two of the functions was exactly the same. This patch moves this code to a new function which is called from the two functions mentioned initially.
2014-02-23ruby: remove few not required #includesNilay Vaish
2014-02-23ruby: slicc: remove unused COPY_HEAD functionalityNilay Vaish
2014-02-23ruby: protocols: remove unused action z_stallNilay Vaish
2014-02-21config: ruby_random_test: updates due to recent unrelated changesNilay Vaish
2014-02-21ruby: network: move message buffers to base network class.Nilay Vaish
2014-02-21ruby: network: garnet: fixed: removes net_ptr from linksNilay Vaish
2014-02-21ruby: cache: remove not required variable m_cache_nameNilay Vaish
2014-02-20ruby: network: garnet: fixed: removes next cycle functionsNilay Vaish
At several places, there are functions that take a cycle value as input and performs some computation. Along with each such function, another function was being defined that simply added one more cycle to input and computed the same function. This patch removes this second copy of the function. Places where these functions were being called have been updated to use the original function with argument being current cycle + 1.
2014-02-20ruby: controller: slight code refactoringNilay Vaish
2014-02-20ruby: mesi three level: rename incorrectly named filesNilay Vaish
Two files had been incorrectly named with a .cache suffix. --HG-- rename : src/mem/protocol/MESI_Three_Level-L0.cache => src/mem/protocol/MESI_Three_Level-L0cache.sm rename : src/mem/protocol/MESI_Three_Level-L1.cache => src/mem/protocol/MESI_Three_Level-L1cache.sm
2014-02-20ruby: network: removes unused code.Nilay Vaish
2014-02-20ruby: slicc: slight code refactoringNilay Vaish
2014-02-20ruby: message buffer: removes some unecessary functions.Nilay Vaish
2014-02-20kvm: Add support for multi-system simulationAndreas Sandberg
The introduction of parallel event queues added most of the support needed to run multiple VMs (systems) within the same gem5 instance. This changeset fixes up signal delivery so that KVM's control signals are delivered to the thread that executes the CPU's event queue. Specifically: * Timers and counters are now initialized from a separate method (startupThread) that is scheduled as the first event in the thread-specific event queue. This ensures that they are initialized from the thread that is going to execute the CPUs event queue and enables signal delivery to the right thread when exiting from KVM. * The POSIX-timer-based KVM timer (used to force exits from KVM) has been updated to deliver signals to the thread that's executing KVM instead of the process (thread is undefined in that case). This assumes that the timer is instantiated from the thread that is going to execute the KVM vCPU. * Signal masking is now done using pthread_sigmask instead of sigprocmask. The behavior of the latter is undefined in threaded applications. * Since signal masks can be inherited, make sure to actively unmask the control signals when setting up the KVM signal mask. There are currently no facilities to multiplex between multiple KVM CPUs in the same event queue, we are therefore limited to configurations where there is only one KVM CPU per event queue. In practice, this means that multi-system configurations can be simulated, but not multiple CPUs in a shared-memory configuration.
2014-02-19arm: Bump stats after FS config script updateAndreas Hansson
This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-18arm: armv8 boot options to enable v8Anthony Gutierrez
Modifies FSConfig.py to enable ARMv8 compatibility. To boot gem5 with ARMv8: Download the v8 kernel, .dtb file, and root FS from: http://gem5.org/Download Download the ARMv8 toolchain, and add the bin dir to your path: http://www.linaro.org/engineering/engineering-projects/armv8 Build gem5 for ARM Build the v8 bootloader (in gem5/system/arm/aarch64_bootloader) Make script in gem5/system/arm/aarch64_bootloader will require v8 toolchain, drop the produced boot_emm.arm64 in $(M5_PATH)/binaries/ Run: $ build/ARM/gem5.fast configs/example/fs.py --machine-type=VExpress_EMM64 \ --kernel=/path/to/kernel/vmlinux-linaro-tracking \ --dtb-filename=/path/to/dtb/rtsm_ve-aemv8a.dtb \ --disk-image=/path/to/img/linaro-minimal-armv8.img
2014-02-18mem: Fix bug in PhysicalMemory use of mmap and munmapAndreas Hansson
This patch fixes a bug in how physical memory used to be mapped and unmapped. Previously we unmapped and re-mapped if restoring from a checkpoint. However, we never checked that the new mapping was actually the same, it was just magically working as the OS seems to fairly reliably give us the same chunk back. This patch fixes this issue by relying entirely on the mmap call in the constructor.
2014-02-18dev: Include basic devices in NULL ISA buildAndreas Hansson
This patch enbles use of the basic PIO devices as part of the NULL build. Although it might seem counter intuitive to have a PIO device without being able to execute a driver, this change enables us to break a device class hierarchy into an ISA-agnostic part, and an ISA-specific part, without requiring multiple-inheritance. The ISA-agnostic base class is a PIO device, but does not make use of the port.
2014-02-18scons: Add PROTOC from the environmentAndreas Hansson
This patch adds PROTOC to the build environment.
2014-02-18mem: Filter cache snoops based on address rangesAndreas Hansson
This patch adds a filter to the cache to drop snoop requests that are not for a range covered by the cache. This fixes an issue observed when multiple caches are placed in parallel, covering different address ranges. Without this patch, all the caches will forward the snoop upwards, when only one should do so.
2014-02-18mem: Add a wrapped DRAMSim2 memory controllerAndreas Hansson
This patch adds DRAMSim2 as a memory controller by wrapping the external library and creating a sublass of AbstractMemory that bridges between the semantics of gem5 and the DRAMSim2 interface. The DRAMSim2 wrapper extracts the clock period from the config file. There is no way of extracting this information from DRAMSim2 itself, so we simply read the same config file and get it from there. To properly model the response queue, the wrapper keeps track of how many transactions are in the actual controller, and how many are stacking up waiting to be sent back as responses (in the wrapper). The latter requires us to move away from the queued port and manage the packets ourselves. This is due to DRAMSim2 not having any flow control on the response path. DRAMSim2 assumes that the transactions it is given are matching the burst size of the choosen memory. The wrapper checks to ensure the cache line size of the system matches the burst size of DRAMSim2 as there are currently no provisions to split the system requests. In theory we could allow a cache line size smaller than the burst size, but that would lead to inefficient use of the DRAM, so for not we fatal also in this case.
2014-02-18util: Enhance the error messages for packet encode/decodeAndreas Hansson
This patch adds a more verbose error message when the Python protobuf module cannot be loaded.
2014-02-18mem: Fix input to DPRINTF in CommMonitorAndreas Hansson
Minor fix of the debug message parameters.
2014-02-16stats: updates due to branch predictor warmingNilay Vaish
2014-02-15Added tag stable_2014_02_15 to the changeset 459491344fcfNilay Vaish
2014-02-09cpu: simple: Add support for using branch predictorsAndreas Sandberg
This changesets adds branch predictor support to the BaseSimpleCPU. The simple CPUs normally don't need a branch predictor, however, there are at least two cases where it can be desirable: 1) A simple CPU can be used to warm the branch predictor of an O3 CPU before switching to the slower O3 model. 2) The simple CPU can be used as a quick way of evaluating/debugging new branch predictors since it exposes branch predictor statistics. Limitations: * Since the simple CPU doesn't speculate, only one instruction will be active in the branch predictor at a time (i.e., the branch predictor will never see speculative branches). * The outcome of a branch prediction does not affect the performance of the simple CPU.
2014-02-06base: calls abort() from fatalNilay Vaish
Currently fatal() ends the simulation in a normal fashion. This results in the call stack getting lost when using a debugger and it is not always possible to debug the simulation just from the information provided by the printed error message. Even though the error is likely due to a user's fault, the information available should not be thrown away. Hence, this patch to call abort() from fatal().
2014-02-06ruby: memory controller: use MemoryNode *Nilay Vaish
2014-02-05x86: Fix x87 state transfer bugAndreas Sandberg
Changeset 7274310be1bb (isa: clean up register constants) increased the value of NumFloatRegs, which triggered a bug in X86ISA::copyRegs(). This bug is caused by the x87 stack being copied twice since register indexes past NUM_FLOATREGS are mapped into the x87 stack relative to the top of the stack, which is undefined when the copy takes place. This changeset updates the copyRegs() function to use access registers using the non-flattening interface, which guarantees that undesirable register folding does not happen.
2014-02-02x86, kvm: Fix bug in the RFlags get and set functionsNikos Nikoleris
The getRFlags and setRFlags utility functions were not updated correctly when condition registers were separated into their own register class. This lead to incorrect state transfer in calls from kvm into the simulator (e.g., m5 readfile ended up in an infinite loop) and when switching CPUs. This patch makes these utility functions use getCCReg and setCCReg instead of getIntReg and setIntReg which read and write the integer registers. Reviewed-by: Andreas Sandberg <andreas@sandberg.pp.se>
2014-01-31config: correct bug in x86 drive sys instantiationNilay Vaish
2014-01-30unittest: Fix build errorsOla Jeppsson
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-01-29mem: Add additional tolerance to stride prefetcherMitch Hayenga
Forces the prefetcher to mispredict twice in a row before resetting the confidence of prefetching. This helps cases where a load PC strides by a constant factor, however it may operate on different arrays at times. Avoids the cost of retraining. Primarily helps with small iteration loops. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-01-29mem: Allowed tagged instruction prefetching in stride prefetcherMitch Hayenga
For systems with a tightly coupled L2, a stride-based prefetcher may observe access requests from both instruction and data L1 caches. However, the PC address of an instruction miss gives no relevant training information to the stride based prefetcher(there is no stride to train). In theses cases, its better if the L2 stride prefetcher simply reverted back to a simple N-block ahead prefetcher. This patch enables this option. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-01-29mem: prefetcher: add options, support for unaligned addressesMitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E)
This patch extends the classic prefetcher to work on non-block aligned addresses. Because the existing prefetchers in gem5 mask off the lower address bits of cache accesses, many predictable strides fail to be detected. For example, if a load were to stride by 48 bytes, with 64 byte cachelines, the current stride based prefetcher would see an access pattern of 0, 64, 64, 128, 192.... Thus not detecting a constant stride pattern. This patch fixes this, by training the prefetcher on access and not masking off the lower address bits. It also adds the following configuration options: 1) Training/prefetching only on cache misses, 2) Training/prefetching only on data acceses, 3) Optionally tagging prefetches with a PC address. #3 allows prefetchers to train off of prefetch requests in systems with multiple cache levels and PC-based prefetchers present at multiple levels. It also effectively allows a pipelining of prefetch requests (like in POWER4) across multiple levels of cache hierarchy. Improves performance on my gem5 configuration by 4.3% for SPECINT and 4.7% for SPECFP (geomean).
2014-01-29cpu: fix bug when TrafficGen deschedules eventXiangyu Dong
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-01-28arm: Enable umask syscall in SE modeMitch Hayenga
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-01-28base: Fix race condition in the socket listen functionMitch Hayenga
gem5 makes the incorrect assumption that by binding a socket, it effectively has allocated a port. Linux only allocates ports once you call listen on the given socket, not when you call bind. So even if the port was free when bind was called, another process (gem5 instance) could race in between the bind & listen calls and steal the port. In the current code, if the call to bind fails due to the port being in use (EADDRINUSE), gem5 retries for a different port. However if listen fails, gem5 just panics. The fix is testing the return value of listen and re-trying if it was due to EADDRINUSE. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-01-28mem: Remove redundant findVictim() input argumentAmin Farmahini
The patch (1) removes the redundant writeback argument from findVictim() (2) fixes the description of access() function Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-01-28mem: Fixes a bug in simple_dram write mergingAmin Farmahini
Fixes updating the value of size in the write merge function. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-01-28x86: add a warning about the number of memory controllersNilay Vaish
When memory size > 3GB, print a warning that twice the number of memory controllers would be created.
2014-01-27x86: use lfpimm instead of limm for fptanNilay Vaish