| Age | Commit message (Expand) | Author |
|---|
| 2018-01-29 | arm: DT autogeneration - Generate energy controller node | Glenn Bergmans |
| 2018-01-29 | arm: DT autogeneration - autogenerate RealView Platform devices | Glenn Bergmans |
| 2018-01-29 | arm: DT autogeneration - Generate memory node | Glenn Bergmans |
| 2018-01-29 | arm: DT autogeneration - Generate cpus node | Glenn Bergmans |
| 2018-01-29 | arm: DT autogeneration - Device Tree generation methods | Glenn Bergmans |
| 2018-01-29 | ext: DT autogeneration - Add PyFtd to m5 space | Glenn Bergmans |
| 2018-01-29 | arm: make Arm GenericTimer a ClockedObject | Curtis Dunham |
| 2018-01-27 | base: Add an "override" to name() in the HardBreakpoint class. | Gabe Black |
| 2018-01-27 | base: Get bitunions to compile on clang 3.8. | Gabe Black |
| 2018-01-25 | util: Implement Lua module for m5ops. | Hanhwi Jang |
| 2018-01-23 | arch-x86: Adding clflush, clflushopt, clwb instructions | Swapnil Haria |
| 2018-01-23 | arch: Remove the "arch/tlb.hh" switching header. | Gabe Black |
| 2018-01-23 | tarch, mem: Abstract the data stored in the SE page tables. | Gabe Black |
| 2018-01-23 | x86, mem: Rewrite the multilevel page table class. | Gabe Black |
| 2018-01-20 | util: Implement PIC version of m5ops for X86. | Hanhwi Jang |
| 2018-01-20 | x86, mem: Don't try to force physical addresses on the system. | Gabe Black |
| 2018-01-20 | x86, mem: Get rid of PageTableOps::getBasePtr. | Gabe Black |
| 2018-01-20 | x86, mem: Pass the multi level page table layout in as a parameter. | Gabe Black |
| 2018-01-20 | arch, mem: Make the page table lookup function return a pointer. | Gabe Black |
| 2018-01-20 | base: Hide the BitUnion::__StorageType type. | Gabe Black |
| 2018-01-20 | arm, base: Generalize and move the BitUnion hash struct. | Gabe Black |
| 2018-01-20 | sim: Use the new BitUnion templates in serialize.hh. | Gabe Black |
| 2018-01-20 | base: Enable specializing templates on BitUnion types. | Gabe Black |
| 2018-01-20 | base: Rework bitunions so they can be more flexible. | Gabe Black |
| 2018-01-20 | sim, arch, base: Refactor the base remote GDB class. | Gabe Black |
| 2018-01-19 | arch, mem, sim: Consolidate and rename the SE mode page table classes. | Gabe Black |
| 2018-01-18 | util: Add an option to specify paths in list_changes.py | Andreas Sandberg |
| 2018-01-17 | mem: Change the multilevel page table to inherit from FuncPageTable. | Gabe Black |
| 2018-01-16 | arch-riscv: Fix floating-poing op classes | Alec Roelke |
| 2018-01-16 | arch-riscv: Fix floating-point conversion bugs | Alec Roelke |
| 2018-01-16 | sim: Simplify registerThreadContext a little bit. | Gabe Black |
| 2018-01-15 | mem: Track TLB entries in the lookup cache as pointers. | Gabe Black |
| 2018-01-15 | arch: Fix a fatal_if in most of the arch's process classes. | Gabe Black |
| 2018-01-12 | sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy(). | Xiaoyu Ma |
| 2018-01-11 | util/m5: add Android.mk | Earl Ou |
| 2018-01-11 | arch-riscv: Don't crash when printing unknown CSRs | Alec Roelke |
| 2018-01-11 | mem-ruby: Fix wakeup timeouts for the MOESI_CMP_token protocol | Nikos Nikoleris |
| 2018-01-11 | mem-ruby: Remove function that maps responses to a DMA engine | Nikos Nikoleris |
| 2018-01-11 | mem-ruby: Add support for multiple DMA engines in MESI_Two_Level | Nikos Nikoleris |
| 2018-01-11 | cpu: Make the CPU's TLB parameter a BaseTLB. | Gabe Black |
| 2018-01-11 | arm, power: Make the python TLB simobjects inherit from BaseTLB. | Gabe Black |
| 2018-01-11 | arch,mem: Remove the default value for page size. | Gabe Black |
| 2018-01-11 | arch,mem: Move page table construction into the arch classes. | Gabe Black |
| 2018-01-10 | configs: Fill in the cpu.isa field in etrace_replay.py since no default are p... | Chen Zou |
| 2018-01-10 | style: change C/C++ source permissions to noexec | BKP |
| 2018-01-10 | arch-riscv: Make use of ImmOp's polymorphism | Alec Roelke |
| 2018-01-10 | alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT. | Gabe Black |
| 2018-01-10 | arch-riscv,sim: Support clone syscall in RISC-V | Tuan Ta |
| 2018-01-09 | mem-cache: Prune unnecessary writebacks in exclusive caches | Nikos Nikoleris |
| 2018-01-09 | util: Add the missing wakecpu m5op in X86. | Hanhwi Jang |
