gem5 - gem5

Age	Commit message (Expand)	Author
2006-10-27	Merge zizzer:/bk/newmem	Ali Saidi
2006-10-27	add packet_access.hh	Ali Saidi
2006-10-27	A more complete attempt to fix the clock skew.	Gabe Black
2006-10-27	Potential fix to clock skew problem.	Gabe Black
2006-10-27	Merge zizzer.eecs.umich.edu:/bk/newmem	Gabe Black
2006-10-27	Update stats for fill/spill handlers	Gabe Black
2006-10-27	Got rid of some outdated comments.	Gabe Black
2006-10-27	Made the regfile compatible with the new definitions in MiscRegFile	Gabe Black
2006-10-27	Clean up MiscRegFile	Gabe Black
2006-10-26	Reorganized the MiscRegFile	Gabe Black
2006-10-26	Cleaned up the decoder slightly.	Gabe Black
2006-10-26	Added a few functions to stuff values into bitfields in an instruction.	Gabe Black
2006-10-26	Changed the number of register windows to be more realistic.	Gabe Black
2006-10-26	Got rid of some debug output	Gabe Black
2006-10-26	Change the default function from setMiscRegWithEffect to setMiscReg	Gabe Black
2006-10-26	Merge zizzer:/bk/newmem	Lisa Hsu
2006-10-26	se.py:	Lisa Hsu
2006-10-26	Merge zizzer:/bk/newmem	Ali Saidi
2006-10-25	Fix simple timing port keep a list of all packets, have only one event, and s...	Ali Saidi
2006-10-25	Fixed the priv instruction format.	Gabe Black
2006-10-25	Implemented the saved and restored instructions, fixed up register window ins...	Gabe Black
2006-10-25	Fixed the bitfield FCN to include the right bits.	Gabe Black
2006-10-25	Implemented the SPARC fill and spill handlers.	Gabe Black
2006-10-25	Fix fixPacket functionality to calculate sizes properly	Ron Dreslinski
2006-10-24	Replace the Alpha No op with a SPARC one.	Gabe Black
2006-10-24	Fix fs.py. Lisa did you test this? Is there some wierd python version thing?	Ali Saidi
2006-10-24	Merge zizzer:/bk/newmem	Ali Saidi
2006-10-24	Add more traceflags for ethernet	Ali Saidi
2006-10-24	Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem	Steve Reinhardt
2006-10-23	warmup of 1B cpu cycles.	Lisa Hsu
2006-10-23	Merge zizzer:/bk/newmem	Lisa Hsu
2006-10-23	get rid of the "resume" step at the end of changeToTiming/Atomic because this...	Lisa Hsu
2006-10-23	make this parallel to the other cpu types so that resume works correctly.	Lisa Hsu
2006-10-23	make a lot of the same changes as to fs.py for checkpointing.	Lisa Hsu
2006-10-23	changes regarding fs.py	Lisa Hsu
2006-10-23	Minor compile fix. Not sure why this is broken.	Gabe Black
2006-10-23	Move around more SPARC memory code, and make block memory operations work wit...	Gabe Black
2006-10-23	Merge zizzer.eecs.umich.edu:/bk/newmem	Gabe Black
2006-10-23	Add reference outputs for SPARC on the atomic timing cpu model	Gabe Black
2006-10-23	Broke Load/Store instructions into microcode, and partially refactored memory...	Gabe Black
2006-10-23	Don't let interupts interupt microcode at undesired points.	Gabe Black
2006-10-23	Files in base shouldn't depend on things in sim. Changed "sim/host.hh" to <in...	Gabe Black
2006-10-23	Start making memory ops work with InitiateAcc and CompleteAcc, and some minor...	Gabe Black
2006-10-23	Change the default constructors to take ExtMachInsts rather than regular Mach...	Gabe Black
2006-10-22	Clean up cache DPRINTFs	Steve Reinhardt
2006-10-22	s/pktuest/request/ (all in comments)	Steve Reinhardt
2006-10-22	Add DPRINTF for non-timed quiesce.	Steve Reinhardt
2006-10-22	Add mutex test to Benchmarks.py.	Steve Reinhardt
2006-10-22	Another missing case in a switch (like Nate's earlier fix).	Steve Reinhardt
2006-10-22	Have tracediff print warning if no traceflags are set.	Steve Reinhardt