gem5 - gem5

Age	Commit message (Expand)	Author
2012-10-15	Checkpoint: Make system serialize call children	Andreas Hansson
2012-10-15	Mem: Use deque instead of list for bus retries	Andreas Hansson
2012-10-15	Fix: Address a few minor issues identified by cppcheck	Andreas Hansson
2012-10-15	Stats: Update stats for cache timings in cycles	Andreas Hansson
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-10-15	Stats: Update memtest stats after setting clock	Andreas Hansson
2012-10-15	Configs: Set the memtest clock to a reasonable value	Andreas Hansson
2012-10-15	Stats: Update stats for new default L1-to-L2 bus clock and width	Andreas Hansson
2012-10-15	Regression: Use CPU clock and 32-byte width for L1-L2 bus	Andreas Hansson
2012-10-15	Stats: Update stats for use of two-level builder	Andreas Hansson
2012-10-15	Regression: Use addTwoLevelCacheHierarchy in configs	Andreas Hansson
2012-10-15	Clock: Inherit the clock from parent by default	Andreas Hansson
2012-10-15	Param: Fix proxy traversal to support chained proxies	Andreas Hansson
2012-10-15	Mem: Use range operations in bus in preparation for striping	Andreas Hansson
2012-10-11	Mem: Determine bus block size during initialisation	Andreas Hansson
2012-10-11	Doxygen: Update the version of the Doxyfile	Andreas Hansson
2012-10-02	Regression Tests: Update statistics	Nilay Vaish
2012-10-02	ruby: makes some members non-static	Nilay Vaish
2012-10-02	ruby: changes to simple network	Nilay Vaish
2012-10-02	ruby: rename template_hack to template	Nilay Vaish
2012-10-02	ruby: remove unused code in protocols	Nilay Vaish
2012-10-02	ruby: remove some unused things in slicc	Nilay Vaish
2012-10-02	ruby: move functional access to ruby system	Nilay Vaish
2012-09-30	MI coherence protocol: add copyright notice	Nilay Vaish
2012-09-28	Configs: SE script fix for Alpha and Ruby simulations	Malek Musleh
2012-09-27	Configs: Fix memtest cache latency to match new parameters	Andreas Hansson
2012-09-27	Configs: Fix memtest.py by moving the system port	Andreas Hansson
2012-09-25	ARM: update stats for bp and squash fixes.	Ali Saidi
2012-09-25	MEM: Put memory system document into doxygen	Djordje Kovacevic
2012-09-25	Cache: add a response latency to the caches	Mrinmoy Ghosh
2012-09-25	Statistics: Add a function to configure periodic stats dumping	Sascha Bischoff
2012-09-25	ARM: added support for flattened device tree blobs	Dam Sunwoo
2012-09-25	O3: Pack the comm structures a bit better to reduce their size.	Ali Saidi
2012-09-25	mem: Add a gasket that allows memory ranges to be re-mapped.	Ali Saidi
2012-09-25	ARM: Squash outstanding walks when instructions are squashed.	Ali Saidi
2012-09-25	Util: Added script to semantically diff two config.ini files	Sascha Bischoff
2012-09-25	arm: Use a static_assert to test that miscRegName[] is complete	Andreas Sandberg
2012-09-25	base: Check for static_assert support and provide fallback	Andreas Sandberg
2012-09-25	sim: Move CPU-specific methods from SimObject to the BaseCPU class	Andreas Sandberg
2012-09-25	sim: Remove SimObject::setMemoryMode	Andreas Sandberg
2012-09-25	CPU: Add abandoned instructions to O3 Pipe Viewer	Djordje Kovacevic
2012-09-25	ARM: Inst writing to cntrlReg registers not set as control inst	Nathanael Premillieu
2012-09-25	ARM: Predict target of more instructions that modify PC.	Ali Saidi
2012-09-25	gem5: Update the README file to be a bit less out-of-date.	Ali Saidi
2012-09-25	build: Add missing dependencies when building param SWIG interfaces	Andreas Sandberg
2012-09-24	Stats: Update stats for twosys-tsunami after setting CPU clock	Andreas Hansson
2012-09-24	Regression: Set the clock for twosys-tsunami CPUs	Andreas Hansson
2012-09-23	RubyPort and Sequencer: Fix draining	Joel Hestness
2012-09-21	SimpleDRAM: A basic SimpleDRAM regression	Andreas Hansson
2012-09-21	DRAM: Introduce SimpleDRAM to capture a high-level controller	Andreas Hansson